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DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

DLPC2607 低功耗 DLP^®显示控制器

1 特性

–

DMD 水平和垂直显示图像抖动

显示图像旋转

1

•

支持 0.2 nHD、0.24 VGA 和

0.3 WVGA DMD 的可靠运行

基于闪存的配置批处理文件

I/F 睡眠静止图像省电模式

•

多模式，24 位输入像素接口：

–

支持并行或 BT656 总线协议

支持从 QVGA 到 WVGA 的输入大小

支持 1 至 60Hz 的帧速率

•

测试支持：

–

内置测试信号生成

支持边界扫描测试的 JTAG

支持高达 33.5MHz 的像素时钟

支持竖排和横排方向

2 应用范围

•

嵌入式移动投影

支持 8、16、18 和 24 位总线选项

支持 3 输入色彩位深选项：

–

智能手机

平板电脑

摄像机

–

RGB888，YCrCb888

RGB666，YCrCb666

RGB565，4:2:2 YCrCb

笔记本电脑

•

移动附件

•

像素数据处理

可佩戴（近眼）显示

电池供电投影仪

–

图像大小调整（缩放）

帧速率转换

色彩坐标调整

3 说明

自动增益控制

DLPC2607 是一款用于电池供电™显示应用的低功耗

DLP 数字控制器中运行。该控制器支持 0.3 WVGA、

0.24 VGA 和 0.2 nHD DMD 的可靠运行。DLPC2607

控制器提供了用于连接系统电子产品和 DMD 的便捷多

功能接口，从而能够实现小尺寸、低功耗显示器。

可编程后期色彩校正 (Degamma)

空间-时间复用（抖动显示）

视频处理支持：

–

色彩空间转换

4:2:2 至 4:4:4 色度插值

场缩放去隔行

器件信息⁽¹⁾

器件型号

DLPC2607

封装

封装尺寸（标称值）

•

封装在 176 引脚，0.4mm 焊球间距，极细间距球

状引脚栅格阵列 (VFBGA) 封装

VFBGA (176)

7.00mm × 7.00mm

支持外部存储器：

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

–

166MHz 移动 DDR SDRAM

33.3MHz 串行闪存

•

WVGA，VGA 和 nHD DMD 显示支持

–

DMD 位平面生成和格式化

可编程位平面显示排序器（控制发光二极管

(LED) 使能和 DMD 加载）

–

76.2MHz 双倍数据速率 (DDR) DMD 接口 (I/F)

针对微镜的脉宽调制 (PWM)：

–

断电时的自动 DMD 停止

DMD 24 位位深

•

系统控制：

–

器件配置的 I²C 控制

可编程 Splash 屏幕

可编程 LED 电流控制

DMD 电源和微镜驱动器控制

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS030

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

7.2 Functional Block Diagram ....................................... 23

7.3 Feature Description................................................. 23

7.4 Programming........................................................... 25

Application and Implementation ........................ 27

8.1 Application Information............................................ 27

8.2 Typical Application ................................................. 27

Power Supply Recommendations...................... 32

9.1 System Power Considerations................................ 32

9.2 System Power-Up and Power-Down Sequence ..... 32

9.3 System Power I/O State Considerations ............... 34

9.4 Power-Up Initialization Sequence ........................... 34

9.5 Power-Good (PARK) Support ................................ 35

1

2

3

4

5

6

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 5

Specifications....................................................... 12

6.1 Absolute Maximum Ratings .................................... 12

6.2 ESD Ratings............................................................ 12

6.3 Recommended Operating Conditions..................... 12

6.4 Thermal Information................................................ 13

6.5 Typical Current and Power Dissipation................... 13

6.6 I/O Characteristics................................................... 14

6.7 Internal Pullup and Pulldown Characteristics ........ 14

6.8 Parallel I/F Frame Timing Requirements ................ 15

6.9 Parallel I/F General Timing Requirements.............. 15

8

9

10 Layout................................................................... 36

10.1 Layout Guidelines ................................................. 36

10.2 Layout Example .................................................... 42

11 器件和文档支持 ..................................................... 43

11.1 器件支持................................................................ 43

11.2 社区资源................................................................ 44

11.3 商标....................................................................... 44

11.4 静电放电警告......................................................... 44

11.5 术语表 ................................................................... 44

12 机械、封装和可订购信息....................................... 44

12.1 封装选项附录......................................................... 45

6.10 Parallel I/F Maximum Parallel Interface Horizontal

Line Rate.................................................................. 16

6.11 BT.656 I/F General Timing Requirements ............ 17

6.12 100- to 120-Hz Operational Limitations ................ 17

6.13 Flash Interface Timing Requirements .................. 18

6.14 DMD Interface Timing Requirements ................... 18

6.15 mDDR Memory Interface Timing Requirements .. 19

Detailed Description ............................................ 23

7.1 Overview ................................................................. 23

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision D (May 2017) to Revision E

Page

•

已更改将标题从“DLPC2607 DLP PICO 处理器 2607 ASIC”更改为“DLPC2607 低功耗 DLP^®显示控制器”.......................... 1

Added ZVB Package Bottom View ........................................................................................................................................ 5

Changed to "Add external pullup or pulldown resistors as needed to these signals to avoid floating inputs" ...................... 5

Changed PAD1000 to DLPA1000 .......................................................................................................................................... 5

Changed to "Establish this setting" ....................................................................................................................................... 5

Changed "low a minimum" to "low to a minimum" ................................................................................................................ 5

Changed "Should be pulled up to" to "Pull up to" .................................................................................................................. 5

Changed "Unused inputs should be pulled down" to "Pull unused inputs" ........................................................................... 6

Added DMD INTERFACE pin descriptions ........................................................................................................................... 7

Added SDRAM INTERFACE pin descriptions ....................................................................................................................... 8

Changed "It should be connected" to "Connect". .................................................................................................................. 9

Changed globally "Should be left open or unconnected for typical use." to "Leave open or unconnected for typical

use." ..................................................................................................................................................................................... 10

•

Changed globally "An external pullup should not be applied to this pin..." to "Do not apply an external pullup to this

pin..."..................................................................................................................................................................................... 10

•

Swapped all values under I_OHand I_OL................................................................................................................................. 14

Changed "that should be applied" to "can safely be applied" ............................................................................................. 14

Changed "_OHand _OL" to VOH and VOL to clarify meaning.................................................................................................... 14

Changed "VCCIO =" to "VCCIO (V)" ................................................................................................................................... 14

Changed "MAX Supported" to "Maximum Parallel Interface" .............................................................................................. 16

2

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

修订历史记录 (接下页)

•

Changed Changed "BT.565" to "BT.656" ............................................................................................................................ 17

Added link to ITU-R BT.656 specification ............................................................................................................................ 17

Changed "NOTE:" to "The table below" ............................................................................................................................... 17

Deleted "Note that" ............................................................................................................................................................... 17

Changed f_clockmin................................................................................................................................................................. 18

Changed t_{p_clkper}min and max .............................................................................................................................................. 18

Changed "should support" to "supports" ............................................................................................................................. 25

Changed "Thus, those pins should be tied" to "Tie these pins" .......................................................................................... 26

Changed "1.8-, 2.5-, or 3.3-V" to "1.8 V, 2.5 V, or 3.3 V" .................................................................................................... 26

Changed "the ASIC only supports periodic sources" to "the ASIC supports periodic sources only" .................................. 27

Changed "multi media" to "multimedia" ............................................................................................................................... 27

Changed Device Functional Modes to System Functional Modes and moved to correct position ..................................... 27

Added Reference to TSTPT_6 for Crystal nominal frequency ............................................................................................. 28

Changed "ASIC, and the PLL_REFCLK_O pins hould be left unconnected" to "ASIC. Leave the PLL_REFCLK_O

pins unconnected" ............................................................................................................................................................... 29

•

Changed "The benefit of an oscillator is that it can be made to provide a spread-spectrum clock that reduces EMI."

to "An oscillator that provides a spread-spectrum clock reduces EMI."............................................................................... 29

•

Changed "can only accept" to "accepts" ............................................................................................................................. 29

Added kHz ........................................................................................................................................................................... 29

Changed several items in Table 7 ....................................................................................................................................... 29

Changed " the ODM’s own risk" to "the risk of the ODM" ................................................................................................... 29

Changed " Layout guidelines should be followed" to "Follow the layout guidelines" .......................................................... 29

Changed "To complete DLP system . . . is requiered" to "The DLP system requires" ........................................................ 29

Changed "The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an

optical OEM who specializes in designing optics for DLP projectors." to "An optical OEM that specializes in

designing optics for DLP projectors typically supplies the optical engine that has the LED packages and the DMD

mounted to it." ...................................................................................................................................................................... 29

•

Deleted "Note that" .............................................................................................................................................................. 30

Changed "this allows these inputs to be driven high" to "This protection allows the device to drive these inputs high" ..... 30

Changed .............................................................................................................................................................................. 30

Changed "All I/O power should remain" to "Ensure that all I/O power remains" ................................................................. 32

Changed "is defined" to "operates as" ................................................................................................................................ 35

Changed "should alert" to "alerts" ........................................................................................................................................ 35

Changed "Note that the reference clock should continue to run and RESET should remain" to "The reference clock

continues to run. RESET remains" ...................................................................................................................................... 35

•

Changed "At a minimum, VDD_PLL power and VSS_PLL ground pins should be isolated" to "Isolate VDD_PLL

power and VSS_PLL ground pins" ...................................................................................................................................... 36

Changed "It is important that the quiet ground and power are treated like analog signals" to "The ground and power

domains are analog signals, and should be treated as such to achieve minimum noise.".................................................. 36

Changed "The power and ground traces should be as short as possible" to "Ensure that the power and ground

traces are as short as possible" ........................................................................................................................................... 36

•

Changed "and should not be expected" to "so do not expect them" ................................................................................... 37

Changed "they should be" to "ensure they are" .................................................................................................................. 37

Changed "should be split" to "Split the" ............................................................................................................................... 37

Changed "In addition, the SPICLK trace . . . should be" to "Make the SPICLK trace" ........................................................ 37

Changed "should be split" to "Split the" ............................................................................................................................... 37

Changed "In addition, the SPIDOUT trace . . . should be" to "Make the SPIDOUT trace".................................................. 37

3

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

修订历史记录 (接下页)

•

Changed "The SPIDIN .... should be split" to "Make the SPDIN" ....................................................................................... 37

Changed "on their way back" to "on the return" .................................................................................................................. 37

Changed "They should then share" to "Make sure they share" .......................................................................................... 37

Changed "Variation from these recommendations may also work, but should be confirmed with PCB signal integrity

analysis or lab measurements" to "Make sure to confirm any variation from these recommendations with PCB signal

integrity analysis or lab measurements" .............................................................................................................................. 37

•

Changed PCB Design table to itemized list ........................................................................................................................ 38

Changed "should take" to "takes" ........................................................................................................................................ 40

Changed "should" to "must" ................................................................................................................................................ 40

Changed "The pair should also be terminated" to "Terminate the pair" .............................................................................. 41

Changed "Specifically ... should be terminated" to "Terminate" .......................................................................................... 41

Changed "kept" to "maintained to a length of" .................................................................................................................... 41

Changed "should" to "does" ................................................................................................................................................ 41

Changes from Revision C (November 2015) to Revision D

Page

•

Removed table 'Compatible SPI Serial Flash Devices' from Serial Flash Interface since listed devices are end of life.

Replaced with new suggested devices as well as Table 4 which lists minimum performance specifications to

determine flash device compatibility..................................................................................................................................... 26

•

在封装信息中添加了“MSL 峰值温度” ................................................................................................................................... 45

Changes from Revision B (January 2014) to Revision C

Page

•

添加了 ESD 额定值表、热性能信息表、特性说明部分、器件功能模式、应用和实施部分、电源建议部分、布局

部分、器件和文档支持部分以及机械、封装和可订购信息部分............................................................................................. 1

Changes from Revision A (December 2013) to Revision B

Page

•

删除了产品预览横幅 ............................................................................................................................................................... 1

Changes from Original (December 2013) to Revision A

Page

•

Corrected columns for I_OHand I_OLin I/O Characteristics ..................................................................................................... 14

Updated B38 I/O Type value for V_OH(min) in I/O Characteristics ....................................................................................... 14

Added additional table notes to I/O Characteristics ............................................................................................................ 14

Added table note to Internal Pullup and Pulldown Characteristics ...................................................................................... 14

Corrected device reference to DLPC2607 in the notes for mDDR Memory Interface Timing Requirements ..................... 19

4

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

5 Pin Configuration and Functions

ZVB Package

176-Pin NFBGA

Bottom View

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1 2 3 4 5 6 7 8 9 101112131415

(1)

Pin Functions

I/O

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

DEVICE INITIALIZATION AND REFERENCE CLOCK⁽¹⁾

DLPC2607 power-on reset. Self-configuration starts when a low-to-high

transition is detected on this pin. All ASIC power and clocks must be stable

before this reset is de-asserted (hysteresis buffer). Note that the following

seven signals tri-state while RESET is asserted: DMD_PWR_EN,

LEDDVR_ON, LED_SEL_0,LED_SEL_1, SPICLK, SPIDOUT, SPICSZ0

Add external pullup or pulldown resistors as needed to these signals to avoid

floating inputs.

RESETZ

J14

VCC18

I1

Async

Reference clock crystal input. If an external oscillator is used in place of a

crystal, then use this pin as the oscillator Input.

PLL_REFCLK_I

PLL_REFCLK_O

K15

J15

I4

N/A

VCC18 (filter)

Reference clock crystal return. If an external oscillator is used in place of a

crystal, then leave this pin unconnected (floating).

O14

FLASH INTERFACE⁽²⁾

SPICLK

A4

B4

A5

C6

O24

I2

N/A

Clock for the external SPI device or devices

SPIDIN

SPICLK

Serial data input from the external SPI device or devices

Chip select 0 output for the external SPI flash device. Active low

Chip select 1 output for the external SPI DLPA1000 device. Active low

SPICSZ0

O24

VCC_ FLSH

SPICSZ1

Serial data output to the external SPI device or devices. This pin sends

address and control information as well as data when programming

SPIDOUT

C5

O24

SPICLK

MAIN VIDEO DATA AND CONTROL

DMD park control (active low) is set high to enable typical operation.

Establish this setting prior to releasing RESET, or within 500 µs after

releasing RESET. It should be set low to a minimum of 500 µs before any

power is to be removed from the DLPC2607 (hysteresis buffer).

PARK

B8

VCC_ INTF

I3

Async

LED enable (active high input). A logic low on this signal forces

LED_ENABLE

DBIC_CSZ

SCL

A11

B10

A10

VCC_ INTF

I3

Async

SCL

N/A

LEDDRV_ON low and LED_SEL(1:0) = b00. These signals are enabled 100

ms after LED_ENABLE transitions from low to high (hysteresis buffer).

Unused/reserved: Pull up to VCC_INTF.

I²C clock (hysteresis buffer) bidirectional, open-drain signal. An external

pullup is required. No I²C activity is permitted for a minimum of 100 ms after

PARK and RESET are set high.

B38

I²C data (hysteresis buffer) bidirectional, open-drain signal. An external

pullup is required.

SDA

C10

VCC_ INTF

B38

SCL

(1) Each device connected to the serial peripheral interface (SPI) bus must be operated off VCC_FLSH

(2) Each device connected to the SPI bus must be operated off VCC_FLSH

5

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

(1)

Pin Functions

(continued)

I/O

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

General purpose I/O 4 (hysteresis buffer). Primary usage is to indicate when

auto-initialization is complete (also referred to as INIT-DONE, which is when

GPIO4 transitions high then low following release of RESET) and to flag a

detected error condition in the form of a logic high, pulsed Interrupt flag

subsequent to INIT-DONE.

GPIO4_INTF

C9

VCC_ INTF

B34

Async

General purpose I/O 5 (hysteresis buffer). For applications that use focus

motor control with a sensor, this pin is an input that is connected to the motor

position sensor. For applications that use non-focus motor control with a

sensor, configure this pin with an output at logic 0 and left unconnected.

GPIO5_INTF

B9

B34

MAIN VIDEO DATA AND CONTROL

PARALLEL RGB MODE

BT.656 I/F MODE

(3)

PCLK (Hysteresis)

PDM_CVS_TE

VSYNC_WE

HSYNC_CS

DATEN_CMD

PDATA[0]

D13

H15

H14

H13

G15

G14

G13

F15

F14

F13

E15

E14

E13

D15

D14

C15

C14

C13

B15

B14

A15

A14

B13

A13

C12

B12

A12

C11

B11

VCC_ INTF

I3

B34

I3

N/A

ASYNC

PCLK

Pixel clock

(4)

(5)

Parallel data mask

Unused

Unused⁽⁵⁾

(6)

Vsync

(6)

(5)

Hsync

Unused

(6)

(5)

Data valid

(7)

Data

Data0

Data1

Data2

Data3

Data4

Data5

Data6

Data7

(7)

PDATA[1]

Data

(7)

PDATA[2]

Data

(7)

PDATA[3]

Data

(7)

PDATA[4]

Data

(7)

PDATA[5]

Data

(7)

PDATA[6]

Data

(7)

PDATA[7]

Data

(7)

(5)

PDATA[8]

Data

Unused

(7)

PDATA[9]

Data

(7)

PDATA[10]

PDATA[11]

PDATA[12]

PDATA[13]

PDATA[14]

PDATA[15]

PDATA[16]

PDATA[17]

PDATA[18]

PDATA[19]

PDATA[20]

PDATA[21]

PDATA[22]

PDATA[23]

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

(7)

Data

Unused⁽⁵⁾

(7)

(5)

Data

Unused

(3) Pixel clock capture edge is software programmable.

(4) Data mask is optional for parallel bus operation. If unused, pull to ground through a resistor.

(5) Pull unused inputs to ground through an external resistor.

(6) VSYNC, HSYNC, and data valid polarity is software programmable.

(7) PDATA(23:0) bus mapping is pixel format and source mode dependent.

6

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

(1)

Pin Functions

(continued)

I/O

CLOCK SYSTEM

DESCRIPTION

NAME

DMD INTERFACE

DMD_D0

NO.

POWER

TYPE

M15

N14

M14

N15

P13

P14

P15

R15

R12

N11

P11

R11

N10

P10

R10

N13

R13

DMD_DCLK

DMD Data Pins. DMD Data pins are double data rate (DDR) signals that are

clocked on both edges of DMD_DCLK.

DMD_D1

All 15 DMD data signals are use to interface to the WVGA and VGA DMDs;

however, only 12 of the 15 are used to interface to an nHD DMD.

The standard nHD interconnect is to utilize pins DMD_D(11:0). However,

DMD_D(14:3) must be used to interface to the nHD DMD when the I²C

programmable option to reverse the bit-order of the DMD interface pins is

selected (DMD Bus Swap Control, I²C: 0xA7).

DMD_D2

DMD_D3

DMD_D4

DMD_D5

DMD_D6

DMD_D7

DMD_D8

DMD_D9

DMD_D10

DMD_D11

DMD_D12

DMD_D13

DMD_D14

DMD_DCLK

DMD_LOADB

VCC18

O58

N/A

DMD Data Clock (DDR)

DMD_DCLK

DMD Data Load Signal (active low). This signal requires an external pullup to

VCC18.

DMD_SCTRL

R14

P12

L13

K13

M13

DMD_DCLK

DMD Data Serial Control Signal

DMD Data Toggle Rate Control

DMD_TRC

DMD_DAD_BUS

DMD_DAD_STRB

DMD_DAD_OEZ

DMD_SAC_CLK DMD DAD Bus Data

DMD_SAC_CLK DMD DAD Bus Strobe

Async

DMD Reset Driver Output Enable (active low). To properly park the DMD,

this signal requires a 30-kΩ to 100-kΩ external pullup resistor connected to

VCC18.

DMD_SAC_BUS

DMD_SAC_CLK

L15

L14

DMD_SAC_CLK DMD SAC Bus Data

N/A DMD SAC Bus Clock

7

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

(1)

Pin Functions

(continued)

I/O

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

SDRAM INTERFACE

MEM0_CLK_P

MEM0_CLK_N

MEM0_A0

D1

E1

P1

R3

R1

R2

A1

B1

A2

B2

D2

A3

P2

B3

D3

M3

P3

P4

R4

R5

J3

O74

N/A

mDDR memory, Differential Memory Clock

mDDR memory, Multiplexed Row, and Column Address

mDDR memory, Bank Select

MEM0_A1

MEM0_A2

MEM0_A3

MEM0_A4

MEM0_A5

MEM0_A6

MEM0_A7

MEM0_A8

MEM0_A9

O64

MEM_CLK

MEM0_A10

MEM0_A11

MEM0_A12

MEM0_BA0

MEM0_BA1

MEM0_RASZ

MEM0_CASZ

MEM0_WEZ

MEM0_CSZ

MEM0_CKE

MEM0_LDQS

MEM0_LDM

MEM0_DQ0

MEM0_DQ1

MEM0_DQ2

MEM0_DQ3

MEM0_DQ4

MEM0_DQ5

MEM0_DQ6

MEM0_DQ7

MEM0_UDQS

MEM0_UDM

MEM0_DQ8

MEM0_DQ9

MEM0_DQ10

MEM0_DQ11

MEM0_DQ12

MEM0_DQ13

MEM0_DQ14

MEM0_DQ15

mDDR memory, Row Address Strobe (active low)

mDDR memory, Column Address Strobe (active low)

mDDR memory, Write Enable (active low)

mDDR memory, Chip Select (active low)

VCC18

C1

J2

mDDR memory, Clock Enable (active high)

mDDR memory, Lower Byte, R/W Data Strobe

mDDR memory, Lower Byte, Write Data Mask

B64

O64

N/A

J1

MEM0_LDQS

N1

M2

M1

L3

B64

MEM0_LDQS

mDDR memory, Lower Byte, Bidirectional R/W Data

L2

K2

L1

K1

G1

H1

H2

G2

H3

F3

F1

E2

F2

E3

B64

O64

N/A

mDDR memory, Upper Byte, R/W Data Strobe

mDDR memory, Upper Byte, Write Data Mask

MEM0_UDQS

B64

MEM0_UDQS

mDDR memory, Upper Byte, Bidirectional R/W Data

8

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

(1)

Pin Functions

(continued)

I/O

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

O14

LED DRIVER INTERFACE

General-purpose I/O 1 (output only). If the DLPA1000 is not used, then this

output must be used as the red LED PWM signal used to control the LED

current.⁽⁸⁾If the DLPA1000 is used, then this output can be used as a

general purpose output controlled by the WPC processor.

GPIO1_RPWM

GPIO2_GPWM

N8

P9

Async

General-purpose I/O 2 (output only). If the DLPA1000 is not used, then this

output must be used as the green LED PWM signal used to control the LED

current.⁽⁸⁾If the DLPA1000 is used, then this output can be used as a

general purpose output controlled by the WPC processor.

O14

General-purpose I/O 3 (output only). If the DLPA1000 is not used, then this

output must be used as the blue LED PWM signal used to control the LED

current.⁽⁸⁾If the DLPA1000 is used, then this output can be used as a

general-purpose output controlled by the WPC processor.

GPIO3_BPWM

LED_SEL_0

R8

R6

O14

Async

LED enable SELECT. Controlled by programmable DMD sequence timing

(hysteresis buffer).

LED_SEL(1:0)

Selected LED

None

00

01

10

11

VCC18

Red

Green

LED_SEL_1

N6

O14

Async

Blue

These outputs should be input directly to the DLPA1000 if used. If the

DLPA1000 is not used, then a decode circuit is required to decode the

selected LED enable.

LED driver enable. Active-high output control to external LED driver logic

(master enable). It is driven high 100 ms after LED_ENABLE is driven high

and driven low immediately when either LED_ENABLE or PARK is driven

low.

LEDDRV_ON

P7

O14

Async

DMD power regulator enable (active high). This is an active-high output that

should be used to control DMD V_OFFSET, V_BIAS, and V_RESETvoltages.

DMD_PWR_EN is driven high when the PARK input signal is set high.

However, DMD_PWR_EN is held high for 500 µs after the PARK input signal

is set low before it is driven low. TI recommends a weak external pulldown

resistor to keep this signal at a known state during power-up reset.

DMD_PWR_EN

K14

WHITE POINT CORRECTION LIGHT SENSOR I/F

Successive approximation ADC comparator output (DLPC2607 input).

Assumes a successive approximation ADC is implemented with either a light

sensor or thermocouple or both feeding one input of an external comparator

and the other side of the comparator driven from the CMP_PWM pin of the

ASIC. If this function is not used, pull it down to ground (hysteresis buffer).

CMP_OUT

A6

I1

Async

Successive approximation comparator pulse-width modulation input.

Supplies a PWM signal to drive the successive approximation ADC

Comparator used in light-to-voltage light sensor applications. If this function

is not used, leave it unconnected.

VCC_ 18

CMP_PWM

B7

P5

O14

Async

Power control signal for the WPC light sensor and other analog support

circuits using the DLPC2607 ADC. Alternately, it provides general purpose

I/O to the WPC microprocessor internal to the DLPC2607 device. If not used,

leave it unconnected (hysteresis buffer).

GPIO0_CMPPWR

B14

I3

Manufacturing test enable signal. Connect directly to ground on the PCB for

typical operation. Includes weak internal pulldown.

HWTEST_EN

JTAGTDI

A9

P6

VCC _INTF

VCC _18

N/A

JTAG, serial data in. Includes weak internal pullup. (When JTAGRSTZ is

held low, this input can be used as ICP/ WPC debug port RXD.)

JTAGTCK

I1

JTAGTCK

JTAGTMS

JTAGTDO

N5

N7

R7

N/A

JTAG, serial data clock. Includes weak internal pullup.

JTAG, test mode select. Includes weak internal pullup.

JTAG, serial data out

JTAGTCK

O14

I1

JTAG, RESET (active low). Includes weak internal pullup. This signal must

be tied to ground, through an external ≤15-kΩ resistor, for typical operation.

JTAGRSTZ

P8

ASYNC

(8) The DLPA1000 is not available for initial DLPC2607 design applications. When the DLPA1000 is not used, all LED PWM signals are

forced high when LEDDRV_ON = 0, software LED control is disabled, or the sequence stops.

9

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

(1)

Pin Functions

(continued)

I/O

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

TEST AND DEBUG INTERFACES

Test pin 0 – Sampled as an input test mode selection control upon release of

RESET, and then driven as an output. Includes weak internal pulldown.⁽⁹⁾

Normal use: Reserved for test output (ICP/ WPC debug port TXD). Leave

open or unconnected for typical use.

Alternative use: If focus motor control is used, use this pin as the motor

driver chip enable. Do not apply an external pullup to this pin to avoid putting

the DLPC2607 device in a test mode.

TSTPT_0

TSTPT_1

TSTPT_2

TSTPT_3

B6

A8

C7

B5

VCC18

B18

Async

Test pin 1 – Sampled as an input test mode selection control upon release of

RESET, and then driven as an output. Includes weak internal pulldown.⁽⁹⁾

Normal use: Reserved for test output. Leave open or unconnected for typical

use.

Alternative use: If focus motor control is used, use this pin as the motor

driver data bit1 (LSB). Do not apply an external pullup to this pin to avoid

putting the DLPC2607 device in a test mode.

VCC18

B18

Test pin 2 – Sampled as an input test mode selection control upon release of

RESET, and then driven as an output. Includes weak internal pulldown.⁽⁹⁾

Normal use: Reserved for test output. Leave open or unconnected for typical

use.

Alternative use: If focus motor control is used, use this pin as the motor

driver data bit2. Do not apply an external pullup to this pin to avoid putting

the DLPC2607 device in a test mode.

Test Pin 3 – Sampled as an input test mode selection control upon release of

RESET, and then driven as an output. Includes weak internal pulldown.⁽⁹⁾

Normal use: Reserved for test output. Leave open or unconnected for typical

use.

Alternative use: If focus motor control is used, use this pin as the motor

driver motor driver data bit3. Do not apply an external pullup to this pin to

avoid putting the DLPC2607 device in a test mode.

Test pin 4 – Sampled as an input test mode selection control upon release of

RESET, and then driven as an output. Includes weak internal pulldown.⁽⁹⁾

Normal use: Reserved for test output. Leave open or unconnected for typical

use.

Alternative use: If focus motor control is used, use this pin as the motor

driver data bit4 (MSB). Do not apply an external pullup to this pin to avoid

putting the DLPC2607 device in a test mode.

TSTPT_4

A7

VCC18

B18

Async

(9)

(10)

Without External Pullup

With External Pullup

Disables auto-initialization and

facilitates flash programming via

I²C of a blank flash

Enables auto-initialization from flash

Test pin 5 – Sampled as an input test mode selection control upon release of

RESET and then driven as an output. Includes weak internal pulldown.⁽⁹⁾

Normal use: Reserved for test output. Leave open or unconnected for typical

use.

TSTPT_5

C8

VCC18

B18

Async

Alternative use: Not yet defined. Do not apply an external pullup to this pin to

avoid putting the DLPC2607 device in a test mode.

Test pin 6 and PLL REFCLK frequency selection – Sampled as an input test

mode selection control upon release of RESET and then driven as an output.

Includes a weak internal pulldown.⁽⁹⁾

Normal use: Reserved for test output. Leave open or unconnected for typical

use.

Alternative use: Not yet defined.

This pin is sampled upon de-assertion of RESTZ to determine REFCLK

frequency selection. DLPC2607 I²C address is set corresponding to the

sampled input value as follows:

TSTPT_6

N9

VCC18

B18

Async

(9)

(10)

Without External Pullup

With External Pullup

PLL assumes REFCLK = 8.33

MHz

PLL assumes REFCLK = 16.67 MHz

(9) If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor,

then this I/O can be left open or unconnected for typical operation. If operation does not call for an external pullup, but there is external

logic that might overcome the weak internal pulldown resistor, then TI recommends an external pulldown resistor to ensure a logic low.

(10) External pullup resistor must be 15 kΩ or less.

10

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

(1)

Pin Functions

(continued)

I/O

CLOCK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

Test pin 7 and I²C address selection – Sampled as an input test mode

selection control upon release of RESET, and then driven as an output.

Includes weak internal pulldown.

Normal use: Reserved for test output. Leave open or unconnected for typical

use.

Alternative use: Not yet defined.

This pin is sampled upon deassertion of RESET to determine I²C address

selection. DLPC2607 I²C address is set corresponding to the sampled input

value as follows:

TSTPT_7

R9

VCC18

B18

Async

(9)

(10)

Without External Pullup

With External Pullup

I²C slave Write Address = x36

I²C slave Read Address = x37

I²C slave Write Address = x3A

I²C slave Read Address = x3B

POWER AND GROUND⁽¹¹⁾

D5, D9,

F4, F12,

VDD10

J4, J12,

M6, M8,

M11

1-V core logic power supply

VDD_PLL

H12

1-V power supply for the internal PLL

C4, D8,

E4, G3,

K3, K12,

L4, M5,

M9,

1.8-V power supply for all I/O other than the host, video interface, and SPI

flash buses

VCC18

M12, N4,

N12

VCC_FLSH

VCC_INTF

D6

1.8-V, 2.5-V, or 3.3-V power supply for SPI flash bus I/O

1.8-V, 2.5-V, or 3.3-V power supply for all I/Os on the host or video interface

(includes I²C, PDATA, video syncs, PARK, and LED_ENABLE pins)

D11,

E12

D4, D7,

D10,

D12, G4,

G12, H4,

K4, L12,

M4, M7,

M10

GND

Common ground

Analog ground return for the PLL (This must be connected to the common

ground GND through a ferrite.)

RTN_PLL

Reserved

J13

C2, C3,

N2, N3

No connects. Other signals can be routed through the ball on these pins

(versus going around them) to ease routing if desired

(11) 134 total signal I/O pins, 38 total power or ground pins, and 4 total reserved pins

11

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

MIN

–0.5

–30

MAX

1.32

2.75

3.6

UNIT

V_DD10

VDD_PLL

V_CC18

Voltage⁽²⁾

V

VCC_FLSH

V_{CC_INTF}

3.6

(3)

V_I1.8 V, 2.5 V, 3.3 V

3.6

T_J

Operating junction temperature

Operating ambient temperature

Storage temperature

105

85

ºC

°C

(4) (5)

T_A

–30

T_stg

–40

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND and are at the device not at the power supply.

(3) Applies to external input and bidirectional buffers.

(4) TI strongly recommends I/O simulations (using IBIS models) for operation near the extremes of the supported ambient operating

temperature range to ensure that the PCB design provides acceptable signal integrity.

(5) The operating ambient temperature range assumes zero forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value

at zero forced air flow (R_θJAat 0 m/s), a JEDEC JESD51 standard test card and environment, along with minimum and maximum

estimated power dissipation across process, voltage, and temperature. Thermal conditions vary by application, which impacts R_θJA

.

Thus, maximum operating ambient temperature varies by application.

(a) T_{A_min}= T_{J_min}– (P_{D_min}× R_θJA) = –30°C – (0.0 W × 64.96°C/W) = –30°C

(b) T_{A_min}= T_{J_min}– (P_{D_min}× R_θJA) = 105°C – (0.3 W × 64.96°C/W) = 85°C

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0.95

1.71

2.375

3.135

1.71

2.375

3.135

–0.3

0

NOM

1

MAX UNIT

VDD10

1-V supply voltage, core logic

1.05

V

µs

VDD_PLL

VCC18

Analog voltage for PLL

1

1.8-V supply voltage (for all non-flash and host interface signals)

1.8-V LVCMOS

Configuration and control I/O supply voltage

1.8

2.5

3.3

1.8

2.5

3.3

1.89

VCC_FLSH

2.5-V LVCMOS

2.625

(variable)

3.3-V LVCMOS

1.8-V LVCMOS

3.465

1.89

VCC_INTF Pixel interface supply voltage (variable)

2.5-V LVCMOS

3.3-V LVCMOS

2.625

3.465

V_I

Input voltage

VCCIO⁽¹⁾+ 0.3

VCCIO⁽¹⁾

V_O

Output voltage

t_RAMP

Power supply ramp time

10

(1) VCCIO represents the actual supply voltage applied to the corresponding I/O.

12

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

6.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)

DLPC2607

THERMAL METRIC⁽¹⁾

ZVB (NFBGA)

176 PINS

19.52

UNIT

R_θJC

R_θJA

Junction-to-case thermal resistance

ºC/W

Junction-to-air thermal resistance (with no forced airflow)

64.96

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

6.5 Typical Current and Power Dissipation

over operating free-air temperature range (unless otherwise noted)

WVGA APPLICATIONS

nHD APPLICATIONS

TYPICAL

VOLTAGE (V)

SUPPLY

TYPICAL CURRENT

TYPICAL POWER

(mW)

TYPICAL CURRENT

TYPICAL POWER

(mW)

(mA)

(1) (2) (3)

I/F Sleep Mode Disabled

VCC_INTF

VCC_FLSH⁽⁴⁾

VCC18

1.8

2.5

1.8

1

0

0.1

0

0.1

0

28.2

2.8

39

50.8

2.8

22.7

2.8

37.7

40.9

2.8

VDD_PLL

VDD10

1

39.0

92.7

37.7

81.5

Total

(1) (2) (3)

I/F Sleep Mode Enabled

VCC_INTF

VCC_FLSH

VCC18⁽⁴⁾

1.8

2.5

1.8

1

0

0.1

0

0.1

0

27

48.6

2.8

22.5

2.8

29.3

40.4

2.8

VDD_PLL

2.8

30.6

VDD10

1

30.6

82.1

29.3

72.6

Total

(1) I/F sleep is a programmable parameter that can be set to save power in free-run, sequencer mode when displaying still images on the

DMD. When I/F sleep is enabled, any images applied to the input bus to the DLPC2607 device are ignored.

(2) Power for both I/F sleep mode disabled and I/F sleep mode enabled was measured while transferring a full 864 × 480 landscape image

at periodic 30 frames per second. The image was a 12 × 6 color checkerboard.

(3) All measurements were taken on a TI internal reference design board at 25°C ambient.

(4) VCC_FLSH power was 0 at the time of the measurement because flash accesses are limited when the ASIC is being configured.

13

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

6.6 I/O Characteristics

Voltage and current characteristics for each I/O type signal listed previously in the DLPC2607 table are summarized in I/O

Characteristics. All inputs and outputs are LVCMOS.⁽¹⁾

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

VCCIO

(NOM)

(V)

V_IL

(min)

(V)

V_IH

(MAX)

(V)

I_IN

(MAX)

(µA)

V_OH

(MIN)

(V)

V_OL

(MAX)

(V)

I_OH

(MIN)

(mA)

I_OL

(MIN)

(mA)

ITS

(MAX)

(µA)

V_IL(MAX)

(V)

V_IH(MIN)

(V)

I/O TYPE

DESCRIPTION

I1

Input (STD)

1.8

2.5

3.3

1.8

2.5

3.3

1.8

–0.3

0.5

0.7

0.8

0.5

0.7

0.8

0.5

1.2

1.7

2

3

±10

I2

I3

Input (FLSH)

3.6

3

1.2

1.7

2

Input (INTF)

3.6

3

I4

Input (REFCLK)

1.2

1× output (STD/

REFCLK)

O14

1.8

1.25

0.4

2.58

2.89

±10

1.8

2.5

3.3

1.8

1.25

1.7

0.4

0.7

2.58

6.2

2.89

6.3

±10

O24

1× output (FLSH)

2.4

0.4

5.29

6.41

4

9.38

5.78

4

O58

2× output (DMD)

1× output (MEM)

1.25

1.53

0.4

O64⁽¹⁰⁾

0.19

1× output (MEM

DIFF)⁽¹¹⁾

O74⁽¹⁰⁾

1.8

1.53

1.25

0.19

0.4

4

±10

1× bidirectional

(STD) output

B14

–0.3

0.5

1.2

3

±10

2.58

5.15

2.89

5.72

2× bidirectional

(STD) output

B18⁽¹²⁾

0.4

1.8

2.5

3.3

1.8

2.5

3.3

–0.3

0.5

0.7

0.8

0.5

0.7

0.8

1.2

1.7

2

3

±10

1.25

1.7

0.4

0.7

0.4

0.7

0.4

2.58

6.2

2.89

6.3

±10

1× bidirectional

(INTF) output

B34

3.6

3

2.4

5.29

5.15

12.4

10.57

9.38

5.72

12.7

18.68

1.2

1.7

2.0

2.4

2× bidirectional

(INTF) output

B38

3.6

1.7

1.25

1× bidirectional

(MEM) output

B64⁽¹⁰⁾

1.8

–0.3

0.57

1.19

2.2

±10

1.53

0.19

4

±10

(1) Pin PLL_REFCLK_I is a crystal oscillator input pin and is not tested during VIH/VIL testing.

(2) VIL(min) is the absolute minimum voltage that can safely be applied to each corresponding pin.

(3) VOH(max) is the maximum voltage that can safely be applied to each corresponding pin.

(4) Input leakage current with no internal pullup or pulldown. V_IN= 0 or V_IN= VCCIO where VCCIO = I/O supply voltage

(5) I_OH= – rated current

(6) I_OL= + rated current

(7) V_OH= VOH(max)

(8) V_OL= VOL(max)

(9) Tri-state output leakage current. V_IN= 0 or V_IN= VCCIO where VCCIO = I/O supply voltage

(10) O64, O74, and B64 buffers are tested to only 100 µA for IOH/IOL due to tester limitations.

(11) The O74 mDDR differential clock (CK) output is simply a pair of single-ended drivers driven by a true and complementary signal.

(12) B18 buffers are not tested for I_IH

.

6.7 Internal Pullup and Pulldown Characteristics

The resistance depends on the supply voltage level applied to the I/O.⁽¹⁾

(2)

VCCIO (V)

3.3

MIN

N/A

33

MAX

N/A

UNIT

Weak pullup resistance

2.5

89

kΩ

1.8

50.3

17.8

37

157.3

79.6

109

3.3

Weak pulldown resistance

2.5

1.8

51.8

184.1

(1) The description column of identifies whether the corresponding signal includes an internal pullup or pulldown resistor.

(2) Due to tester limitations, only the 1.8-V pullup resistors are measured and no pulldown resistors are measured.

14

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

6.8 Parallel I/F Frame Timing Requirements

MIN

MAX

UNIT

t_{p_vsw}

t_{p_vbp}

Pulse duration – VSYNC_WE high

50% reference points

1

lines

Vertical back porch – Time from the leading edge of VSYNC_WE

to the leading edge HSYNC_CS for the first active line.⁽¹⁾

2

lines

Vertical front porch – Time from the leading edge of the

HSYNC_CS following the last active line in a frame to the leading

edge of VSYNC_WE.⁽¹⁾

t_{p_vfp}

50% reference points

1

lines

Total vertical blanking – Time from the leading edge of HSYNC_CS

following the last active line of one frame to the leading edge of

HSYNC_CS for the first active line in the next frame. This is equal

to the sum of Vertical back porch (t_{p_vbp}) + Vertical front porch

(t_{p_vfp}).

t_{p_tvb}

12

lines

t_{p_hsw}

t_{p_hbp}

t_{p_hfp}

t_{p_thh}

Pulse duration – HSYNC_CS high

50% reference points

4

128

PCLKs

Horizontal back porch – Time from rising edge of HSYNC_CS to

rising edge of DATAEN_CMD.

Horizontal front porch – Time from falling edge of DATAEN_CMD

to rising edge of HSYNC_CS.

50% reference points

8

PCLKs

Total horizontal blanking – Sum of horizontal front and back

porches

⁽²⁾PCLKs

(1) The programmable parameter vertical sync line delay (I²C: 0x23) must be set such that:

6 – Vertical front porch (t_{p_vfp})’ (min 0) ≤ Vertical sync line delay ≤ Vertical back porch (tp_{_vbp}) – 2 (max 15). The default value for vertical

sync line delay is set to 5; thus, only a vertical back porch less than 7 requires potential action.

(2) Total horizontal blanking is driven by the max line rate for a given source, which is a function of resolution and orientation. See Parallel

I/F Maximum Parallel Interface Horizontal Line Rate for max line rate for each source and display combination. t_{p_thb}= Roundup [(1000

x ƒ_clock)/ LR] – APPL where ƒ_clock= Pixel clock rate in MHz, LR = Line rate in kHz, and the number of active pixels per (horizontal) line is

APPL. If t_{p_thb}is calculated to be less than t_{p_hbp}+ t_{p_hfp}, then the pixel clock rate is too low, or the line rate is too high, and one or both

must be adjusted.

6.9 Parallel I/F General Timing Requirements

MIN

MAX

UNIT

MHz

ns

ƒ_clock

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

Clock frequency, PCLK

1

33.5

Clock period, PCLK

50% reference points

Max ƒ_clock

29.85

1000

(1)

Clock jitter, PCLK

Pulse-duration low, PCLK

Pulse-duration high, PCLK

Setup time – HSYNC_CS, DATEN_CMD, PDATA (23:0)

50% reference points

10

ns

t_{p_wl}

t_{p_su}

50% reference points

3

ns

(2)

valid before the active edge of PCLK

Hold time – HSYNC_CS, DATEN_CMD, PDATA (23:0)

valid after the active edge of PCLK

t_{p_h}

t_t

50% reference points

3

ns

(2)

Transition time – All signals

20% to 80% reference points

0.2

4

(1) Clock jitter (in ns) should be calculated using this formula: Jitter = (1 / ƒ_clock– 28.35 ns). Setup and hold times must be met during clock

jitter.

(2) See Figure 2.

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6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate

LANDSCAPE FORMAT

PORTRAIT FORMAT

PARALLEL BUS

DMD

RESOLUTION (H×V)

MAX LINE RATE

(kHz)

RESOLUTION (HxV)

MAX LINE RATE

(kHz)

SOURCE

(1)

(2)

NSTC

720 × 240

17

20

17

25

30

34

32

39

32

48

50

44

42

40

37

Not supported

N/A

22

27

42

45

51

53

56

N/A

42

52

79

74

66

(1)

(2)

PAL

720 × 288

(2)

QVGA

320 × 240

240 × 320

(2)

QWVGA

427 × 240

240 × 427

(2)

nHD

640 × 360

360 × 640

(2)

3:2 VGA

640 × 430

430 × 640

(2)

4:3 VGA

640 × 480

480 × 640

0.3 WVGA and

0.24 VGA diamond

(2)

WVGA-720

WVGA-752

WVGA-800

WVGA-852

WVGA-853

WVGA-854

WVGA-864

720 × 480

480 × 720

(2)

752 × 480

480 × 752

(2)

800 × 480

480 × 800

(2)

852 × 480

480 × 852

(2)

853 × 480

480 × 853

(2)

854 × 480

480 × 854

(2)

864 × 480

480 × 864

(1)

(2)

NSTC

720 × 240

Not supported

(1)

(2)

PAL

720 × 288

(2)

QVGA

320 × 240

427 × 240

640 × 360

240 × 320

(2)

QWVGA

240 × 427

(2)

nHD

360 × 640

(2)

3:2 VGA

640 × 430

430 × 640

(2)

4:3 VGA

640 × 480

480 × 640

0.2 nHD Manhattan

(2)

WVGA-720

WVGA-752

WVGA-800

WVGA-852

WVGA-853

WVGA-854

WVGA-864

720 × 480

480 × 720

(2)

752 × 480

480 × 752

(2)

800 × 480

480 × 800

(2)

852 × 480

480 × 852

(2)

853 × 480

480 × 853

(2)

854 × 480

480 × 854

(2)

864 × 480

480 × 864

(1) NTSC and PAL are assumed to be interlaced sources

(2) Not supported for 100- to 120-Hz operation

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6.11 BT.656 I/F General Timing Requirements

The DLPC2607 ASIC input interface supports the industry standard BT.656 parallel video interface. See the appropriate ITU-

R BT.656 specification for detailed interface timing requirements. Map the BT.656 data bits to the DLPC2607 PDATA bus as

(1)

shown in Figure 3.

MIN

MAX UNIT

ƒ_clock

t_{p_clkper}

t_{p_clkjit}

t_{p_wh}

Clock frequency, PCLK

Clock period, PCLK

Clock jitter, PCLK⁽²⁾

1

33.5

MHz

ns

50% reference points

Maximum ƒ_clock

29.85

1000

(2)

Pulse duration low, PCLK

Pulse duration high, PCLK

50% reference points

10

ns

t_{p_wl}

Setup time – HSYNC, DATEN, PDATA(23:0) valid

before the active edge of PCLK

t_{p_su}

50% reference points

3

ns

Hold time – HSYNC, DATEN, PDATA(23:0) valid

after the active edge of PCLK

t_{p_h}

t_t

50% reference points

3

ns

Transition time – All signals

20% to 80% reference points

0.2

4

(1) The BT.656 I/F accepts 8-bit per color, 4:2:2 YCb/Cr data encoded per the industry standard though PDATA(7:0) on the active edge of

PCLK (that is, programmable) as shown in Figure 2.

(2) Clock jitter should be calculated using this formula: Jitter = (1 / ƒ_clock– 28.35 ns). Setup and hold times must be met during clock jitter.

6.12 100- to 120-Hz Operational Limitations

The table below assumes that a front-end device ahead of the DLPC2607 device converts all 3-D sources to the 3-D format

defined previously and provides any needed left-eye or right-eye selection control directly to the 3-D glasses (that is, the

DLPC2607 device does not control the glasses). The DLPC2607 device includes a double buffer frame memory, which

causes the displayed image to be delayed one frame relative to its input. This requires left or right eye-frame shutter control

to be inverted prior to being sent to the glasses.

MIN FRAME NOM FRAME MAX FRAME

MIN TVB

(tp_tvb)

(LINES)

MAX LINE

RATE

(kHz)

MIN LINE

RATE

(kHz)

(1)

MIN CLOCK

RATE

RESOLUTION

(APPL x ALPF)

SOURCE

RATE

(Hz)

RATE

(Hz)

RATE

(Hz)

(MHz)

(2)

nHD

640 × 360

427 × 240

320 × 240

640 × 360

427 × 240

320 × 240

99

100

120

101

12

48

32

48

32

(1)

(2)

WQVGA

QVGA

nHD

99

101

118.8

121.2

WQVGA

QVGA

(1) Use the following equation to determine the minimum line rate for a given application. The application cannot be supported if the

calculated minimum line rate exceeds the maximum line rate defined elsewhere in this table;

Line_Rate_min (kHz) = Frame_Rate_max (Hz) × [ALPF + TVB] /1000

Where: TVB = Total vertical blanking (in lines)

ALPF = Active lines per frame

Frame_Rate_max = Max frame rate including all expected wander

(2) The following equation should be used to determine the minimum pixel clock rate for a given application. The application cannot be

supported if the calculated minimum pixel clock rate exceeds the max pixel clock rate defined in Parallel I/F General Timing

Requirements.

Pixel_Clock_min (MHz) = Line_Rate_max (kHz) × (APPL + 12) / 1000

Where: APPL = Active pixels per line

Line_Rate_max = Max line rate including all expected wander

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6.13 Flash Interface Timing Requirements

The DLPC2607 ASIC flash memory interface consists of a SPI flash serial interface at 33.3 MHz (nominal).

(1) (2)

MIN

MAX

UNIT

MHz

ns

ƒ_clock

t_{p_clkper}Clock period, SPI_CLK

Clock frequency, SPI_CLK⁽³⁾

33.3266

29.994

10

33.34

50% reference points

20% to 80% reference points

50% reference points

30.006

t_{p_wh}

t_{p_wl}

t_t

Pulse duration low, SPI_CLK

ns

Pulse duration high, SPI_CLK

10

ns

Transition time – all signals

0.2

4

1

ns

t_{p_su}

t_{p_h}

Setup time – SPI_DIN valid before SPI_CLK falling edge

Hold time – SPI_DIN valid after SPI_CLK falling edge

10

ns

0

ns

t_{p_clqv}

SP_ICLK clock low to output valid time – SPIDOUT and

SPI_CSZ

ns

t_{p_clqx}

SPI_CLK clock low output hold time – SPI_DOUT and

SPI_CSZ

50% reference points

–1

(1) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC2607 device

does transmit data on the falling edge, but it captures data on the falling edge rather than the rising edge. This provides support for SPI

devices with long clock-to-Q timing. The DLPC2607 device hold capture timing is set to facilitate reliable operation with standard

external SPI protocol devices.

(2) With the above output timing, the DLPC2607 device provides the external SPI device 14-ns input set-up and 14-ns input hold relative to

the rising edge of SPI_CLK.

(3) This range includes the 200 ppm of the external oscillator (but no jitter).

6.14 DMD Interface Timing Requirements

The DLPC2607 ASIC DMD interface consists of a 76.19-MHz (nominal) DDR output-only interface with LVCMOS signaling.

(1)

(see

)

MIN

76.175

13.122

6.2

MAX UNIT

ƒ_clock

t_{p_clkper}

t_{p_wh}

t_{p_wl}

t_t

Clock frequency, DMD_DCLK and DMD_SAC_CLK⁽²⁾

Clock period, DMD_DCLK and DMD_SAC_CLK

Pulse duration low, DMD_DCLK and DMD_SAC_CLK

Pulse duration high, DMD_DCLK and DMD_SAC_CLK

Transition time – all signals

76.206

MHz

ns

50% reference points

20% to 80% reference points

13.128

ns

6.2

ns

0.3

2

ns

Output setup time – DMD_D(14:0),

t_{p_su}

DMD_SCTRL, DMD_LOADB and DMD_TRC

50% reference points

1.5

ns

relative to both rising and falling edges of DMD_DCLK^{(3) (4)}

Output hold time – DMD_D(14:0),

DMD_SCTRL,DMD_LOADB and DMD_TRC

signals relative to both rising and falling edges of

DMD_DCLK^{(3) (4)}

t_{p_h}

50% reference points

1.5

DMD data skew – DMD_D(14:0),

t_{p_d1_skew}DMD_SCTRL, DMD_LOADB, and DMD_TRC

50% reference points

0.2

ns

signals relative to each other⁽⁵⁾

Clock skew – DMD_DCLK and DMD_SAC_CLK relative to each

t_{p_clk_skew}

other

DAD/SAC data skew - DMD_SAC_BUS,

t_{p_d2_skew}DMD_DRC_OEZ⁽⁶⁾, DMD_DRC_BUS,

and DMD_DRC_STRB signals relative to DMD_SAC_CLK

(1) Assumes a 30-Ω series termination for all DMD interface signals (except DAD_DMD_OEZ)

(2) This range includes the 200 ppm of the external oscillator (but no jitter).

(3) Assumes minimum DMD setup time = 1 ns and minimum DMD hold time = 1 ns

(4) Output setup and hold numbers already account for controller clock jitter. Only routing skew and DMD setup/hold must be considered in

system timing analysis.

(5) Assumes DMD data routing skew = 0.1 ns max

(6) DMD_DAD_OEZ requires a 30- to 100-kΩ external pullup resistor connected to VCC18 to achieve proper timing.

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6.15 mDDR Memory Interface Timing Requirements

The DLPC2607 controller mDDR memory interface consists of a 16-bit wide, mDDR interface (that is, LVCMOS signaling)

(1) (2) (3)

operated at 133.33 MHz (nominal). (see

)

MIN

7500

2700

–2870

MAX

UNIT

ps

t_CYCLE

t_CH

Cycle-time reference

CK high pulse width⁽⁴⁾

CK low pulse width⁽⁴⁾

DQS high pulse width⁽⁴⁾

DQS low pulse width⁽⁴⁾

ps

t_CL

ps

t_DQSH

t_DQSL

t_WAC

t_QAC

ps

CK to address and control outputs active

CK to DQS output active

2870

200

ps

t_DAC

DQS to DQ and DM output active

Input (read) DQS and DQ skew⁽⁵⁾

–1225

1225

1000

ps

t_DQSRS

ps

(1) This includes the 200 ppm of the external oscillator (but no jitter).

(2) Output setup and hold numbers already account for controller clock jitter. Only routing skew and memory setup/hold must be considered

in system timing analysis.

(3) Assumes a 30-Ω series termination on all signal lines.

(4) CK and DQS pulse duration specifications for the DLPC2607 assume it is interfacing to a 166-MHz mDDR device. Even though these

memories are only operated at 133.33 MHz, according to memory vendors, the rated t_CKspecification (that is 6 ns) can be applied to

determine minimum CK and DQS pulse duration requirements to the memory.

(5) Note that DQS must be within the t_DQSRSread data-skew window, but need not be centered.

1 Frame

t_{p_vsw}

VSYNC_WE

(This diagram assumes the VSYNC

active edge is the Rising edge)

t_{p_vbp}

t_{p_vfp}

HSYNC_CS

DATAEN_CMD

1 Line

t_{p_hsw}

HSYNC_CS

(This diagram assumes the HSYNC

active edge is the Rising edge)

t_{p_hbp}

t_{p_hfp}

DATAEN_CMD

PDATA(23/15:0)

PCLK

P

n-2

P

n-1

P0

P1

P2

P3

Pn

Figure 1. Parallel I/F Frame Timing

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t_{p_clkper}

t_{p_wh}

t_{p_wl}

PCLK

t_{p_h}

t_{p_su}

Figure 2. Parallel and BT.656 I/F General Timing

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA (7:0) of the Input Pixel data bus

Bus Assignment Mapping

Y

7

Y

6

Y

5

Y

4

Y

3

Y

2

Y

1

Y

0

n/a

Data bit mapping on the pins of the ASIC

Figure 3. DLPC2607 PDATA Bus – BT.656 I/F Mode Bit Mapping (YCrCb 4:2:2 Source)

t_clkper

SPI_CLK

t_wh

t_wl

(ASIC Output)

t_{p_su}

t_{p_h}

SPI_DIN

(ASIC Inputs)

t_{p_clqv}

SPI_DOUT, SPI_CS(1:0)

(ASIC Outputs)

t_{p_clqx}

Figure 4. Flash I/F Timing

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tp_d1_skew

DMD_D(14:0)

DMD_SCTRL

DMD_TRC

DMD_LOADB

tp_h

tp_su

DMD_DCLK

tp_wl

tp_wh

tclk_skew

DMD_SAC_CLK

tp_d2_skew

DMD_SAC_BUS

DMD_DAD_OEZ

DMD_DAD_BUS

DMD_DAD_STRB

Figure 5. DMD I/F Timing

tCYCLE

MEM0_CK_P

MEM0_CK_N

tCH

tCL

MEM0_ADDRS(12:0)

MEM0_BA(1:0)

MEM0_RASZ

MEM0_CASZ

MEM0_WEZ

MEM0_CSZ

tWAC

MEM0_CKE

Figure 6. mDRR Memory Address and Control Timing

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tCYCLE

MEM0_CK_P

MEM0_CK_N

tCH

tCL

tQAC

(tDQSCK)

tCYCLE

tDQSH

tDQSL

MEM0_xDQS

tDAC

MEM0_xDQ(7:0)

MEM0_xDQ(15:8)

tDAC

MEM0_xDM

Figure 7. mDRR Memory Write Dtat Timing

tCYCLE

MEM0_xDQS

MEM0_xDQ(first)

MEM0_xDQ(last)

tDQSH

tDQSL

tDQSRS

MEM0xDQ(7:0)

Data Valid Window

Figure 8. mDDR Memory Read Data Timing

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7 Detailed Description

7.1 Overview

The DLPC2607 is the display controller for the 0.3-WVGA, 0.24-VGA and 0.2-nHD DMDs. Both the controller

and the DMD must be used in conjunction with each other for reliable operation of the DMD. The DLPC2607

display controller provides interfaces and data/image processing functions that are optimized for small form factor

and low power display applications. Applications include pico projectors, smart projectors, screen less display,

interactive display, wearable displays and many more. In typical systems a separate applications processor is

used to provide various multimedia functionality (such as video decoder, HDMI receiver, VGA, SD card, or USB

I/F chip).

7.2 Functional Block Diagram

DLPC2607

Pixel

Data

I/F

16

Frame

Memory

Controller

Mobile

DDR

DRAM

Front End

Processing

Vector Graphics

Processing

24

DDR

DMD

Formatting

Clocks

& Resets

Display

Control

Configuration

Control

PLL

DDR

SPI

I2C

Crystal

or

Osc

LED

Driver

Serial

Flash

0.3 WVGA

0.2 nHD, or

0.24 VGA

DMD

Host

Controller

7.3 Feature Description

7.3.1 Parallel Bus Interface

The parallel bus interface complies with standard graphics interface protocol, which includes a vertical sync

signal (VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit

data bus (PDATA), and a pixel clock (PCLK). The user can program the polarity of both syncs and the active

edge of the clock. Figure 1 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is

optional in that the DLPC2607 device provides auto-framing parameters that can be programmed to define the

data valid window based on pixel and line counting relative to the horizontal and vertical syncs.

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Feature Description (continued)

In addition to these standard signals, an optional side-band signal (PDM_CVS_TE) is available, which allows the

user to stop the periodic frame updates without losing the displayed image. When PDM_CVS_TE is active, it acts

as a data mask and does not allow the source image to be propagated to the display. A programmable PDM

polarity parameter determines if it is active high or active low. This parameter defaults to make PDM_CVS_TE

active high. Therefore, if this function is not desired, tie it to a logic low on the PCB. PDM_CVS_TE is restricted

to change only during vertical blanking. Note that VSYNC_WE must remain active at all times (in Lock-to-VSYNC

mode) or the display sequencer stops and causes the LEDs to be shut off.

The parallel bus interface supports six data transfer formats:

•

16-bit RGB565

18-bit RGB666

18-bit 4:4:4 YCrCb666

24-bit RGB888

24-bit 4:4:4 YCrCb888

16-bit 4:2:2 YCrCb (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, …)

Figure 9 shows the required PDATA(23:0) bus mapping for these six data transfer formats.

Parallel Bus Mode œ 4:4:4 RGB and YCrCb Sources

PDATA(15:0) œ 565 Mapping to 888

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(15:0) of the Input Pixel data bus

Bus Assignment Mapping

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B4

B3

B2

B1

B0

RGB Data bit mapping on the ASIC

4:4:4 YCrCb Data bit mapping on the ASIC

PDATA(17:0) œ 666 Mapping to 888

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(17:0) of the Input Pixel data bus

Bus Assignment Mapping

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

RGB Data bit mapping on the ASIC

4:4:4 YCrCb Data bit mapping on the ASIC

Cr

5

Cr

4

Cr

3

Cr

2

Cr

1

Cr

0

Y

5

Y

4

Y

3

Y

2

Y

1

Y

0

Cb

5

Cb

4

Cb

3

Cb

2

Cb

1

Cb

0

PDATA(23:0) œ 888 Mapping

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(23:0) of the Input Pixel data bus

Bus Assignment Mapping

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

RGB Data bit mapping on the ASIC

4:4:4 YCrCb Data bit mapping on the ASIC

Cr

7

Cr

6

Cr

5

Cr

4

Cr

3

Cr

2

Cr

1

Cr

0

Y

7

Y

6

Y

5

Y

4

Y

3

Y

2

Y

1

Y

0

Cb

7

Cb

6

Cb

5

Cb

4

Cb

3

Cb

2

Cb

1

Cb

0

Parallel Bus Mode - 16-bit YCrCb 4:2:2 Source

PDATA(23:0) œ Cr/CbY880 Mapping

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDATA(23:0) of the Input Pixel data bus

Bus Assignment Mapping

Cr/

Cb

7

Cr/

Cb

6

Cr/

Cb

5

Cr/

Cb

4

Cr/

Cb

3

Cr/

Cb

2

Cr/

Cb

1

Cr/

Cb

0

Y

7

Y

6

Y

5

Y

4

Y

3

Y

2

Y

1

Y

0

n/a

Data bit mapping on the pins of the ASIC

Figure 9. PDATA Bus – Parallel I/F Mode Bit Mapping

7.3.2 100- to 120-Hz 3-D Display Operation

The DLPC2607 device supports 100- to 120-Hz 3-D display operation, but is limited to a narrow set of

configurations. 3-D operation is limited to:

•

0.2-nHD DMDs only

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DLPC2607

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ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

Feature Description (continued)

•

nHD, WQVGA and QVGA source resolutions

Parallel bus interface only (all pixel formats are supported)

Landscape source and display orientation only

Non-interlaced video-graphics only

100-Hz ±1% or 120-Hz ±1% source frame rates

Unpacked, full resolution, frame sequential, 3-D format (that is each 100- or 120-Hz source frame contains a

single, full resolution, eye frame separated by VSYNCs, where an eye frame contains image data for a single

left or right eye; not both)

•

Minimum line rates that satisfy the high frame rates

To support 3-D operation, run the DLPC2607 device in Lock-to-VSYNC mode with 1× frame rate multiplication

(that is, no frame rate multiplication). Each DMD frame is displayed at the source frame rate in the order it is

received.

Because of the high frame rate of the source, the source line rate must be much higher than typical, but still

cannot exceed the rates defined in Parallel I/F Maximum Parallel Interface Horizontal Line Rate. The minimum

line rate is limited by the maximum frame rate and minimum total vertical blanking (TVB). 100- to 120-Hz

Operational Limitations provides a summary of the line rate range assuming the minimum TVB.

7.4 Programming

7.4.1 Serial Flash Interface

The DLPC2607 device uses an external SPI serial flash memory device for configuration support. The minimum

required size depends on the desired minimum number of sequences, CMT tables, and splash options while the

maximum supported is 16 Mb. Table 1 provides the list of the configuration options.

Table 1. Serial Flash Support Features by Density⁽¹⁾

QUANTITY OF FEATURES THAT CAN BE SUPPORTED

TARGET

OPTICAL TEST

SPLASH

SCREENS

STANDARD

SPLASH

SCREENS

SERIES

DATA

SECTOR

DLP DISPLAY

FLASH

DENSITY (Mb)

UNIT DATA ODM DATA

CMT TABLES PER

SEQUENCE

SEQUENCES

(3)

SECTOR

(2)

4 Mb

8 Mb

0

1

3

4

1

16

7

16 Mb

(1) All rows in this table have passed DVT at TI.

(2) Assumes individual DLP display sequences are limited to 5 KB each

(3) An equal number of CMT tables are required for each sequence (CMT tables define the DeGamma Curve). The DLPC2607 device uses

a single SPI, employing SPI mode 0 protocol, operating at a frequency of 33.3 MHz. It supports two independent SPI chip selects.

However, the primary flash must be connected to SPI chip select 0 (SPICS0) because the auto-initialization routine is always executed

from the device connected to this chip select. The auto-initialization routine executed from flash consists of the following:

(a) The DLPC2607 device first uploads the size and location of the auto-initialization routine from address range 0x0000 through 0x0007

of the serial flash memory connected to SPICS0.

(b) The DLPC2607 device then uploads the actual auto-initialization routine to its ICP program memory from the serial flash memory

connected to SPICS0.

(c) The DLPC2607 device then executes an auto-init routine, which includes uploading default control parameter values, uploading

mailbox memory contents, turning on the sequence and LEDs, and then enabling the display.

(d) Upon completion of the auto-initialization routine, the DLPC2607 signals INIT DONE with GPIO4_INTF.

The DLPC2607 device supports any flash device that is compatible with these modes of operation. However, the

DLPC2607 device does not support the Normal (slow) Read Opcode, and thus cannot automatically adapt

protocol and clock rate based on the flash’s electronic signature ID. The flash instead uses a fixed SPI clock and

assumes certain attributes of the flash have been ensured by PCB design. The DLPC2607 device also assumes

the flash supports address auto-incrementing for all read operations. Table 2 and Table 3 list the specific

instruction OpCode and timing compatibility requirements for a DLPC2607 device compatible flash.

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Table 2. SPI Flash Instruction OpCode and Timing Compatibility Requirements

SPI FLASH COMMAND

Fast READ (single output)

All others

OPCODE (hex)

0x0B

ADDRESS BYTES

DUMMY BYTES

MIN CLOCK RATE

33.3 MHz

3

1

Can vary

33.3 MHz

Table 3. SPI Flash Key Timing Parameter Compatibility Requirements

MIN

MAX

UNIT

ns

Minimum chip select high time

Minimum output hold time

Maximum output valid time

Minimum data in setup time

Minimum data in hold time

300

0

ns

9

5

ns

The DLPC2607 device does not have any specific page, block, or sector size requirements, except that

programming with the I²C interface requires the use of page mode programming. However, if the user would like

to use a portion of the serial flash for storing external data (such as calibration data) with the I²C interface, then

the minimum sector size must be considered as it drives minimum erase size. Note that use of serial flash for

storing external data may impact the number of features that can be supported.

NOTE

The DLPC2607 device does not drive the HOLD (active low hold) or WP (active low write

protect) pins on the flash device. Tie these pins to a logic high on the PCB with an

external pullup.

The DLPC2607 device supports 1.8 V, 2.5 V, or 3.3 V serial flash devices. Some suggested devices would

include the W25Q16DWSSIG or MX25U4035. If a different flash device is used, Table 4 lists the minimum

performance specifications necessary.

Table 4. Specifications of Compatible SPI Serial Flash Devices

SPI Flash Timing Parameter

Minimum Chip Select High Time

Minimum Output Hold Time

Maximum Output Valid Time

Minimum Data in Setup Time

Minimum Data in Hold Time

Minimum Clock Rate

MIN

MAX

300ns

0ns

9ns

5ns

33.3MHz

7.4.2 Serial Flash Programming

The flash can be programmed through the DLPC2607 device over I²C (for directions, see the DLPC2607

Software Programmer's Guide, DLPU013) or by driving the SPI pins of the flash directly while the DLPC2607

device I/O are tri-stated. SPICLK, SPIDOUT, and SPICZ0 I/O can be tri-stated by holding RESET in a logic-low

state while power is applied. Note that SPICSZ1 is not tri-stated by this same action.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DLPC2607 controller supports reliable operation of .3-WVGA, .24-VGA and .2-nHD DMDs and must be

always used with the DMD to provide a reliable display solution for various data and video display applications.

The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two

directions, with the primary direction being into a projection or collection optic. Each application is derived

primarily from the optical architecture of the system and the format of the data coming into the DLPC2607.

Applications of interest include accessory projectors, projectors embedded in display devices like notebooks,

laptops, tablets, and set top box. Other applications include wearable (near-eye or head mounted) displays,

interactive display and low latency gaming display.

8.2 Typical Application

Figure 10 shows a typical accessory projector application. For this application, the DLPC2607 device is

controlled by a separate control processor (typically a MSP430) and the image data is received from a TVP5151

video decoder device. For this application, the ASIC supports periodic sources only. A common application when

using DLPC2607 controller is for creating an accessory Pico projector for a smartphone, tablets or any other

display source. The DLPC2607 in the accessory Pico projector typically receives images from a host processor

or a multimedia processor.

Figure 10. Typical Standalone Projector System Block Diagram

8.2.1 System Functional Modes

The application system has two functional modes (ON/OFF) controlled by a single pin PROJ_ON:

•

When pin PROJ_ON is set high, the projector automatically powers up and an image is projected from the

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Typical Application (continued)

DMD.

•

When pin PROJ_ON is set low, the projector automatically powers down to save power.

8.2.2 Design Requirements

8.2.2.1 Reference Clock

The device requires an external reference clock to feed its internal PLL. This reference may be supplied by a

crystal or oscillator. For flexibility, the DLPC2607 device accepts either of two reference clock frequencies (see

Table 5), but both must have a maximum frequency variation of 200 ppm (including aging, temperature, and trim

component variation). When a crystal is used, the configuration requires several discrete components, as shown

in Figure 11.

PLL_REFCLK_O

PLL_REFCLK_I

CL = Crystal load capacitance (Farads)

CL1 = 2 x (CL - Cstray_pll_refclk_i)

CL2 = 2 x (CL - Cstray_pll_refclk_o)

R_FB

R_S

Where:

Cstray_pll_refclk_i = Sum of package and PCB

Crystal

stray capacitance at the crystal pin associated

with the ASIC pin pll_refclk_i.

Cstray_pll_refclk_o = Sum of package and PCB

stray capacitance at the crystal pin associated

with the ASIC pin pll_refclk_o.

C_L1

C_L2

Figure 11. Recommended Crystal Oscillator Configuration

Table 5. Crystal Port Characteristics

PARAMETER

NOM

4.5

UNIT

pF

PLL_REFCLK_I TO GND capacitance

PLL_REFCLK_O TO GND capacitance

4.5

pF

Table 6. Recommended Crystal Configuration

PARAMETER

Crystal circuit configuration

Crystal type

RECOMMENDED

UNIT

Parallel resonant

Fundamental (first harmonic)

Crystal nominal frequency (See TSTPT_6 in the Pin Functions

table)

16.667 or 8.333

±200

MHz

PPM

Crystal frequency tolerance (including accuracy, temperature, aging,

and trim sensitivity)

Crystal drive level

100 max

80 max

12

µW

Ω

Crystal equivalent series resistance (ESR)

Crystal load

pF

Ω

R_Sdrive resistor (nominal)

R_FBfeedback resistor (nominal)

100

1

MΩ

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Table 6. Recommended Crystal Configuration (continued)

PARAMETER

RECOMMENDED

UNIT

pF

C_L1external crystal load capacitor

C_L2external crystal load capacitor

PCB layout

See Figure 11

pF

TI recommends a ground isolation ring around the crystal

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC2607

ASIC. Leave the PLL_REFCLK_O pins unconnected. An oscillator that provides a spread-spectrum clock

reduces EMI.

NOTE

The DLPC2607 device accepts between 0% to –2% spreading (that is, down spreading

only) with a modulation frequency between 20 kHz and 65 kHz and a triangular waveform.

Similar to the crystal option, the oscillator input frequency is limited to 16.667 or 8.333 MHz. To configure the

DLPC2607 device to accept the 8.333-MHz reference clock option, an external pullup resistor to VCC18 must be

applied to the TSTPT (6) pin. To configure the DLPC2607 device to accept the 16.667-MHz reference clock

option, leave the TSTPT (6) pin unconnected.

It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied.

8.2.2.2 mDDR DRAM Compatibility

The following are the basic SDRAM compatibility requirements for the DLPC2607 SDRAM:

•

SDRAM memory type: mDDR

Size: 128 Mb minimum

Organization: N × 16-bits wide × 4 banks

Speed grade t_CK: 6-ns max

CAS latency (C_L), t_RCD, t_RPparameters (clocks): 3, 3, 3

Burst length options to include: Burst of 4

Refresh period (full device): ≥64 ms

The following mDDR DRAM devices are recommended for use with the DLPC2607 device:

Table 7. Compatible mDDR DRAM Device Options^{(1) (2)}

SPEED GRADE t_CK

DVT⁽³⁾

VENDOR

PART NUMBER

SIZE (Mb) ORGANIZATION

C_L, t_RCD, t_RP(Clocks)

⁽⁴⁾(ns)

(5)

(3)

No

Yes

No

Elpida

EDK1216CFBJ-60-F

128

256

8 M × 16

16 M × 16

6

EDD25163HBH-6ELS-F

(6)

Samsung

Micron

K4X56163PL-FGC6

Yes

K4X56163PN-FGC6

MT46H16M16LFBF-6IT:H

H5MS2562JFR-J3M

Hynix

(1) The DLPC2607 device does not use partial array self-refresh or temperature-compensated self-refresh options.

(2) These part numbers reflect Pb-free package.

(3) All these SDRAM devices appear compatible with the DLPC2607 device, but only those marked with 'yes' in the DVT column have been

validated on a TI internal reference design board. Those marked with 'no' can be used at the risk of the ODM.

(4) A 6-ns speed grade corresponds to a 166-MHz mDDR device.

(5) These devices are EOL and no replacement with the same footprint. Do not use these in new designs.

(6) The manufacturer has issued an upcoming end of life notice on this device.

8.2.3 Detailed Design Procedure

For connecting together the DLPC2607 controller and the DMD, see the reference design schematic. Follow the

layout guidelines to achieve a reliable projector. The DLP system requires an optical module or light engine. An

optical OEM that specializes in designing optics for DLP projectors typically supplies the optical engine that has

the LED packages and the DMD mounted to it.

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8.2.3.1 Hot-Plug Usage

The DLPC2607 device provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF). This

protection allows the device to drive these inputs high even when no I/O power is applied.

Under this condition, the DLPC2607 device does not load the input signal, nor draw excessive current that could

degrade ASIC reliability. For example, the I²C bus from the host to other components would not be affected by

powering off VCC_INTF to the DLPC2607 device. Note that TI recommends weak pullups or pulldowns on

signals feeding back to the host to avoid floating inputs.

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8.2.3.2 Maximum Signal Transition Time

Unless otherwise noted, the maximum recommended 20% to 80% rise and fall time to avoid input buffer

oscillation is 10 ns. This applies to all DLPC2607 device input signals.

NOTE

The PARK input signal includes an additional small digital filter that ignores any input-

buffer transitions caused by a slower rise and fall time for up to 150 ns.

8.2.3.3 Configuration Control

The primary configuration control mechanism for the DLPC2607 device is the I²C interface. See the DLPC2607

Software Programmer's Guide, DLPU004, for details on how to configure and control the DLPC2607.

8.2.3.4 White Point Correction Light Sensor

With the addition of a light-to-voltage light sensor (such as a phototransistor) and a voltage comparator circuit,

the DLPC2607 device supports automatic white point correction and power control.

8.2.4 Application Curve

As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the

brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white

screen lumens changes with LED currents is shown in Figure 12. For the LED currents shown, it is assumed that

the same current amplitude is applied to the red, green, and blue LEDs.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0

500

1000

1500

2000

2500

3000

Current (mA)

D001

Figure 12. Luminance vs Current

As with prior DLP electronics solutions, image data is 100% digital from the DLPC2607 device input port to the

image projected on to the display screen. The image stays in digital form and is never converted into an analog

signal. The DLPC2607 device processes the digital input image and converts the data into bit-plane format as

needed by the DMD. The DMD then reflects light to the screen using binary pulse-width modulation (PWM) for

each pixel mirror. The viewer’s eyes integrate this light to form brilliant, crisp images.

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9 Power Supply Recommendations

9.1 System Power Considerations

Table 8 provides a summary of the required power delivery requirements for DLPC2607 for various VCC_FLSH

and VCC_INTF power options.

Table 8. Configuration Based Power Supply Requirements

NOMINAL VOLTAGE

(V)

TOTAL SUPPLY

MARGIN

ASIC POWER RAIL

USAGE

(1)

(2)

VCC_INTF

Video interface I/O

Flash I/O

1.8, 2.5, or 3.3

±5%

(3)

VCC_FLSH

1.8, 2.5, or 3.3

(4)

VDD_PLL

Internal PLL

1

1.8

1

VCC18

VDD10

mDDR and DMD I/O

ASIC core

(1) Total supply margin = DC offset budget + AC noise budget

(2) VCC_INTF is independent of all other supplies.

(3) VCC_FLSH is independent of all other supplies.

(4) When possible, TI recommends to use a tighter supply tolerance (±3%) for the power to the PLL in

order to improve system noise immunity.

9.2 System Power-Up and Power-Down Sequence

Although the DLPC2607 device requires an array of power supply voltages, (that is, VDD, VDD_PLL, VCC_18,

VCC_FLSH, and VCC_INTF), there are no restrictions regarding the relative order of power supply sequencing

to avoid damaging the DLPC2607 device. This is true for both power-up and power-down scenarios. Similarly

there is no minimum time between powering-up or powering-down the different supplies feeding the DLPC2607

device.

NOTE

Often, there are power sequencing requirements for devices that share the supplies with

the DLPC2607 device.

From a functional standpoint, there is one specific power-sequencing recommendation to ensure proper

operation. In particular, apply all ASIC power and allow it to reach the minimum specified voltage levels before

RESET is deasserted to ensure proper power-up initialization is performed. Ensure that all I/O power remains

applied as long as 1-V core power is applied and RESET is de-asserted.

NOTE

When VDD10 core power is applied but I/O power is not applied, additional leakage

current may be drawn.

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System Power-Up and Power-Down Sequence (continued)

Point at which ALL supplies

VDD10 (1.0 V)

reach 95% of the their

specified nominal value.

VCC_PLL (1.0 V)

VCC_INTF (1.8 to 3.3 V)

VCC_FLSH (1.8 to 3.3 V)

PARKZ must be set high within

500 µs after RESETZ is released to

support Auto-initialization

The TI internal reference design board requires

VCC18

(1.8 V)

VCC18 to remain active for a minimum of

100 ms after DMD_PWR_EN is de-asserted to

satisfy DMD power sequence requirements.

Per DMD

Power

Sequencing

Requirement

500 µs

max

PARKZ

DMD_PWR_EN

(ASIC output signal)

500 ±5 µs

PARKZ must be set

low a min of 500 µs

before any power is

removed, before

PLL_REFCLK is

PLL_REFCLK

RESETZ

PLL_REFCLK may be

active before power is

applied

Tstable

stopped and before

RESETZ is asserted

to allow time for the

DMD mirrors to be

Parked.

100 ms min

GPIO4_INTF will be

driven high shortly

after reset is release

to indicate

I2C

(SCL,SDA)

500 µs

Min

0 µs

500 µs

Min

GPIO4_INTF

(INIT_BUSY)

Initialization Busy

The min requirement to set RESETZ = 1 is anytime after

PLL_REFCLK becomes stable. For external oscillator

application this is oscillator dependent & for crystal

applications it is Crystal dependent.

I2C access CAN start immediately after GPIO4_INTF (INIT_BUSY flag)

goes low (this should occur within 100ms from the release of RESETZ

if the Motor Control function is not utilized. If Motor Control is

utilized it may take several seconds.)

Figure 13. Power-Up and Power-Down Timing

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9.3 System Power I/O State Considerations

Note that:

•

If VCC18 I/O power is applied when VDD10 core power is not applied, then all mDDR (non-fail-safe) and non-

mDDR (fail-safe) output signals associated with the VCC18 supply are in a high-impedance state.

If VCC_INTF or VCC_FLSH I/O power is applied when VDD10 core power is not applied, then all output

signals associated with these inactive I/O supplies are in a high-impedance state.

If VDD10 core power is applied but VCC_INTF or VCC_FLSH I/O power is not applied, then all output signals

associated with these inactive I/O supplies are in a high-impedance state.

If VDD10 core power is applied but VCC18 I/O power is not applied, then all mDDR (non-fail-safe) and non-

mDDR (fail-safe) output signals associated with the VCC18 I/O supply are in a high-impedance state.

However, if driven high externally, only the non-mDDR (fail-safe) output signals remain in a high-impedance

state, and the mDDR (non fail-safe) signals are shorted to ground through clamping diodes.

9.4 Power-Up Initialization Sequence

It is assumed that an external power monitor holds the DLPC2607 device in system reset during power-up. It

must do this by driving RESET to a logic low state. It should continue to assert system reset until all ASIC

voltages have reached minimum specified voltage levels, PARK is asserted high, and input clocks are stable.

During this time, most ASIC outputs are driven to an inactive state and all bidirectional signals are configured as

inputs to avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated, which includes

DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0. After power is

stable and the PLL_REFCLK clock input to the DLPC2607 device is stable, then RESET should be deactivated

(set to a logic high). The DLPC2607 device then performs a power-up initialization routine that first locks its PLL,

followed by loading self configuration data from the external flash. Upon release of RESET, all DLPC2607 device

I/Os become active. Immediately following the release of RESET, the GPIO4_INTF signal is driven high to

indicate that the auto-initialization routine is in progress. Upon completion of the auto-initialization routine, the

DLPC2607 device drives GPIO4_INTF low to signal INITIALIZATION DONE (also known as INIT DONE).

NOTE

The host processor can start sending standard I²C commands after GPIO4 (INIT_DONE)

goes low, or a 100-ms timer expires in the host processor, whichever is earlier,

irrespective of whether the motor is enabled or not. However, before sending any

compound I²C commands at power-up, the host processor must wait until GPIO4

(INIT_DONE) goes low, irrespective of whether the motor control function is enabled or

not. Due to motor movement, the worst-case time to wait for GPIO4 to go low is when the

motor control function is enabled and system dependent; it may take several seconds.

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Power-Up Initialization Sequence (continued)

An active high pulse on GPIO4_INTF following the initialization

period will indicate an error condition has been detected. The

source of the error is reported in the system status.

RESETZ

100ms max

(INIT_BUSY)

(ERR IRQ)

GPIO4_INTF

0ms min

3us min

5ms max

I2C access to DLPC2607 should not start until GPIO4_INTF

(INIT_BUSY flag) goes low (this should occur within 100 ms

from the release of RESETZ if the Motor Control function is

not utilized. However, If Motor Control is utilized this may

take several seconds.)

GPIO4_INTF will be driven high within 5 ms

after reset is release to indicate Auto-

Initialization is Busy

I2C traffic

(SCL,SDA,CSZ)

Figure 14. Initialization Timeline

9.5 Power-Good (PARK) Support

The PARK signal operates as an early warning signal that alerts the controller 500 µs before DC supply voltages

have dropped below specifications. This allows the controller time to park the DMD, ensuring the integrity of

future operation. The reference clock continues to run. RESET remains deactivated for at least 500 µs after

PARK has been deactivated (set to a logic low) to allow the park operation to complete.

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10 Layout

10.1 Layout Guidelines

10.1.1 Internal ASIC PLL Power

TI recommends the following guidelines to achieve desired ASIC performance relative to the internal PLL. The

DLPC2607 device contains one internal PLL, which has a dedicated analog supply (VDD_PLL and VSS_PLL).

Isolate VDD_PLL power and VSS_PLL ground pins using an RC-filter consisting of two 50-Ω series ferrites and

two shunt capacitors (to widen the spectrum of noise absorption). TI recommends one 0.1-µF capacitor and that

the other is a 0.01-µF capacitor. Place all four components as close to the ASIC as possible; it is especially

important to keep the leads of the high-frequency capacitors as short as possible. Note that the user should

connect both capacitors across VDD_PLL and VSS_PLL on the ASIC side of the ferrites.

The PCB layout is critical to PLL performance. The ground and power domains are analog signals, and should

be treated as such to achieve minimum noise. Therefore, VDD_PLL must be a single trace from the DLPC2607

device to both capacitors, and then through the series ferrites to the power source. Ensure that the power and

ground traces are as short as possible, parallel to each other, and as close as possible to each other.

Signal VIA

PCB Pad

VIA to Common Analog

Digital Board Power Plane

ASIC Pad

VIA to Common Analog

Digital Board Ground Plane

11

12

13

14

15

A

Local

Decoupling

for the PLL

Digital Supply

G

VDD_

PLL

1.0V

PWR

Signal

H

J

FB

PLL _

REF

CLK_O

VSS_

PLL

VDD

GND

PLL_

REF

CLK_I

Crystal Circuit

Signal

K

Figure 15. PLL Filter Layout

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Layout Guidelines (continued)

10.1.2 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends to tie unused

ASIC input pins through a pullup resistor to their associated power supply or a pulldown to ground. For ASIC

inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown unless

specifically recommended.

NOTE

Internal pullup and pulldown resistors are weak so do not expect them to drive the

external line. The DLPC2607 device implements very few internal resistors and these are

noted in the pin list.

Never tie unused output-only pins directly to power or ground. These pins can be left open.

When possible, TI recommends that unused bidirectional I/O pins be configured to their output state such that

the pin can be left open. If this control is not available and the pins may become an input, then ensure they are

pulled-up (or pulled-down) using an appropriate, dedicated resistor.

10.1.3 SPI Signal Routing

The DLPC2607 device is designed to support two SPI slave devices, specifically, a serial flash and the

PMD1000. Given this requires routing associated SPI signals to two locations while attempting to operate at 33.3

MHz, ensure that reflections do not compromise signal integrity. TI recommends the following:

•

Split the SPICLK PCB signal trace from the DLPC2607 source to each slave device into separate routes as

close to the DLPC2607 device as possible. Make the SPICLK trace length to each device equal in total

length.

Split the SPIDOUT PCB signal trace from the DLPC2607 source to each slave device into separate routes as

close to the DLPC2607 device as possible. Make the SPIDOUT trace length to each device equal in total

length (that is, use the same strategy as SPICLK).

Make the SPIDIN PCB signal trace from each slave device to the point where they intersect on the return to

the DLPC2607 device equal in length and as short as possible. Make sure they share a common trace back

to the DLPC2607 device.

SPICSZ0 and SPICSZ1 do not require special treatment because they are dedicated signals which drive only

one device.

10.1.4 mDDR Memory and DMD Interface Considerations

High-speed interface waveform quality and timing on the DLPC2607 ASIC (that is, the mDDR memory I/F and

the DMD interface) depend on the total length of the interconnect system, the spacing between traces, the

characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus,

ensuring positive timing margin requires attention to many factors.

As an example, the DMD interface system timing margin can be calculated as follows:

Setup margin = (DLPC2607 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)

Hold-time margin = (DLPC2607 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

(1)

where

•

PCB SI degradation is signal integrity degradation due to PCB effects. This includes things such as

simultaneously switching output (SSO) noise, crosstalk, and inter-symbol interference (ISI) noise.

(2)

The DLPC2607 device I/O timing parameters, as well as mDDR and DMD I/O timing parameters, can be found in

their corresponding data sheets. Similarly, PCB routing mismatch can be easily budgeted and met by controlled

PCB routing. However, PCB SI degradation is not so straight forward.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing

requirements (accounting for both PCB routing mismatch and PCB SI degradation). Make sure to confirm any

variation from these recommendations with PCB signal integrity analysis or lab measurements.

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Layout Guidelines (continued)

10.1.5 PCB Design

•

Configuration: Asymmetric dual stripline

Etch thickness (T): 0.5 oz copper

Single-ended signal impedance: 50 Ω (±10%)

Single-ended signal impedance: 100-Ω differential (±10%)

SPACE

•

Reference plane 1 is assumed to be a ground plane for proper return path.

Reference plane 2 is assumed to be the I/O power plane or ground.

Dielectric FR4, (Er): 4.2 (nominal)

Signal trace distance to reference plane 1 (H1): 5 mil (nominal)

Signal trace distance to reference plane 2 (H2): 34.2 mil (nominal)

Reference Plane 1

H1

H2

W

T

Trace

S

Trace

Dielectric Er

H2

T

Trace

H1

Reference Plane 2

Figure 16. PCB Stacking Geometries

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Layout Guidelines (continued)

10.1.6 General PCB Routing (Applies to All Corresponding PCB Signals)

Table 9. PCB Line and Spacing Recommendations^{(1) (2) (3)}

SINGLE-ENDED

SIGNALS

DIFFERENTIAL

PARAMETER

APPLICATION

Escape routing in ball field

PCB etch – Outer layer data or control

PCB etch - Inner layer data or control

PCB etch clocks

UNIT

PAIRS

3

mil

(mm)

(0.762)

7.25

(0.184)

4.5

(0.114)

mil

(mm)

Line width (W)

4.5

(0.114)

4.5

(0.114)

mil

(mm)

4.5

(0.114)

4.5

(0.114)

mil

(mm)

7.75 [1]

(0.305)

mil

(mm)

PCB etch data or control

PCB etch clocks

N/A

Differential signal pair spacing (S)

7.75 [1]

(0.305)

mil

(mm)

3

mil

(mm)

Escape routing in ball field

PCB etch – Outer layer data or control

PCB etch - Inner layer data or control

PCB etch clocks

(0.762)

7.25

(0.184)

4.5

(0.114)

mil

(mm)

Minimum line spacing to other signals

(S)

4.5

(0.114)

4.5

(0.114)

mil

(mm)

11

(0.279)

11

(0.279)

mil

(mm)

Maximum differential pair P-to-N

length mismatch

25

(0.635)

mil

(mm)

Total clock

N/A

(1) Spacing may vary to maintain differential impedance requirements.

(2) The DLPC2607 device only includes one differential signal pair – MEM0_CK_P and MEM0_CK_N.

(3) These values are merely recommendations to achieve good signal integrity. The OEM is free to apply their own rules as long as they

maintain good signal integrity.

These PCB design guidelines are purposefully conservative to minimize potential signal integrity issues. Given

this device is targeted for low-cost, handheld application, there is a need to be more aggressive with these best

practices. TI highly recommends to perform a full-board-level signal integrity analysis, if these guidelines cannot

be followed. The DLPC2607 IBIS models are available for such analysis.

10.1.7 Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths

Table 10. Max Pin-to-Pin PCB Interconnect Recommendations^{(1) (2)}

SIGNAL INTERCONNECT TOPOLOGY

BUS

UNIT

SINGLE BOARD SIGNAL

ROUTING LENGTH

MULTI-BOARD SIGNAL

ROUTING LENGTH

DMD

DMD_D(14:0), DMD_DCLK, DMD_TRC, DMD_SCTRL,

DMD_LOADB, DMD_OEZ DMD_DAD_STRB,

DMD_DAD_BUS, DMD_SAC_CLK and DMD_SAC_BUS

4 max

(101.5 max)

3.5 max

(88.91 max)

inch

(mm)

mDDR

1.5 max

38.1 max

inch

(mm)

MEM0_DQ(15:8), MEM0_UDM and MEM0_UDQS

NA

mDDR

1.5 max

(38.1 max)

inch

(mm)

MEM0_DQ(7:0), MEM0_LDM and MEM0_LDQS

mDDR

(1) Max signal routing length includes escape routing.

(2) Multi-board DMD routing length is more restricted due to the impact of the connector.

39

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

Table 10. Max Pin-to-Pin PCB Interconnect Recommendations^{() ()}(continued)

SIGNAL INTERCONNECT TOPOLOGY

BUS

UNIT

SINGLE BOARD SIGNAL

MULTI-BOARD SIGNAL

ROUTING LENGTH

MEM0_CK_P, MEM0_CK_N, MEM0_A(12:0),

MEM0_BA(1:0), MEM0_CKE, MEM0_CSZ,

MEM0_RASZ, MEM0_CASZ and MEM0_WEZ

2.5 max

(63.5 max)

inch

(mm)

N/A

10.1.8 I/F Specific PCB Routing

Table 11. High-Speed PCB Signal Routing Matching Requirements^{(1) (2) (3)}

SIGNAL INTERCONNECT TOPOLOGY

IF

SINGLE GROUP

DMD_D(14:0), DMD_TRC,

DMD_SCTRL, DMD_LOADB,

DMD_OEZ

REFERENCE SIGNAL

MAX MISMATCH

UNIT

±500

(±12.7)

mil

(mm)

DMD_DCLK

±750

(±19.05)

mil

(mm)

DMD_DAD_STRB, DMD_DAD_BUS

DMD_SAC_BUS

DMD_DCLK

DMD_SAC_CLK

DMD_DCLK

DMD

±750

(±19.05)

mil

(mm)

±500

(±12.7)

mil

(mm)

DMD_SAC_CLK

±150

(±3.81)

mil

(mm)

MEM0_CLK_P

MEM0_CLK_N

MEM0_LDQS

MEM0_UDQS

Read/ Write Data Lower Byte:

MEM0_LDM and MEM0_DQ(7:0) 38.1 max

±300

(±7.62)

mil

(mm)

Read/ Write Data Upper Byte:

MEM0_UDM and MEM0_DQ(15:8)

±300

(±7.62)

mil

(mm)

mDDR:

Address and control:

MEM0_A(12:0), MEM0_BA(1:0),

MEM0_RASZ , MEM0_CASZ,

MEM0_WEZ, MEM0_CSZ,

MEM0_CKE

MEM0_CLK_P/

MEM0_CLK_N

±1000

(±25.4)

mil

(mm)

Data strobes:

MEM0_LDQS and MEM0_UDQS

MEM0_CLK_P/

MEM0_CLK_N

±300

(±7.62)

mil

(mm)

(1) These values apply to PCB routing only. They do not include any internal package routing mismatch associated with the DLPC2607

device, DMD, or mDDR memory.

(2) DMD data and control lines are DDR, whereas DMD_SAC and DMD_DAD lines are single data rate. Matching the DDR lines is more

critical and takes precedence over matching single data rate lines.

(3) mDDR data, mask, and strobe lines are DDR, whereas address and control are single data rate. Matching the DDR lines is more critical

and takes precedence over matching single data rate lines.

10.1.9 Number of Layer Changes

•

Single-ended signals: Minimize the number of layer changes.

Differential signals: Individual differential pairs can be routed on different layers, but the signals of a given pair

must not change layers.

10.1.10 Stubs

Avoid stubs.

40

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

10.1.11 Termination Requirements:

DMD I/F

Terminate all DMD I/F signals, with the exception of DMD_OEZ (specifically

DMD_D(14:0), DMD_DCLK, DMD_TRC, DMD_SCTRL, DMD_LOADB,

DMD_DAD_STRB, DMD_DAD_BUS, DMD_SAC_CLK, and DMD_SAC_BUS), at the

source with a 10- to 30-Ω series resistor. TI recommends a 30-Ω series resistor for most

applications because this minimizes overshoot, undershoot, and reduces EMI; however,

for systems that must operate below –20°C, it may be necessary to reduce this series

resistance to avoid narrowing the data eye too much under worse-case PVT conditions.

TI recommends IBIS simulations for this worse-case scenario.

mDDR memory I/F

mDDR differential

clock

Terminate each line, specifically MEM0_CK(P:N), at the source with a 30-Ω series

resistor. Terminate the pair with an external 100-Ω differential termination across the two

signals as close to the DRAM as possible. (It may be possible to use a 200-Ω differential

termination at the DRAM to save power while still providing sufficient signal integrity, but

this has not been validated.)

mDDR data, strobe, Terminate MEM0_DQ(15:0), MEM0_LDM, MEM0_UDM, MEM0_LDQS, and

and mask MEM0_UDQS with a 30-Ω series resistor located midway between the two devices.

mDDR address and Terminate MEM0_A(12:0), MEM0_BA(1:0), MEM0_CKE, MEM0_CSZ, MEM0_RASZ,

control MEM0_CASZ, and MEM0_WEZ at the source with a 30-Ω series resistor.

For applications where the routed distance of the mDDR or DMD signal can be maintained to a length of less

than 0.75 inches, this signal is short enough not be considered a transmission line and does not need a series

terminating resistor.

41

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

10.2 Layout Example

Figure 17. PCB Layout Example

42

DLPC2607

www.ti.com.cn

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.1.2 器件命名规则

11.1.2.1 器件标记

TRM

DLP

DPP2607

2510465-AB

LLLLLLLL.ZZ

SSSSSYYWWQQ

1

SC

2

3

4

Terminal A1 corner identifier

标记定义：

1. DLP 器件名称

SC：焊球成分

e1：表示含有 SnAgCu 的无铅焊球

G8：表示含有锡-银-铜 (SnAgCu) 的无铅焊球，其中银含量 ≤1.5% 且模压混合物符合 TI 的“绿色环保”定义

2. TI 器件型号

AB（1 或 2 位字母数字）=“A”对应于 TI 器件零件编号。“B”是为不合格器件标记保留的。所有不合格器件（包

括原型和偏差批次样片）均在“B”标记（紧随 TI 器件型号之后）位置用“X”字母标记。合格器件的“B”标记位置留

空。

3. LLLLLLLL.ZZ 半导体晶圆的铸造批次代码以及无铅焊锡球标记

LLLLLLLL：制造批次代码

ZZ：分批编号

4. SSSSSYYWWQQ：封装和组装信息

SSSSS：制造基地

YYWW：日期代码（YY = 年 :: WW = 周）

QQ：合格等级选项 – 工程样片在该字段中以 ES 后缀标记。

例如，KOREA0914ES 是于 2009 的第 14 个周在韩国构建的工程样片。

43

DLPC2607

ZHCSC07E –DECEMBER 2013–REVISED MARCH 2019

www.ti.com.cn

11.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 商标

供电, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

44

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	DLPC2607
厂家：	TEXAS INSTRUMENTS
描述：	DLP® display controller for DLP2000 (0.2 nHD) DMD
文件：	总48页 (文件大小：1932K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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