DRV201A [TI]
VOICE COIL MOTOR DRIVER FOR CAMERA AUTO FOCUS; 音圈电机驱动器，用于摄像机自动聚焦
| 型号： | DRV201A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | VOICE COIL MOTOR DRIVER FOR CAMERA AUTO FOCUS |
| 文件： | 总25页 (文件大小：881K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV201A
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SLVSBN6 –JUNE 2013
VOICE COIL MOTOR DRIVER FOR CAMERA AUTO FOCUS
Check for Samples: DRV201A
1
FEATURES
•
Configurable for Linear or PWM Mode VCM
Current Generation
•
Improved PWM-to-Linear Mode Settling Time
vs. DRV201
•
•
•
High Efficiency PWM Current Control for VCM
Advanced Ringing Compensation
•
•
•
•
•
Improved EMC Performance vs. DRV201
Operating Temperature Range: -40ºC to 85ºC
6-Ball WCSP Package With 0.4-mm Pitch
Max Die Size: 0.806 mm x 1.49 mm
Max Package Height: 0.3 mm
Integrated 10-bit D/A Converter for VCM
Current Control
•
•
Protection
–
–
–
–
–
Open and Short-Circuit Detection
Undervoltage Lockout (UVLO)
Thermal Shutdown
APPLICATIONS
•
•
•
•
•
•
Cell Phone Auto Focus
Digital Still Camera Auto Focus
Iris and Exposure Control
Security Cameras
Internal Current Limit for VCM Driver
4-kV ESD-HBM
I2C Interface
Web and PC Cameras
Actuator Controls
DESCRIPTION
The DRV201A is an advanced voice coil motor driver for camera auto focus. It has an integrated D/A converter
for setting the VCM current. VCM current is controlled with a fixed frequency PWM controller or a linear mode
driver. Current generation can be selected via I2C register. The DRV201A has an integrated sense resistor for
current regulation and the current can be controlled through I2C.
When changing the current in the VCM, the lens ringing is compensated with an advanced ringing compensation
function. Ringing compensation reduces the needed time for auto focus significantly. The device also has VCM
short and open protection functions.
FUNCTIONAL BLOCK DIAGRAM
Cin
VBAT
OSCILLATOR
REFERENCE
10-bit
DAC
POR
ISOURCE
DIGITAL
VCM
REGISTERS
I2C
RINGING
ISINK
COMPENSATION
SCL
SDA
R
sense
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
DRV201A
SLVSBN6 –JUNE 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
YMB (non-coated)
YMB (coated)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
201A YMDS
DRV201AYMBR
-40°C to 85°C
DRV201AYMBRB
201AB YMDS
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVICE INFORMATION
NanoFree YMB PACKAGE
(TOP VIEW)
NanoFree YMB PACKAGE
(BOTTOM VIEW)
NanoFree YMB PACKAGE
(TOP VIEW)
I
YMB package package markings:
SCL
VBAT
SOURCE
2
1
201AB
YMDS
201A
YMDS
YM = YEAR / MONTH DATE CODE
D
S
0
= DAY OF LASER MARK
= ASSEMBLY SITE CODE
= Pin A1 (Filled Solid)
I
SDA
GND
SINK
C
B
A
NON-COATED
COATED
The coated package option has a backside polymer coating that is 40µm thick. The final package heights of both
the packages are the same for both options. This coating helps minimize edge chipping or die cracking during
assembly and manufacturing.
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
VBAT
NO.
2A
1A
2B
1B
2C
1C
Power
GND
Ground
I_SOURCE
I_SINK
SCL
Voice coil positive terminal
Voice coil negative terminal
I2C serial interface clock input
I
SDA
I/O
I2C serial interface data input/output (open drain)
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
V
VBAT, ISOURCE, ISOURCE pin voltage range(2)
Voltage range at SDA, SCL
–0.3 to 5.5
–0.3 to 3.6
V
Continuous total power dissipation
Internally limited
θJA
TJ
Junction-to-ambient thermal resistance(3)
Operating junction temperature
Operating ambient temperature
Storage temperature
130
°C/W
°C
-40 to 125
-40 to 85
-55 to 150
±4000
TA
°C
Tstg
°C
(HBM) Human body model
ESD rating
V
(CDM) Charged device model
±500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) This thermal data is measured with high-K board (4-layer board).
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient
temperature range of 25°C) (unless otherwise noted)
PARAMETER
INPUT VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBAT
Input supply voltage
2.5
3.7
4.8
2.2
V
V
VBAT rising
VBAT falling
VUVLO
VHYS
Undervoltage lockout threshold
Undervoltage lockout hysteresis
2
50
100
250
mV
INPUT CURRENT
Input supply current shutdown,
ISHUTDOWN
MAX: VBAT = 4.4 V
MAX: VBAT = 4.4 V
0.15
120
1
µA
µA
includes switch leakage currents
Input supply current standby, includes
switch leakage currents
ISTANDBY
200
STARTUP, MODE TRANSITIONS, AND SHUTDOWN
t1
t2
t3
t4
Shutdown to standby
Standby to active
Active to standby
Shutdown time
100
100
100
1
µs
µs
µs
ms
Active or standby to shutdown
0.5
VCM DRIVER STAGE
Resolution
10
bits
IRES
Relative accuracy
-10
-1
10
1
LSB
Differential nonlinearity
Zero code error
Offset error
0
mA
mA
At code 32
3
% of
FSR
Gain error
±3
Gain error drift
0.3
0.3
0.4 %/°C
0.5 %/°C
mA
Offset error drift
IMAX
Maximum output current
Average VCM current limit
102.3
160
(1)
ILIMIT
See
110
240
mA
(1) During short circuit condition driver current limit comparator will trip and short is detected and driver goes into STANDBY and short flag
is set high in the status register.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient
temperature range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
256
0.5
TYP
MAX UNIT
Minimum VCM code for OPEN and
SHORT detection
(2)
IDETCODE
See
mA
fSW
Switching frequency
Internal dropout
VCM inductance
VCM resistance
Selectable through CONTROL register
4
0.4
150
22
MHz
V
(3)
VDRP
LVCM
RVCM
See
30
11
µH
Ω
LENS MOVEMENT CONTROL
tset1
tset2
Lens settling time
±10% error band
±10% error band
2/fVCM
1/fVCM
ms
ms
Hz
Lens settling time
VCM resonance frequency
50
-10
-30
150
10
fVCM
When 1/fVCM compensation is used
When 2/fVCM compensation is used
VCM resonance frequency tolerance
%
30
(2) When testing VCM open or short this is the recommended minimum VCM code (in dec) to be used.
(3) This is the voltage that is needed for the feedback resistor and high side driver. It should be noted that the maximum VCM resistance is
limited by this voltage and supply voltage. E.g. 3-V supply maximum VCM resistance is: RVCM = (VBAT – VDRP)/IVCM = (3 V - 0.4
V)/102.3 mA = 25.4 Ω.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient
temperature range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LOGIC I/Os (SDA AND SCL)
V = 1.8 V, SCL
V = 1.8 V, SDA
-4.25
-1
4.25
µA
1
IIN
Input leakage current
RPullUp
VIH
I2C pull-up resistors
SDA and SCL pins
4.7
kΩ
(4)
Input high level
See
1.17
0
3.6
0.63
1
V
V
(5)
VIL
Input low level
See
tTIMEOUT
RPD
SCL timeout for shutdown detection
Pull down resistor at SCL line
I2C clock frequency
0.5
ms
kΩ
500
fSCL
400 kHz
INTERNAL OSCILLATOR
fOSC
Internal oscillator
20°C ≤ TA ≤ 70°C
-40°C ≤ TA ≤ 85°C
-3
-5
3
5
%
%
Frequency accuracy
THERMAL SHUTDOWN
TTRIP Thermal shutdown trip point
140
°C
(4) During shutdown to standby transition VIH low limit is 1.28 V.
(5) During shutdown to standby transition VIL high limit is 0.51 V.
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PARAMETER MEASUREMENT INFORMATION
DRV201A
VBAT ISOURCE
VCM
Vin
C
in
SCL
SDA
ISINK
GND
To/From a
controller
List of components:
•
•
•
•
•
•
•
Cin - Panasonic ECJ0EB1A105M
VCM - Mitsumi VCM KAF-V85S60
Actuator size: 8.5 x 8.5 x 3.4 (mm)
Lens in the VCM: M6 (Pitch: 0.35)
Weight: 75 mg
TTL: 4.2 mm
FB: 1.1 mm
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TYPICAL CHARACTERISTICS
Figure 1. Lens Positions With and Without Ringing
Compensation With 100-µm Step on the Lens Position
Figure 2. Lens Positions With and Without Ringing
Compensation With 100-µm Step on the Lens Position,
Zoomed In
Figure 3. Lens Positions With and Without Ringing
Compensation With 30-µm Step on the Lens Position
Figure 4. Lens Positions With and Without Ringing
Compensation With 30-µm Step on the Lens Position,
Zoomed In
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FUNCTIONAL DESCRIPTION
The DRV201A is intended for high performance autofocus in camera modules. It is used to control the current in
the voice coil motor (VCM). The current in the VCM generates a magnetic field which forces the lens stack
connected to a spring to move. The VCM current and thus the lens position can be controlled via the I2C
interface and an auto focus function can be implemented.
The DRV201A offers a higher level of performance than the DRV201 in two areas. First, the transition between
PWM and linear modes is free of any resonance. This allows faster image capture after achieving focus in the
PWM mode. The other performance enhancement is in the area of EMC performance. When operating in PWM
mode, transitions were significantly slowed down resulting in lower conducted and radiated noise versus the
DRV201.
The device connects to a video processor or image sensor through a standard I2C interface which supports up to
400-kbit/s data rate. The digital interface supports IO levels from 1.8 V to 3.3 V. All pins have 4-kV HBM ESD
rating.
When SCL is low for at least 0.5 ms, the device enters SHUTDOWN mode. If SCL goes from low to high the
driver enters STANDBY mode in less than 100 μs and default register values are set as shown in Figure 5.
ACTIVE mode is entered whenever the VCM_CURRENT register is set to something else than zero.
Vbat
t4
t1
t2
t3
ISC/SCL
=0
STANDBY
0
DAC
=0
ACTIVE
SHUTDOWN
SHUTDOWN
STANDBY
mode
Figure 5. Power Up and Down Sequence
VCM current can be controlled via an I2C interface and VCM_CURRENT registers. Lens stack is connected to a
spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is
compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT
register is changed. This enables a fast autofocus algorithm and pleasant user experience.
Current in the VCM can be generated with a linear or PWM control. In linear mode the high side PMOS is
configured as a current source and current is set by the VCM_CURRENT control register. In PWM control the
VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM
between VBAT and GND through the high side PMOS and then released to a ‘freewheeling’ mode through the
sense resistor and low side NMOS. PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz
through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register.
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MODES OF OPERATION
SHUTDOWN If the driver detects SCL has a DC level below 0.63 V for duration of at least 0.5 ms, the driver will
enter shutdown mode. This is the lowest power mode of operation. The driver will remain in shutdown for
as long as SCL pin remain low.
STANDBY If SCL goes from low to high the driver enters STANDBY mode and sets the default register values.
In this mode registers can be written to through the I2C interface. Device will be in STANDBY mode when
VCM_CURRENT register is set to zero. From ACTIVE mode the device will enter STANDBY if the
SW_RST bit of the CONTROL register is set. In this case all registers will be reset to default values.
STANDBY mode is entered from ACTIVE mode if any of the following faults occur: Over
temperature protection fault (OTPF), VCM short (VCMS), or VCM open (VCMO). When
STANDBY mode is entered due to a fault condition current register is cleared.
ACTIVE The device is in ACTIVE mode whenever the VCM_CURRENT control is set to something else than
zero through the I2C interface. In ACTIVE mode VCM driver output stage is enabled all the time resulting
in higher power consumption. The device remains in active mode until the SW_RST bit in the CONTROL
register is set, SCL is pulled low for duration of 0.5 ms, VCM_CURRENT control is set to zero, or any of
the following faults occur: Over temperature protection fault (OTPF), VCM short (VCMS), or VCM open
(VCMO). If active mode is entered after fault the status register is automatically cleared.
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VCM DRIVER OUTPUT STAGE OPERATION
Current in the VCM can be controlled with a linear or PWM mode output stage. Output stage is enabled in
ACTIVE mode which can be controlled through VCM_CURRENT control register and the output stage mode is
selected from MODE register bit PWM/LIN.
In linear mode the output PMOS is configured to a high side current source and current can be controlled from a
VCM_CURRENT registers.
In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by
connecting the VCM between VBAT and GND through the high side PMOS and then released to a ‘freewheeling’
mode through the sense resistor and low side NMOS. Current in the VCM is sensed with a 1-Ω sense resistor
which is connected into an error amplifier input where the other input is controlled by the 10-bit DAC output.
PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM
or linear mode can be selected with the PWM/LIN bit in the MODE register.
RINGING COMPENSATION
VCM current can be controlled via an I2C interface and VCM_CURRENT registers. Lens stack is connected to a
spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is
compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT
register is changed. This enables a fast auto focus algorithm and pleasant user experience.
Ringing compensation is dependent on the VCM resonance frequency and this can be controlled via
VCM_FREQ register (07h) from 50 Hz up 150 Hz. Table 1 shows the VCM_FREQ register setting for each
resonance frequency in 1-Hz steps. If more accurate resonance frequency is available, the control value can be
calculated with Equation 1.
Ringing compensation is designed in a way that it can tolerate ±30% frequency variation in the VCM resonance
frequency when 2/fVCM compensation is used and ±10% variation with 1/fVCM so only statistical data from the
VCM is needed in production.
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Table 1. VCM Resonance Frequency Control Register (07h) Table
VCM
Resonance
Frequency
[Hz]
VCM_FREQ[7:0] (07h)
VCM
Resonance
Frequency
[Hz]
VCM_FREQ[7:0] (07h)
VCM
Resonance
Frequency
[Hz]
VCM_FREQ[7:0] (07h)
DEC
BIN
DEC
BIN
DEC
BIN
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
0
0
84
85
154
157
160
162
165
167
170
172
174
177
179
181
183
185
187
189
191
193
195
197
198
200
202
204
205
207
208
210
212
213
215
216
217
219
10011010
10011101
10100000
10100010
10100101
10100111
10101010
10101100
10101110
10110001
10110011
10110101
10110111
10111001
10111011
10111101
10111111
11000001
11000011
11000101
11000110
11001000
11001010
11001100
11001101
11001111
11010000
11010010
11010100
11010101
11010111
11011000
11011001
11011011
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
-
220
222
223
224
226
227
228
229
231
232
233
234
235
236
238
239
240
241
242
243
244
245
246
247
248
249
250
251
251
252
253
254
255
-
11011100
11011110
11011111
11100000
11100010
11100011
11100100
11100101
11100111
11101000
11101001
11101010
11101011
11101100
11101110
11101111
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11111010
11111011
11111011
11111100
11111101
11111110
11111111
-
7
111
14
1110
86
21
10101
87
27
11011
88
34
100010
89
40
101000
90
46
101110
91
52
110100
92
58
111010
93
63
111111
94
68
1000100
1001001
1001110
1010011
1011000
1011100
1100000
1100101
1101001
1101101
1110001
1110100
1111000
1111100
1111111
10000010
10000110
10001001
10001100
10001111
10010010
10010101
10011000
95
73
96
78
97
83
98
88
99
92
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
96
101
105
109
113
116
120
124
127
130
134
137
140
143
146
149
152
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User Example 1
In Figure 6, lens settling time and settling window shows how lens control is defined. Below is an example case
how the lens is controlled and what settling time is achieved:
Measured VCM resonance frequency = 100 Hz
•
According to Table 1, VCM_FREQ[7:0] = ‘10111111’ (reg 0x07h)
VCM resonance frequency, fVCM, variation is within ±10% (min 90 Hz … max 110 Hz)
1/fVCM ringing compensation is used : RING_MODE = ‘1’ (reg 0x06h)
Stepping the lens by 50 µm
The lens is settled into a ±5-µm window within 10 ms (1/fVCM
•
•
)
User Example 2
If the case is otherwise exactly the same, but VCM resonance frequency cannot be guaranteed to stay at more
than ±30% variation, slower ringing compensation should be used:
Measured VCM resonance frequency = 100 Hz
•
According to Table 1, VCM_FREQ[7:0] = ‘10111111’ (reg 0x07h)
VCM resonance frequency, fVCM, variation is within ±30% (min 70 Hz … max 130 Hz)
2/fVCM ringing compensation is used : RING_MODE = ‘0’ (reg 0x06h)
Stepping the lens by 50 µm
•
•
The lens is settled into a ±5-µm window within 20 ms (2/fVCM)
10% step
size window
Lens position
settling time
Time
Figure 6. Lens Settling Time and Settling Window
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I2C BUS OPERATION
The I2C bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
The DRV201A hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I2C standard 3.0.
DRV201A supports four different read and two different write operations; single read from a defined location,
single read from a current location, sequential read starting from a defined location, sequential read from current
location, single write to a defined location, sequential write starting from a defined location. All different read and
write operations are described below.
Single Write to a Defined Location
Figure 7 shows the format of a single write to a defined register. First, the master issues a start condition
followed by a seven-bit I2C address. Next, the master writes a zero to conduct a write operation. Upon receiving
an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a
second acknowledge, DRV201A sets the I2C register to a defined value and the master writes the eight-bit data
value across the bus. Upon receiving a third acknowledge, DRV201A auto increments the internal I2C register
number by one and the master issues a stop condition. This action concludes the register write.
CURRENT REGISTER NUMBER K
REGISTER NUMBER M
M+1
REGISTER NUMBER
DRV201A ADDRESS
0
DATA
M
0
0 0 1 1 1 0
SINGLE WRITE TO A DEFINED LOCATION
Figure 7. Single Write
Single Read from a Defined Location and Current Location
Figure 8 shows the format of a single read from a defined location. First, the master issues a start condition
followed by a seven-bit I2C address. Next, the master writes a zero to conduct a write operation. Upon receiving
an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a
second acknowledge, DRV201A sets the internal I2C register number to a defined value. Then the master issues
a repeat start condition and a seven-bit I2C address followed by a one to conduct a read operation. Upon
receiving a third acknowledge, the master releases the bus to the DRV201A. The DRV201A then writes the
eight-bit data value from the register across the bus. The master acknowledges receiving this byte and issues a
stop condition. This action concludes the register read.
CURRENT REGISTER NUMBER K
REGISTER NUMBER M
M+1
REGISTER NUMBER
DRV201A ADDRESS
DRV201A ADDRESS
0
1
DATA
M
0
0
0
1
1
1
0
0 0 0 1 1 1 0
Figure 8. Single Read from a Defined Location
Figure 9 shows the single read from the current location. If the read command is issued without defining the
register number first, DRV201A writes out the data from the current register from the device memory.
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CURRENT REGISTER NUMBER K
REGISTER NUMBER K+1
K+2
DRV201A ADDRESS
1
DATA
DRV201A ADDRESS
1
DATA
0
0
0
1
1
1
0
0 0 0 1 1 1 0
Figure 9. Single Read from the Current Location
Sequential Read and Write
Sequential read and write allows simple and fast access to DRV201A registers. Figure 10 shows sequential read
from a defined location. If the master doesn’t issue a stop condition after giving ACK, DRV201A auto increments
the register number and writes the data from the next register.
CURRENT REGISTER NUMBER K
REGISTER NUMBER M
REGISTER NUMBER M+1 K+2
REGISTER NUMBER M+L-1
M+L
REGISTER NUMBER
M
0
1
DRV201A ADDRESS
DATA
DATA
DATA
DRV201A ADDRESS
0
0
0
1
1
1
0
0 0 0 1 1 1 0
L bytes of DATA
Figure 10. Sequential Read from a Defined Location
Figure 11 shows the sequential write. If the master doesn’t issue a stop condition after giving ACK, DRV201A
auto increments it’s register by one and the master can write to the next register.
M+L
CURRENT REGISTER NUMBER K
REGISTER NUMBER M
REGISTER NUMBER M+1
M+2
REGISTER NUMBER M+L-1
REGISTER NUMBER
M
DRV201A ADDRESS
0
DATA
DATA
DATA
0
0 0 1 1 1 0
L bytes of DATA
Figure 11. Sequential Write
If read is started without writing the register value first, DRV201A writes out data from the current location. If the
master doesn’t issue a stop condition after giving ACK, DRV201A auto increments the I2C register and writes out
the data. This continues until the master issues a stop condition. This is shown in Figure 12.
CURRENT REGISTER NUMBER K
REGISTER NUMBER K+1 K+2
REGISTER NUMBER K+L-1
K+L
DRV201A ADDRESS
1
DATA
DATA
DATA
0
0 0 1 1 1 0
L bytes of DATA
Figure 12. Sequential Read Starting from a Current Location
I2C Device Address, Start and Stop Condition
Data transmission is initiated with a start bit from the controller as shown in Figure 13. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. SDA data is latched by DRV201A on the rising edge of the SCL line. If the appropriate device
address bits are set for the device, DRV201A issues the ACK by pulling the SDA line low on the next falling edge
after 8th bit is latched. SDA is kept low until the next falling edge of the SCL line.
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Data transmission is completed by either the reception of a stop condition or the reception of the data word sent
to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion
of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An
acknowledge is issued after the reception of valid address, sub-address and data words. Reference Figure 14.
. . .
SDA
. . .
SCL
1
2
3
4
5
6
7
8
9
START CONDITION
ACKNOWLEDGE
STOP CONDITION
Figure 13. I2C Start/Stop/Acknowledge Protocol
tLOW
tH(STA)
tr
tf
SCL
tH(STA)
tH(DAT)
tS(STO)
tHIGH
tS(DAT)
tS(STA)
SDA
t(BUF)
P
S
S
P
Figure 14. I2C Data Transmission Protocol
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DATA TRANSMISSION TIMING
VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
PARAMETER
Serial clock frequency
TEST CONDITIONS
MIN
100
TYP
MAX
UNIT
f(SCL)
tBUF
400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
4.7
1.3
Bus Free Time Between Stop and Start Condition
Tolerable spike width on bus
SCL low time
µs
50
ns
tSP
4.7
1.3
4
tLOW
µs
µs
ns
tHIGH
SCL high time
600
250
100
4.7
600
4
tS(DAT)
tS(STA)
tS(STO)
tH(DAT)
tH(STA)
tr(SCL)
tf(SCL)
tr(SDA)
tf(SDA)
SDA → SCL setup time
Start condition setup time
Stop condition setup time
SDA → SCL hold time
ns
µs
ns
µs
ns
600
0
3.45
µs
0
0.9
4
µs
ns
Start condition hold time
Rise time of SCL Signal
Fall time of SCL Signal
Rise time of SDA Signal
Rise time of SDA Signal
600
1000
ns
300
300
ns
300
1000
ns
300
300
ns
300
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REGISTER ADDRESS MAP
DEFAULT
VALUE
REGISTER
ADDRESS (HEX)
NAME
DESCRIPTION
1
2
3
4
5
6
7
01
02
03
04
05
06
07
not used
CONTROL
0000 0010
0000 0000
0000 0000
0000 0000
0000 0000
1000 0011
Control register
VCM_CURRENT_MSB
VCM_CURRENT_LSB
STATUS
Voice coil motor MSB current control
Voice coil motor LSB current control
Status register
MODE
Mode register
VCM_FREQ
VCM resonance frequency
CONTROL REGISTER (CONTROL)
Address – 0x02h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
EN_RING
R/W
D0
RESET
R/W
0
not used
not used
not used
not used
not used
not used
R
0
R
0
R
0
R
0
R
0
R
0
1
FIELD NAME
BIT DEFINITION
Forced software reset (reset all registers to default values) and device goes into STANDBY. RESET
bit is automatically cleared when written high.
RESET
0 – inactive
1 – device goes to STANDBY
Enables ringing compensation.
0 – disabled
EN_RING
1 – enabled
VCM MSB CURRENT CONTROL REGISTER (VCM_CURRENT_MSB)
Address – 0x03h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
not used
not used
not used
not used
not used
not used
VCM_CURRENT[9:8]
R/W
R
0
R
0
R
0
R
0
R
0
R
0
0
0
FIELD NAME
BIT DEFINITION
VCM current control
00 0000 0000b – 0 mA
00 0000 0001b – 0.1 mA
00 0000 0010b – 0.2 mA
…
11 1111 1110b – 102.2 mA
11 1111 1111b – 102.3 mA
VCM_CURRENT[9:8]
NOTE
When setting the current in DRV201A both
VCM_CURRENT_MSB and VCM_CURRENT_LSB
registers have to be updated. DRV201A starts updates the
current after LSB register write is completed.
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VCM LSB CURRENT CONTROL REGISTER (VCM_CURRENT_LSB)
Address – 0x04h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
VCM_CURRENT[7:0]
R/W
0
0
0
0
0
0
0
0
FIELD NAME
BIT DEFINITION
VCM current control
00 0000 0000b – 0 mA
00 0000 0001b – 0.1 mA
00 0000 0010b – 0.2 mA
…
11 1111 1110b – 102.2 mA
11 1111 1111b – 102.3 mA
VCM_CURRENT[7:0]
NOTE
When setting the current in DRV201A both
VCM_CURRENT_MSB and VCM_CURRENT_LSB
registers have to be updated. DRV201A starts updates the
current after LSB register write is completed.
STATUS REGISTER (STATUS)(1)
Address – 0x05h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
not used
R/WR
0
D5
D4
TSD
R
D3
VCMS
R
D2
VCMO
R
D1
UVLO
R
D0
OVC
R
not used
not used
R
0
R
0
0
0
0
0
0
(1) Status bits are cleared when device changes it’s state from standby to active. If TSD was tripped the device goes into Standby and will
not allow the transition into Active until the device cools down and TSD is cleared.
FIELD NAME
OVC
BIT DEFINITION
Over current detection
UVLO
Undervoltage Lockout
VCMO
VCMS
TSD
Voice coil motor open detected
Voice coil motor short detected
Thermal shutdown detected
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MODE REGISTER (MODE)
Address – 0x06h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
RING_MOD
E
FIELD NAME
not used
not used
not used
PWM_FREQ[2:0]
PWM/LIN
READ/WRITE
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RESET VALUE
FIELD NAME
BIT DEFINITION
Ringing compensation settling time
RING_MODE
0 – 2x(1/fVCM
)
)
1 – 1x(1/fVCM
Driver output stage in linear or PWM mode
0 – PWM mode
PWM/LIN
1 – Linear mode
Output stage PWM switching frequency
000 – 0.5 MHz
001 – 1 MHz
010 – N/A
PWM_FREQ[2:0]
011 – 2 MHz
100 – N/A
101 – 4.8 MHz
110 – 6.0 MHz
111 – 4 MHz
VCM RESONANCE FREQUENCY REGISTER (VCM_FREQ)
Address – 0x07h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
VCM_FREQ[7:0]
R/W
1
0
0
0
0
0
1
1
FIELD NAME
BIT DEFINITION
VCM mechanical ringing frequency for the ringing compensation can be selected with the below
formula. The formula gives the VCM_FREQ[7:0] register value in decimal which should be rounded to
the nearest integer.
19200
VCM _ FREQ = 383-
VCM_FREQ[7:0]
Fres
(1)
Default VCM mechanical ringing frequency is 76.4 Hz.
19200
VCM _ FREQ = 383-
=131.69 Þ132 Þ '1000 0011'
76.4
(2)
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YMB PACKAGE DIMENSIONS
DIMENSION
MIN
TYP
MAX
1.49
0.806
0.3
UNIT
mm
mm
mm
mm
µm
Length
Width
Height(1)
0.278
0.39
4.8
0.289
0.4
6
Ball pitch
0.41
7.2
Ball height
Coating thickness(2)
0.39
0.4
0.41
mm
(1) Height tolerances valid for both coated and non-coated packages.
(2) Coating thickness only applies to DRV201AYMBRB (coated) package option.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2013
PACKAGING INFORMATION
Orderable Device
DRV201AYMBR
DRV201AYMBRB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
PICOSTAR
YMB
6
6
3000
Green (RoHS
& no Sb/Br)
Call TI
Call TI
Level-1-260C-UNLIM
201A
201AB
PREVIEW PICOSTAR
YMB
3000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV201AYMBR
PICOST
AR
YMB
6
3000
180.0
8.4
0.91
1.59
0.36
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
PICOSTAR YMB
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
DRV201AYMBR
6
3000
Pack Materials-Page 2
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