DRV3220QPHPRQ1 [TI]
具有增强保护功能的汽车类 12V 和 24V 电池三相栅极驱动器 | PHP | 48 | -40 to 125;
| 型号： | DRV3220QPHPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有增强保护功能的汽车类 12V 和 24V 电池三相栅极驱动器 | PHP | 48 | -40 to 125 电池 栅极驱动 驱动器 |
| 文件： | 总31页 (文件大小：866K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
DRV3220-Q1 Three-Phase Automotive Gate Driver With Enhanced Protection,
Diagnostics, and Monitoring
1 Features
2 Applications
1
•
AEC-Q100 Qualified for Automotive Applications:
•
Automotive Motor-Control Applications
–
Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
–
–
–
–
Electrical Power Steering (EPS, EHPS)
Electrical Brake and Brake Assist
Transmission
•
•
•
•
•
•
•
•
•
Three-Phase Bridge Driver for Motor Control
Suitable for 12-V and 24-V Applications
Integrated Boost Converter, Gate Drive to 4.75 V
Drives 6 Separate N-Channel Power MOSFETs
Strong 1-A Gate Drive for High-Current FETs
Programmable Dead Time
Pumps
•
Industrial Motor-Control Applications
3 Description
The DRV3220-Q1 bridge driver is dedicated to
automotive three-phase brushless DC motor control
applications. The device provides six dedicated
drivers for standard-level N-channel MOSFET
transistors. A boost converter with an integrated FET
provides the overdrive voltage, allowing full control on
the power stages even for low battery voltage down
to 4.75 V. The strong driver strength is suitable for
high-current applications and programmable to limit
peak output current.
PWM Frequency up to 20 kHz
Supports 100% Duty Cycle Operation
Short-Circuit Protection
–
VDS-Monitoring (Adjustable Detection Level)
•
•
•
Overvoltage and Undervoltage Protection
Overtemperature Warning and Shut Down
Sophisticated Failure Detection and Handling
Through SPI
The device incorporates robust FET protection and
system monitoring functions like a Q&A watchdog
and voltage monitors for I/O supplies and ADC
reference voltages. Integrated internal diagnostic
functions can be accessed and programmed through
an SPI interface.
•
System Supervision
–
–
–
Q&A Watchdog
I/O Supply Monitoring
ADREF Monitoring
•
•
•
Programmable Internal Fault Diagnostics
Sleep Mode Function
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
Thermally-Enhanced 48-Pin HTQFP PowerPAD™
IC Package (7-mm × 7-mm Body)
DRV3220-Q1
HTQFP (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
3.3 V, 5 V
12 V, 24 V
DRV3220-Q1
Driver
PWM
(3× or 6× pins)
/
M
FETs
Controller
SPI
Protection
Diagnostics
S/D
//
Paths
ADC
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
Table of Contents
7.4 Register Maps......................................................... 17
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 20
8.3 System Example ..................................................... 20
Power Supply Recommendations...................... 22
1
2
3
4
5
6
Features.................................................................. 1
8
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 Serial Peripheral Interface Timing Requirements ... 11
6.7 Typical Characteristics............................................ 12
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Programming........................................................... 14
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1 Documentation Support ........................................ 23
11.2 Receiving Notification of Documentation Updates 23
11.3 Community Resources.......................................... 23
11.4 Trademarks........................................................... 23
11.5 Electrostatic Discharge Caution............................ 23
11.6 Glossary................................................................ 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
February 2017
*
Initial release.
2
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
5 Pin Configuration and Functions
PHP PowerPAD™ Package
48-Pin HTQFP
Top View
GLS3
SLS3
GHS3
SHS3
VSH
1
36
35
34
33
32
31
30
29
28
27
26
25
NU
2
NU
3
NU
4
ADREF
VCC5
NU
5
SHS2
GHS2
SLS2
GLS2
TEST
GLS1
SLS1
6
Thermal
Pad
7
GNDA
VCC3
SDI
8
9
10
11
12
SDO
SCLK
VDDIO
Not to scale
Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1
GLS3
SLS3
GHS3
SHS3
VSH
PWR
PWR
PWR
PWR
HVI_A
PWR
PWR
PWR
PWR
HVI_A
Gate low-side 3, connected to gate of external power MOSFET.
2
Source low-side 3, connected to external power MOSFET for gate discharge and VDS monitoring.
Gate high-side 3, connected to gate of external power MOSFET.
3
4
Source high-side 3, connected to external power MOSFET for gate discharge and VDS monitoring.
Sense high-side, sensing VS connection of the external power MOSFETs for VDS monitoring.
Source high-side 2, connected to external power MOSFET gate discharge and VDS monitoring.
Gate high-side 2, connected to gate of external power MOSFET.
5
6
SHS2
GHS2
SLS2
GLS2
TEST
7
8
Source low-side 2, connected to external power MOSFET for gate discharge and VDS monitoring.
Gate low-side 2, connected to gate of external power MOSFET.
9
10
Test mode input, during normal application connected to ground.
(1) Description of pin type: GND = Ground; HVI_A = High-voltage input analog; HVI_D = High-voltage input digital; LVI_A = Low-voltage
input analog; LVO_A = Low-voltage output analog; LVO_D = Low-voltage output digital; NC = No connect; PWR = Power output; Supply
= Supply input
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
11
12
13
14
15
16
17
18
19
20
21
22
NAME
GLS1
SLS1
GHS1
SHS1
VS
PWR
PWR
Gate low-side 1, connected to gate of external power MOSFET.
Source low-side 1, connected to external power MOSFET for gate discharge and VDS monitoring.
Gate high-side 1, connected to gate of external power MOS transistor.
Source high-side 1, connected to external power MOS transistor for gate discharge and VDS.
Power-supply voltage (externally protected against reverse battery connection).
Analog ground.
PWR
PWR
Supply
GND
GNDA
ERR
LVO_D
HVI_D
HVI_A
Supply
PWR
Error (low active), Error pin to indicate detected error.
DRVOFF
RVSET
BOOST
SW
Driver OFF (high active), secondary bridge driver disable.
VDDIO / ADREF OV/UV configuration resister.
Boost output voltage, used as supply for the gate drivers.
Boost converter switching node connected to external coil and external diode.
SPI chip select.
NCS
HVI_D
Boost GND to set current limit. Boost switching current goes through this pin through external resistor to
ground.
23
GNDLS_B
GND
24
25
26
27
28
EN
VDDIO
SCLK
SDO
SDI
HVI_D
Supply
HVI_D
LVO_D
HVI_D
Enable (high active) of the device.
I/O supply voltage, defines the interface voltage of digital I/O, for example, SPI.
SPI clock.
SPI data output.
SPI data input.
VCC3 regulator, for internal use only. TI recommends an external decoupling capacitor of 0.1 µF.
External load < 100 µA.
29
VCC3
LVO_A
30
31
GNDA
NU
GND
—
Analog ground.
Not used. Leave this pin open.
VCC5 regulator, for internal use only. Recommended external decoupling capacitor 1 µF. External load
< 100 µA.
32
VCC5
LVO_A
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
ADREF
NU
LVI_A
—
ADC reference of MCU. Connect to VDDIO
Not used. Leave this pin open.
NU
—
Not used. Leave this pin open.
NU
—
Not used. Leave this pin open.
NU
—
Not used. Connect this pin to ground.
Not used. Connect this pin to ground.
Not used. Connect this pin to ground.
Not used. Connect this pin to ground.
Not used. Connect this pin to ground.
Not used. Connect this pin to ground.
High-side input 3, digital input to drive the HS3.
Input HS 2, digital input to drive the HS2.
Input HS 1, digital input to drive the HS1.
Low-side input 3, digital input to drive the LS3.
Input LS 2, digital input to drive the LS2.
Input LS 1, digital input to drive the LS1.
NU
—
NU
—
NU
—
NU
—
NU
—
IHS3
IHS2
IHS1
ILS3
ILS2
ILS1
HVI_D
HVI_D
HVI_D
HVI_D
HVI_D
HVI_D
4
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
POS
MIN
MAX
UNIT
2.1
VS, VSH
VS
–0.3
60
V
Negative voltages with minimum serial resistor 5 Ω,
TA = 25°C
2.1a
–5
–2.5
–5
V
V
V
V
Negative voltages with minimum serial resistor 5 Ω,
TA = 105°C
2.1c
2.1b
2.1d
DC voltage
Negative voltages with minimum serial resistor 10 Ω,
TA = 25°C
VSH
Negative voltages with minimum serial resistor 10 Ω,
TA = 105°C
–2.5
2.2A Gate high-side voltage
2.2B Source high-side voltage
GHSx
SHSx
–9
–9
70
70
V
V
Gate-source high-side voltage
difference
GHSx-
SHSx
Externally driven, internal limited, see position 5.4 in
Electrical Characteristics
2.3
–0.3
15
V
2.4
2.5
Gate low-side voltage
GLSx
SLSx
–9
–9
20
7
V
V
Source low-side voltage
Gate-source low-side voltage
difference
GLSx-
SLSx
Externally driven, internal limited, see position 5.5 in
Electrical Characteristics
2.6
–0.3
15
V
2.7
2.9
Boost converter
BOOST, SW
VDDIO
–0.3
–0.3
–0.3
–0.3
–0.3
70
60
60
60
60
V
V
V
V
V
2.9a Analog input voltage
2.11
ADREF
RVSET
2.10 Digital input voltage
ILSx,IHSx, EN, DRVOFF, SCLK, NCS, SDI
Difference between GNDA and
GNDLS_B
2.13
GNDA, GNDLS_B
–0.3
–250
–0.3
0.3
250
6
V
V/µs
V
2.20 Maximum slew rate of SHSx pins, SRSHS
Analog and digital output
voltages
2.21
ERR, SDO, RO
2.22 Unused pins (connect to GND)
TEST
VCC5
VCC3
–0.3
–0.3
–0.3
0.3
6
V
V
V
2.24
Internal supply voltage
2.25
3.6
2.21
Forced input and output current
A
ERR, SDO, RO
–10
10
80
mA
mA
2.24
A
(3)
Short-to-ground current, IVCC5
Internal current limit
2.26 Short-to-ground current, IVCC3
Limited by VCC5
80
mA
nC
nC
2.27
VS = 12 V, ƒPWM = 20 kHz, 6 FETs ON/OFF per PWM cycle
VS = 24 V, ƒPWM = 20 kHz, 6 FETs ON/OFF per PWM cycle
200(4)
100(4)
Driver FET total gate charge (per
FET), Qgmax
2.28
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal, unless specified otherwise.
(3) IVCC5 is not specifying VCC5 output current capability for external load. The allowed external load on VCC5 is specified at position 3.18
in Recommended Operating Conditions.
(4) The maximum value also depends on PCB thermal design, modulation scheme, and motor operation time.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted)(1)(2)
POS
MIN
–40
–55
MAX
150
UNIT
°C
2.14 Operating virtual junction temperature, TJ
2.15 Storage temperature, Tstg
165
°C
6.2 ESD Ratings
POS
VALUE UNIT
±2000
All pins
2.17
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Pins 4, 6, and 14
All pins
±4000
Electrostatic
discharge
V(ESD)
V
2.18
2.19
±500
Corner pins (1, 12, 13, 24, 25, 36, 37,
and 48)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
POS
MIN
NOM
MAX UNIT
Full device functionality. Operation at VS = 4.75 V
only when coming from higher VS. Minimum VS
for startup = 4.85 V
Supply voltage, normal voltage
operation
3.1
VVS
4.75
40
V
Logic functional (during battery cranking after
coming from full device functionality)
3.2
VVSLO
VVDDIO
VCC3
Supply voltage, logic operation
Supply voltage for digital I/Os
Internal supply voltage
4
2.97
3(1)
40
5.5
3.3
V
V
V
3.3
VS > 4 V, external load current <100 µA,
decoupling capacitor typical 0.1 µF
3.14
VS > 6 V, external load current < 100 µA,
decoupling capacitor typical 1 µF
3.17
VCC5
Internal supply voltage
5.15
5.45
22
V
Boost converter enabled, see and for SHSx/SLSx
connections. EN_GDBIAS = 1
3.6A
3.61A
mA
mA
VS quiescent current normal
operation (boost converter
enabled, drivers not switching)
IVSn
Boost converter enabled, see and for SHSx/SLSx
connections. EN_GDBIAS = 0
22.3
3.6B
4.75 V < VS < 20 V, TA = 25°C to 125°C
4.75 V < VS < 20 V, TA = –40°C
20 < VS < 40 V, TA = 25°C to 125°C
20 < VS < 40 V, TA = –40°C
9
10
BOOST pin quiescent current
normal operation (drivers not
switching)
3.62B
3.6C
IBOOSTn
mA
mA
9.5
3.6C1
10.5
VS quiescent additional current
normal operation because of
RVSET thermal voltage output
enabled (boost converter
3.61B
IVSn
THERMAL_RVSET_EN = 1
0.6
enabled, drivers not switching)
Excluding FET gate charge current. 20-kHz all
gate drivers switching at the same time.
EN_GDBIAS = 1
3.6D
4
BOOST pin additional load
current because of switching gate
drivers
IBOOST,sw
mA
Excluding FET gate charge current. 20-kHz all
gate drivers switching at the same time.
EN_GDBIAS = 0
3.61D
5.4
VS quiescent current shutdown
(sleep mode) 1
VS = 14 V, no operation, TJ < 25°C, EN = Low,
total leakage current on all supply connected pins
3.75
IVSq_1
IVSq_2
20
30
µA
µA
VS quiescent current shutdown
(sleep mode) 2
VS = 14 V, no operation, TJ < 85°C, EN = Low,
total leakage current on all supply connected pins
3.75a
3.15
3.18
3.16
3.19
3.4
IVCC3
IVCC5
CVCC3
CVCC5
D
VCC3 output current
Intended for MCU ADC input
Intended for MCU ADC input
0
0
100
100
µA
µA
µF
µF
VCC5 output current
VCC3 decoupling capacitance
VCC5 decoupling capacitance
Duty cycle of bridge drivers
PWM switching frequency
0.075
0.5
0%
0
0.1
1
0.2
1.5
100%
22(1)
3.5
ƒPWM
kHz
(1) Maximum PWM allowed also depends on maximum operating temperature, FET gate charge current, VS supply voltage, modulation
scheme, and PCB thermal design.
6
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
Recommended Operating Conditions (continued)
POS
MIN
NOM
MAX UNIT
3.8
3.9
TJ
Junction temperature
–40
150
125
°C
°C
Operating ambient free-air
temperature
TA
With proper thermal connection
–40
6.4 Thermal Information
DRV3220-Q1
THERMAL METRIC(1)
PHP (HTQFP)
UNIT
48 PINS
25.7
10.3
6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.9
RθJC(bot)
0.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V(1), ƒPWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.4
ADREF / VDDIO
4.4.3
4.4.4
4.4.4a
4.4.5
4.4.5a
4.4.7
4.4.7a
4.4.8
4.4.8a
IADREF
ADREF bias current
ADREF = 3.3 V, pin to ground
300
3.894
5.9
µA
V
V
V
V
V
V
V
V
ADREF: 3.3-V setting by RVSET resistor
ADREF: 5-V setting by RVSET resistor
ADREF: 3.3-V setting by RVSET resistor
ADREF: 5-V setting by RVSET resistor
VDDIO: 3.3-V setting by RVSET resistor
VDDIO: 5-V setting by RVSET resistor
VDDIO: 3.3-V setting by RVSET resistor
VDDIO: 5-V setting by RVSET resistor
3.696 3.795
5.6 5.75
2.706 2.805
4.1 4.25
3.696 3.795
5.6 5.75
2.706 2.805
Vovadref
Overvoltage threshold, ADREF
2.904
4.4
Vuvadref
Vovvddio
Vuvvddio
Undervoltage threshold, ADREF
Overvoltage threshold, VDDIO
Undervoltage threshold, VDDIO
3.894
5.9
2.904
4.4
4.1
4.25
150
VDDIO = 3.3 V; ADREF = 3.3-V mode;
STAT6 bit[3:0] = 4’b0001
4.4.10 RRVSET33
4.4.11 RRVSET53
4.4.12 RRVSET35
4.4.13 RRVSET55
135
165
56.5
16.5
5.65
kΩ
kΩ
kΩ
kΩ
VDDIO = 5 V; ADREF = 3.3-V mode; STAT6
bit[3:0] = 4’b0100
46
51
15
RVSET resistance
VDDIO = 3.3 V; ADREF = 5-V mode; STAT6
bit[3:0] = 4’b1000
13.5
VDDIO = 5 V; ADREF = 5-V mode; STAT6
bit[3:0] = 4’b0010
4.6
5.1
4.4.30 RRVSETopen
4.4.31 RRVSETshort
4.4.32 VRVSETn40
4.4.33 VRVSET25
4.4.34 VRVSET125
Open
650
RVSET resistor error detection
RVSET output voltage
kΩ
Short
1.5
1.82
–40°C TJ, THERMAL_RVSET_EN = 1
25°C TJ, THERMAL_RVSET_EN = 1
125°C TJ, THERMAL_RVSET_EN = 1
1.67 1.745
1.445 1.535
1.085 1.195
1.625
1.305
V
VCC3 / VCC5 REGULATORS
4.4.14 VCC3
VCC3 regulator output voltage
VS > 4 V
VS > 4 V
3
3.15
2.85
3.3
3
V
V
VCC3 regulator undervoltage
threshold
4.4.15 VCC3UV
2.7
VCC3 regulator overvoltage
threshold(2)
4.4.16 VCC3OV
VS > 4 V
3.3
3.45
3.6
V
(1) Product life time depends on VS voltage, PCB thermal design, modulation scheme, and motor operation time. The product is designed
for 12-V and 24-V battery system.
(2) ADREF / VDDIO overvoltage and undervoltage is set by RVSET.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
Electrical Characteristics (continued)
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V(1), ƒPWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
5.15
4.6
TYP
MAX
5.45
5.45
UNIT
4.4.17 VCC5_1
4.4.18 VCC5_2
VCC5 regulator output voltage 1 VS > 6 V
5.3
V
VCC5 regulator output voltage 2 6 V > VS > 4.75 V
V
VCC5 regulator undervoltage
VS > 4.75 V
4.4.19 VCC5UV
4.4.20 VCC5OV
4.3
4.6
V
V
threshold
VCC5 regulator overvoltage
VS > 4.75 V
5.45
5.6
5.75
threshold
5.
GATE DRIVER
Gate-source voltage low, high-
side/low-side driver
5.1
5.2
5.3
VGS,low
RGSp
Active pulldown, Iload = –2 mA
0
0.2
330
4
V
Passive gate-source resistance
Vgs ≤ 200 mV
110
220
2
kΩ
kΩ
Semi-active gate-source
resistance
RGSsa
In sleep mode, VGS > 2 V
Gate driven low by gate driver,
CURR1, 3 = 01, SPI configurable
Gate driven low by gate driver(2)
,
5.3b
5.3c
5.3d
5.3f
IGSL01
IGSL00
IGSL10
IGSH01
IGSH00
IGSH11
IGSHsd
TYP × 0.65
TYP × 0.1
TYP × 0.65
TYP × 0.65
TYP × 0.1
TYP × 0.65
2
0.65
0.15
1.1
TYP × 1.35
TYP × 1.9
TYP × 1.35
TYP × 1.35
TYP × 1.9
TYP × 1.35
70
A
A
Low-side driver pullup/pulldown
current
CURR1, 3 = 00, SPI configurable
Gate driven low by gate driver,
CURR1, 3 = 11, SPI configurable
A
Gate driven low by gate driver,
CURR0, 2 = 01, SPI configurable
0.65
0.15
1.1
A
High-side driver pullup/pulldown Gate driven low by gate driver(2)
,
5.3g
5.3h
5.3i
A
current
CURR0, 2 = 00, SPI configurable
Gate driven low by gate driver,
CURR0, 2 = 11, SPI configurable
A
High-side/low-side driver
shutdown current
30
mA
5.4
5.5
VGS,HS,high
VGS,LS,high
High-side output voltage
Low-side output voltage
Iload = –2 mA; 4.75 V < VS < 40 V
Iload = –2 mA
9
9
13.4
13.4
V
V
After ILx/IHx rising edge, Cload = 10 nF,
CURR1, 3 = 10, VGS = 1 V
5.27
tDon
Propagation on delay time
Accuracy of dead time
100
200
200
350
ns
5.31
5.32
5.32a
Adt
If not disabled in CFG1
–15%
–5
15%
5
IHSxlk_1
IHSxlk_2
EN = L, SHSx = 1.5 V, TJ < 125°C
EN = L, SHSx = 1.5 V, 125°C < TJ < 150°C
µA
µA
Source leak current, total
leakage current of source pins
–40
40
ILx/IHx falling edge to VGS,LS,high(VGS,HS,high) –
1 V Ciss = 10 nF, CURR1,3 = 10,
5.29
5.30
tDoff
Propagation off delay time(3)
100
350
50
ns
ns
Propagation off delay time
difference(3)
LSx to LSy and HSx to HSy Cload = 10 nF,
CURR1,3 = 10, VGS,LS,high(VGS,HS,high) – 1 V
tDoffdiff
Difference between propagation For each gate driver in each channel:
5.30a
tDon_Doff_diff
on delay time and propagation
Cload = 10 nF, CURR1, 3 = 10, VGS = 1 V
(rising), VGS,LS,high(VGS,HS,high) – 1 V (falling)
150
ns
off delay time(3)
Propagation off (EN) deglitch
time(3)
5.30c
5.30d
5.30e
tENoff
tSD
After falling edge on EN
After falling edge on EN
After rising edge on DRVOFF
2.5
6
12
24
10
µs
µs
µs
Time until gate drivers initiate
shutdown(3)
12
Time until gate drivers initiate
shutdown(3)
tSDDRV
(3) Ensured by characterization.
8
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
Electrical Characteristics (continued)
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V(1), ƒPWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6.
BOOST CONVERTER
Boost output voltage excluding
switching ripple and response
delay.
6.1
VBOOST
VBOOSTOV
IBOOST
BOOST – VS voltage
14
64
15
16.5
70
V
V
Boost output voltage overvoltage
with respect GND
6.1b
6.2
67.5
External load current including external
MOSFET gate charge current
BOOST – VS > VBOOSTUV
Output current capability
40
mA
BOOST – VS > VBOOSTUV; ensured by
characterization(4)
6.3
1.8
2.5
3
ƒBOOST
Switching frequency
MHz
BOOST – VS > VBOOSTUV; VS < 6 V; ensured
6.31
6.4
1.1
7
3
8
(4)
by characterization
VBOOSTUV
VBOOSTUV2
Undervoltage shutdown level
BOOST – VS voltage
BOOST – GND voltage
V
V
Undervoltage condition that
device may enter RESET state
6.4a
10
Filter time for undervoltage
detection
6.5
tBCSD
5
6
200
100
µs
mV
ns
Voltage at GNDLS_B pin at
VGNDLS_B,off which boost FET switches off
because of current limit
6.7
110
150
Delay of the GNDLS_B current
limit comparator
6.7a
tSW,off
Specified by design
6.8
6.9
6.9a
7.
ISW,fail
Internal second-level current limit GNDLS_B = 0 V
S ≥ 6; ISW = VGNDLS_B,off / 0.33 Ω
840
1600
1.5
2
mA
Ω
V
0.25
Rdson_BSTfet
Rdson resistance boost FET
VS < 6; ISW= VGNDLS_B,off / 0.33 Ω
Ω
DIGITAL INPUTS
All digital inputs NCS, DRVOFF, ILSx, IHSx,
SDI
7.1
INL
Input low threshold
VDDIO × 0.3
0.7
V
7.1a
7.1b
ENH
ENL
EN input high threshold
EN input low threshold
VS > 4 V
VS > 4 V
2.7
V
V
All digital inputs NCS, DRVOFF, ILSx, IHSx,
SDI
7.2
7.3
INH
Input high threshold
VDDIO × 0.7
0.3
V
V
All digital inputs EN, NCS, DRVOFF, ILSx,
IHSx, SDI, VDDIO = 5 V
0.4
Inhys
Input hysteresis
All digital inputs EN, NCS, DRVOFF, ILSx,
IHSx, SDI, VDDIO = 3.3 V
7.3a
7.4
0.2
0.3
V
Rpd,EN
Input pulldown resistor at EN pin EN
140
200
360
5
kΩ
ms
Power-up time after EN pin high
7.4a
tdeg,ENon
ERR = L → H
from sleep mode to active mode
Input pullup resistance
7.5
7.6
Rpullup
NCS, DRVOFF
200
100
280
140
400
200
kΩ
kΩ
Rpulldown
Input pulldown resistance
ILSx, IHSx, SDI , SCLK Input voltage = 0.1 V
ILSx, IHSx, SDI, SCLK Input voltage =
VDDIO
7.6a
8.
Rpulldown
Input pulldown current
4
50
µA
DIGITAL OUTPUTS
All digital outputs: SDO, I = ±2 mA; VDDIO in
functional range(5)
8.1
OH1
OL1
Output high voltage 1
VDDIO × 0.9
V
V
All digital outputs: SDO, I = ±2 mA; VDDIO in
functional range
8.2
Output low voltage 1
VDDIO × 0.1
8.1
8.2
9.
OH2
OL2
Output high voltage 2
Output low voltage 2
ERR I = –0.2 mA; VDDIO in functional range
ERR I = +0.2 mA; VDDIO in functional range
VDDIO × 0.9
0.1
V
V
VDDIO × 0.1
2
VDS, VGS, MONITORING
VSCTH VDS short-circuit threshold range If not disabled in CFG1
9.1
V
(4) During startup when BOOST – VS < VBOOSTUV , ƒBOOST is typically 1.25 MHz.
(5) All digital outputs have a push-pull output stage between VDDIO and ground.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
Electrical Characteristics (continued)
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V(1), ƒPWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
0.1-V to 0.5-V threshold setting
0.6-V to 2-V threshold setting
MIN
TYP
MAX
UNIT
–50
50
mV
9.2
Avds
Accuracy of VDS monitoring
–10%
10%
Only rising edge of VDS comparators are
filtered
9.3
tVDS
Detection filter time
5
µs
9.4
Vgserr+_1
Vgserr–
tVGS
VGS error detection 1
VGS error detection
Detection filter time
Detection mask time
STAT7, IHSx (ILSx) = H
STAT7, IHSx (ILSx) = L
CFG6[5:4]
7
8.5
2
V
V
9.5
9.6
1.0
2.5
µs
µs
9.6a
10.
tVGSm
CFG6[2:0]
THERMAL SHUTDOWN
10.1
10.2
10.3
10.4
10.5
10.6
12.
Tmsd0
Tmsd1
Tmsd2
Thmsd
tTSD1
tTSD2
Thermal recovery
Specified by characterization
Specified by characterization
Specified by characterization
Specified by characterization
Specified by characterization
Specified by characterization
130
140
170
153
165
195
40
178
190
220
°C
°C
°C
°C
µs
µs
Thermal warning
Thermal global reset
Thermal shutdown×2 hysteresis
Thermal warning filter time
Thermal shutdown×2 filter time
40
45
50
12
2.5
6
VS MONITORING
Overvoltage shutdown level
Programmable CFG5 mode1, 12-V/24-V
mode
12.1
VVS,OVoff0
VVS,OVoff1
VVS, OVon1
VVS,OVoff2
VVS, OVon2
VVS,OVoff3
VVS, OVon3
VVS,UVoff
29
27.5
26.5
32
38
30.5
29.5
35
V
V
V
V
V
V
V
V
V
range(6)
12.1a
12.1b
12.1c
12.1d
12.1e
12.1f
12.2
Overvoltage shutdown level(6)
29-V threshold setting
29
28
Recovery level form overvoltage
shutdown(6)
Overvoltage shutdown level(6)
29-V threshold setting
33-V threshold setting
33.5
32.5
38
Recovery level form overvoltage
shutdown(6)
Overvoltage shutdown level(6)
33-V threshold setting
31
34
38-V threshold setting
36.5
35.5
4.5
39.5
38.5
4.75
4.85
Recovery level form overvoltage
shutdown(6)
Undervoltage shutdown level(6)
38-V threshold setting
37
VS is falling from higher voltage than 4.75 V
Minimum VS for device startup
Recovery level form
12.2a
VVS,UVon
4.6
undervoltage shutdown(6)
Filter time for
12.3
tVS,SHD
overvoltage/undervoltage
shutdown
5
6
µs
(6) Shutdown signifies predriver shutdown, not VCC3/VCC5 regulator shutdown.
10
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
6.6 Serial Peripheral Interface Timing Requirements
POS
13
MIN NOM MAX UNIT
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
ƒSPI
tSPI
thigh
tlow
tsucs
td1
SPI clock (SCLK) frequency
SPI clock period(2)
High time: SCLK logic high duration(2)
Low time: SCLK logic low duration(2)
Setup time NCS: time between falling edge of NCS and rising edge of SCLK(2)
Delay time: time delay from falling edge of NCS to data valid at SDO(3)
Setup time at SDI: setup time of SDI before the rising edge of SCLK(2)
Delay time: time delay from falling edge of SCLK to data valid at SDO(3)
Hold time: time between the falling edge of SCLK and rising edge of NCS(2)
SPI transfer inactive time (time between two transfers)(2)
Tri-state delay time: time between rising edge of NCS and SDO in tri-state(2)
4(1)
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
250
90
90
tSPI / 2
60
60
tsusi
td2
30
0
thcs
45
13.10 thlcs
13.11 ttri
250
30
(1) The maximum SPI clock tolerance is ±10%.
(2) Ensured by characterization.
(3) Ensured by characterization.
NCS
thcs
thlcs
tsucs
SCLK
tsucs
thigh
tlow
SDI
tsusi
tsusi
SDO
td1
td2
ttri
td1
Figure 1. SPI Timing Parameters
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
6.7 Typical Characteristics
45
20
19.5
19
VS = 36 V
VS = 14 V
VS = 4.75 V
VS = 36 V
VS = 14 V
VS = 4.75 V
40
35
30
25
20
15
10
5
18.5
18
17.5
17
0
16.5
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
D001
D002
Figure 2. VS Quiescent Current Shutdown
Figure 3. VS Quiescent Current Shutdown
12
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
7 Detailed Description
7.1 Overview
The DRV3220-Q1 is designed to control 3-phase brushless DC motors in automotive applications using pulse-
width modulation. Three high-side and three low-side gate drivers can be switched individually with low
propagation delay. The input logic prevents simultaneous activation of the high-side and low-side driver of the
same channel. A configuration and status register can be accessed through a SPI communication interface.
7.2 Functional Block Diagram
Battery voltage
5 ꢀ
22 µH
1 …F
Controller
GNDLS_B
330 mꢀ
6x VDS Monitor
VSH
Safety and Diagnostic
- Overtemperature
- Overvoltage,
+
œ
Undervoltage
- Watch dog
3 Phase Gate Driver
3 × PowerStage
Rgate
ERR
- Clock Monitoring
- Overtemperature
Detection
- Short Circuit
- Shoot-through
Protection
GHSx(1)
SHSx(1)
VDDIO
ADREF
BLDC
Motor
- VDS/VGS Monitoring
- Dead Time Control
GLSx(1)
SLSx(1)
Rgate
Level
shift
VDDIO
RVSET
EN
NCS
SCLK
SDI
Control Logic
- Program Gate Current
- Program Gain
- Sleep Mode Control
SDO
Power Supply
IHSx, ILSx
DRVOFF
Bridge Driver
Reference and Bias
Digital
VCC5
VCC3
Bandgap,
Bias, Oscillator
Safety Relevant
1 …F
0.1 …F
Copyright © 2017, Texas Instruments Incorporated
(1) x = 1, 2, 3
(2) y = 1, 2, 3
(3) An external reference voltage (VCC5 or VCC3) cannot be used for ADREF voltage.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
7.3 Programming
7.3.1 SPI
The SPI slave interface is used for serial communication with the external SPI master (external MCU). The SPI
communication starts with the NCS falling edge and ends with NCS rising edge. The NCS high level keeps the
SPI slave interface in reset state, and the SDO output in tri-state.
7.3.1.1 Address Mode Transfer
The address mode transfer is an 8-bit protocol. Both SPI slave and SPI master transmit the MSB first.
1
2
3
4
5
6
7
8
NCS
SCLK
SDI
R7
D7
R6
D6
R5
D5
R4
D4
R3
D3
R2
D2
R1
D1
R0
D0
X
X
SDO
NOTE: SPI master (MCU) and SPI slave (DRV3220-Q1) sample received data on the falling SCLK edge and transmit on the
rising SCLK edge.
Figure 4. Single 8-Bit SPI Frame/Transfer
After the NCS falling edge, the first word of 7 bits are address bits followed by the RW bit. During first address
transfer, the device returns the STAT1 register on SDO.
Each complete 8-bit frame will be processed. If NCS goes high before a multiple of 8 bits is transferred, the bits
are ignored.
7.3.1.1.1 SPI Address Transfer Phase
Figure 5. SPI Address Transfer Phase Bits
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
RW
ADDR [6:0] Register address
RW Read and write access
RW = 0: Read access. The SPI master performs a read access to selected register. During
following SPI transfer, the device returns the requested register read value on SDO, and
device interprets SDI bits as a next address transfer.
RW = 1: Write access. The master performs a write access on the selected register. The
slave updates the register value during next SPI transfer (if followed immediately) and
returns the current register value on SDO.
7.3.1.2 SPI Data Transfer Phase
14
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
Figure 6. SPI Data Transfer Phase Bits
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
DATA7
DATA6
DATA5
DATA4
ADDR3
DATA2
DATA1
DATA0
DATA [7:0] Data value for write access (8-Bit).
The table shows data value encoding scheme during a write access It is possible to mix the
two access modes (write and read access) during one SPI communication sequence (NCS =
0). The SPI communication can be terminated after single 8-bit SPI transfer by asserting
NCS = 1. Device returns STAT1 register (for the very first SPI transfer after power-up) or
current register value that was addressed during SPI Transfer Address Phase.
7.3.1.3 Device Data Response
Figure 7. Device Data Response Bits
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
REG7
REG6
REG5
REG4
REG3
REG2
REG1
REG0
REG [7:0] Internal register value. All unused bits are set to 0.
Figure 8 shows a complete 16-bit SPI frame. Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, and Figure 14
show the frame examples.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NCS
SCLK
SDI
R7
D7
R6
D6
R5
D5
R4
D4
R3
D3
R2
D2
R1
D1
R0
D0
R7
D7
R6
D6
R5
D5
R4
D4
R3
D3
R2
D2
R1
D1
R0
D0
X
X
SDO
8-bit SPI Transfer
8-bit SPI Transfer
16-bit SPI Frame
SPI Master (MCU) and SPI slave (DRV3220-Q1) sample received data on the rising SCLK edge, and transmit data
on the falling SCLK edge
Figure 8. 16-Bit SPI Frame
NCS
ADDR1, RW = 1 (WR)
1st Transfer
WR DATA1
2nd Transfer
ADDR2, RW = 0 (RD)
3rd Transfer
SDI
Zero Vector
SDO
Status Flags
Response to Transfer 1
Status Flags
Response to Transfer 3
Figure 9. Write Access Followed by Read Access
NCS
SDI
ADDR1, RW = 0 (RD)
1st Transfer
ADDR2, RW = 0 (RD)
—Zero Vector“
Zero Vector
3rd Transfer
Status Flags
Response to Transfer 1
Status Flags
Response to Transfer 3
SDO
Figure 10. Read Access Followed by Read Access
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
NCS
ADDR1, RW = 1 (WR)
WR DATA1
2nd Transfer
ADDR2, RW = 1 (WR)
3rd Transfer
WR DATA2
4th Transfer
SDI
1st Transfer
SDO
Status Flags
Response to Transfer 1
Status Flags
Response to Transfer 3
Figure 11. Write Access Followed by Write Access
NCS
SDI
ADDR1, RW = 0 (RD)
1st Transfer
ADDR2, RW = 1 (WR)
2nd Transfer
WR DATA2
3rd Transfer
Zero Vector
Status Flags
Status Flags
Response to Transfer 1
Response to Transfer 2
SDO
Figure 12. Read Access Followed by Write Access
NCS
SDI
ADDR1, RW = 0 (RD)
1st Transfer
ADDR2, RW = 0 (RD)
2nd Transfer
ADDR3, RW = 1 (WR)
3rd Transfer
WR DATA3
4th Transfer
SDO
Status Flags
Response to Transfer 1
Response to Transfer 2
Response to Transfer 3
Figure 13. Read Access Followed by Read Access Followed by Write Access
NCS
SDI
ADDR1, RW = 0 (RD)
1st Transfer
ADDR2, RW = 0 (RD)
2nd Transfer
ADDR3, RW = 0 (RD)
3rd Transfer
Zero Vector
SDO
Status Flags
Response to Transfer 1
Response to Transfer 2
Response to Transfer 3
Figure 14. Read Access Followed by Read Access Followed by Read Access
16
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
7.4 Register Maps
Table 1. Register Address Map and Summary Table
Reset Event(2)
(bit wide exception)
CRC
Check
Address Name
Reset Value
Access State(1)
Section
W/R : D,
A([6:3])
0×01
Configuration register 0 (CFG0)
8'h3F
Yes
RST1-4
Go
R : A(7,[2:0], SF
W/R: D
R: A, SF
0×02
0×04
0×05
0×06
0×07
0×08
0×09
Configuration register 1 (CFG1)
8'h3F
8'h00
8'h00
8'h00
8'h00
8'hC0
8'h80
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RST1-4
RST1-4
RST1-4
RST1-4
RST1-4
RST1
Go
Go
Go
Go
Go
Go
Go
W/R: D
R: A, SF
HS 1/2/3 drive register (CURR0) ON
LS 1/2/3 drive register (CURR1) ON
HS 1/2/3 drive register (CURR2) OFF
LS 1/2/3 drive register (CURR3) OFF
W/R: D
R: A, SF
W/R: D
R: A, SF
W/R: D
R: A, SF
W/R: D
R: A, SF
Safety/error configuration register
(SECR1)
W/R: D
R: A, SF
Safety function configuration register
(SFCR1)
RST1-3
0×0A
0×0B
0×0C
0×0D
0×0E
Status register 0 (STAT0)
Status register 1 (STAT1)
Status register 2 (STAT2)
Status register 3 (STAT3)
Status register 4 (STAT4)
8'h00
8'h80
8'h00
8'h03
8'h00
No
No
No
No
No
R: D, A, SF
R: D, A, SF
R: D, A, SF
R: D, A, SF
R: D, A, SF
RST1-4
RST1-3
RST1-3
RST1-3
RST1-3
Go
Go
Go
Go
Go
RST1-3
(Bit[4]:RST1)
0×0F
Status register 5 (STAT5)
8'h03
No
R: D, A, SF
Go
0×10
0×11
Status register 6 (STAT6)
Status register 7 (STAT7)
8'h00
8'h00
No
No
R: D, A, SF
R: D, A, SF
RST1-3
RST1-4
Go
Go
RST1-4
(Bit[0]:RST1)
0×12
0×13
Status register 8 (STAT8)
8'h00
8'h00
No
No
R: D, A, SF
R: D, A, SF
Go
RST1-3
(Bit[3:1]:RST1)
Safety error status
(SAFETY_ERR_STAT)
Go
Go
0×14
0×15
0×16
Status register 9 (STAT9)
Reserved 1
8'h00
8'h00
8'h00
No
No
No
R: D, A, SF
W/R: D, A, SF
W/R: D, A, SF
RST1-3
RST1-3
RST1-3
Reserved 2
SPI transfer write CRC register
(SPIWR_CRC)
0×1E
0×1F
0×20
8'h00
8'hFF
8'h01
No
No
No
W/R: D, A, SF
R: D, A, SF
RST1-3
RST1-3
RST1-3
Go
Go
Go
SPI transfer read CRC register
(SPIRD_CRC)
W/R: D
R: A, SF
SAFETY_CHECK_CTRL register (
SFCC1)
W/R: D, A
R: SF
0×21
0×22
CRC control register (CRCCTL)
8'h00
N/A
No
No
RST1-3
RST1-3
Go
Go
W/R: D
R: A, SF
CRC calculated check sum register
(CRCCALC)
0×23
0×24
Reserved 3
8'h00
8'h00
No
No
W/R: D, A, SF
R: D, A, SF
RST1-3
RST1-3
HS/LS read back (RB0)
Go
Go
Go
Go
W/R: D, A
R: SF
0×25
0×26
0×27
HS/LS count control (RB1)
HS/LS count (RB2)
8'h00
8'h00
8'hAB
No
No
RST1-4
RST1-4
RST1-4
R: D, A, SF
W/R: D
R: A, SF
Configuration register 3 (CFG3)
Yes
(1) W/R: Write and Read access possible, W: Write access possible, R: Read access possible
D: DIAGNOSITC STATE, A: ACTIVE STATE, SF: SAFE STATE, SY: STANDBY STATE, R: RESET
(2) RST1: Power up, RST2: System clock error detected by clock monitor RST3: VCC3 UV/OV or from other state to RESET, RST4: LBIST
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback 17
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
Register Maps (continued)
Table 1. Register Address Map and Summary Table (continued)
Reset Event(2)
(bit wide exception)
CRC
Check
Address Name
Reset Value
Access State(1)
Section
Go
W/R: D
R: A, SF
0×28
0×29
0×2A
0×2B
0×2C
0×2D
Configuration register 4 (CFG4)
8'h00
Yes
Yes
No
RST1-4
W/R: D
R: A, SF
Configuration register 5 (CFG5)
CSM unlock (CSM_UNLOCK1)
CSM unlock (CSM_UNLOCK2)
Reserved 4
8'hAB
RST1-3
RST1-4
RST1-4
RST1-4
RST1-3
Go
W/R: D
R: A, SF
8'h00
Go
W/R: D
R: A, SF
8'h3F
No
Go
W/R: D
R: A, SF
8'h00
Yes
Yes
W/R: D
R: SF, A
Safety BIST control register 1
(SAFETY_BIST_CTL1)
8'h00
Go
Go
0×2E
0×2F
SPI test register (SPI_TEST)
Reserved 5
8'h00
8'h00
No
No
W/R: D, A, SF
W/R: D, A, SF
RST1-4
RST1-3
W/R: D
R: SF, A
RST1-3
(Bit[5]:RST1)
Safety BIST control register 2
(SAFETY_BIST_CTL2)
0×30
0×31
0×32
8'h00
8'h02
8'h08
Yes
Yes
Yes
Go
Go
Go
W/R: D
R: SF, A
Watch dog timer configuration register
(WDT_WIN1_CFG)
RST1-4
RST1-4
W/R: D
R: SF, A
Watch dog timer configuration register
(WDT_WIN2_CFG)
W/R: D
R: SF, A
Watch dog timer TOKEN register
(WDT_TOKEN_FDBCK)
0×33
0×34
0×35
0×36
0×37
8'h04
8'h40
8'h00
8'hC0
8'hEC
Yes
No
RST1
Go
Go
Go
Go
Go
Watch dog timer TOKEN register
(WDT_TOKEN_VALUE)
R: D, SF, A
W/R: D, A, SF
R: D, A, SG
RST1-4
RST1-4
RST1-4
RST1-4
Watch dog timer ANSWER register
(WDT_ANSWER)
No
Watch dog timer status register
(WDT_STATUS)
No
W/R: D
R: SF, A
Watch dog failure detection configuration
register (WD_FAIL_CFG)
Yes
W/R: D
R: A, SF
0×38
0×39
Configuration register 6 (CFG6)
Configuration register 7 (CFG7)
8'h10
8'h13
Yes
Yes
RST1-4
RST1-4
Go
Go
Go
W/R : D
R : A, SF
W/R : D
R : A, SF
0×3A
0×3B
Configuration register 8 (CFG8)
Reserved 6
8'h20
0
Yes
—
RST1-4
—
—
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV3220-Q1 is a predriver for automotive applications featuring three-phase brushless DC-motor control.
Because this device has a boost regulator for charging high-side gates, it can handle gate charges of 250 nC. A
boost converter allows full control on the power-stages even for a low battery voltage down to 4.75 V.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
8.2 Typical Application
8.2.1 Three-Phase Motor Drive-Device for Automotive Application
From MCU
PGND
VBAT
10 ꢀ(3)
5
2
ë{I
37
bÜ
{[{3
Rgate
bÜ 38
Q3LS
Q3HS
D[{3
{I{3
DI{3
GNDA
SLS2
D[{2
{I{2
DI{2
Dbꢀ!
SLS1
D[{1
{I{1
GHS1
1
3
bÜ
bÜ
36
35
Rgate
4
16
8
2.2 mF
PGND
ë//3
29
10
32
Rgate
0.1 µF
1 µF
DRV3220-Q1(1)
Q2LS
Q2HS
9
BLDC
Motor
Çꢁ{Ç (Dbꢀ)
ë//5
6
Rgate
7
30
12
11
14
13
2.2 mF
PGND
ꢁww
17
19
To MCU
Rgate
Q1LS
Q1HS
wë{ꢁÇ
ꢁb
Rgate
From TPS6538x-Q1,
connect to ENDRV
24
2.2 mF
PGND
330 mꢀ
D1(5)
MCU SPI
10 µF
5 ꢀ(3)
L1(4)
22 µH
1 …F
0.1 µF
0.1 µF
Copyright © 2017, Texas Instruments Incorporated
(1) This schematic of the DRV3220-Q1 48-pin HTQFP does not provide a true representation of physical pin locations.
(2) Use same supply from the TPS6538x as the supply used for the MCU IO.
(3) Resistor not required for reverse protected battery.
(4) L1 = B82442A1223K000 INDUCTOR, SMT, 22 uH, 10%, 480 mA). The maximum inductor current must be more than
VGNDLS_B / 330 mΩ.
(5) D1 = SS28 (DIODE, SMT, SCHOTTKY, 80 V, 2 A). A fast recovery diode is recommended.
(6) QxHS, QxLS = IRFS3004PBF (HEXFET, N-CHANNEL, POWER MOSFET, D2PACK)
(7) Rgate = Must be adjust based on system requirement such as EMI, Slew rate, and power
Figure 15. Typical Application Diagram
8.3 System Example
Figure 16 shows a typical system example for an electric power-steering system.
20
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
FR
Flexray
CAN
CAN
IGN
VBAT
BOOST
CAN
Supply
CAN
FR
OUT
OUT
EN
EN
WakeUp
Relay Driver
Voltage
Monitoring
VBAT
µC IO
Supply
Preregulator
KL30
3 × PowerStage
NHET
Charge
Pump
µC Core
Supply
- Input Capture
- Input Capture
VSH
Vds
Mon
Bandgap
Ref 2
GHSx
SHSx
SPR
Switch
Motor
Protected
Sensor
Supply
- PWM
Bridge
Driver
Voltage
Monitoring
3 × IHSx
3 × ILSx
GLSx
SLSx
Sensors
WD
OFF
Reset /
Enable
nRESET
nERROR
SPI
x = [1..3]
ADC1
ADC2
µC ERROR
Monitor
Q&A
Watchdog
Diagnose
and Config
SPI
SPI
Error Monitoring:
- VDS Monitoring
- Shoot-through
- Voltage Monitoring on
VBAT, VBOOST, and
internal supplies.
- Temperature Warning
- And so forth
Tj Over
Temp
shutdown
Ta/Tj Over
Temp
shutdown
Bridge Error
Monitoring
Diagnose
and Config
INT
TPS6538x-Q1
TMS570
DRV3220-Q1
Analog Sensor Signal
Digital Sensor Signal
Power Supply
Bridge Driver
Networks
Copyright © 2017, Texas Instruments Incorporated
Safety Diagnostics
Figure 16. Typical System – Electrical Power Steering Example
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: DRV3220-Q1
DRV3220-Q1
SLVSDM3 –FEBRUARY 2017
www.ti.com
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range of 4.75 V to 40 V. The protection circuit
must be placed for protection against reverse supply connection.
10 Layout
10.1 Layout Guidelines
Use the following guidelines when designing a PCB for the DRV3220-Q1:
•
In addition to the GND pins, the DRV3220-Q1 makes an electrical connection to GND through the
PowerPAD. Always check that the PowerPAD has been properly soldered (see PowerPAD™ Thermally
Enhanced Package [SLMA002]).
•
•
The VS bypass capacitors should be placed close to the power supply terminals. See the VS box in Figure 17
Place the VCC5 and VCC5 bypass capacitors close to the corresponding pins with a low impedance path to
the ground plane pin (pin 16). See the VCC3 VCC5 bypass box in Figure 17.
•
•
•
AGND should all be tied to the ground plane through a low impedance trace or copper fill.
Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
Try to clear the space around and below the DRV3220-Q1 to allow for better heat spreading from the
PowerPAD.
•
•
Keep the BOOST components close to the device and current loops small. See the BOOST boxes in
Figure 17.
Place the GNDLS_B resistor close to the device pin. See the GNDLS_B box in Figure 17.
10.2 Layout Example
BOOST
Bypass
SENSE
SENSE
SENSE
BOOST
L
BOOST
D
VS
VCC3
VCC5
Bypass
Figure 17. Layout Schematic
22
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV3220-Q1
DRV3220-Q1
www.ti.com
SLVSDM3 –FEBRUARY 2017
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
•
DRV3220-Q1 Applications in 24-V Automotive Systems
DRV3220-Q1 Negative Voltage Stress on Source Pins
Electric Power Steering Design Guide with DRV3220-Q1
PowerPAD™ Thermally Enhanced Package
Protecting Automotive Motor Drive Systems from Reverse Polarity Conditions
Q&A Watchdog Timer Configuration for DRV3220-Q1
TPS653850-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant Applications
TPS653853-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant Applications
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: DRV3220-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV3220QPHPRQ1
ACTIVE
HTQFP
PHP
48
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV3220Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV3220QPHPRQ1
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PHP 48
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
DRV3220QPHPRQ1
1000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PHP 48
7 x 7, 0.5 mm pitch
TQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226443/A
www.ti.com
PACKAGE OUTLINE
PHP0048G
PowerPADTM HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
7.2
6.8
B
NOTE 3
37
48
PIN 1 ID
1
36
7.2
6.8
9.2
TYP
8.8
NOTE 3
12
25
13
24
A
0.27
48X
44X 0.5
0.17
0.08
C A B
4X 5.5
1.2 MAX
C
SEATING PLANE
SEE DETAIL A
0.08
(0.13)
TYP
13
24
12
25
0.25
(1)
GAGE PLANE
5.17
3.89
49
0.75
0.45
0.15
0.05
0 -7
A
16
36
DETAIL A
TYPICAL
1
48
37
5.17
3.89
4X (0.109) NOTE 5
4225861/A 4/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
5. Feature may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PHP0048G
PowerPADTM HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
6.5)
NOTE 10
(5.17)
SYMM
48
37
SOLDER MASK
DEFINED PAD
48X (1.6)
1
36
48X (0.3)
SYMM
49
(5.17)
(1.1 TYP)
(8.5)
44X (0.5)
12
25
(R0.05) TYP
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
13
24
(1.1 TYP)
SEE DETAILS
(8.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225861/A 4/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PHP0048G
PowerPADTM HTQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(5.17)
BASED ON
0.125 THICK STENCIL
SEE TABLE FOR
SYMM
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
48
37
48X (1.6)
1
36
48X (0.3)
(8.5)
(5.17)
SYMM
49
BASED ON
0.125 THICK
STENCIL
44X (0.5)
12
25
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
24
13
(8.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
5.78 X 5.78
5.17 X 5.17 (SHOWN)
4.72 X 4.72
0.125
0.150
0.175
4.37 X 4.37
4225861/A 4/2020
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明