DRV602PW [TI]
DIRECTPATH™, 2Vrms Line Driver with Adjustable gain; DIRECTPATH ™ ，具有可调增益2Vrms的线路驱动器
| 型号： | DRV602PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIRECTPATH™, 2Vrms Line Driver with Adjustable gain |
| 文件： | 总12页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572–DECEMBER 2008
DIRECTPATH™, 2Vrms Line Driver with Adjustable gain
Designed using TI's patented DIRECTPATH™
technology, the DRV602 is capable of driving 2Vrms
1
FEATURES
234
•
DIRECTPATH™
into a 2.5kΩ load with 3.3V supply voltage. The
device has differential inputs and uses external gain
setting resistors, that supports a gain range of ±1V/V
to ±10V/V. The use of external gain resistors also
allows the implementation of a 2nd order low pass
filter to compliment DAC's and SOC converters. The
line output of the DRV602 has ±8kV IEC ESD
protection. The DRV602 (referred to as the '602) has
build-in shutdown control for pop-free on/off control.
–
–
–
Eliminates Pop/Clicks
Eliminates Output DC-Blocking Capacitors
Provides Flat Frequency Response
20Hz–20kHz
•
Low Noise and THD
–
–
–
SNR > 102 dB
Typical VN < 15 µVms
THD+N < 0.05% 20 Hz–20 kHz
Using the DRV602 in audio products can reduce
component count compared to traditional methods of
generating a 2Vrms output. The DRV602 doesn't
require a power supply greater than 3.3V to generate
its 5.6VPP output, nor does it require a split rail power
supply. The DRV602 integrates its own charge pump
to generate a negative supply rail that provides a
clean, pop-less ground biased 2Vrms output.
•
•
2Vrms Output Voltage into 2.5 kΩR Load With
3.3V Supply Voltage
Differential Input
APPLICATIONS
•
•
•
•
Set-Top Boxes
PDP / LCD TV
Blu-ray Disc™, DVD-Players
Home Theater in a Box
The DRV602 is available in a 14 pin TSSOP
package.
If higher SNR, trimmed DC-offset and external
undervoltage-mute functions are beneficial in the
application, TI recommends the footprint compatible
DRV603 (SLOS617).
DESCRIPTION
The DRV602PW is a 2Vrms Pop-less stereo line
driver designed to allow the removal of the output
dc-blocking capacitors for reduced component count
and cost. The device is ideal for single supply
electronics where size and cost are critical design
parameters.
-
RIGHT
DAC
SOC
+
DRV602
+
LEFT
DAC
-
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
DIRECTPATH, TI FilterPro are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
DRV602
SLOS572–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PW (TSSOP) PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
+INR
-INR
OUTR
SGND
EN
+INL
-INL
OUTL
NC
PGND
PVDD
CP
VDD
CN
Charge Pump
8
PIN FUNCTIONS
PIN
TSSOP (PW)
I/O(1)
DESCRIPTION
NAME
+INR
-INR
OUTR
SGND
EN
1
2
I
I
Right channel OPAMP positive input
Right channel OPAMP negative input
Right channel OPAMP output
Signal ground
3
O
I
4
5
I
Enable input, active high
Supply voltage
VDD
CN
6
O
I/O
I/O
I
7
Charge pump flying capacitor negative terminal
Charge pump flying capacitor positive terminal
Positive supply
CP
8
PVDD
PGND
NC
9
10
11
12
13
14
I
Power ground
No internal connection
OUTL
-INL
O
I
Left channel OPAMP output
Left channel OPAMP negative input
Left channel OPAMP positive input
+INL
I
(1) I = input, O = output, P = power
2
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572–DECEMBER 2008
ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range
VALUE
–0.3 V to 5.5
VSS – 0.3 to VDD + 0.3
> 600
UNIT
V
Supply voltage, VDD to GND
Input voltage
VI
V
RL
Minimum load impedance
EN to GND
Ω
–0.3 to VDD +0.3
0 to 70
V
TJ
Maximum operating junction temperature range,
Storage temperature range
°C
°C
kV
Tstg
–40 to 150
±8
ESD IEC Contact ESD Protection per IEC6100-4-2, on output pins measured on DRV602EVM
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION
TA
PACKAGE(1)
DESCRIPTION
0°C to 70°C
DRV602PW
14-Pin TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
3.3
60
MAX
UNIT
V
VDD
VIH
VIL
TA
Supply voltage,
DC Supply Voltage
3
4.5
High-level input voltage
Low-level input voltage
Operating free-air temperature
EN
EN
% of VDD
% of VDD
°C
40
0
70
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
|VOS
|
Output offset voltage
VDD = 3 V to 4.5 V, Voltage follower - gain = 1
VDD = 3.3 V to 4.5 V
5
mV
dB
V
PSRR Supply Rejection Ratio
88
VOH
VOL
High-level output voltage
Low-level output voltage
High-level input current (EN)
Low-level input current (EN)
VDD = 3.3 V, RL = 2.5 kΩ
3.10
VDD = 3.3 V, RL = 2.5 kΩ
–3.05
V
|IIH
|
VDD = 4.5 V, VI = VDD
1
1
µA
µA
|IIL|
VDD = 4.5 V, VI = 0 V
VDD = 3.3 V, No load, EN = VDD
VDD = 4.5 V, No load, EN = VDD
Shutdown mode, Vdd = 3 V to 4.5 V
8
11
mA
mA
IDD
Supply Current
12.5
20
2
Copyright © 2008, Texas Instruments Incorporated
3
Product Folder Link(s): DRV602
DRV602
SLOS572–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
OPERATING CHARACTERISTICS
VDD = 3.3 V , TA = 25°C, RL = 2.5kΩ, C(PUMP) = C(PVSS) = 1 µF , CIN = 1 µF, RIN = 33 kΩ, Rfb = 68kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VO
Output Voltage (Outputs In Phase)
THD = 1%, VDD = 3.3 V, f = 1 kHz
2.05
Vrms
VO = 2 Vrms, f = 1 kHz
VO = 2 Vrms, f = 6.8 kHz
0.01%
0.05%
THD+N
Total harmonic distortion plus noise
Crosstalk
VO = 2 Vrms, f = 1 kHz
VDD = 3.3 V
–80
20
dB
IO
Output current limit
Input resistor range
Feedback resistor range
Slew rate
mA
RIN
Rfb
1
10
47
kΩ
kΩ
4.7
20
100
4.5
220
15
V/µs
pF
Maximum capacitive load
Noise output voltage
VN
A-weighted, BW 20Hz–22kHz
µVrms
VO = 2 Vrms, THD+N = 0.1%, 22 kHz BW,
A-weighted
SNR
Signal to noise ratio
102
dB
GBW
AVO
Fcp
Unity Gain Bandwidth
Open-loop voltage gain
Charge Pump frequency
8
150
450
MHz
dB
225
675
kHz
APPLICATION CIRCUIT
LEFT
OUTPUT
3.3V
supply
R2
+
R1
R1
R3
R3
C3
C3
LEFT
INPUT
C2
C1
R2
1mF
-
C2
1mF
R2
C1
C2
+
R1
R1
R3
R3
C3
C3
RIGHT
INPUT
-
1mF
C2
RIGHT
OUTPUT
ENABLE
R2
R1 = 33kΩ, R2 = 68kΩ, R3 = 100kΩ, C1 = 150pF, C2 = 15pF, C3 = 1 µF
Differential input, single ended output, 2nd order filter. 40kHz –3dB frequency, Gain 2.06.
4
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572–DECEMBER 2008
TYPICAL CHARACTERISTICS
VDD = 3.3V , TA = 25°C, C(PUMP) = C(PVSS) = 1 µF , CIN = 1 µF, RIN = 33 kΩ, Rfb = 68 kΩ (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT VOLTAGE
FREQUENCY
10
5
10
5
1
1
0.1
0.1
20 Hz
200 mVrms
6.7 kHz
0.01
0.01
2 Vrms
1 kHz
0.001
0.001
0.0001
0.0001
100m
200m
500m 800m 2
- Output Voltage - Vrms
3
4
5
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k
20k
V
O
Figure 1.
Figure 2.
FFT
vs
FREQUENCY
QUIESCENT SUPPLY CURRENT
vs
SUPPLY VOLTAGE
+0
No Load,
V = 0 V
14m
12m
10m
8m
V
= 2mVrms
O
I
-20
-40
-60
-80
-100
-120
6m
4m
2m
0
-140
+5
+4
+2 +3
- Supply Voltage - V
-0
+1
10k
5k
15k
20k
0
V
DD
f - Frequency - Hz
Figure 3.
Figure 4.
Copyright © 2008, Texas Instruments Incorporated
5
Product Folder Link(s): DRV602
DRV602
SLOS572–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
Line Driver Amplifiers
Single-supply line driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 5 illustrates
the conventional line driver amplifier connection to the load and output signal.
DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click &
pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can reduce
the fidelity of the audio output signal.
9-12 V
Conventional Solution
VDD
+
Mute Circuit
Co
+
+
-
Output
VDD/2
OPAMP
GND
Enable
5 V
DVR602 Solution
DirectPath
VDD
+
Output
GND
DRV602
-
VSS
Enable
Figure 5. Conventional and DirectPath Line Driver
The DirectPath™ amplifier architecture operates from a single supply, but makes use of an internal charge pump
to provide a negative voltage rail.
Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.
The DirectPath amplifier requires no output dc blocking capacitors.
The bottom block diagram and waveform of Figure 5 illustrate the ground-referenced Line Driver architecture.
This is the architecture of the DRV602.
6
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572–DECEMBER 2008
Charge Pump Flying Capacitor and PVSS Capacitor
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge
transfer. Low ESR capacitors are an ideal selection, and a value of 1µF is typical. Capacitor values that are
smaller than 1µF can be used, but the maximum output voltage may be reduced and the device may not operate
to specifications.
Decoupling Capacitors
The DRV602 is a DirectPath Line Driver amplifier that require adequate power supply decoupling to ensure that
the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 1µF, placed as close as possible to the device VDD lead works best. Placing this decoupling
capacitor close to the DRV602 is important for the performance of the amplifier. For filtering lower frequency
noise signals, a 10-µF or greater capacitor placed near the audio power amplifier would also help, but it is not
required in most applications because of the high PSRR of this device.
Gain setting resistors ranges
The gain setting resistors, RIN and Rfb, must be chosen so that noise, stability and input capacitor size of the
DRV602 is kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN . Selecting values that are too
high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different gain
settings.
Table 1. Recommended Resistor Values
INPUT RESISTOR
VALUE, RIN
FEEDBACK RESISTOR
VALUE, Rfb
DIFFERENTIAL INPUT INVERTING INPUT GAIN NON INVERTING INPUT
GAIN
1.0 V/V
1.5 V/V
2.1 V/V
10.0 V/V
GAIN
2.0 V/V
2.5 V/V
3.1 V/V
11.0 V/V
22 kΩ
15 kΩ
33 kΩ
10 kΩ
22 kΩ
30 kΩ
68 kΩ
100 kΩ
–1.0 V/V
–1.5 V/V
–2.1 V/V
–10.0 V/V
C
R
C
IN
R
IN
IN
IN
-In
-In
R
R
fb
fb
-
-
Differential
Input
Inverting
+
+
+In
R
C
R
IN
fb
IN
Figure 6. Differential Input
Figure 7. Inverting
R
Cx
IN
R
fb
-
Non
Inverting
+
+In
C
Rx
Figure 8. Non-Inverting
IN
Copyright © 2008, Texas Instruments Incorporated
7
Product Folder Link(s): DRV602
DRV602
SLOS572–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
Input-Blocking Capacitors
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV602. These capacitors block the DC portion of the audio source and allow the DRV602 inputs to be properly
biased to provide maximum performance. The input blocking capacitors also limit the DC gain to 1, limiting the
DC-offset voltage at the output.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 1, then the frequency and/or capacitance can be determined when one of the
two values are given.
1
1
fcIN
+
CIN
+
or
2p RIN CIN
2p fcIN RIN
(1)
Using the DRV602 as 2nd Order Filter
Several audio DACs used today require an external low-pass filter to remove out of band noise. This is possible
with the DRV602 as it can be used like a standard OPAMP.
Several filter topologies can be implemented both single ended and differential. In Figure 9, a Multi FeedBack -
MFB, with differential input and single ended input is shown.
An ac-coupling capacitor to remove dc-content from the source is shown, it serves to block any dc content from
the source and lowers the dc-gain to 1 helping reducing the output dc-offset to minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI website
at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
Differential Input
Inverting Input
R2
C1
R2
C1
C3
C3
R1
R3
R1
R3
- In
- In
-
-
C2
DRV602
+
DRV602
+
C2
+ In
R1
R3
C1
R2
C3
Figure 9. 2nd Order Active Low Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small size ac-coupling cap. With the proposed values, 33k, 68k, 100k, a DNR of 102dB can be achieved
with a small 1µF input ac-coupling capacitor.
8
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com ........................................................................................................................................................................................... SLOS572–DECEMBER 2008
Pop-Free Power Up
Pop-free power up is ensured by keeping the SD (shutdown pin) low during power supply ramp up and down.
The EN pin should be kept low until the input ac-coupling capacitors are fully charged before asserting the EN
pin high, this way proper precharge of the ac-coupling is performed, and pop-less power-up is achieved.
Figure 10 illustrates the preferred sequence.
Supply
Supply ramp
SD
Time for ac-coupling
capacitors to charge
Figure 10. Power-Up Sequence
Capacitive Load
The DRV602 has the ability to drive a high capacitive load up to 220pF directly, higher capacitive loads can be
accepted by adding a series resistor of 10Ω or larger. The figure below shows a 10kHz signal into a 470pF
capacitor using the 10R series resistor.
Layout Recommendations
A proposed layout for the DRV602 can be seen in the DRV602EVM user's guide (SLOU248) and the Gerber files
can be downloaded on www.ti.com, open the DRV602 product folder and look in the Tools and Software folder.
The gain setting resistors, RIN and Rfb , must be placed close to the input pins to minimize the capacitive loading
on these input pins and to ensure maximum stability of the DRV602. For the recommenced PCB layout, see the
DRV602EVM user's guide.
Copyright © 2008, Texas Instruments Incorporated
9
Product Folder Link(s): DRV602
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jan-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DRV602PW
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
14
14
90
TBD
TBD
Call TI
Call TI
Call TI
Call TI
DRV602PWR
PW
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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