DRV8830DGQR [TI]
LOW-VOLTAGE MOTOR DRIVER WITH SERIAL INTERFACE; 带有串行接口低压电机驱动器
| 型号： | DRV8830DGQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE MOTOR DRIVER WITH SERIAL INTERFACE |
| 文件： | 总23页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8830
www.ti.com
SLVSAB2F –MAY 2010–REVISED FEBRUARY 2012
LOW-VOLTAGE MOTOR DRIVER WITH SERIAL INTERFACE
Check for Samples: DRV8830
1
FEATURES
2
•
H-Bridge Voltage-Controlled Motor Driver
•
•
Current Limit Circuit and Fault Output
Thermally Enhanced Surface Mount Packages
–
–
–
Drives DC Motor, One Winding of a Stepper
Motor, or Other Actuators/Loads
APPLICATIONS
Efficient PWM Voltage Control for Constant
Motor Speed With Varying Supply Voltages
•
Battery-Powered:
Low MOSFET On-Resistance:
–
–
–
–
–
Printers
Toys
HS + LS 450 mΩ
•
•
1-A Maximum DC/RMS or Peak Drive Current
Robotics
Cameras
Phones
2.75-V to 6.8-V Operating Supply Voltage
Range
•
•
•
300-nA (Typical) Sleep Mode Current
Serial I2C-Compatible Interface
•
Small Actuators, Pumps, etc.
Multiple Address Selections Allow Up to 9
Devices on One I2C Bus
DESCRIPTION
The DRV8830 provides an integrated motor driver solution for battery-powered toys, printers, and other
low-voltage or battery-powered motion control applications. The device has one H-bridge driver, and can drive
one DC motor or one winding of a stepper motor, as well as other loads like solenoids. The output driver block
consists of N-channel and P-channel power MOSFET’s configured as an H-bridge to drive the motor winding.
Provided with sufficient PCB heatsinking, the DRV8830 can supply up to 1-A of DC/RMS or peak output current.
It operates on power supply voltages from 2.75 V to 6.8 V.
To maintain constant motor speed over varying battery voltages while maintaining long battery life, a PWM
voltage regulation method is provided. The output voltage is programmed via an I2C-compatible interface, using
an internal voltage reference and DAC.
Internal protection functions are provided for over current protection, short circuit protection, under voltage
lockout and overtemperature protection.
The DRV8830 is available in tiny 3-mm x 3-mm 10-pin MSOP and WSON packages with PowerPAD™
(Eco-friendly: RoHS & no Sb/Br).
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
PACKAGE(2)
PowerPAD™ (MSOP) - DGQ
Reel of 2500
Tube of 80
DRV8830DGQR
DRV8830DGQ
DRV8830DRCR
DRV8830DRCT
8830
8830
8830
8830
Reel of 3000
Reel of 250
PowerPAD™ (WSON) - DRC
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
DRV8830
SLVSAB2F –MAY 2010–REVISED FEBRUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION
Functional Block Diagram
Battery
VCC
VCC
VCC
OCP
-
Integ.
DAC
Comp
Gate
Drive
OUT1
Ref
+
5
DCM
SDA
SCL
VCC
Logic
OCP
A0
A1
I2C
Addr
Sel
Gate
Drive
OUT2
Over-
Temp
Osc
FAULTn
Current
Sense
ISENSE
GND
2
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Product Folder Link(s): DRV8830
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SLVSAB2F –MAY 2010–REVISED FEBRUARY 2012
Table 1. TERMINAL FUNCTIONS
EXTERNAL COMPONENTS
OR CONNECTIONS
NAME
GND
VCC
PIN
5
I/O(1)
DESCRIPTION
Device ground
-
-
Bypass to GND with a 0.1-μF (minimum)
ceramic capacitor.
4
Device and motor supply
SDA
SCL
A0
9
10
7
IO
Serial data
Data line of I2C serial bus
Clock line of I2C serial bus
I
I
I
Serial clock
Address set 0
Address set 1
Connect to GND, VCC, or open to set I2C
base address. See serial interface description.
A1
8
Open-drain output driven low if fault condition
present
FAULTn
6
OD
Fault output
OUT1
OUT2
3
1
O
O
Bridge output 1
Bridge output 2
Connect to motor winding
Connect current sense resistor to GND.
Resistor value sets current limit level.
ISENSE
2
IO
Current sense resistor
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
DGQ OR DRC PACKAGE
(TOP VIEW)
1
OUT2
ISENSE
OUT1
10
9
SCL
SDA
A1
2
3
4
GND
(PPAD)
8
7
VCC
A0
5
6
GND
FAULTn
ABSOLUTE MAXIMUM RATINGS(1)(2)
VALUE
–0.3 to 7
–0.5 to 7
UNIT
VCC
Power supply voltage range
V
V
A
A
Input pin voltage range
Peak motor drive output current(3)
Continuous motor drive output current(3)
Continuous total power dissipation
Operating virtual junction temperature range
Storage temperature range
Internally limited
1
See Dissipation Ratings table
TJ
–40 to 150
–60 to 150
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
Copyright © 2010–2012, Texas Instruments Incorporated
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UNITS
THERMAL INFORMATION
DRV8830
DGQ
10 PINS
69.3
DRV8830
DRC
10 PINS
50.2
THERMAL METRIC(1)
θJA
Junction-to-ambient thermal resistance(2)
θJCtop
θJB
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
63.5
78.4
51.6
18.8
°C/W
ψJT
1.5
1.1
ψJB
23.2
17.9
θJCbot
9.5
5.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
2.75
0
NOM
MAX
6.8
1
UNIT
V
VCC
IOUT
Motor power supply voltage range
Continuous or peak H-bridge output current(1)
A
(1) Power dissipation and thermal limits must be observed.
4
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SLVSAB2F –MAY 2010–REVISED FEBRUARY 2012
ELECTRICAL CHARACTERISTICS
VCC = 2.75 V to 6.8 V, TA = -40°C to 85°C (unless otherwise noted)
PARAMETER
POWER SUPPLIES
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVCC
VCC operating supply current
VCC = 5 V
1.4
0.3
2
1
mA
IVCCQ
VCC sleep mode supply current VCC = 5 V, TA = 25°C
μA
VCC rising
VCC falling
2.575
2.47
2.75
VCC undervoltage lockout
voltage
VUVLO
V
LOGIC-LEVEL INPUTS
VIL
VIH
VHYS
IIL
Input low voltage
0.25 x VCC
-10
0.38 x VCC
0.46 x VCC
0.08 x VCC
V
V
Input high voltage
Input hysteresis
Input low current
Input high current
0.5 x VCC
V
VIN = 0
10
50
μA
μA
IIH
VIN = 3.3 V
LOGIC-LEVEL OUTPUTS (FAULTn)
VOL Output low voltage
H-BRIDGE FETS
IOL = 4 mA, VCC = 5 V
0.5
V
VCC = 5 V, I O = 0.8 A, TJ = 85°C
VCC = 5 V, I O = 0.8 A, TJ = 25°C
VCC = 5 V, I O = 0.8 A, TJ = 85°C
VCC = 5 V, I O = 0.8 A, TJ = 25°C
290
250
230
200
400
320
20
RDS(ON)
HS FET on resistance
mΩ
RDS(ON)
IOFF
LS FET on resistance
mΩ
μA
Off-state leakage current
–20
MOTOR DRIVER
tR
Rise time
VCC = 3 V, load = 4 Ω
VCC = 3 V, load = 4 Ω
50
50
300
300
ns
ns
tF
Fall time
fSW
Internal PWM frequency
44.5
kHz
PROTECTION CIRCUITS
IOCP
tOCP
TTSD
Overcurrent protection trip level
1.3
150
3
180
A
OCP deglitch time
2
μs
°C
Thermal shutdown temperature
Die temperature(1)
160
VOLTAGE CONTROL
VREF
Reference output voltage
1.235
1.285
1.335
V
VCC = 3.3 V to 6 V, VOUT = 3 V,(1)
IOUT = 500 mA
ΔVLINE
Line regulation
Load regulation
±1
%
VCC = 5 V, VOUT = 3 V,
ΔVLOAD
±1
%
IOUT = 200 mA to 800 mA(1)
CURRENT LIMIT
VILIM Current limit sense voltage
tILIM
160
0
200
275
240
1
mV
ms
Current limit fault deglitch time
Current limit sense resistance
(external resistor value)
RISEN
Ω
(1) Not production tested.
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I2C TIMING REQUIREMENTS(1)
VCC = 2.75 V to 6.8 V, TA = -40°C to 85°C (unless otherwise noted)
STANDARD MODE
FAST MODE
MIN TYP
UNIT
MIN
0
TYP
MAX
MAX
400
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
100
0
0.6
1.3
0
kHz
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
4
4.7
0
50
50
tsds
tsdh
ticr
I2C serial data setup time
I2C serial data hold time
I2C input rise time
I2C input fall time
250
0
100
0
1000 20+0.1Cb(2)
300
300
300
ticf
300 20+0.1Cb(2)
300 20+0.1Cb(2)
tocf
tbuf
tsts
tsth
tsps
I2C output fall time
I2C bus free time
I2C Start setup time
I2C Start hold time
I2C Stop setup time
4.7
4.7
4
1.3
0.6
0.6
4
0.6
tvd (data) Valid data time (SCL low to SDA valid)
1
1
1
Valid data time of ACK (ACK signal from SCL low
to SDA low)
tvd (ack)
1
µs
(1) Not production tested.
(2) Cb = total capacitance of one bus line in pF
ticf
ticr
tsdh
tvd
0.7 VCC
0.3 VCC
SDA
Start Condition
tsds
ticf
ticr
tsch
3
0.7 VCC
SCL
1
2
4
0.3 VCC
tscl
tsth
1/fscl
Figure 1. I2C Timing Requirements
Stop Condition
tvd
tbuf
0.7 VCC
0.3 VCC
SDA
SCL
D7/A
Start Condition
tsds
0.7 VCC
0.3 VCC
8
9
tsps
Figure 2. I2C Timing Requirements
6
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SLVSAB2F –MAY 2010–REVISED FEBRUARY 2012
TYPICAL PERFORMANCE GRAPHS
EFFICIENCY
vs
LOAD CURRENT
(VIN = 5 V, VOUT = 3 V)
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
0.2
0.4
0.6
0.8
LOAD - A
Figure 3.
EFFICIENCY
vs
OUTPUT VOLTAGE
(VIN = 5 V, IOUT = 500 mA)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
Linear Regulator
DRV8830
0.5
1.5
2.5
3.5
VOUT - V
Figure 4.
4.5
5.5
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FUNCTIONAL DESCRIPTION
PWM Motor Driver
The DRV8830 contains an H-bridge motor driver with PWM voltage-control circuitry with current limit circuitry. A
block diagram of the motor control circuitry is shown below.
VCC
VCC
OCP
IN1
OUT1
Pre-
drive
IN2
PWM
DCM
OUT2
+
VSET
COMP
-
OCP
DIFF
/4
Integrator
ISEN
ITRIP
+
COMP
-
REF
Figure 5. Motor Control Circuitry
Bridge Control
The IN1 and IN2 control bits in the serial interface register enable the H-bridge outputs. The following table
shows the logic:
Table 2. H-Bridge Logic
IN1
0
IN2
0
OUT1
OUT2
Function
Standby/coast
Reverse
Z
L
Z
H
L
0
1
1
0
H
H
Forward
1
1
H
Brake
When both bits are zero, the output drivers are disabled and the device is placed into a low-power shutdown
state. The current limit fault condition (if present) is also cleared.
At initial power-up, the device will enter the low-power shutdown state. Note that when transitioning from either
brake or standby mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle
slowly ramps up to the commanded voltage. This can take up to 12 ms to go from standby to 100% duty cycle.
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SLVSAB2F –MAY 2010–REVISED FEBRUARY 2012
Voltage Regulation
The DRV8830 provides the ability to regulate the voltage applied to the motor winding. This feature allows
constant motor speed to be maintained even when operating from a varying supply voltage such as a
discharging battery.
The DRV8830 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current
consumption and maximize battery life.
The circuit monitors the voltage difference between the output pins and integrates it, to get an average DC
voltage value. This voltage is divided by 4 and compared to the output voltage of the VSET DAC, which is set
through the serial interface. If the averaged output voltage (divided by 4) is lower than VSET, the duty cycle of
the PWM output is increased; if the averaged output voltage (divided by 4) is higher than VSET, the duty cycle is
decreased.
During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on
time. This is shown in the diagram below as case 1. The current flow direction shown indicates the state when
IN1 is high and IN2 is low.
Note that if the programmed output voltage is greater than the supply voltage, the device will operate at 100%
duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional
H-bridge driver.
During the PWM off time, winding current is re-circulated by enabling both of the high-side FETs in the bridge.
This is shown as case 2 below.
VCC
2
1
Shown with
IN1=1, IN2=0
OUT1
OUT2
1
2
PWM on
PWM off
Figure 6. Voltage Regulation
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Voltage Setting (VSET DAC)
The DRV8830 includes an internal reference voltage that is connected to a DAC. This DAC generates a voltage
which is used to set the PWM regulated output voltage as described above.
The DAC is controlled by the VSET bits from the serial interface. The commanded output voltage is as follows:
VSET[5..0]
0x00h
0x01h
0x02h
0x03h
0x04h
0x05h
0x06h
0x07h
0x08h
0x09h
0x0Ah
0x0Bh
0x0Ch
0x0Dh
0x0Eh
0x0Fh
0x10h
0x11h
0x12h
0x13h
0x14h
0x15h
0x16h
0x17h
0x18h
0x19h
0x1Ah
0x1Bh
0x1Ch
0x1Dh
0x1Eh
0x1Fh
Output Voltage
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.48
VSET[5..0]
0x20h
0x21h
0x22h
0x23h
0x24h
0x25h
0x26h
0x27h
0x28h
0x29h
0x2Ah
0x2Bh
0x2Ch
0x2Dh
0x2Eh
0x2Fh
0x30h
0x31h
0x32h
0x33h
0x34h
0x35h
0x36h
0x37h
0x38h
0x39h
0x3Ah
0x3Bh
0x3Ch
0x3Dh
0x3Eh
0x3Fh
Output Voltage
2.57
2.65
2.73
2.81
2.89
2.97
3.05
3.13
3.21
3.29
3.37
3.45
3.53
3.61
3.69
3.77
3.86
3.94
4.02
4.10
4.18
4.26
4.34
4.42
4.50
4.58
4.66
4.74
4.82
4.90
4.98
5.06
0.56
0.64
0.72
0.80
0.88
0.96
1.04
1.12
1.20
1.29
1.37
1.45
1.53
1.61
1.69
1.77
1.85
1.93
2.01
2.09
2.17
2.25
2.33
2.41
2.49
The voltage can be calculated as 4 x VREF x (VSET +1) / 64, where VREF is the internal 1.285-V reference.
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Current Limit
A current limit circuit is provided to protect the system in the event of an overcurrent condition, such as what
would be encountered if driving a DC motor at start-up or with an abnormal mechanical load (stall condition).
The motor current is sensed by monitoring the voltage across an external sense resistor. When the voltage
exceeds a reference voltage of 200 mV for more than approximately 3 µs, the PWM duty cycle is reduced to limit
the current through the motor to this value. This current limit allows for starting the motor while controlling the
current.
If the current limit condition persists for some time, it is likely that a fault condition has been encountered, such
as the motor being run into a stop or a stalled condition. An overcurrent event must persist for approximately
275 ms before the fault is registered. After approximately 275 ms, a fault signaled to the host by driving the
FAULTn signal low and setting the FAULT and ILIMIT bits in the serial interface register. Operation of the motor
driver will continue.
The current limit fault condition is cleared by setting both IN1 and IN2 to zero to disable the motor current, by
putting the device into the shutdown state (IN1 and IN2 both set to 1), by setting the CLEAR bit in the fault
register, or by removing and re-applying power to the device.
The resistor used to set the current limit must be less than 1 Ω. Its value may be calculated as follows:
200 mV
RISENSE =
ILIMIT
(1)
Where:
RISENSE is the current sense resistor value.
ILIMIT is the desired current limit (in mA).
If the current limit feature is not needed, the ISENSE pin may be directly connected to ground.
Protection Circuits
The DRV8830 is fully protected against undervoltage, overcurrent and overtemperature events. A FAULTn pin is
available to signal a fault condition to the system, as well as a FAULT register in the serial interface that allows
determination of the fault source.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled, the FAULTn
signal will be driven low, and the FAULT and OCP bits in the FAULT register will be set. The device will remain
disabled until the CLEAR bit in the FAULT register is written to 1, or VCC is removed and re-applied.
Overcurrent conditions are sensed independently on both high and low side devices. A short to ground, supply,
or across the motor winding will all result in an overcurrent shutdown. Note that OCP is independent of the
current limit function, which is typically set to engage at a lower current level; the OCP function is intended to
prevent damage to the device under abnormal (e.g., short-circuit) conditions.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the FAULTn signal will be
driven low, and the FAULT and OTS bits in the serial interface register will be set. Once the die temperature has
fallen to a safe level operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all FETs in the
H-bridge will be disabled, the FAULTn signal will be driven low, and the FAULT and UVLO bits in the FAULT
register will be set. Operation will resume when VCC rises above the UVLO threshold.
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I2C-Compatible Serial Interface
The I2C interface allows control and monitoring of the DRV8830 by a microcontroller. I2C is a two-wire serial
interface developed by Philips Semiconductor (see I2C – Bus Specification, Version 2.1, January 2000). The bus
consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both
SDA and SCL lines are pulled high.
A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer.
A slave device receives and/or transmits data on the bus under control of the master device. This device
operates only as a slave device.
I2C communication is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while
SCL is held high. After the start condition, the device address byte is sent, most-significant bit (MSB) first,
including the data direction bit (R/W). After receiving a valid address byte, this device responds with an
acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse.
The lower three bits of the device address are input from pins A0 - A1, which can be tied to VCC (logic high),
GND (logic low), or left open. These three address bits are latched into the device at power-up, so cannot be
changed dynamically.
The upper address bits of the device address are fixed at 0xC0h, so the device address is as follows:
A3..A0 BITS
(as below)
A1 PIN
A0 PIN
ADDRESS (WRITE)
ADDRESS (READ)
0
0
0
open
1
0000
0xC0h
0xC2h
0xC4h
0xC6h
0xC8h
0xCAh
0xCCh
0xCEh
0xD0h
0xC1h
0xC3h
0xC5h
0xC7h
0xC9h
0xCBh
0xCDh
0xCFh
0xD1h
0001
0
0010
open
open
open
1
0
0011
open
1
0100
0101
0
0110
1
open
1
0111
1
1000
The DRV8830 does not respond to the general call address.
A data byte follows the address acknowledge. If the R/W bit is low, the data is written from the master. If the R/W
bit is high, the data from this device are the values read from the register previously selected by a write to the
subaddress register. The data byte is followed by an acknowledge sent from this device. Data is output only if
complete bytes are received and acknowledged. A stop condition, which is a low-to-high transition on the SDA
I/O while the SCL input is high, is sent by the master to terminate the transfer.
A master bus device must wait at least 60 μs after power is applied to VCC to generate a START condition.
I2C transactions are shown in the timing diagrams below:
R
1 1
1 1
S
S
(An)
(Dn)
Data
(Dn+1)
Data
(As)
(As)
0
W
0
Slave
Address
Sub
Address
Slave
Address
Figure 7. I2C Read Mode
12
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Product Folder Link(s): DRV8830
DRV8830
www.ti.com
SLVSAB2F –MAY 2010–REVISED FEBRUARY 2012
1 1
S
(An)
(Dn)
Data
(Dn+1)
Data
(As)
0
W
Slave
Address
Sub
Address
Figure 8. I2C Write Mode
I2C Register Map
REGISTER
SUB ADDRESS (HEX)
REGISTER NAME
DEFAULT VALUE
0x00h
0x00h
DESCRIPTION
Sets state of outputs and output
voltage
0
0x00
CONTROL
FAULT
Allows reading and clearing of fault
conditions
1
0x01
REGISTER 0 – CONTROL
The CONTROL register is used to set the state of the outputs as well as the DAC setting for the output voltage.
The register is defined as follows:
D7 - D2
D1
D0
VSET[5..0]
IN2
IN1
VSET[5..0]:
IN2:
Sets DAC output voltage. Refer to Voltage Setting above.
Along with IN1, sets state of outputs. Refer to Bridge Control above.
Along with IN2, sets state of outputs. Refer to Bridge Control above.
IN1:
REGISTER 1 – FAULT
The FAULT register is used to read the source of a fault condition, and to clear the status bits that indicated the
fault. The register is defined as follows:
D7
D6 - D5
D4
D3
D2
D1
D0
CLEAR
Unused
ILIMIT
OTS
UVLO
OCP
FAULT
CLEAR:
When written to 1, clears the fault status bits
ILIMIT:
OTS:
If set, indicates the fault was caused by an extended current limit event
If set, indicates that the fault was caused by an overtemperature (OTS) condition
If set, indicates the fault was caused by an undervoltage lockout
If set, indicates the fault was caused by an overcurrent (OCP) event
Set if any fault condition exists
UVLO:
OCP:
FAULT:
Copyright © 2010–2012, Texas Instruments Incorporated
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SLVSAB2F –MAY 2010–REVISED FEBRUARY 2012
www.ti.com
THERMAL INFORMATION
Thermal Protection
The DRV8830 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
160°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8830 is dominated by the power dissipated in the output FET resistance, or RDS(ON)
.
Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.
2
· ·
PTOT = 2 RDS(ON) (IOUT(RMS)
)
(2)
where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current for each
winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
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Product Folder Link(s): DRV8830
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DRV8830DGQ
DRV8830DGQR
DRV8830DRCR
DRV8830DRCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGQ
DGQ
DRC
DRC
10
10
10
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSOP-
PowerPAD
2500
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
SON
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8830DGQR
MSOP-
Power
PAD
DGQ
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DRV8830DRCR
DRV8830DRCT
SON
SON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8830DGQR
DRV8830DRCR
DRV8830DRCT
MSOP-PowerPAD
DGQ
DRC
DRC
10
10
10
2500
3000
250
346.0
346.0
210.0
346.0
346.0
185.0
29.0
29.0
35.0
SON
SON
Pack Materials-Page 2
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