DRV8870 [TI]
具有电流调节功能的 50V、3.6A、H 桥电机驱动器;型号: | DRV8870 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有电流调节功能的 50V、3.6A、H 桥电机驱动器 电机 驱动 驱动器 |
文件: | 总25页 (文件大小:1457K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DRV8870
ZHCSE25 –AUGUST 2015
DRV8870 3.6A 刷式直流电机驱动器(PWM 控制)
1 特性
3 说明
1
•
独立的 H 桥电机
DRV8870 是一款刷式直流电机驱动器,适用于打印
机、电器、工业设备以及其他小型机器。 两个逻辑输
入控制 H 桥驱动器,该驱动器由四个 N 沟道金属氧化
物半导体场效应晶体管 (MOSFET) 组成,能够以高达
3.6A 的峰值电流双向控制电机。 利用电流衰减模式,
可通过对输入进行脉宽调制 (PWM) 来控制电机转速。
如果将两个输入均置为低电平,则电机驱动器将进入低
功耗休眠模式。
–
驱动一个直流电机、一个步进电机的绕组或其他
负载
•
•
•
•
•
•
•
6.5V 至 45V 宽工作电压范围
565mΩ(典型值)RDS(on) (HS + LS)
3.6A 峰值电流驱动能力
脉宽调制 (PWM) 控制接口
集成电流调节功能
低功耗休眠模式
DRV8870 具有集成电流调节功能,该功能基于模拟输
入 VREF 以及 ISEN 引脚的电压(与流经外部感测电
阻的电机电流成正比)。 该器件能够将电流限制在某
一已知水平,这可显著降低系统功耗要求,并且无需大
容量电容来维持稳定电压,尤其是在电机启动和停转
时。
小型封装尺寸
–
–
8 引脚 HSOP 封装,带有 PowerPAD™
4.9mm × 6.0mm
•
集成保护特性
–
–
–
–
VM 欠压闭锁 (UVLO)
过流保护 (OCP)
热关断 (TSD)
该器件针对故障和短路问题提供了全面保护,包括欠压
锁定 (UVLO)、过流保护 (OCP) 和过热保护 (TSD)。
故障排除后,器件会自动恢复正常工作。
自动故障恢复
2 应用范围
器件信息 (1)
•
•
•
•
打印机
部件号
DRV8870
封装
HSOP (8)
封装尺寸(标称值)
电器
4.90mm × 6.00mm
工业设备
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
其他机电一体化应用
空白
简化电路原理图
H 桥状态
6.5 to 45 V
DRV8870
3.6 A
IN1
Controller
IN2
Brushed DC
Motor Driver
BDC
VREF
Current
Regulation
ISEN
Fault
Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCY8
DRV8870
ZHCSE25 –AUGUST 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 11
Power Supply Recommendations...................... 14
9.1 Bulk Capacitance .................................................... 14
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 10
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations........................................ 15
10.4 Power Dissipation ................................................. 15
11 器件和文档支持 ..................................................... 17
11.1 文档支持................................................................ 17
11.2 社区资源................................................................ 17
11.3 商标....................................................................... 17
11.4 静电放电警告......................................................... 17
11.5 Glossary................................................................ 17
12 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
日期
修订版本
注释
2015 年 8 月
*
首次发布。
2
Copyright © 2015, Texas Instruments Incorporated
DRV8870
www.ti.com.cn
ZHCSE25 –AUGUST 2015
5 Pin Configuration and Functions
DDA Package
8-Pin HSOP
Top View
1
8
7
6
5
GND
OUT2
ISEN
OUT1
VM
2
IN2
Thermal
Pad
3
IN1
4
VREF
Pin Functions
PIN
TYPE
DESCRIPTION
Connect to board ground
NAME
GND
NO.
1
PWR
I
Logic ground
Logic inputs
IN1
IN2
3
Controls the H-bridge output. Has internal pulldowns. (See Table 1.)
If using current regulation, connect ISEN to a resistor (low-value,
2
ISEN
7
PWR
O
High-current ground path high-power-rating) to ground. If not using current regulation, connect
ISEN directly to ground.
OUT1
OUT2
6
8
H-bridge output
Thermal pad
Connect directly to the motor or other inductive load.
Connect to board ground. For good thermal dissipation, use large
ground planes on multiple layers, and multiple nearby vias
connecting those planes.
PAD
—
—
6.5-V to 45-V power
supply
Connect a 0.1-µF bypass capacitor to ground, as well as sufficient
bulk capacitance, rated for the VM voltage.
VM
5
4
PWR
I
Apply a voltage between 0.3 to 5 V. For information on current
regulation, see the Current Regulation section.
VREF
Analog input
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
0
MAX
UNIT
V
Power supply voltage (VM)
50
Power supply voltage ramp rate (VM)
Logic input voltage (IN1, IN2)
2
V/µs
V
–0.3
–0.3
–0.7
–0.5
–40
–65
7
Reference input pin voltage (VREF)
Continuous phase node pin voltage (OUT1, OUT2)
6
VM + 0.7
1
V
V
(2)
Current sense input pin voltage (ISEN)
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable
Copyright © 2015, Texas Instruments Incorporated
3
DRV8870
ZHCSE25 –AUGUST 2015
www.ti.com.cn
6.2 ESD Ratings
VALUE
±6000
±750
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
V(ESD)
Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
45
UNIT
V
VM
Power supply voltage range
6.5
(1)
VREF
VI
VREF input voltage range
0.3
5
V
Logic input voltage range (IN1, IN2)
Logic input PWM frequency (IN1, IN2)
0
0
5.5
100
3.6
125
V
fPWM
Ipeak
TA
kHz
A
(2)
Peak output current
0
(2)
Operating ambient temperature
–40
°C
(1) Operational at VREF = 0 to 0.3 V, but accuracy is degraded
(2) Power dissipation and thermal limits must be observed
6.4 Thermal Information
DRV8870
(1)
THERMAL METRIC
DDA (HSOP)
8 PINS
41.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
53.1
23.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.2
ψJB
23
RθJC(bot)
2.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
DRV8870
www.ti.com.cn
ZHCSE25 –AUGUST 2015
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
POWER SUPPLY (VM)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VM
VM operating voltage
6.5
45
10
V
VM operating supply
current
IVM
VM = 12 V
3
mA
IVMSLEEP
VM sleep current
Turn-on time
VM = 12 V
10
50
µA
µs
(1)
tON
VM > VUVLO with IN1 or IN2 high
40
LOGIC-LEVEL INPUTS (IN1, IN2)
VIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
Propagation delay
0.5
V
V
VIH
VHYS
IIL
1.5
-1
0.5
V
VIN = 0 V
1
μA
μA
kΩ
μs
ms
IIH
VIN = 3.3 V
33
100
0.7
1
100
RPD
tPD
to GND
INx to OUTx change (see Figure 6)
Inputs low to sleep
1
tsleep
Time to sleep
1.5
MOTOR DRIVER OUTPUTS (OUT1, OUT2)
High-side FET on
resistance
RDS(ON)
VM = 24 V, I = 1 A, TA = 25°C
307
360
320
mΩ
Low-side FET on
resistance
RDS(ON)
tDEAD
Vd
VM = 24 V, I = 1 A, TA = 25°C
258
220
0.8
mΩ
ns
V
Output dead time
Body diode forward
voltage
IOUT = 1 A
1
CURRENT REGULATION
AV
ISEN gain
VREF = 2.5 V
9.4
10
25
2
10.4
V/V
µs
tOFF
tBLANK
PWM off-time
PWM blanking time
µs
PROTECTION CIRCUITS
VM falls until UVLO triggers
6.1
6.3
6.4
6.5
V
VUVLO
VM undervoltage lockout
VM rises until operation recovers
VM undervoltage
hysteresis
VUV,HYS
IOCP
Rising to falling threshold
100
3.7
180
4.5
mV
A
Overcurrent protection trip
level
6.4
tOCP
Overcurrent deglitch time
Overcurrent retry time
1.5
3
μs
tRETRY
ms
Thermal shutdown
temperature
TSD
150
175
40
°C
°C
Thermal shutdown
hysteresis
THYS
(1) tON applies when the device initially powers up, and when it exits sleep mode.
Copyright © 2015, Texas Instruments Incorporated
5
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ZHCSE25 –AUGUST 2015
www.ti.com.cn
6.6 Typical Characteristics
1.6
1.5
1.4
1.3
1.2
1.1
1
10.5
10.25
10
9.75
9.5
0.9
0.8
0.7
-40
-20
0
20
40
60
80
100
120
140
1
1.5
2
2.5
3
3.5
4
Ambient Temperature (qC)
VREF (V)
D001
D003
Figure 1. RDS(on) vs Temperature
Figure 2. AV vs VREF
10
8
6
4
2
0
0
5
10
15
20
25
30
35
40
45
VM (V)
D004
Figure 3. IVMSLEEP vs VM at 25°C
6
Copyright © 2015, Texas Instruments Incorporated
DRV8870
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ZHCSE25 –AUGUST 2015
7 Detailed Description
7.1 Overview
The DRV8870 is an optimized 8-pin device for driving brushed DC motors with 6.5 to 45 V and up to 3.6-A peak
current. The integrated current regulation restricts motor current to a predefined maximum. Two logic inputs
control the H-bridge driver, which consists of four N-channel MOSFETs that have a typical Rds(on) of 565 mΩ
(including one high-side and one low-side FET). A single power input, VM, serves as both device power and the
motor winding bias voltage. The integrated charge pump of the device boosts VM internally and fully enhances
the high-side FETs. Motor speed can be controlled with pulse-width modulation, at frequencies between 0 to 100
kHz. The device has an integrated sleep mode that is entered by bringing both inputs low. An assortment of
protection features prevent the device from being damaged if a system fault occurs.
7.2 Functional Block Diagram
VCP
VM
Power
VCP
VM
VM
Charge
Pump
Gate
Driver
OUT1
bulk
0.1µF
OCP
GND
BDC
PPAD
VCP
VM
Gate
Driver
OUT2
IN1
IN2
Core
Logic
OCP
ISEN
x
10
+
-
RSENSE
VREF
Protection Features
Overcurrent
Monitoring
Temperature
Sensor
Voltage
Monitoring
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE25 –AUGUST 2015
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7.3 Feature Description
7.3.1 Bridge Control
The DRV8870 output consists of four N-channel MOSFETs that are designed to drive high current. They are
controlled by the two logic inputs IN1 and IN2, according to Table 1.
Table 1. H-Bridge Control
IN1
0
IN2
0
OUT1
OUT2
DESCRIPTION
Coast; H-bridge disabled to High-Z (sleep entered after 1 ms)
Reverse (Current OUT2 → OUT1)
High-Z
High-Z
0
1
L
H
L
H
L
L
1
0
Forward (Current OUT1 → OUT2)
1
1
Brake; low-side slow decay
The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM)
for variable motor speed. When using PWM, it typically works best to switch between driving and braking. For
example, to drive a motor forward with 50% of its max RPM, IN1 = 1 and IN2 = 0 during the driving period, and
IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current
decay is also available. The input pins can be powered before VM is applied.
VM
VM
1
2
3
1
2
3
Reverse drive
Forward drive
Slow decay (brake)
High-Z (coast)
Slow decay (brake)
High-Z (coast)
1
1
OUT1
OUT2
OUT1
OUT2
2
3
2
3
FORWARD
REVERSE
Figure 4. H-Bridge Current Paths
7.3.2 Sleep Mode
When IN1 and IN2 are both low for time tSLEEP (typically 1 ms), the DRV8870 enters a low-power sleep mode,
where the outputs remain High-Z and the device uses IVMSLEEP (microamps) of current. If the device is powered
up while both inputs are low, sleep mode is immediately entered. After IN1 or IN2 are high for at least 5 µs, the
device will be operational 50 µs (tON) later.
7.3.3 Current Regulation
The DRV8870 limits the output current based on the analog input VREF and the resistance of an external sense
resistor on pin ISEN, according to this equation:
8
Copyright © 2015, Texas Instruments Incorporated
DRV8870
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ZHCSE25 –AUGUST 2015
VREF (V)
VREF (V)
ITRIP (A)
Av u RISEN (:) 10 u RISEN (:)
(1)
For example, if VREF = 3.3 V and a RISEN = 0.15 Ω, the DRV8870 will limit motor current to 2.2 A no matter how
much load torque is applied. For guidelines on selecting a sense resistor, see Sense Resistor.
When ITRIP has been reached, the device enforces slow current decay by enabling both low-side FETs, and it
does this for time tOFF (typically 25 µs).
ITRIP
tBLANK
tDRIVE
tOFF
Figure 5. Current Regulation Time Periods
After tOFF has elapsed, the output is re-enabled according to the two inputs INx. The drive time (tDRIVE) until
reaching another ITRIP event heavily depends on the VM voltage, the motor’s back-EMF, and the motor’s
inductance.
7.3.4 Dead Time
When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically
inserted to prevent shoot-through. tDEAD is the time in the middle when the output is High-Z. If the output pin is
measured during tDEAD, the voltage will depend on the direction of current. If current is leaving the pin, the
voltage will be a diode drop below ground. If current is entering the pin, the voltage will be a diode drop above
VM. This diode is the body diode of the high-side or low-side FET.
IN1
IN2
OUT1
tPD
tR
tDEAD
tPD
tF
tDEAD
OUT2
tPD
tF
tDEAD
tPD
tR
tDEAD
Figure 6. Propagation Delay Time
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ZHCSE25 –AUGUST 2015
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7.3.5 Protection Circuits
The DRV8870 is fully protected against VM undervoltage, overcurrent, and overtemperature events.
7.3.5.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all FETs in the H-
bridge will be disabled. Operation will resume when VM rises above the UVLO threshold.
7.3.5.2 Overcurrent Protection (OCP)
If the output current exceeds the OCP threshold IOCP for longer than tOCP, all FETs in the H-bridge are disabled
for a duration of tRETRY. After that, the H-bridge will be re-enabled according to the state of the INx pins. If the
overcurrent fault is still present, the cycle repeats; otherwise normal device operation resumes.
7.3.5.3 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled. After the die temperature has
fallen to a safe level, operation automatically resumes.
Table 2. Protection Functionality
FAULT
VM undervoltage lockout (UVLO)
Overcurrent (OCP)
CONDITION
VM < VUVLO
H-BRIDGE BECOMES
Disabled
RECOVERY
VM > VUVLO
IOUT > IOCP
TJ > 150°C
Disabled
Disabled
tRETRY
Thermal Shutdown (TSD)
TJ < TSD – THYS
7.4 Device Functional Modes
The DRV8870 can be used in multiple ways to drive a brushed DC motor.
7.4.1 PWM With Current Regulation
This scheme uses all of the device’s capabilities. ITRIP is set above the normal operating current, and high
enough to achieve an adequate spin-up time, but low enough to constrain current to a desired level. Motor speed
is controlled by the duty cycle of one of the inputs, while the other input is static. Brake/slow decay is typically
used during the off-time.
7.4.2 PWM Without Current Regulation
If current regulation is not needed, pin ISEN should be directly connected to the PCB ground plane. VREF must
still be 0.3 to 5 V, and larger voltages provide greater noise margin. This mode provides the highest possible
peak current: up to 3.6 A for a few hundred milliseconds (depending on PCB characteristics and the ambient
temperature). If current exceeds 3.6 A, the device might reach overcurrent protection (OCP) or overtemperature
shutdown (TSD). If that happens, the device disables and protects itself for about 3 ms (tRETRY) and then
resumes normal operation.
7.4.3 Static Inputs With Current Regulation
IN1 and IN2 can be set high and low for 100% duty cycle drive, and ITRIP can be used to control the motor’s
current, speed, and torque capability.
7.4.4 VM Control
In some systems it is desirable to vary VM as a means of changing motor speed. See Motor Voltage for more
information.
10
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DRV8870
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ZHCSE25 –AUGUST 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8870 is typically used to drive one brushed DC motor.
8.2 Typical Application
GND
IN2
OUT2
ISEN
OUT1
VM
3.3 V
0.2
BDC
Controller
DRV8870
IN1
3.3 V
VREF
PPAD
+
±
6.5 to 45 V
Power Supply
0.1 µF
47 µF
Figure 7. Typical Connections
8.2.1 Design Requirements
Table 3 lists the design parameters.
Table 3. Design Parameters
DESIGN PARAMETER
REFERENCE
VM
EXAMPLE VALUE
Motor voltage
24 V
0.8 A
2 A
Motor RMS current
Motor startup current
Motor current trip point
VREF voltage
IRMS
ISTART
ITRIP
2.2 A
3.3 V
0.15 Ω
5 kHz
VREF
RISEN
fPWM
Sense resistance
PWM frequency
8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.
8.2.2.2 Drive Current
The current path is through the high-side sourcing DMOS power driver, motor winding, and low-side sinking
DMOS power driver. Power dissipation losses in one source and sink DMOS power driver are shown in the
following equation.
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PD I2
R
ꢂ RDS(on)Sink
DS(on)Source
(2)
The DRV8870 has been measured to be capable of 2-A RMS current at 25°C on standard FR-4 PCBs. The max
RMS current will vary based on PCB design and the ambient temperature.
8.2.2.3 Sense Resistor
For optimal performance, it is important for the sense resistor to be:
•
•
•
•
Surface-mount
Low inductance
Rated for high enough power
Placed closely to the motor driver
2
The power dissipated by the sense resistor equals IRMS × R. For example, if peak motor current is 3 A, RMS
motor current is 1.5 A, and a 0.2-Ω sense resistor is used, the resistor will dissipate 1.5 A2 × 0.2 Ω = 0.45 W.
The power quickly increases with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a PCB is shared with other components generating heat, the system
designer should add margin. It is always best to measure the actual sense resistor temperature in a final system.
Because power resistors are larger and more expensive than standard resistors, it is common practice to use
multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat
dissipation.
8.2.3 Application Curves
Figure 8. Current Ramp With a 2-Ω, 1 mH,
Figure 9. Current Ramp With a 2-Ω, 1 mH,
RL Load and VM = 12 V
RL Load and VM = 24 V
12
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DRV8870
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ZHCSE25 –AUGUST 2015
Figure 10. Current Ramp With a 2-Ω, 1 mH,
Figure 11. tPD
RL Load and VM = 45 V
Figure 12. Current Regulation With VREF = 2 V and
Figure 13. OCP With 45 V and the Outputs Shorted
Together
150 mΩ
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VBB
+
Motor
Driver
+
±
GND
Local
IC Bypass
Bulk Capacitor
Capacitor
Figure 14. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
14
Copyright © 2015, Texas Instruments Incorporated
DRV8870
www.ti.com.cn
ZHCSE25 –AUGUST 2015
10 Layout
10.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I² x RDS(on) heat that is generated in the device.
10.2 Layout Example
Recommended layout and component placement is shown in the following diagram.
GND
IN2
OUT2
ISEN
OUT1
VM
IN1
VREF
+
Figure 15. Layout Recommendation
10.3 Thermal Considerations
The DRV8870 device has thermal shutdown (TSD) as described in the Thermal Shutdown (TSD) section. If the
die temperature exceeds approximately 175°C, the device is disabled until the temperature drops below the
temperature hysteresis level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high of an ambient temperature.
10.4 Power Dissipation
Power dissipation in the DRV8870 device is dominated by the power dissipated in the output FET resistance,
RDS(on). Use the equation in the Drive Current section to calculate the estimated average power dissipation when
driving a load.
Note that at startup, the current is much higher than normal running current; this peak current and its duration
must be also be considered.
Copyright © 2015, Texas Instruments Incorporated
15
DRV8870
ZHCSE25 –AUGUST 2015
www.ti.com.cn
Power Dissipation (continued)
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
NOTE
RDS(on) increases with temperature, so as the device heats, the power dissipation
increases. This fact must be taken into consideration when sizing the heatsink.
The power dissipation of the DRV8870 is a function of RMS motor current and the FET resistance (RDS(ON)) of
each output.
2
Power | IRMS u High-side RDS(ON) ꢂ Low-side RDS(ON)
(3)
For this example, the ambient temperature is 58°C, and the junction temperature reaches 80°C. At 58°C, the
sum of RDS(ON) is about 0.72 Ω. With an example motor current of 0.8 A, the dissipated power in the form of heat
will be 0.8 A2 × 0.72 Ω = 0.46 W.
The temperature that the DRV8870 reaches will depend on the thermal resistance to the air and PCB. It is
important to solder the device PowerPAD to the PCB ground plane, with vias to the top and bottom board layers,
in order dissipate heat into the PCB and reduce the device temperature. In the example used here, the DRV8870
had an effective thermal resistance RθJA of 48°C/W, and:
TJ TA ꢀ (PD u RTJA ) 58qC ꢀ (0.46 W u 48qC/W) 80qC
(4)
10.4.1 Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground plane.
On PCBs without internal planes, a copper area can be added on either side of the PCB to dissipate heat. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
For details about how to design the PCB, refer to the TI application report, PowerPAD™ Thermally Enhanced
Package (SLMA002), and the TI application brief, PowerPAD Made Easy™ (SLMA004), available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
16
版权 © 2015, Texas Instruments Incorporated
DRV8870
www.ti.com.cn
ZHCSE25 –AUGUST 2015
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
•
•
•
•
•
应用报告《PowerPAD™ 耐热增强型封装》,SLMA002
应用简介《PowerPAD™ 速成》,SLMA004
应用报告《电流再循环和衰减模式》,SLVA321
应用报告《计算电机驱动器的功耗》,SLVA504
应用报告《了解电机驱动器的额定电流》,SLVA505
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
17
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Copyright © 2015, 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8870DDA
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
75
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
8870
8870
DRV8870DDAR
2500 RoHS & Green
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
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flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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