HD3SS2522RHU [TI]
带 DFP 控制器的 10Gbps USB 3.1 Type-C 多路复用器 | RHU | 56 | 0 to 70;
| 型号： | HD3SS2522RHU |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 带 DFP 控制器的 10Gbps USB 3.1 Type-C 多路复用器 | RHU | 56 | 0 to 70 控制器 接口集成电路 复用器 |
| 文件： | 总22页 (文件大小：724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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HD3SS2522
ZHCSDQ8 –APRIL 2015
HD3SS2522 具有 DFP 控制器的 USB Type-C SS MUX
1 特性
3 说明
1
•
符合 USB Type-C 规范 1.0
模式配置
仅主机 - 下行端口 (DFP)
通道配置 (CC)
HD3SS2522 是一款配有 DFP CC 逻辑的 2:1 USB
复用器。 根据 USB Type-C 规范，HD3SS2522 用作
DFP。 CC 逻辑块通过监视 CC1 和 CC2 引脚的电压
来确定何时连接了 USB 端口。 连接 USB 端口
后，CC 逻辑还将确定电缆方向并相应地配置 USB SS
复用器。
•
•
–
–
–
–
USB 端口连接检测
电缆方向检测
Type-C 电流模式（默认、中等和高）
HD3SS2522 通过 VBUS_EN 信号来控制传统电源开
关，从而为 VBUS 提供 5V 电压。 此外，该器件还可
提供相应的控制信号，从而为生态系统实现 USB
Type-C 提供 5V VCONN 电源。
•
•
电源电压：3.3V ± 10%
用于 USB 3.1 信号传输的 2:1 复用器 (Mux) 解决方
案
•
•
运行速率高达 10Gbps，-3dB 带宽 (BW) 宽达
8GHz
该器件具有出色的动态特性，可在信号眼图衰减最小的
情况下实现高速转换，并且附加抖动极少。 此外，该
器件在待机模式下具有较低的电流消耗。
出色动态特性（2.5GHz 时）
–
–
–
–
串扰 = -39dB
断开隔离 = -22dB
插入损耗 = –1.2dB
输入回波损耗 = –12dB
器件信息(1)
器件型号
HD3SS2522
封装
封装尺寸（标称值）
WQFN (56)
11.00mm x 5.00mm
•
低功耗：激活模式为 2mW；待机模式为 50μW
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
•
•
台式机和笔记本电脑
USB Type-C DFP 应用
主板
4 简化电路原理图
5V
VBUS
VCONN
VBUS_EN
VCTL2
VCTL1
CC1
VCC
DFP
CC Controller
CC2
CRX1
CTX1
CRX2
CTX2
USB SS MUX
USB SS Signals
USB 2.0 Signals
USB
Host
HD3SS2522
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEM6
HD3SS2522
ZHCSDQ8 –APRIL 2015
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 USB Type-C DFP Typical Application..................... 12
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 7
7.7 Switching Characteristics.......................................... 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
9
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 器件和文档支持 ..................................................... 17
12.1 商标....................................................................... 17
12.2 静电放电警告......................................................... 17
12.3 术语表 ................................................................... 17
13 机械、封装和可订购信息....................................... 17
8
5 修订历史记录
日期
修订版本
注释
2015 年 4 月
*
首次发布。
2
Copyright © 2015, Texas Instruments Incorporated
HD3SS2522
www.ti.com.cn
ZHCSDQ8 –APRIL 2015
6 Pin Configuration and Functions
RHU Package
Top View
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
B0p
B0p
2
3
A0p
A0p
B0n
B0n
A0n
A0n
B1p
B1p
4
VCC
VCC
B1n
B1n
5
A1p
A1p
C0p
C0p
6
A1n
A1n
C0n
C0n
7
SS_SEL_IN
SS_SEL_IN
C1p
C1p
8
SS_Oen_IN
SS_Oen_IN
C1n
C1n
9
CC_Oen_IN
CC_Oen_IN
VCC
VCC
10
11
12
13
14
15
16
17
18
19
20
RSVD
RSVD
GND
GND
Thermal PAD
CC_OUT
CC_OUT
RSVD
RSVD
CC1
CC1
CC_SEL_IN
CC_SEL_IN
VCC
VCC
RSVD
RSVD
VCC
VCC
CC2
CC2
MODE_LED
MODE_LED
SS_OEn_OUT/VBUSEnPol
SS_OEn_OUT/VBUSEnPol
VBUS_FAULT#
VBUS_FAULT#
GND
GND
VCONN_FAULT#
VCONN_FAULT#
CC_OEn_OUT/VconnEnPol
CC_OEn_OUT/VconnEnPol
CC_IN
CC_IN
RSVD
RSVD
CC_SEL_OUT
CC_SEL_OUT
RST
RST
SS_SEL_OUT
SS_SEL_OUT
GPIO2
GPIO2
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A0p
NO.
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port A0, High Speed Positive Signal
A0n
3
Port A0, High Speed Negative Signal
Port A1, High Speed Positive Signal
Port A1, High Speed Negative Signal
Port B0, High Speed Positive Signal
Port B0, High Speed Negative Signal
Port B1, High Speed Positive Signal
Port B1, High Speed Negative Signal
Port C0, High Speed Positive Signal
Port C0, High Speed Negative Signal
Port C1, High Speed Positive Signal
Port C1, High Speed Negative Signal
A1p
5
A1n
6
B0p
48
47
46
45
44
43
42
41
18
B0n
B1p
B1n
C0p
C0n
C1p
C1n
CC_IN
Selected CC signal back to the device as input - connect to CC_OUT pin
Copyright © 2015, Texas Instruments Incorporated
3
HD3SS2522
ZHCSDQ8 –APRIL 2015
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
11
12
19
9
CC_OUT
I/O
Selected CC signal as output - connect to CC_IN pin
CC Signal select pin input – Connect to CC_SEL_OUT
CC Signal select pin output – Connect to CC_SEL_IN
Active Low CC MUX Enable input – connect to CC_OEn_OUT
CC_SEL_IN
CC_SEL_OUT
CC_OEn_IN
I
O
I
Active Low CC MUX Enable output – connect to CC_OEn. The pin is also sampled
upon reset to set the polarity of the VCTRL1 and VCTRL2.
0 = VCTRL1/2 polarity is active high.
CC_OEn_OUT /
VconnEnPol
32
I/O
1 = VCTRL1/2 polarity is active low.
CC1
37
I/O
I/O
G
USB Type-C configuration channel for position 1
USB Type-C configuration channel for position 2
Ground
CC2
35
33 , 39, 53
28
GND
GPIO1
GPIO2
I/O
I/O
GPIO or SCL for FW update
29
GPIO or SDA for FW update
IMODE1
IMODE2
Low
Current Mode
Default
Low
IMODE1
IMODE2
26
27
I
Low
High
Mid (1.5 A)
Reserved
High (3A)
High
High
Low
High
MODE_LED
NC
15
O
High when UFP attach detected
1, 24, 49, 50, 51,
54, 55, 56
Not connected
RST
30
I
I/O
I
CC Controller Reset
Reserved
RSVD
10, 25, 31, 36, 38
8
SS_OEn_IN
Active Low SS MUX Enable input – connect to SS_OEn_OUT
Active Low SS MUX Enable output – connect to SS_OEn_IN. The pin is also sampled
upon reset to set the polarity of the VBUS_EN.
0 = VBUS_EN polarity is active high.
SS_OEn_OUT /
VBUSEnPol
34
I/O
1 = VBUS_EN polarity is active low.
SS_SEL_IN
7
I
SS Port select pin input – Connect to SS_SEL_OUT
SS Port select pin output – Connect to SS_SEL_IN
SS_SEL_OUT
20
O
Active low: Low when UFP attach detected. Open drain output. This signal drives
VBUS power switch.
VBUS_EN
21
O
VBUS_FAULT#
VCC
16
I
VBUS Fault signal in from VBUS Power switch. Active low.
3.3V Power
4 , 13, 14, 40, 52
P
I
VCONN_FAULT#
VCTRL1
17
22
23
VCONN Fault signal in from VCONN switches. Active low.
Active low open drain control output for VCONN switch for CC1
Active low open drain control output for VCONN switch for CC1
O
O
VCTRL2
4
Copyright © 2015, Texas Instruments Incorporated
HD3SS2522
www.ti.com.cn
ZHCSDQ8 –APRIL 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.4
–0.4
–0.4
MAX
UNIT
Power supply voltage range, VCC
4
Differential I/O (High bandwidth signal path, AxP/N, BxP/N, CxP/N)
Control Pins and Single Ended I/Os including CC1 and CC2
2.4
V
Voltage Range
VCC + 0.4
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
VCC
0.8
1.6
2
UNIT
V
VCC
Supply voltage
3.3
VIH
Input high voltage
Input low voltage
Differential voltage
Common voltage
Control/Status pins
2
V
VIL
Control/Status pins
–0.1
0
V
VI/O(Diff)
VI/O(CM)
Switch I/O diff voltage
Switch I/O common mode voltage
VPP
V
0
CC_OUT, CC_IN, and selected CC pin for
configuration
VI/O
Input / output voltage
0
VCC
V
VIN
TA
Input voltage
Selected CC pin for VCONN
HD3SS2522RHU
0
0
5.5
70
V
Operating free-air temperature
°C
7.4 Thermal Information
HD3SS2521A
RHU
THERMAL METRIC(1)
UNIT
56 PINS
31.6
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.9
8.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJB
8.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
5
HD3SS2522
ZHCSDQ8 –APRIL 2015
www.ti.com.cn
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply current
I(STANDBY) Standby current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 3.6 V,
SS_OEn, CC_OEn = GND
ICC
0.6
1
mA
VCC = 3.3 V, SS_OEN, CC_OEn =
VCC
15
µA
V
VBUS_FAULT#, VCONN_FAULT#, IMODE1, IMODE2, RST, RSVD, GPIO1, GPIO2
Positive-going input threshold
voltage
VIT+
0.45 x VCC
0.75 x VCC
Negative-going input threshold
voltage
VIT-
0.25 x VCC
0.55 x VCC
V
Vhys
RPULL
CI
nput voltage hysteresis (VIT+ – VIT–
)
VCC = 3 V
0.3
20
1
V
Pullup: VIN = GND,
Pulldown: VIN = VCC, VCC = 3 V
Pullup/pulldown resistor
35
5
50
kΩ
pF
nA
Input capacitance
VIN = GND or VCC
VIN = GND or VCC, VCC = 3 V,
Pullup/Pulldown disabled
ILGK
High-impedance leakage current
±50
VCTRL1, VCTRL2, VBUS_EN
(1)
VOL
Low-level output voltage
IOL(max) = 6 mA
GND + 0.3
V
MODE_LED
VOH
(1)
High-level output voltage
Low-level output voltage
IOH(max) = –6 mA
VCC – 0.3
V
V
(1)
VOL
IOL(max) = 6 mA
GND + 0.3
AxP/N, BxP/N, CxP/N
VCC = 3.6 V, VIN = 0 V, VOUT = 2 V
(ILKG on open outputs Port B and C)
130
4
µA
µA
ILGK
High-impedance leakage current
VCC = 3.6 V, VIN = 0 V, VOUT = 2 V
(ILKG on open outputs Port A)
CC1, CC2
VCC = 3.6 V, VIN = 0 V,
VOUT = 0 V to 4 V
ILGK
High-impedance leakage current
1
µA
(1) The maximum total current, IOH(max) and IOL(max), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
6
Copyright © 2015, Texas Instruments Incorporated
HD3SS2522
www.ti.com.cn
ZHCSDQ8 –APRIL 2015
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
AxP/N, BxP/N, CxP/N HIGH-BANDWIDTH SIGNAL PATH
tPD
Switch Propagation Delay
SS_SEL_IN -to-Switch tON
SS_SEL_IN -to-Switch tOFF
RSC and RL = 50 Ω
85
250
250
ps
ns
ns
tON
tOFF
70
70
RSC and RL = 50 Ω
50%
HS_SEL_IN/SS_SEL_IN90%
90%
10%
VOUT
tON
tOFF
Figure 1. Select to Switch tON and tOFF
Copyright © 2015, Texas Instruments Incorporated
7
HD3SS2522
ZHCSDQ8 –APRIL 2015
www.ti.com.cn
VCC
50 O
50 O
Ax(p)
Bx/Cx(p)
Bx/Cx(p)
Ax(p)
50 O
50 O
Bx/Cx(n)
Ax(n)
Ax(n)
Bx/Cx(n)
SEL
Cx/Bx (p)
50%
50%
Cx/Bx (n)
Ax (p)
50%
50%
Ax (n)
tP1
tP2
Inter-pair skew
tPD = Max(tp1, tp2)
tSK(O) = Difference between tPD for any two pairs of outputs
t1
t2
t3
t4
DCx/DBx/DAx (p)
50%
Cx/Bx/Ax (n)
Cx/Bx/Ax (p)
tSK(O)
Cx/Bx/Ax (n)
Intra-pair skew
tSK(b-b) = 0.5 X |(t4 t t3) + (t1 t t2)|
(1) Measurements based on an ideal input with zero intra-pair skew on the input, i.e. the input at A to B/C or the input at
B/C to A
(2) Inter-pair skew is measured from lane to lane on the same channel, e.g. C0 to C1
(3) Intra-pair skew is defined as the relative difference from the p and n signals of a single lane
Figure 2. Propagation Delay and Skew
8
Copyright © 2015, Texas Instruments Incorporated
HD3SS2522
www.ti.com.cn
ZHCSDQ8 –APRIL 2015
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
AxP/N, BxP/N, CxP/N
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Inter-pair output skew
(channel-channel)
tSK(O)
20
8
ps
RSC and RL = 50 Ω
tSK(b-b)
CON
Inter-pair output skew (bit-bit)
Outputs ON capacitance
Outputs OFF capacitance
ps
pF
pF
VIN = 0 V, outputs open, switch ON
VIN = 0 V, outputs open, switch OFF
1.5
1
COFF
VCC = 3.3 V, VCM = 0.5 V – 1.5 V,
IO = –8 mA
RON
Output ON resistance
5
8
2
Ω
On resistance match between
channels
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V;
IO = –8 mA
ΔRON
Ω
On resistance match between pairs
of the same channel
0.7
1.15
On resistance flatness
R(FLAT_ON)
RL
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V
Ω
[RON(MAX) – RON(MIN)
]
f = 2.5 GHz
f = 4 GHz
f = 2.5 GHz
f = 4 GHz
f = 2.5 GHz
f = 4 GHz
f = 2.5 GHz
f = 4 GHz
At 3 dB
–12
–11
–39
–35
–22
–19
–1.1
–1.5
6
Differential input return loss
(VCM = 0 V)
dB
XTALK
Differential crosstalk (VCM = 0 V)
Differential off-isolation (VCM = 0 V)
dB
dB
OIRR
Differential insertion loss
(VCM = 0 V)
IL
dB
BW
Bandwidth
GHz
Copyright © 2015, Texas Instruments Incorporated
9
HD3SS2522
ZHCSDQ8 –APRIL 2015
www.ti.com.cn
8 Detailed Description
8.1 Overview
HD3SS2522 is a 10-Gbps USB mux with Configuration Channel (CC) logic with DFP support. The HD3SS2522
presents itself as a DFP according to the USB Type-C Spec. The CC logic block monitors the CC1 and CC2 pin
voltages to determine when a USB port has been attached. Once a USB port has been attached, the CC logic
also determines the orientation of the cable and configures the USB SS mux accordingly.
The device provides an VBUS_EN signal to control legacy power switch to provide 5 V to VBUS. The device also
provides IOs needed to support 5 V VCONN sourcing for ecosystems implementing USB Type-C.
Excellent dynamic characteristics of the device allow high speed switching with minimum attenuation to the
signal eye diagram and little added jitter. The device also has low current consumption in Standby mode.
8.2 Functional Block Diagram
5V
VBUS
VCONN
CC_OEn_OUT
CC_OEn_IN
CC1
CC2
SS_OEn_OUT
SS_OEn_IN
CC_OUT
DFP
CC
CC_IN
Controller
CC_SEL_OUT
CC_SEL_IN
SS_SEL_OUT
SS_SEL_IN
MODE_LED
CRX1
VCC
CTX1
USB SS
MUX
CRX2
CTX2
USB SS Signals
USB
Host
HD3SS2522
USB 2.0 Signals
10
Copyright © 2015, Texas Instruments Incorporated
HD3SS2522
www.ti.com.cn
ZHCSDQ8 –APRIL 2015
8.3 Feature Description
8.3.1 Adaptive Common Mode Tracking for USB 3.1 MUX
The device provides an integrated USB 3.1 2:1 passive MUX. The MUX provides adaptive common mode
tracking allowing RX and TX channels to have different common mode voltage. This feature allows simpler
system implementation.
8.3.2 DFP-to-UFP Attach/Detach Detection
The HD3SS2522 monitors the CC lines as a Type-C DFP port. When the device senses that one of the CC has
a resistance to GND, it detects that an UFP is attached. The device provides an emulated ID signal (VBUS_EN)
in the event of a UFP attach.
The device also monitors specified pull down resistor according to Type-C specifications to determine if an active
cable is attached. In the event of active cable detection, HD3SS2522 provides necessary control signals for
VCONN switches that provide 5-V VCONN power to appropriate CC pin.
8.3.3 Plug Orientation/Cable Twist Detection
According to USB Type-C specifications plug can be inserted into a receptacle in either one of two orientations.
HD3SS2522 monitors for a pull-down resistors from an attached UFP port determining the MUX orientation.
8.3.4 VBUS Fault
HD3SS2522 does not take any action in case of a VBUS fault. VBUS fault needs to be handled by legacy power
management implementations.
8.3.5 VCONN Fault
If a VCONN fault is determined by the external power switch and fed into the device through VCONN_FAULT
pin, HD3SS2522 will latch it off until the cable is unplugged if there is a fault that does not clear within 5 ms.
Which is a sufficient amount of time to charge the 10-µF inrush capacitance.
8.4 Device Functional Modes
8.4.1 Unattached.DFP State
In this state, the HD3SS2522 as a DFP port is waiting to detect the presence of a UFP. The device injects pull-
up currents to both of the CC lines.
8.4.2 Attached.DFP State
When HD3SS2522 is in the Attached.DFP state, the port is attached and operating as a DFP. The device
continues to monitor the CC pins to make sure the appropriate pin is within vRd range specified by Type-C
specification. The device source current on one of the this CC pins and monitor its voltage. The port advertises
one of the three levels of VBUS power capability as specified in Type-C spec according to GPIO pins IMODE1
and IMODE2.
The device controls the VCONN power switches to apply VCONN to the unused CC pin if the voltage on the
unused CC pin is within the vRa range as specified in Type-C specification.
Copyright © 2015, Texas Instruments Incorporated
11
HD3SS2522
ZHCSDQ8 –APRIL 2015
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The HD3SS2522 is a high speed switch with integrated DFP CC controller. The HD3SS2522 can be
implemented in any USB Type-C DFP applications in conjunction with VBUS and VCONN switches.
9.2 USB Type-C DFP Typical Application
This section depicts the typical Type-C system with a USB Host or Hub. The Type C receptacle in this system is
a DFP only providing VBUS and VCONN upon the connection of UFP device. The HD3SS2522 DFP CC
controller determines the UFP attachment and provides VBUS and VCONN based upon the Type-C specification
state diagram and timing definition.
VBUS Switch
VBUS
5V
Vconn Switch
5V
Vconn Switch
CC1
CC2
CC_OUT
CC Pull-up Resistor value
per Type C Specification
Current Advertisement
definition
CC Switch
CC_SEL
CC_IN
VCTRL2
USB Host/
Hub
Type C
Receptacle
DigitalLogic
VCTRL1
VBUS_EN
SS_EN
SS_SEL
TX1
RX1
TX
RX
2:1 High
Speed switch
TX2
RX2
HD3SS2522
D+
D-
This Figure represents high level block diagram of the Type C DFP implementation not a circuit level implementation.
Figure 3. USB Type-C DFP
12
Copyright © 2015, Texas Instruments Incorporated
HD3SS2522
www.ti.com.cn
ZHCSDQ8 –APRIL 2015
USB Type-C DFP Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 1.
Table 1. Design Parameters
PARAMETER
VCC
VALUE
3.3 V
AxP/N, BxP/N, CxP/N VCM Voltage
CC_IN, CC_OUT, CC1, CC2
Control Pin Vmax for Low
Control Pin Vmax for High
0 V – 2 V
0 V –3.3 V
0.8 V
2 V
9.2.2 Detailed Design Procedure
9.2.2.1 USB Type-C Current Advertising
HD3SS2522 can be used to advertise USB Type-C current in conjunction with pull up resistors to CC1 and CC2
pins. These pull up resistors must meet the Type C spec requirements. The IMODE1 and IMODE2 setting must
match the CC resistor configuration for the current mode: default, mid or high.
9.2.2.2 VCONN and VBUS Power Switch Control
VCTRL1# and VCTRL2# are outputs from the HD3SS2522 CC controller to enable or disable the VCONN switch
based upon the orientation detection, audio accessory termination Ra detection, and/or fault condition.
VBUS_EN is an output from the HD3SS2522 CC controller to enable VBUS switch. Upon detection of UFP
attachment, the VBUS_EN is asserted to enable VBUS switch.
9.2.2.3 Firmware Upgradability
If necessary, the CC controller firmware (FW) can be updated via GPIO1, GPIO2 and SYS_COM_REQ. Contact
Texas Instruments for further assistance with upgrading the FW.
9.2.3 USB Type-C DFP Circuit Schematics with a Type C Receptacle
The schematics below depicts the circuit level implementation of the Type C system with HD3SS2522 and a DFP
only Type C connector. The system should select a power switch that complies with the Type C specification and
application requirements. The power switch can be controlled by the HD3SS2522. See the Detailed Design
Procedure section of the datasheet for design details.
Copyright © 2015, Texas Instruments Incorporated
13
HD3SS2522
ZHCSDQ8 –APRIL 2015
www.ti.com.cn
3P3V_VCC
Place near the part
C4
0.1uF
C5
C1
0.1uF
C2
0.1uF
C3
0.1uF
0.1uF
10V
10V
3P3V_VCC
U1
48
47
CTX2P
CTX2N
B0P
B0N
Connect to
Type USB3
TX/RX pins
C
USB3_TX0N
USB3_TX0P
2
3
A0P
A0N
Connect to
USB3 Host
44
43
CTX1N
CTX1P
C0P
C0N
46
45
CRX2P
CRX2N
3P3V
B1P
B1N
USB3_RX0N
USB3_RX0P
5
6
A1P
A1N
42
41
CRX1P
CRX1N
C1P
C1N
SS_SEL
7
SS_SEL
SS_SEL_IN
SS_SEL_OUT
CC2
20
35
37
Connect to
Type CC pins
and VCONN
switch
CC2
CC1
C
11
18
3P3V
CC_OUT
CC_IN
3P3V
CC1
CC_OE#
SS_OE#
9
8
R8
R7
R13
R14
100K
100K
NC, 100K
NC, 100K
CC_OE#_IN
SS_OE#_IN
Configured for
Active Low
Vconn_EN and
VBUS_EN
3P3V
3P3V
12
19
CC_SEL_IN
32
34
CC_OE#_OUT/VConnEnPol
SS_OE#_OUT/VBUSEnPol
Optional LED
for debug
purposes
CC_SEL_OUT
Pull-up or pull-down
resistor based upon
current configuration
26
27
IMODE1
IMODE2
IMODE1
IMODE2
LED
Green
R9
D3
Connect to VBUS
switch control signal
MODE_LED
660R
15
28
29
25
21
ID
MODE_LED
GPIO1
GPIO2
VBUS_EN
Add headers
for field
upgradability
GPIO1
GPIO2
SYS_COM_REQ
22
23
VCTRL1#
VCTRL2#
VCTRL1#
VCTRL2#
Connect to VCONN
switch control signal
SYS_COM_REQ
VCONN_FAULT#
VBUS_FAULT#
17
16
VCONN_FAULT#
VBUS_FAULT#
Connect to Vconn/VBUS switch
for fault condition detection
R10
100K
RST
30
RST
57
PAD
Resets CC Control
logic
HD3SS2522
VBUS
J3
TypeC Connector Pin Mapping
A4
A9
B4
B9
VBUS1
VBUS2
VBUS3
VBUS4
C8
10uF
GND
A1
A2
A3
GND
B12
B11
B10
A5
B5
CC1
CC2
CC1
CC2
SSTXP1
SSTXP2
SSRXP1
SSRXP2
A8
B8
CSBU1
CSBU2
SBU1
SBU2
SSTXN1
SSTXN2
SSRXN1
SSRXN2
USB2_N0
USB2_P0
A7
A6
DN1
DP1
VBUS A4
B9 VBUS
B6
B7
DP2
DN2
CC1
DP1
DN1
A5
A6
A7
B8 SBU2
B7 DN2
B6 DP2
B5 CC2
B4 VBUS
A2
A3
CTX1P
CTX1N
SSTXP1
SSTXN1
A11
A10
CRX2P
CRX2N
SSRXP2
SSRXN2
B2
B3
CTX2N
CTX2P
SSTXP2
SSTXN2
8
7
6
5
4
3
2
1
SBU1 A8
VBUS A9
Shield8
B11
B10
CRX1P
CRX1N
Shield7 SSRXP1
Shield6 SSRXN1
Shield5
A1
A12
B1
Shield4
Shield3
Shield2
Shield1
GND0
GND1
GND2
GND3
SSRXN2
SSRXN1
B3 SSTXN2
SSTXN1
A10
A11
A12
B12
USB_TypeC_Receptacle_
SSRXP2
SSRXP1
B2 SSTXP2
SSTXP1
GND
B1 GND
Figure 4. Example Schematics With a Type-C Receptacle
14
Copyright © 2015, Texas Instruments Incorporated
HD3SS2522
www.ti.com.cn
ZHCSDQ8 –APRIL 2015
10 Power Supply Recommendations
The HD3SS2522 does not have any special requirement for power supply as long as it is within the
recommended range. The device also does not have any special reset requirement.
11 Layout
11.1 Layout Guidelines
11.1.1 Critical Routes
The high speed differential signals must be routed with great care to minimize signal quality degradation between
the connector and the source or sink of the high speed signals by following the guidelines provided in this
document. Depending on the configuration schemes, the speed of each differential pair can reach a maximum
speed of 10 Gbps. These signals are to be routed first before other signals with highest priority.
•
Each differential pair should be routed together with controlled differential impedance of 85 to 90-Ω and 50-Ω
common mode impedance. Keep away from other high speed signals. The number of vias should be kept to
minimum. Each pair should be separated from adjacent pairs by at least 3 times the signal trace width. Route
all differential pairs on the same group of layers (Outer layers or inner layers) if not on the same layer. No 90
degree turns on any of the differential pairs. If bends are used on high speed differential pairs, the angle of
the bend should be greater than 135 degrees.
•
Length matching:
–
Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum.
The inter-pair matching of the differential pairs is not as critical as intra-pair matching. The SSTX and
SSRX pairs do not have to match while they need to be routed as short as possible.
•
•
•
Keep high speed differential pair traces adjacent to ground plane.
Do not route differential pairs over any plane split.
ESD components on the high speed differential lanes should be placed nearest to the connector in a pass
through manner without stubs on the differential path.
•
For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS2522 pins can be
swapped.
11.1.2 General Routing/Placement Rules
•
Route all high-speed signals first on un-routed PCB. The stub on USB2 D+ and D- pairs should not exceed
3.5 mm.
•
Follow 20H rule (H is the distance to ref-plane) for separation of the high speed trace from the edge of the
plane
•
•
Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines
All differential pairs should be routed on the top or bottom layer (microstrip traces) if possible or on the same
group of layers. Vias should only be used in the breakout region of the device to route from the top to bottom
layer when necessary. Avoid using vias in the main region of the board at all cost. Use a ground reference via
next to signal via. Distance between ground reference via and signal need to be calculated to have similar
impedance as traces.
•
•
All differential signals should not be routed over plane split. Changing signal layers is preferable to crossing
plane splits.
Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for high-
frequency return current path
•
•
Route differential traces over a continuous plane with no interruptions.
Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or
any magnetic source.
•
•
•
Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keep-
out distance where possible.
Decoupling caps should be placed next to each power terminal on the HD3SS2522. Care should be taken to
minimize the stub length of the trace connecting the capacitor to the power pin.
Avoid sharing vias between multiple decoupling caps.
Copyright © 2015, Texas Instruments Incorporated
15
HD3SS2522
ZHCSDQ8 –APRIL 2015
www.ti.com.cn
Layout Guidelines (continued)
•
•
•
Place vias as close as possible to the decoupling cap solder pad.
Widen VCC/GND planes to reduce effect of static and dynamic IR drop.
The VBUS traces/planes must be wide enough to carry max current for the application.
11.2 Layout Example
B0p
B0n
B1p
B1n
C0p
C0n
C1p
C1n
A0p
A0n
To USB
Host/Hub
To TypeC
Connector
A1p
A1n
Thermal PAD
Figure 5. Layout
16
版权 © 2015, Texas Instruments Incorporated
HD3SS2522
www.ti.com.cn
ZHCSDQ8 –APRIL 2015
12 器件和文档支持
12.1 商标
All trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS2522RHU
HD3SS2522RHUR
PREVIEW
ACTIVE
WQFN
WQFN
RHU
RHU
56
56
250
TBD
Call TI
NIPDAU
Call TI
0 to 70
0 to 70
2000 RoHS & Green
Level-3-260C-168 HR
HD3S2522
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RHU0056A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
11.15
10.85
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
2.4 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
21
28
20
29
SYMM
57
8.4 0.1
2X 9.5
1
48
0.30
0.18
52X 0.5
PIN 1 ID
56X
56
49
0.1
C A B
0.5
0.3
56X
0.05
4219076/A 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHU0056A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.4)
SEE SOLDER MASK
DETAIL
SYMM
49
56
56X (0.6)
56X (0.24)
1
48
52X (0.5)
(R0.05) TYP
(8.4)
(
0.2) TYP
VIA
SYMM
(10.8)
57
4X (1.28)
2X (3.95)
29
20
21
28
2X (0.95)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219076/A 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHU0056A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.63) TYP
49
56
56X (0.6)
56X (0.24)
1
48
52X (0.5)
(R0.05) TYP
5X (1.28)
(0.64)
57
SYMM
(10.8)
12X (1.08)
12X
(1.06)
20
29
21
28
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 57
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219076/A 01/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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