LM118QML_16 [TI]
LM118QML Operational Amplifier;
| 型号： | LM118QML_16 |
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TEXAS INSTRUMENTS |
| 描述： | LM118QML Operational Amplifier |
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LM118QML
LM118QML Operational Amplifier
Literature Number: SNOSAJ3
July 2005
LM118QML
Operational Amplifier
General Description
The LM118 is a precision high speed operational amplifier
designed for applications requiring wide bandwidth and high
slew rate. It features a factor of ten increase in speed over
general purpose devices without sacrificing DC perfor-
mance.
The high speed and fast settling time of this op amp makes
it useful in A/D converters, oscillators, active filters, sample
and hold circuits, or general purpose amplifiers. This device
is easy to apply and offers an order of magnitude better AC
performance than industry standards such as the LM709.
Features
The LM118 has internal unity gain frequency compensation.
This considerably simplifies its application since no external
components are necessary for operation. However, unlike
most internally compensated amplifiers, external frequency
compensation may be added for optimum performance. For
inverting applications, feed forward compensation will boost
the slew rate to over 150V/µs and almost double the band-
width. Overcompensation can be used with the amplifier for
greater stability when maximum bandwidth is not needed.
Further, a single capacitor can be added to reduce the 0.1%
settling time to under 1 µs.
n 15 MHz small signal bandwidth
n Guaranteed 50V/µs slew rate
n Maximum bias current of 250 nA
n Operates from supplies of 5V to 20V
n Internal frequency compensation
n Input and output overload protected
n Pin compatible with general purpose op amps
Ordering Information
NS Part Number
JAN Part Number
NS Package Number
Package Description
8LD TO-99 Metal Can
8LD CERDIP
LM118H/883
H08C
J08A
LM118J-8/883
LM118J/883
J14A
14LD CERDIP
LM118WG/883
WG10A
10LD Ceramic SOIC
Fast Voltage Follower
(Note 1)
20128313
Note 1: Do not hard-wire as voltage follower (R1 ≥ 5 kΩ)
© 2005 National Semiconductor Corporation
DS201283
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Connection Diagram
Metal Can Package
(Note 2)
Dual-In-Line Package
20128302
20128324
Top View
See NS Package Number H08C
Top View
See NS Package Number J14A
Ceramic SOIC Package
Dual-In-Line Package
20128363
Top View
See NS Package Number WG10A
20128303
Top View
See NS Package Number J08A
Note 2: Pin connections shown on schematic diagram and typical applica-
tions are for TO-5 package.
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2
Schematic Diagram
20128301
3
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Absolute Maximum Ratings (Note 3)
Supply Voltage
20V
Power Dissipation (Note 4)
8 LD Metal Can
750mW
1000mW
8LD CERDIP
14LD CERDIP
1250mW
10LD Ceramic SOIC
Differential Input Current (Note 5)
Input Voltage (Note 6)
Output Short-Circuit Duration
Operating Temperature Range
Thermal Resistance
θJA
600mW
10 mA
15V
Continuous
−55˚C ≤ TA ≤ +125˚C
@
8 LD Metal Can (Still Air 0.5W)
160˚C/W
86˚C/W
120˚C/W
66˚C/W
87˚C/W
51˚C/W
198˚C/W
124˚C/W
@
8 LD Metal Can (500LF / Min Air flow 0.5W)
@
8LD CERDIP (Still Air 0.5W)
@
8LD CERDIP (500LF / Min Air flow 0.5W)
@
14LD CERDIP (Still Air 0.5W)
@
14LD CERDIP (500LF / Min Air flow 0.5W)
@
10LD Ceramic SOIC (Still Air 0.5W)
10LD Ceramic SOIC (500LF / Min Air flow 0.5W)
θJC
@
8 LD Metal Can
48˚C/W
17˚C/W
8LD CERDIP
14LD CERDIP
17˚C/W
10LD Ceramic SOIC
22˚C/W
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
ESD Tolerance (Note 7)
−65˚C ≤ TA ≤ +150˚C
300˚C
2000V
Quality Conformance Inspection
Mil-Std-883, Method 5005; Group A
Subgroup
Description
Static tests at
Temp˚C
25
1
2
Static tests at
125
-55
25
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
5
125
-55
25
6
7
8A
8B
9
125
-55
25
10
11
12
13
14
125
-55
25
125
-55
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4
LM118
883 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified.
DC
VCC
=
15V, VCM = 0V
Sub-
groups
1
Symbol
Parameter
Conditions
Notes
Min Max
Unit
VIO
Input Offset Voltage
VCM
VCC
VCC
=
=
=
11.5V, RS = 50Ω
-4.0 +4.0
-6.0 +6.0
-4.0 +4.0
-6.0 +6.0
-4.0 +4.0
-6.0 +6.0
-4.0 +4.0
-6.0 +6.0
mV
mV
mV
mV
mV
mV
mV
mV
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
dB
dB
2, 3
1
20V, RS = 50Ω
2, 3
1
20V, VCM
=
15V,
RS = 50Ω
2, 3
1
VCC
VCM
VCC
VCC
VCM
VCC
VCC
=
=
=
=
=
=
=
5V, RS = 50Ω
2, 3
1
IIO
Input Offset Current
11.5V, RS = 10KΩ
20V, RS = 10KΩ
5V, RS = 10KΩ
11.5V, RS= 10KΩ
20V, RS = 10KΩ
5V, RS = 10KΩ
-50
-100 +100
-50 +50
-100 +100
-50 +50
-100 +100
+50
2, 3
1
2, 3
1
2, 3
1
IIB
Input Bias Current
1.0
1.0
1.0
1.0
1.0
1.0
70
250
500
250
500
250
500
2, 3
1
2, 3
1
2, 3
1, 2, 3
1, 2, 3
PSRR
CMRR
Power Supply Rejection Ratio
+VCC = 20V to 5V, RS = 50Ω
-VCC = -20V to -5V, RS = 50Ω
70
Common Mode Rejection Ratio VCC
=
15V, VCM
=
11.5V,
80
dB
1, 2, 3
RS = 50Ω
<
<
+IOS
-IOS
Short Circuit Current
Short Circuit Current
t
t
25mS
25mS
-65
5.0
5.0
-5.0
65
mA
mA
1, 2, 3
1, 2
80
mA
3
ICC
Power Supply Current
VCC
=
20V
8.0
7.0
11
mA
1
mA
2
mA
3
1
VIO adj.
RI
Input Offset Voltage Adjust
Input Resistance
VCC
VCC
=
=
20V
15V
4.0
1.0
-4.0
mV
(Note 9)
MΩ
V
1
VI
Input Voltage Range
(Note 8) -11.5 +11.5
1, 2, 3
4
AVS
Large Signal Voltage Gain
RL = 2KΩ, VO = 0 to -10V
RL = 2KΩ, VO = 0 to +10V
RL= 2KΩ
(Note 10)
(Note 10)
(Note 10)
(Note 10)
50
25
V/mV
V/mV
V/mV
V/mV
V
5, 6
4
50
25
5, 6
4, 5, 6
VO
Output Voltage Swing
+12
-12
5
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LM118
883 Electrical Characteristics (Continued)
AC Parameters
The following conditions apply parameters, unless otherwise specified.
AC
VCC
=
15V, VCM = 0V,
RS = 0Ω, RL = 2KΩ,, CL = 33pF
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Unit
V/µS
V/µS
SR
Slew Rate
VCC
=
20V, VI = -5V to +5V,
20V, VI = +5V to -5V,
50
50
7
7
AV=1
VCC
=
AV=1
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(maximum junction temperature), θ (package junction
JA
Jmax
to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is P
= (T
- T )/θ or the
A
Dmax
Jmax A JA
number given in the Absolute Maximum Ratings, whichever is lower.
Note 5: The inputs are shunted with back-to-back diodes for over voltage protection. Therefore, excessive current will flow if a differential input voltage in excess
of 1V is applied between the inputs unless some limiting resistance is used.
Note 6: For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 7: Human body model, 1.5 kΩ in series with 100 pF.
Note 8: Guaranteed by CMRR
Note 9: Guaranteed parameter not tested
Note 10: Datalog in K = V/mV
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6
Typical Performance Characteristics
Input Current
Voltage Gain
20128326
20128328
20128330
20128325
Power Supply Rejection
Input Noise Voltage
20128327
Common Mode Rejection
Supply Current
20128329
7
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Typical Performance Characteristics (Continued)
Closed Loop Output
Impedance
Current Limiting
Unity Gain Bandwidth
Inverter Settling Time
20128332
20128334
20128336
20128331
Input Current
20128333
Voltage Follower Slew Rate
20128335
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8
Typical Performance Characteristics (Continued)
Large Signal Frequency
Response
Open Loop Frequency
Response
20128337
20128338
Voltage Follower Pulse
Response
Large Signal Frequency
Response
20128340
20128339
Open Loop Frequency
Response
Inverter Pulse Response
20128342
20128341
9
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Auxiliary Circuits
Offset Balancing
Feedforward Compensation
for Greater Inverting Slew Rate
(Note 11)
20128310
Isolating Large Capacitive Loads
20128308
*Balance circuit necessary for increased slew.
Note 11: Slew rate typically 150V/µs.
Compensation for Minimum Settling Time
(Note 12)
20128311
Overcompensation
20128312
20128309
Note 12: Slew and settling time to 0.1% for a 10V step change is 800 ns.
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10
Typical Applications
Fast Voltage Follower
(Note 13)
20128313
Integrator or Slow Inverter
20128314
C
F
= Large
(C ≥ 50 pF)
F
*Do not hard-wire as integrator or slow inverter; insert a 10k-5 pF network in series with the input, to prevent oscillation.
Note 13: Do not hard-wire as voltage follower (R1 ≥ 5 kΩ)
Differential Amplifier
Fast Summing Amplifier
20128316
20128315
11
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Typical Applications (Continued)
Fast Sample and Hold
20128318
D/A Converter Using Ladder Network
20128319
*Optional — Reduces settling time.
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12
Typical Applications (Continued)
Four Quadrant Multiplier
20128317
∆Output zero.
*“Y” zero
+“X” zero
‡
Full scale adjust.
D/A Converter Using Binary Weighted Network
20128320
*Optional — Reduces settling time.
13
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Typical Applications (Continued)
Fast Summing Amplifier with Low Input Current
20128321
Instrumentation Amplifier
Wein Bridge Sine Wave Oscillator
20128322
20128323
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14
Revision History Section
Date
Released
07/12/05
Revision
Section
Originator
Changes
A
New Release, Corporate format
L. Lytle
1 MDS data sheet, MNLM118–X Rev 0A0
was converted into the Corp. datasheet
format. MDS datasheet will be archived.
15
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Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
NS Package Number H08C
Ceramic Dual-In-Line Package (J)
NS Package Number J08A
Ceramic Dual-In-Line Package (J)
NS Package Number J14A
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16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Ceramic SOIC (WG)
NS Package Number WG10A
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