LM8322JGR8X/NOPB [TI]
SPECIALTY MICROPROCESSOR CIRCUIT, PBGA36, ROHS COMPLIANT, MICRO ARRAY-36;
| 型号： | LM8322JGR8X/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA36, ROHS COMPLIANT, MICRO ARRAY-36 外围集成电路 |
| 文件： | 总46页 (文件大小：688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM8322
LM8322 Mobile I/O Companion Supporting Key-Scan, I/O Expansion, PWM, and
ACCESS.bus Host Interface
Literature Number: SNLS268F
OBSOLETE
October 4, 2011
LM8322
Mobile I/O Companion Supporting Key-Scan, I/O
Expansion, PWM, and ACCESS.bus Host Interface
Three host-programmable PWM outputs useful for smooth
LED brightness modulation.
Supports general-purpose I/O expansion on pins not
otherwise used for keypad interface.
Key-scan event storage in a FIFO buffer for up to 15
events.
Key events, errors, and dedicated hardware interrupts
request host service by asserting the IRQ output.
The correct receon of a command may be assumed, if
no error is repd frthe LM8322 after receiving a
command.
Wake-up m Halt n any matrix key-scan event,
any use e SF keys, oany activity on the ACCESS.bus
interfa.
■
■
■
■
■
1.0 General Description
The LM8322 Mobile I/O Companion is a dedicated device to
unburden a host processor from scanning a matrix-addressed
keypad. In addition, the LM8322 provides general-purpose
I/O expansion, and PWM outputs useful for dynamic LED
brightness modulation.
It communicates with the host through an I2C-compatible
ACCESS.bus interface. An interrupt output is available for
signaling key-press and key-release events. Communication
frequencies up to 400 kHz (Fast-mode) bus speed are sup-
ported. The LM8322 supports a predefined set of commands.
These commands enable a host device to keep control over
all functions.
■
2.0 Features
3.0 pplications
Key Features
bilhones
■
■
■
Supports keypad matrices of up to 8 × 12 keys plus 8
■
Perl Dtal Assistants (PDAs)
special-function (SF) keys for a total of 104 keys. SF keys
pull keypad scan inputs directly to ground, rather than
connecting to a keypad scan output.
Smart hdheld devices
Persoal media players
■
Supports I2C-compatible ACCESS.bus interface in slave
mode up to 400 kHz (Fast-mode).
■
4.0 Block Diagram
30013620
© 2011 National Semiconductor Corporation
300136
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
5.0 Ordering Information
NSID
Spec.
NOPB
NOPB
No. of Pins
Package Type
Micro-Array
Micro-Array
Temperature
−40 to + 85°C
−40 to + 85°C
Package Method
1000 pcs Tape & Reel
3500 pcs Tape & Reel
LM8322JGR8
LM8322JGR8X
36
36
NOPB = No PB (No Lead)
6.0 Pin Assignments
30013621
Top View
6–PiICRO-ARRAY Package
Pkage Number GRA36A
www.national.com
2
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Applications .................................................................................................................................... 1
4.0 Block Diagram ................................................................................................................................ 1
5.0 Ordering Information ........................................................................................................................ 2
6.0 Pin Assignments ............................................................................................................................. 2
7.0 Signal Descriptions .......................................................................................................................... 5
7.1 TERMINATION OF UNUSED SIGNALS ...................................................................................... 6
8.0 Application Example ........................................................................................................................ 7
8.1 FEATURES ............................................................................................................................. 7
9.0 Clocks ........................................................................................................................................... 8
9.1 INTERNAL EXECUTION CYCLE ............................................................................................... 8
9.2 BUFFERED CLOCK ................................................................................................................. 8
9.3 CLOCK CONFIGURATION ....................................................................................................... 9
10.0 Reset ......................................................................................................................................... 10
10.1 EXTERNAL RESET ........................................................................................................... 10
10.2 POWER-ON RESET (POR) ............................................................................................ 10
10.3 PIN CONFIGURATION AFTER RESET .......................................................................... 10
10.4 DEVICE CONFIGURATION AFTER RESET ................................................................ 11
10.5 CONFIGURATION INPUTS .......................................................................................... 11
10.6 INITIALIZATION .......................................................................................................... 11
10.7 INITIALIZATION EXAMPLE ............................................................................................. 13
11.0 Halt Mode ........................................................................................................................... 13
11.1 ACCESS.bus ACTIVITY ..................................................................................................... 13
12.0 Keypad Interface ................................................................................................................ 14
12.1 EVENT CODE ASSIGNMENT ....................................................................................... 14
12.2 KEYPAD SCAN CYCLES .............................................................................................. 14
12.2.1 Timing Parameters ................................................................................................... 15
12.2.2 Multiple Key Pressings ........................................................................................ 15
12.3 EXAMPLE KEYPAD CONFIGURATION ......................................................................... 15
13.0 General-Purpose I/O Ports .............................................................................................. 16
13.1 USING THE CONFIG_X PINS FOR G....................................................................... 17
13.2 GPIO TIMING .................................................................................................... 17
14.0 PWM Output Generation ............................................................................................... 18
14.1 COMMAND QUEUE ................................................................................................. 18
14.2 PWM TIMER OPERATION ................................................................................................ 18
14.3 PWM SCRIPT COMMANDS ................................................................................... 19
14.4 RAMP COMMAND ........................................................................................................... 20
14.5 SET_PWM COMMAND ............................................................................................... 20
14.6 GO_TO_START COM............................................................................................. 20
14.7 BRANCH COMMAND .......................................................................................... 20
14.8 END COMMAND .................................................................................................... 21
14.9 TRIGGER COMM.................................................................................................... 21
14.10 PWM SCRIPT E .................................................................................................... 21
14.10.1 PWM cript .............................................................................................. 22
14.10.2 PWM cript .............................................................................................. 22
14.10.3 PWM CScript .............................................................................................. 22
14.11 SELECTABLE SCRIPT EXAMPLE ........................................................................................ 23
15.0 Digital Multiplexers ....................................................................................................................... 24
16.0 Host Interface ............................................................................................................................. 25
16.1 START AND STOP CONDITIONS .......................................................................................... 25
16.2 CONTINUOUS COMMAND STRINGS .................................................................................... 25
16.3 DEVICE ADDRESS .............................................................................................................. 25
16.4 HOST WRITE COMMANDS .................................................................................................. 25
16.5 HOST READ COMMANDS .................................................................................................... 26
16.6 INTERRUPTS ...................................................................................................................... 26
16.7 INTERRUPT CODE .............................................................................................................. 27
16.8 ERROR CODE ..................................................................................................................... 27
16.9 WAKE-UP FROM HALT MODE .............................................................................................. 27
17.0 Host Commands .......................................................................................................................... 29
17.1 READ_ID COMMAND ........................................................................................................... 30
17.2 WRITE_CFG COMMAND ...................................................................................................... 30
17.3 READ_INT COMMAND ......................................................................................................... 31
17.4 RESET COMMAND .............................................................................................................. 31
3
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
17.5 WRITE_PULL_DOWN COMMAND ......................................................................................... 32
17.6 WRITE_PORT_SEL COMMAND ............................................................................................ 32
17.7 WRITE_PORT_STATE COMMAND ........................................................................................ 33
17.8 READ_PORT_SEL COMMAND ............................................................................................. 33
17.9 READ_PORT_STATE COMMAND ......................................................................................... 34
17.10 READ_FIFO COMMAND ..................................................................................................... 34
17.11 RPT_READ_FIFO COMMAND ............................................................................................. 34
17.12 SET_ACTIVE COMMAND ................................................................................................... 35
17.13 READ_ERROR COMMAND ................................................................................................. 35
17.14 SET_DEBOUNCE COMMAND ............................................................................................. 36
17.15 SET_KEY_SIZE COMMAND ................................................................................................ 36
17.16 READ_KEY_SIZE COMMAND ............................................................................................. 36
17.17 READ_CFG COMMAND ..................................................................................................... 37
17.18 WRITE_CLOCK COMMAND ................................................................................................ 37
17.19 READ_CLOCK COMMAND ................................................................................................. 37
17.20 PWM_WRITE COMMAND ................................................................................................... 38
17.21 PWM_START COMMAND ................................................................................................... 38
17.22 PWM_STOP COMMAND .................................................................................................. 38
18.0 Absolute Maximum Ratings .................................................................................................... 39
19.0 DC Electrical Characteristics ............................................................................................. 39
20.0 AC Electrical Characteristics ............................................................................................. 40
21.0 Physical Dimensions .......................................................................................................... 42
www.national.com
4
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
7.0 Signal Descriptions
Pin
A6
A5
F1
Function
KP-X0
I/O
Input
Input
Input
Input
I/O
Description
Wake-up input/Keyboard scanning input 0
Wake-up input/Keyboard scanning input 1
Wake-up input/Keyboard scanning input 2
Wake-up input/Keyboard scanning input 3
General-purpose I/O port 13
Wake-up input/Keyboard scanning input 4
General-purpose I/O port 12
Wake-up input/Keyboard scanning input 5
General-purpose I/O port 11
Wake-up input/Keyboard scanning input 6
General-purpose I/O port
Wake-up input/Keyboarcang input 7
General-purpose I/O por
Keyboard scanninutput 0
Keyboard scanntput 1
Keyboard scanning ou2
Keyboard nning output
GenerapoI/O port 8
Keyboard sing tput 4
General-purposport 7
Kard scaning output 5
Generse I/O port 6
oard anning output 6
l-purpose I/O port 5
ard scanning output 7
neral-purpose I/O port 4
Keyboard scanning output 8
32.768 kHz clock output
KP-X1
KP-X2
KP-X3
F2
A2
B3
A3
B4
GPIO_13
KP-X4
Input
I/O
GPIO_12
KP-X5
Input
I/O
GPIO_11
KP-X6
Input
I/O
GPIO_10
KP-X7
Input
Input
Output
Output
Output
Output
I/O
GPIO_09
KP_Y0
C6
C5
B6
KP-Y1
KP-Y2
KP-Y3
B5
B2
A1
B1
C2
GPIO_08
KP-Y4
Output
I/O
GPIO_07
KP-Y5
Output
I/O
GPIO_06
KP-Y6
Output
I/O
GPIO_05
KP-Y7
Outpu
I/O
GPIO_04
KP-Y8
Out
tput
I/O
E3
D5
E6
F6
SLOWCLKOUT
GPIO_03
KP-Y9
General-purpose I/O port 3
Keyboard scanning output 9
Multiplexer 2 input 1
tput
put
I/O
MUX2_IN1
GPIO_02
KP-Y
General-purpose I/O port 2
Keyboard scanning output 10
Multiplexer 2 input 2
Output
Input
I/O
MUX2
GPIO_
KP-Y11
General-purpose I/O port 1
Keyboard scanning output 11
Multiplexer 2 output
Output
Output
I/O
MUX2_OUT
GPIO_00
ACB_SDA
ACB_SCL
PWM_0
MUX_IN1
PWM_1
MUX_IN2
PWM_2
MUX1_OUT
CONFIG_2
GPIO_15
General-purpose I/O port 0
ACCESS.bus data signal
E2
E1
I/O
I/O
ACCESS.bus clock signal
Output
Input
Output
Input
Output
Output
Input
I/O
Pulse-width modulated output 0
Multiplexer 1 input 1
E4
F5
Pulse-width modulated output 1
Multiplexer 1 input 2
Pulse-width modulated output 2
Multiplexer 1 output
E5
Slave address select input 2
General-purpose I/O port 15
5
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
Pin
D6
D1
D2
Function
CONFIG_1
GPIO_14
XTAL_OUT
SLOWCLK
XTAL_IN
IRQ
I/O
Input
I/O
Description
Slave address select input 1
General-purpose I/O port 14
32.768 kHz crystal output
32.768 kHz clock
Input
Input
Input
Output
Input
n.a.
32.768 kHz crystal input
Interrupt request output
Reset Input
F3
C1
RESET
VCC
VCC
A4, F4
C3, C4,
D3, D4
GND
n.a.
Ground
7.1 TERMINATION OF UNUSED SIGNALS
TABLE 1. Termination of Unused Signals
Termination
Signal
Connect to VCC if not driven from an external Supervisory .
RESET
Connect to VCC or GND through a pullup or pulldowsistor becthe slave address is selected
by the level on this pin. This pin cannot be left ucted.
CONFIG_1
This pin is a high-impedance input and must be conneco VCC or GND if it is unused.
XTAL_IN
XTAL_OUT
This pin has a weak pullup and can be left en-circuit if it is unused.
These pins are dedicated keypad pins. In mmum configuration, these pins are keypad inputs
with weak pullups.
KP-X[2:0]
KP-X[7:3]
These pins are in high-impedance mode after powon initialization. There are two ways to handle
these pins if unused:
•
•
Connect to VCC or GND.
Program as inputs with lups outputs.
Care must be taken whto VCC or GND. Erroneous parameters sent with the
WRITE_PORT_SEL or T_STATE commands could cause excessive current
consumption. A betr appo leave unused keyboard inputs open-circuit and use the
WRITE_PORT_Sand WRITE_PORT_STATE commands to configure the pins as inputs with
weak pullups or ou
KP-X7 can only be an inputhis pin should be programmed as an input with a weak pullup.
These pindicated ypad pins. In the minimum configuration, these pins are keypad outputs
driven lo
KP-Y[2:0]
These pins mpedance mode after power-on initialization. There are two ways to handle
thesns if un
to VCC or GND.
s inputs with weak pullups or outputs
KP-Y[11:3]
Ce taken when connecting to VCC or GND. Erroneous parameters sent with the
WRITE_PORT_SEL or WRITE_PORT_STATE commands could cause excessive current
consumption. A better approach is to leave unused keyboard inputs open-circuit and use the
WRITE_PORT_SEL and WRITE_PORT_STATE commands to configure the pins as inputs with
weak pullups or outputs.
These pins must be connected to VCC or GND if they are not used for any optional function
described in the datasheet.
PWM_0,
PWM_1
Connect to VCC or GND through a pullup or pulldown resistor because the slave address is selected
by the level on this pin. This pin cannot be left unconnected.
This pin must be connected.
PWM_2/
CONFIG_2
IRQ
www.national.com
6
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
8.0 Application Example
30013601
GURE 1. Typical Application
8.1 FEATURES
•
•
Two LEDs driven by PWM outputs with programmable
ramp-up and ramp-down. PWM_2 (shared with GPIO_15
and CONFIG_2) could be used as an additional PWM
driver port to control a third external LED.
ACCESS.bus address is selected by the CONFIG_1 and
CONFIG_2 inputs. These pins may also be used as GPIO
pins after reset initialization has occurred. If extra GPIO
pins are not needed, CONFIG_1 and CONFIG_2 may be
tied directly to VCC and GND.
Crystal pins XTAL_IN and XTAL_OUT may be used to
connect to an external 32.768 kHz crystal or receive an
external 32.768 kHz clock input for running the PWM
peripheral. By default, the PWM is clocked by an on-chip
clock source.
The application example sh1 supports the fol-
lowing features:
•
•
8 x 9 standard keys.
8 special function keys (SF keys) with wake-up capability
by forcing a WAKE_INx pin to ground. Pressing a SF key
overrides any other key in the same row.
•
•
ACCESS.bus (I2C-compatible) interface for
communication with the host.
•
Hardware IRQ interrupt to host to signal keypad, error, and
status events. By default, this is an open-drain output, so
an external pullup resistor may be required to avoid false
assertion. The host can program this output for push-pull
mode, in which case the pullup might not be required, if
the host can ignore a false assertion before the LM8322
has been programmed.
7
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
Execution Clock. This clock is close to 32 kHz which is in
a good range to source the PWM function block as an
alternative to an external clock source.
External 32.768 kHz Clock — driven into the SLOWCLK
input. May be used internally as the timebase for the PWM
and driven on the SLOWCLKOUT output.
External 32.768 kHz Crystal — connected across the
XTAL_IN and XTAL_OUT pins (XTAL_IN is an alternate
function of the SLOWCLK pin). May be used internally as
the timebase for the PWM and driven on the
SLOWCLKOUT output.
9.0 Clocks
•
System Clock (mclk) — The system clock is in the range
of about 21 MHz (± 7%) typical. This clock is used to drive
the I2C compatible serial ACCESS bus and is the input
clock for other function blocks.
•
•
•
•
Processing and Command Execution Clock (tC) — The
internal processing is based on a 2 MHz clock. This clock
is derived from the System Clock.
Internal PWM Clock — The internal PWM clock is a fixed
scaled down clock (÷ 64) of the Processing and Command
30013602
FIGURE 2. Clock Architecture
9.1 INTERNAL EXECUTION CYCLE
9.2 BUFFERED CLOCK
The Processing - and Command - exelock is aout 2
MHz. This clock is stopped in Halt ly occurs
under control of the LM8322. Howeven set the
period of inactivity which causes the deenter Halt
mode.
The timebase for the PWM comes from any of three sources:
•
•
Prescaled internal Execution clock.
External 32.768 kHz clock received on the SLOWCLK
input.
•
On-chip oscillator with an external crystal connected
across XTAL_IN and XTAL_OUT.
Exit from Halt mode can be ny of these events:
•
•
Occurrence of a key-prese event.
A Start condition driven by n the ACCESS.bus
interface.
Any of these sources may be buffered and driven on the
SLOWCLKOUT output. The clock buffer is enabled with the
WRITE_CLOCK command.
•
Assertion of the RESET input.
If XTAL_IN is not used it must be terminated to VCC or GND.
After reset, the default timebase for the PWM outputs is the
internal execution clock divided by 64.
www.national.com
8
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
9.3 CLOCK CONFIGURATION
mand. The WRITE_CLOCK command must be issued only
once during system initialization. This command is used to
override the default settings.
Table 2 shows the clock configurations available by loading
the clock configuration register with the WRITE_CLOCK com-
TABLE 2. Clock Configuration Register
7
6
5
4
3
2
1
0
0
SLOWCLKOUT
0
0
SLOWCLKEN
0
RCPWM
Bit
Value
Description
0
Disable SLOWCLKOUT buffer.
Enable SLOWCLKOUT buffer.
SLOWCLKOUT
1
0
External 32.768 kHz crystal is installed between the XTAL_IN and XTAL_OUT pins.
SLOWCLKEN
External 32.768 kHz clock is received on the SLOWCLK pin, or no 32.768 kHz clock
is required.
1
00
01
10
11
On-chip RC clock divided by 64 drives the PWand clock buffer.
Reserved.
RCPWM
Reserved.
External 32.768 kHz clock or crystal des the PWnd clock buffer.
The SLOWCLKOUT signal is an alternate function of the pin
used for the KP-Y8 scanning output and the GPIO_03 port. If
the SLCLT function is enabled, these other functions
of the pin are unable.
9
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
When the RESET pin goes high, the LM8322 comes out of
the reset state within about 1400 ns.
10.0 Reset
The LM8322 may be reset by either an external reset, RE-
SET command, or an internally generated power-on reset
(POR) signal. The RESET input must not be allowed to float.
If the external RESET input is not used, it must be connected
to VCC, either directly or through a pull-up resistor.
10.2 POWER-ON RESET (POR)
The POR circuit is always enabled. When VCC rises above the
POR threshold voltage VPOR (about 1.2–1.5V), an on-chip
reset signal is asserted. The VCC rise time must be greater
than 20 µs and less than 10 ms, otherwise the on-chip reset
signal may deassert before VCC reaches the minimum oper-
ating voltage. While VCC is below VPOR, the LM8322 is held
in reset and a timer clocked by the on-chip RC clock is preset
with 0xFF (256 clock cycles). When VCC reaches a value
greater than VPOR, the timer starts counting down. When it
underflows, the on-chip reset signal is deasserted and the
LM8322 begins operation.
10.1 EXTERNAL RESET
The device enters a reset state immediately when the RE-
SET input is driven low. RESET must be held low for a
minimum of 700 ns to guarantee a valid reset. If RESET is
asserted at power-on, it must be held low until VCC rises above
the minimum operating voltage (1.62V). If an RC circuit is
used to drive RESET, it must have a time constant 5 times
(5×) greater than the VCC rise time to this level.
10.3 PIN CONFIGURATION AFTER RESET
When RESET goes low, the I/O ports are initialized immedi-
ately, any observed delay being only propagation delay.
Table 2 shows the n configuration after reset.
TABLE 3. Pin Configuration After Res
Pins
KP-X00
KP-X01
KP-X02
KP-X03
KP-X04
KP-X05
KP-X06
KP-X07
KP-Y00
KP-Y01
KP-Y02
KP-Y03
KP-Y04
KP-Y05
KP-Y06
KP-Y07
KP-Y08
KP-Y09
KP-Y10
KP-Y11
CONFIG_1
CONFIG_2
IRQ
After Reset
AfLM83nilization
High-impedance mode.
Input mode with an-cullup enabled.
High-impedancde, til host configures them as keypad inputs
or GPIO.
High-impedance mode.
High-impedance mode.
ve low.
igh-impedance mode, until host configures them as keypad outputs
or GPIO.
High-impedmode.
The ACCESS.bus slave address must be selected with external
pullup or pulldown resistors or direct connections to VCC or GND.
He mode.
High-idance mode.
Active drive low.
PWM_0
PWM_1
PWM_2
ACB_SDA
ACB_SCL
High-impedance mode.
High-impedance mode.
Open-drain mode.
Open-drain mode.
High-impedance mode. Terminate to VCC or GND if not used.
Weak pullup device.
High-impedance mode.
Weak pullup device.
XTAL_IN
XTAL_OUT
RESET
High-impedance mode.
High-impedance mode.
www.national.com
10
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
10.4 DEVICE CONFIGURATION AFTER RESET
After the LM8322 has completed its reset initialization, it will
have the following internal configuration:
•
PWM Clock — the PWM clock source is the on-chip clock
divided by 64. This remains in effect until changed by a
host command.
•
•
•
•
•
•
Keypad Size — 3 × 3.
Digital Multiplexers — disabled.
IRQ — enabled, active low.
NOINIT Bit — set.
Debounce Time — 3 scan cycles (about 12 milliseconds).
Active Time — 500 milliseconds.
10.5 CONFIGURATION INPUTS
The states sampled from the CONFIG_1 and CONFIG_2 in-
puts during reset select the ACCESS.bus address used by
the LM8322, as shown in Table 4. The address occupies the
high seven bits of the first byte of a bus transaction, with the
LSB (shown as X below) indicating the direction of transfer.
TABLE 4. Bus Address Selection
CONFIG_1
CONFIG_2
Bus Address
1000 010X
1000 011X
1000 100X
1000 101X
0
0
1
1
0
1
0
1
When these pins are used as GPIO ports, the design must
ensure that they have the desired states during reset. For ex-
ample, a 100-kohm resistor to ground can impose a logic 0
during reset without interfering with normal operation a
GPIO port.
30013603
FIGURE 3. LM8322 Initialization Behavior
10.6 INITIALIZATION
The LM8322 waits for a WRITE_CFG command from
host. During this time, IRQ is asserted to requeervice from
the host. Figure 3 describes the behavior of tLMol-
lowing reset.
Figure 4 shows the timing of IRQ relative to a RESET or POR
event and the WRITE_CFG command. 100 µs after a RE-
SET or POR event, IRQ is asserted and any READ_INT
command will return an interrupt code with the NOINIT bit set.
90 µs after a WRITE_CFG command is received, IRQ is de-
asserted.
30013604
FIGURE 4. IRQ Reset Timing
11
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
After sending the WRITE_CFG command, the host must send
a series of commands to configure the LM8322, as shown in
Figure 5 (see left hand side).
quest received from the LM8322 during operation. Such
requests will be made from the LM8322 as a result of key
pressed events, the detection of an error, the termination of
a PWM cycle and others.
This Flow - diagram illustrates also the basic host communi-
cation steps which the host must execute upon an IRQ re-
30013605
FIGURE 5. Host-Side LM8322 Initialization
www.national.com
12
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
10.7 INITIALIZATION EXAMPLE
Most of these settings can be verified by executing com-
mands such as READ_CONF, READ_PORT_SEL,
READ_CLOCK, etc.
In the following example, the LM8322 is configured as:
•
•
Keypad matrix configuration is 8 × 4.
GPIO_03 through GPIO_07 are available to use as GPIO
pins.
ALL GPIO pin states can be read using the
READ_PORT_STATE command, without regard to whether
the pin is an input or an output.
•
•
•
•
•
GPIO_03 is an output driven low.
An open-drain signal can be created by alternating between
input mode and driving the output low.
GPIO_4 and GPIO_5 are outputs driven high.
GPIO_06 and GPIO_07 are inputs with weak pulldowns.
GPIO_14 and GPIO_15 are inputs with weak pullups.
The PWM clock source is the internal execution clock
divided by 64 (about 32 kHz).
All GPIO s can sink and source 16 mA when configured as
an output.
Command
Encoding Parameter 1 Parameter 2
Description
Selects 36-pin package and disables the two digital
multiplexers.
WRITE_CFG
0x81
0x40
SLOWCLKOUT isabled, no external 32.768 kHz clock
required, PWlock source is internal.
WRITE_CLK
SET_KEY_SIZE
SET_ACTIVE
0x93
0x90
0x8B
0x08
0x84
0x4B
Selects a ketrix se of 8 × 4.
Sets the tive tiout 300 milliseconds (75 × 4
milliseds).
Sethe kebouncing time to about 12 milliseconds
(× 4 ms). Thictually the default and would not have
be performed.
SET_DEBOUNCE
0x8F
0x85
0x03
0x00
oure PIO_03, GPIO_04, and GPIO_05 as
os. nfigure GPIO_06, GPIO_07, GPIO_14, and
GPIOas inputs.
WRITE_PORT_SEL
0x38
x3F
Set he direction for the pullup/pulldown devices on
O_06 and GPIO_07 to pulldown. Set the direction for
e pullup/pulldown devices on GPIO_14 and GPIO_15
to pullup.
WRITE_PULL_DOWN
WRITE_PORT_STATE
0x84
0x86
0x00
0xC0
Set GPIO_04 and GPIO_05 to drive high. Enable the
pullups on GPIO_06, GPIO_07, GPIO_14, and
GPIO_15.
Halt mode is entered when no key-press event, key-release
event, or ACCESS.bus activity is detected for a certain period
of time (by default, 500 milliseconds). The mechanism for en-
tering Halt mode is always enabled in hardware, but the host
can program the period of inactivity which triggers entry into
Halt mode.
11.0 Halt Mode
The fully static architecture of the LM83ws stoppthe
internal RC clock in Halt mode, whiower con-
sumption to the minimum level. Figurcurrent in
Halt mode at the maximum VCC (1.98V) fto +85°C.
11.1 ACCESS.bus ACTIVITY
When the LM8322 is in Halt mode, any activity on the
ACCESS.bus interface will cause the LM8322 to exit from
Halt mode. However, the LM8322 will not be able to acknowl-
edge the first bus cycle immediately following wake-up from
Halt mode. It will respond with a negative acknowledgement,
and the host should then repeat the cycle.
The LM8322 will be prevented from entering Halt mode if it
shares the bus with peripherals that are continuously active.
For lowest power consumption, the LM8322 should only
share the bus with peripherals that require little or no bus ac-
tivity after system initialization.
30013606
FIGURE 6. Halt Current vs. Temperature at 1.98V
13
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
mode to minimize power consumption (typically <5 µA stand-
by current).
12.0 Keypad Interface
Table 5 lists the codes assigned to the matrix positions en-
coded by the hardware. Key-press events are assigned the
codes listed in Table 5 , but with the MSB set. When a key is
released, the MSB of the code is clear.
12.1 EVENT CODE ASSIGNMENT
After power-on reset and host initialization, the LM8322 starts
scanning the keypad. It stays active for a default time of about
500 ms after the last key is released, after which it enters Halt
TABLE 5. Keypad Matrix Code Assignments
KP-Y0 KP-Y1 KP-Y2 KP-Y3 KP-Y4 KP-Y5 KP-Y6 KP-Y7 KP-Y8 KP-Y9 KP-Y10 KP-Y11 SF Keys
KP-X0
KP-X1
KP-X2
KP-X3
KP-X4
KP-X5
KP-X6
KP-X7
0x01
0x11
0x21
0x31
0x41
0x51
0x61
0x71
0x02
0x12
0x22
0x32
0x42
0x52
0x62
0x72
0x03
0x13
0x23
0x33
0x43
0x53
0x63
0x73
0x04 0x05 0x06
0x14 0x15 0x16
0x24 0x25 0x26
0x34 0x35 0x36
0x44 0x45 0x46
0x54 0x55 0x56
0x64 0x65 0x66
0x74 0x75 0x76
0x07
0x17
0x27
0x37
0x47
0x57
0x67
0x77
0x08
0x18
0x28
0x38
0x48
0x58
0x68
0x78
0x09
0x19
0x29
0x39
0x49
0x59
0x
0x7
0x0A
0x1A
0x2A
0x3A
0x4A
0x5A
0A
7A
0x0B
0x1B
0x2B
0x3B
0x4B
0x5B
0x6B
0x7B
0x0C
0x1C
0x2C
0x3C
0x4C
0x5C
0x6C
0x7C
0x0F
0x1F
0x2F
0x3F
0x4F
0x5F
0x6F
0x7F
The codes are loaded into the FIFO buffer in the order in
events, anigure 7 shthe resulting sequence of event
which they occurred. Table 6 shows an example sequence of
codes loto the FIFO buffer.
TABLE 6. Example Sequence of Events
Event on Input Den tput
KP-X4 Y4
Event Number
Event Code
0xC5
Description
Key is pressed
1
2
3
4
5
6
7
8
0xB2
KP-X3
KP-X4
KP-X3
KP-X0
KP-
KP-
n.a.
KP
KP-Y4
Y1
KP-Y0
n.a.
Key is pressed
0x45
Key is released
0x32
Key is released
0x81
Key is pressed
0x5F
SF Key is released
Key is released
0x01
KP-Y0
n.a.
0x00
Indicates end of stored events
30013607
E 7. Example Event Codes Loaded in FIFO Buffer
12.2 KEYPAD SCAN CYCLE
The LM8322 starts new scan cycles at fixed time intervals of
about 4 milliseconds. If a change in the state of the keypad is
detected, the keypad is rescanned after a debounce delay.
When the state change has been reliably captured, it is en-
coded and written to the FIFO buffer.
Figure 8 shows the relationship between a KP-Yx output and
a KP-Xx input over multiple scan cycles during a key press
event. Between scan cycles, the KP-Yx outputs that are spec-
ified by the SET_KEY_SIZE command (0x90) for keypad
scanning are driven low.
30013608
FIGURE 8. Keypad Scan Cycles
www.national.com
14
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
During a scan cycle, only one KP-Yx output pin will be driven
low at any time, while the others are driven high or undriven.
At the time scale used in Figure 8, the low phase of a KP-Yx
output during a scan cycle is not visible. The KP-Xx input pins
are pulled high by weak pullups.
two simultaneous key pressings in one input row (see
Figure 9 on the left hand side.)
If all key pressings (two or more) are located in different
input rows (see Figure 9 on the right hand side) then the
key pressed events will be correctly found in the FIFO
buffer without any restriction.
•
There are capacitive loads on the KP-Xx inputs and KP-Yx
outputs due to protection circuits, wiring, etc. The LM8322 in-
serts delays to allow complete charging or discharging of
these loads before sampling the input levels on the KP-Xx
inputs. The maximum parasitic load capacitance on the KP-
Xx inputs is 5 nF.
After detecting a key-press or key-release event, the de-
bounce time specified by the SET_DEBOUNCE command
(0x8F) sets the minimum time for confirming the event before
the IRQ output is asserted.
If more than two keys are pressed simultaneously, the pattern
of key closures may be ambiguous, in which case the the in-
terrupt code indicates an error and the IRQ output is asserted
(if enabled).
30013609
FIGURE Simultaneous Keys Pressed
The SF keys connect KP-Xx inputs directly to ground. There
can be up to eight SF-keys. If any of these keys are pressed,
other keys that use the same KP-Xx pin are ignored.
•
In order to secdeteand store the key codes of
simultaus key gs in the same input row the
followrecautions must be taken from the host side:
“As sooas thst device has detected a key pressed event
the st must sene SET_ACTIVE Command with the pa-
rater set to “00”. This will prevent the LM8322 from enter-
iHAmode. If all keyboard events are resolved (no
reg keressed status in the LM8322 anymore) then
the hosend the SET_ACTIVE Command again with
the paramer setting the desired duration for the active time.
This wenable the LM8322 to enter low power HALT mode
ce e activity time has passed without detecting any
es.
12.2.1 Timing Parameters
Two timing parameters affect scanning of the keypad:
•
Debounce Time — minimum delay between detecting a
keypad event and confirming the event before asserting
IRQ. The default debounce time is 3 scan cycles (about
12 milliseconds), but the host can set values in the range
1–255 cycles (4–1020 milliseconds).
•
Active Time — period without detecting a state change in
the keypad that triggers entry into Halt mode, during wh
keypad scanning is suspended. The default active
500 milliseconds, but the host can set it values in th
4–1020 milliseconds. The active time must be great
the debounce time.
•
Once one or more key (pressed and/or released) events
have been read from the host with the help of the READ
FIFO command there are two conditions cleaning the
FIFO buffer contents:
A second execution of the READ FIFO Command or,
A new key event detected from the LM8322.
—
—
12.2.2 Multiple Key Pressings
If more than two keys are pressed at the smee
LM8322 stores all key pressed and released events ihe
FIFO buffer in the sequence in which tre decod.
12.3 EXAMPLE KEYPAD CONFIGURATION
Figure 10 shows an 8 × 4 keypad matrix. This configuration
occupies all scanning inputs (KP-X0 through KP-X7) and four
scanning outputs (KP-Y0 through KP-Y3). The remaining
scanning outputs KP-Y4 through KP-Y11 are available for use
as GPIO pins.
For multiple key pressings the followces have
to be respected:
•
A multiple key-press event is given if twore key-
press events are reported esponding key-
release event.
•
With the activity time set minimum and
maximum time (4 msec to is not safe to detect
15
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
30013610
FIGURE 10. KeyInterface Example
In the example above, three keys (Up, Down, and Selec
connected as SF keys (connected directly to groun
though they could have shared the KP-Xx inputs us
the scanned keys, the advantage of placing them on the
KP-Xx inputs is that it allows scanning the keyd while
SF key is pressed. If an SF key shares a KP-Xput with any
scanned keys, pressing the SF key prevents thm
reading the scanned keys.
13.0 General-Purpose I/O Ports
Any unused KP-Xx and KP-Yx pins may be used as general-
purpose I/O (GPIO) port pins. The WRITE_PORT_SEL
(0x85) command selects the port direction, in which a clear
bit in the parameter to the command selects the input direction
and a set bit selects the output direction.
The WRITE_PORT_STATE (0x86) command selects either
the port level when configured as output (by the
WRITE_PORT_SEL command) or when configured as an in-
put selects between a high-impedance input or an input with
a pullup or pulldown device. The selection between pullup or
pulldown devices is controlled by the parameter bytes to the
WRITE_PULL_DOWN (0x84) command. Clear bits in the pa-
rameter bytes select pullup devices, while set bits select
pulldown devices.
The SET_KEY_SIZE command includata bythat
specifies the keypad size. The uppedata byte
specify the number of KP-Xx inputer 4 bits
specify the number of KP-Yx outputs. Tm number
of inputs and outputs is 3. Thethe um keypad
configuration supports 3 × 3 s (total of 12 keys).
The maximum number of KPand the maximum
number of KP-Yx pins is 12nd KP-Yx pins not
used for the keyboard interfacsed for general-pur-
pose I/O.
Table 7 shows the GPIO port configurations selected by the
bits in the WRITE_PORT_SEL, WRITE_PORT_STATE, and
WRITE_PULL_DOWN command parameters.
For the example shown in Figure 10, the SET_KEY_SIZE
command would specify 8 KP-Xx inputs and 4 KP-Yx outputs.
TABLE 7. GPIO Port Control Bits
WRITE_PORT_SEL
WRITE_PORT_STATE
WRITE_PULL_DOWN
Description
High-Impedance Input
0
0
0
1
1
0
1
1
0
1
x
0
1
x
x
Input with Pullup Device
Input with Pulldown Device
Output, Drive Low
Output, Drive High
Any pins used as GPIO ports must be configured after the
peripheral configuration has been initialized with the
WRITE_CFG command (0x81) and the keypad configuration
has been initialized with the SET_KEY_SIZE command
(0x90). The default keypad configuration after reset is a 3 × 3
www.national.com
16
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
keyboard matrix. The default GPIO configuration is an input
with the pullup disabled.
WRITE_CFG command (0x81), in which case it will not be
available as a GPIO pin. It can also be configured as a PWM
output, which also would override its use as a GPIO pin.
13.1 USING THE CONFIG_X PINS FOR GPIO
13.2 GPIO TIMING
The CONFIG_1 and CONFIG_2 pins are available for use as
GPIO pins after power-on or reset. However, stable states
must be provided on these pins during power-on or reset to
select the ACCESS.bus (I2C) bus address.
When a WRITE_PORT_STATE command (0x86) is received,
the GPIO outputs do not change to their new states immedi-
ately or simultaneously. The first one changes 54 µs after the
command is acknowledged, and the others change at inter-
vals of 7.3 µs, as shown in Figure 11.
External pullup or pulldown resistors can be used to pull either
CONFIG_x pin low, while retaining the ability to drive it to an-
other state when used as a GPIO pin.
CONFIG_2 has two alternate functions, in addition to GPIO.
It can be configured as a multiplexer output using the
30013611
FIGURE 11. GPIO Port State Change Timing
17
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
•
•
PWM_START — start execution of the script.
PWM_STOP — stop execution of the script.
14.0 PWM Output Generation
Three pulse-width modulated (PWM) outputs are provided
with advanced capabilities for ramp-up and ramp-down of the
PWM duty cycle and execution of simple to complex com-
mand sequences. These capabilities are supported by three
independent script-execution engines capable of au-
tonomous operation after setup and launch by the host.
Figure 12 shows the architecture of a script-execution engine.
Please note: The PWM_STOP command might not take im-
mediate effect if the current command being executed is a
command with long execution time. If a PWM_STOP com-
mand is sent when the PWM engine is running a long RAMP
command, the PWM will only stop after the RAMP is com-
pleted.
The script commands have their own fixed-length 16-bit for-
mat and encoding unrelated to the variable-length, byte-
based format used for host commands. A script command is
sent by the host to the LM8322 as a parameter to the
PWM_WRITE command. Another parameter to the
PWM_WRITE command specifies an address in the script
command file for receiving the command.
14.1 COMMAND QUEUE
After the host issua PWM_START command, script com-
mands are read m thcript command file into a command
queue which cona comand file output register, com-
mand buffend accmand register. This allows one
command be active we another command is queued in
the comuffer, which allows seamless back-to-back
command execn.
A cmand loaded into the command file output register is
shroed to the 32.768 kHz clock and stored in the com-
mfer. Io command is currently active, the command
passroh to the active command register. In this case,
another mand can be read from the script command file,
which is queued in the command buffer. On completion of the
urreactive command, the contents of the command
are transferred to the active command register, and the
command buffer may then receive a new command.
The host does not have direct access to any of the registers
in the command queue. The operations which read script
commands from the script command file occur automatically
after the host issues the PWM_START command.
Script execution stops when the host sends a PWM_STOP
command or when the script engine executes an END com-
mand with the Reset bit set to 1. Executing an END command
with the Reset bit set to “1” or the reception of a PWM_STOP
command asserts IRQ to the host.
30013612
14.2 PWM TIMER OPERATION
The timers implement a fixed 256-cycle period with a pro-
grammable duty cycle and programmable ramp-up/ramp-
down of the duty cycle. Figure 13 shows the architecture of a
PWM timer.
FIGURE 12. PWM Scrution gine
The host has three commanng to the script ex-
ecution engine. The following are always associ-
ated with one particular PWM c
•
PWM_WRITE — load one word into the script command
file at a specified address.
www.national.com
18
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
30013613
FIGURE 13. PTir
The period counter is a free running 8-bit up-counte
starts counting when the script command file issues t
RAMP command. An END command stops the p
counter.
of the 32.768 kHz clock. The ramp counter saturates at either
0x00 or 0xFF depending on the ramp direction.
The number of increment or decrement steps is specified by
the INCREMENT field of the RAMP command, which is load-
ed into the step counter. Even if the ramp counter hits its
saturation value, the requested number of steps will be per-
formed. An option enables assertion of the IRQ output to the
host after the last step is performed.
The duty cycle of the PWM output is controllby tmp
counter. If the PWM period counter is active, thM out
signal is asserted while the period counter has a value ss
than or equal to the value of the ramp r.
The ramp counter can increment or rate con-
trolled by the prescaler and step time prescaler
selects a factor of 16 or 512 for dividing dfrequency
14.3 PWM SCRIPT COMMANDS
Table 8 summarizes the script commands.
TABLE 8. PWM Script Commands
Command
15
0
11
10
9
8
7
6
5
4
3
2
1
0
PRE
CALE
RAMP
STEPTIME
0
SIGN
INCREMENT
PWMVALUE
SET_PWM
GO_TO_
START
0
1
0
BRANCH
END
1
1
1
0
1
1
1
LOOPCOUNT
RESET
WAITTRIGGER
0
ADDRESS
0
1
0
0
TRIGGER
SENDTRIGGER
0
19
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
14.4 RAMP COMMAND
which supports both very fast and very slow ramps. The IN-
CREMENT field specifies the number of steps to be executed
by the command. The maximum value is 126, which corre-
sponds to half of full scale.
The RAMP command generates a duty-cycle ramp starting
from the current value. At each step, the ramp counter is in-
cremented or decremented by one, unless it has reached its
its saturation value (0xFF for increment, or 0x00 for decre-
ment). The time for one step is controlled by the PRESCALE
bit and STEPTIME field. The minimum time for one step is
0.49 milliseconds. and the maximum time is about 1 second,
There are two special cases in the instruction encoding. If all
bits and fields are 0, it is interpreted as the GO TO START
command. If the STEPTIME field is 0 but any other bit or field
is non-zero, it is interpreted as the SET_PWM command.
15
14
13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
PRESCALE
STEPTIME
SIGN
INCREMENT
Bit or Field
PRESCALE
STEPTIME
SIGN
Value
Description
0
1
Divide the 32.768 kHz clock by 16
Divide the 32.768 kHz clock by 512
Number of prescaled clock cycles er step
Increment ramp counter
1–63
0
1
Decrement ramp counter
INCREMENT
1–126
Number of steps executed this inn
14.5 SET_PWM COMMAND
lished biizing the duty cycle to either 100% or 0%
followed by a RP command.
The SET_PWM command loads the ramp counter from the
8-bit DUTYCYCLE field in the instruction.
Please note: Only 0x00 and 0xFF are valid values for the duty
cycle in SET_PWM command. Other values can be estab-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
DUTYCYCLE
Bit or Field
Value
0
Description
0%.
DUTYCYCLE
255
100%.
14.6 GO_TO_START COMMAND
The GO_TO_START command jumps to the st cnd
in the script command file.
15
14
13
12
1
10
8
7
6
5
4
3
2
1
0
0
14.7 BRANCH COMMAND
The BRANCH command jumppecificommand in
the script command file, with looping for a spec-
ified number of repetitions. re not allowed.
15
14
13
1
10
9
8
7
6
5
4
3
2
1
0
1
0
1
LOOPCOUNT
0
ADDRESS
Field
Value
0
Description
Loop until a STOP PWM SCRIPT command is issued by the host.
Number of repetitions to perform, biased by -1. The range is 0–62 repetitions.
LOOPCOUNT
1–63
Branch destination address in the script command file. If this field is greater than 59, no
looping will be performed.
ADDRESS
0–59
www.national.com
20
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
14.8 END COMMAND
Please note: If a PWM channel is waiting for the trigger (last
executed command was "TRIGGER") and the script execu-
tion is halted then the "END" command can’t be executed
because the previous command is still pending. This is an
exception - in this case the IRQ signal will not be asserted.
The END command terminates script execution and asserts
an interrupt to the host if the RESET bit is set to “1” or “0”.
If the END command is executed with the RESET bit set to
“1” , the PWM output will be disabled. If the RESET bit is “0”
when executing the END command, the PWM channel re-
mains active with the fixed duty cycle it was last set to.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
RESET
0
Bit
RESET
14.9 TRIGGER COMMAND
Value
Description
0
1
PWM_x output is active when script execution terminates.
PWM_x output is Tristate when script execution terminates.
Then, it will clear the trigger(s) and continue to the next com-
mand.
Triggers are used to synchronize operations between PWM
channels. A TRIGGER command that sends a trigger takes
sixteen 32.768 kHz clock cycles, and a command that waits
for a trigger takes at least sixteen 32.768 kHz clock cycles.
When a trigger entis stored by the receiving channel
and can only be cwhehe receiving channel executes
a TRIGGER ommaaits for the trigger.
A TRIGGER command that waits for a trigger (or triggers) will
stall script execution until the trigger conditions are satisfied.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
WAITTRIGGER
SENDTRIGGER
0
Field
Value
0001xx
000xx1
000x1x
000xx1
000x1x
0001xx
Description
Wait for ger from channel 2
Wait for trigrom hannel 0
Wgger fchannel 1
o channel 0
WAITTRIGGER
SENDTRIGGER
o channel 1
Ser to channel 2
14.10 PWM SCRIPT EXAMPLE
This example shows a complex ramping sequethat s
triggers for synchronization. Three scriptplement thex-
ample. Figure 14 shows the PWM outthis exaple.
30013614
FIGURE 14. PWM Outputs
21
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
14.10.1 PWM Channel 0 Script
Script
PWM_WRITE PWM_WRITE PWM_WRITE
Script
Command
Command
Address
Description
Parameter 1
Parameter 2
Parameter 3
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x01
0x05
0x09
0x0D
0x11
0x15
0x19
0x1D
0x40
0xE2
0x07
0x07
0x07
0x07
0xA1
0xC8
0x00
0x00
0x7E
0x7E
0xFE
0xFE
0x82
0x00
SET_PWM Initialize channel for 0% duty cycle
TRIGGER Wait for trigger from channel 2
RAMP
RAMP
RAMP
RAMP
BRANCH
END
Ramp up by 126 steps
Ramp up by 126 steps
Ramp down by 126 steps
Ramp down by 126 steps
Loop 2 times starting at address 0x02
Terminate script and assert IRQ to host
14.10.2 PWM Channel 1 Script
Script
PWM_WRITE PWM_WRITE PWM_WRITE
Script
Command
Command
Address
Description
Parameter 1
Parameter 2
Parameter 3
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x02
0x06
0x0A
0x0E
0x12
0x16
0x1A
0x1E
0x22
0x40
0xE2
0x0F
0x0F
0x0F
0x0F
0xA2
0xE0
0xC8
0xFF
0x00
0xFE
0xFE
0x7E
0x7E
0x0
0x08
SET_PInitialize hannel for 100% duty cycle
TRIER Wait for trigger from channel 2
AMP
RAP
Rp down by 126 steps
Ramp down by 126 steps
Ramp up by 126 steps
MP
R
Ramp up by 126 steps
BRANCH
Loop 3 times starting at address 0x02
TRGER Send trigger to channel 2
END
Terminate script and assert IRQ to host
14.10.3 PWM Channel 2 Script
Script
PWM_WRITE PWM_WRITPWE
Script
Command
Command
Address
Description
Parameter 1
Paramet2
Parameter 3
0x00
0x01
0x02
0x03
0x04
0x03
0x07
0x0B
0x0F
0x13
0x40
3
0
x00
0x7E
0x7E
0xFE
0xFE
SET_PWM Initialize channel for 0% duty cycle
RAMP
RAMP
RAMP
RAMP
Ramp up by 126 steps
Ramp up by 126 steps
Ramp down by 126 steps
Ramp down by 126 steps
Send triggers to channels 0 and 1,
wait for trigger from channel 1
Ramp up by 126 steps
0x05
0x1
xE1
0x06
TRIGGER
0x06
0x07
0x08
0x09
0x0A
0x1B
0x1F
0x23
0x27
0x2B
0x03
0x03
0x03
0x03
0xC8
0x7E
0x7E
0xFE
0xFE
0x00
RAMP
RAMP
RAMP
RAMP
END
Ramp up by 126 steps
Ramp down by 126 steps
Ramp down by 126 steps
Terminate script and assert IRQ to host
www.national.com
22
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
14.11 SELECTABLE SCRIPT EXAMPLE
Multiple scripts can be placed in a single buffer. The script
which is executed is selected by the address in the parameter
to the PWM_START command (0x96).
Script
Command
Address
PWM_WRITE
Parameter 1
PWM_WRITE PWM_WRITE
Script
Description
Parameter 2
Parameter 3 Command
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x01
0x05
0x09
0x0D
0x11
0x15
0x19
0x1D
0x21
0x25
0x29
0x2D
0x40
0x0F
0xC0
0x40
0x0F
0xC0
0x40
0x07
0x07
0x07
0x07
0xA5
0x00
0x33
0x00
0xFF
0xD5
0x00
0x00
0x7E
0x7E
0xFE
0xFE
0x
Set PWM_0 to 0% duty cycle
Ramp up 51 steps
Script 1
Script 2
Keep channel at 20% duty cycle
Set PWM_0 to 100% duty cycle
Ramp down 85 steps
Keep channel at 66.6% duty cycle
Set PWM_0 to 0% duty cycle
Raup 126 steps
Ru26 seps
Script 3
Script 4
Ramp n 6 steps
Ramp dow126 steps
p ten times to script address 0x07
SwitPWM_0 off (script 3 automatically
enters here)
0x0C
0x31
0xC8
x00
0x0D
0x0E
0x0F
0x10
0x35
0x39
0x3D
0x41
0x40
0x07
0xC0
0x40
0x
0x00
0
et PWM_0 to 0% duty cycle
Ramp up 37 steps
Script 5
Script 6
Keep channel at 14.5% duty cycle
Set PWM_0 to 0% duty cycle
(Alternates
between 25%
and 75% duty
cycle)
0x11
0x45
0x40
Ramp up 64 steps
0x12
0x13
0x14
0x15
.....
0x49
0x4D
0x51
0x
x3F
A0
0x7E
0xFE
0x12
Ramp up 126 steps
Ramp down 126 steps
Always branch to script address 0x12
Script 7
0x3B
To set a fixed duty cycle on a nnel ruires 3 steps
(see script 1 for duty cycles 9% and script 2 for
duty cycles from 51% to 10
Script 7 can be finished by two commands:
•
•
PWM_STOP command with parameter 0x01
PWM_START command with parameter 0x31 (start
PWM_0 from address 0x0C to run script 4)
To keep a PWM channel acta fixed duty cycle
on its output, the script must tee with the END com-
mand leaving the RESET bit clear. To switch this channel off,
the host must send another PWM_START command (0x96
followed by the parameter bytes) triggering the single com-
mand described in script 4. This END command will set the
RESET bit and the dedicated PWM output will be disabled.
The script address is the physical address to be used from
BRANCH instructions inside the script file buffer. The param-
eter 1 byte contains the same address with the 2 channel bits
appended and will be associated with the PWM_START com-
mand.
Script 3 will automatically enter into this command when the
10 loops of ramping up and down are executed.
23
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
TABLE 9. Digital Multiplexer Function Table
15.0 Digital Multiplexers
MUXxE MUXxSEL MUXx_IN MUXx_IN MUXx_OU
Two 2:1 multiplexers are provided for host-controlled digital
switching. Setting the MUX1EN or MUX2EN bits with the
WRITE_CFG command enables the corresponding multi-
plexer and its input and output signals, which overrides any
other functions which may use these pins. The MUX1 signals
are alternate functions of the PWM_x outputs. The MUX2
signals are alternate functions of three KP-Yx pins.
N Bit
Bit
2
1
T
Pin
Pin
Pin
1
1
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
X
X
The data select inputs for the multiplexers are controlled by
the MUX1SEL and MUX2SEL bits, which are written by the
WRITE_CFG command. If it is important to avoid momentarily
passing an incorrect input to the output, the select bit must be
loaded with a first WRITE_CFG command before sending a
second WRITE_CFG command to set the enable bit. The
truth table for the multiplexers is shown in Table 9.
MUXx_OU
T
0
X
X
X
not enabled
www.national.com
24
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
TABLE 11. Additional Commands
Command Description
Set debounce time
16.0 Host Interface
The two-wire ACCESS.bus interface is used to communicate
with a host. The ACCESS.bus interface is fully compliant with
the I2C bus standard. The LM8322 operates as a bus slave
at 400 kHz (Fast mode).
SET_DEBOUNCE
SET_ACTIVE
READ_CLK
Set active time
Verify PWM clock settings
Verify configuration setting
Read all port states (physical levels
All communication with the LM8322 over the ACCESS.bus
interface is initiated by the host, usually in response to an in-
terrupt request (IRQ low) asserted by the LM8322. The
LM8322 may request service from the host by asserting the
IRQ interrupt output.
READ_CFG
READ_PORT_STATE on pins)
Note: Very long continuous command strings exceeding 30
milliseconds could overrun the ability of the LM8322 to pro-
cess commands if the time from the last clock cycle of a
command until the next Start condition or Repeated Start
condition is always shorter than 60 µs. A very long command
chain could prevent the LM8322 from performing any watch-
dog service and onsequently could trigger a physical
RESET to the dee.
16.1 START AND STOP CONDITIONS
Every transfer is preceded by a Start condition or a Repeated
Start condition. The latter occurs when a command follows
immediately upon another command without an intervening
Stop condition. A Stop condition indicates the end of trans-
mission. Every byte is acknowledged by the receiver.
To avoid overrng LM8322, the host should not send
a Start condiion oped Start condition less than 100
µs after the st Stop cn or the last clock of a preceding
comman
16.3 DEVICE AESS
Thevice address is controlled by states sampled on the
CFIGand CONFIG_2 pins, as shown in Table 12. In the
firof a s transaction, a 7-bit address plus a direction
bit araast by the bus master to all bus slaves.
30013615
FIGURE 15. Start and Stop Conditions
TABLE 12. Device Address Selection
CFIG_1
CONFIG_2
Device Address
1000 010X
16.2 CONTINUOUS COMMAND STRINGS
0
0
1
1
0
1
0
1
A host device may send a continuous string of comm
using the Repeated Start condition, which would blo
other ACCESS.bus device from gaining control of th
After Power-On the host device must send multiple
mands to initialize the LM8322 device. A minimcomma
string will include the commands shown in Ta10.
1000 011X
1000 100X
1000 101X
If the CONFIG_1 and CONFIG_2 pins are left open, on-chip
pullups will select 1000 101X by default.
TABLE 10. Minimal Command Stri
16.4 HOST WRITE COMMANDS
Command
Deion
Some host commands include one or more data bytes written
to the LM8322. Figure 16 shows a SET_KEY_SIZE com-
mand, which consists of an address byte, a command byte,
and one data byte. The first byte is composed of a 7-bit slave
address in bits 7:1 and a direction bit in bit 0. The state of the
direction bit is 0 on writes from the host to the slave and 1 on
reads from the slave to the host.
Read vendare
version
READ_ID
Check OINT bt in
inter
READ_INT
WRITE_CFG
Co8322
SET_KEY_SIZE
Set he keypad
The second byte sends the command. The SET_KEY_SIZE
command is 0x90.
Set the clock mode for the PWM
unit
WRITE_CLK
The third byte send the data, in this case specifying the num-
ber of rows and columns for the keypad.
WRITE_PORT_SEL Set port direction for GPIO pins
WRITE_PORT_STATE Set port states of GPIO pins
A more comprehensive command string may include the ad-
ditional commands shown in Table 11.
25
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
30013616
FIGURE 16. Host Write Command
16.5 HOST READ COMMANDS
The bus master can send any number of Repeated Start con-
ditions without releasing control of the bus. This technique
can be used to impement atomic transactions, in which the
bus master sends command and then reads a register with-
out allowing any er dice to get control of the bus between
these events.
Some host commands include one or more data bytes read
from the LM8322. Figure 17 shows a READ_PORT_SEL
command which consists of an address byte, a command
byte, a second address byte, and two data bytes.
The first address byte is sent with the direction bit driven low
to indicate a write transaction of the command to the LM8322.
The second address byte is sent with the direction bit undriven
(pulled high) to indicate a read transaction of the data from
the LM8322.
The data is nt from ave to the host in the fourth and
fifth bytee fifth byte nds with a negative acknowledge-
ment (CKndicate the end of the data.
The Start (or Repeated Start) condition must be repeated
whenever the slave address or the direction bit is changed. In
this case, the direction bit is changed.
30013617
FIGURE 17. Host Read Command
16.6 INTERRUPTS
•
•
Termination of a PWM script (END command).
Any error condition, which is indicated by the error code.
The IRQ output may be asserted on these conditions:
•
Any new key-event after the last interrupt was asserted but
not yet acknowledged by reading the interrupt code.
www.national.com
26
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
16.7 INTERRUPT CODE
and deasserts the IRQ output. Table 13 shows the format of
the interrupt code.
The interrupt code is read and acknowledged with the
READ_INT command (0x82). This command clears the code
TABLE 13. Interrupt Code
7
6
5
4
3
2
1
0
PWM2END
PWM1END
PWM0END
NOINIT
ERROR
0
0
KEYPAD
Bit
Description
PWM2END
PWM1END
PWM0END
NOINIT
An END script command was executed by PWM channel 2.
An END script command was executed by PWM channel 1.
An END script command was executed by PWM channel 0.
The LM8322 is waiting for an initialization sequence.
An error condition occurred.
ERROR
KEYPAD
A key-press or key-release event occurred.
16.8 ERROR CODE
If the LM8322 reports an error, the READ_ERROR command
(0x8C) is used to read the error code. This command clears
the error code. Table 14 shows the format of the error code.
TABLE 14. Error Cde
7
6
5
4
3
2
1
0
0
FIFOOVR
0
0
0
EYO
CMDUNK
BADPAR
Bit
Description
FIFOOVER
KEYOVR
CMDUNK
BADPAR
Event occurred while the FIFs f
More than two keys essed multaneously.
Not a valid comm
Bad command pa
16.9 WAKE-UP FROM HALT MODE
terminates without being acknowledged (shown as NACK in
Figure 18). The host then aborts the transaction by sending
a Stop condition. After aborting the bus cycle, the host may
then retry the bus cycle. On the second attempt, the LM8322
will be able to acknowledge the slave address, because it will
be in Active mode.
Alternatively, the I2C specification allows sending a START
byte (00000001), which will not be acknowledged by any de-
vice. This byte can be used to wake up the LM8322 from Halt
mode. The LM8322 may also stall the bus transaction by
pulling the SCL low, which is a valid behavior defined by the
I2C specification.
Any bus transaction initiated by the host may ncouthe
LM8322 device in Halt mode or busy with prg a,
such as controlling the FIFO buffer or executing interrupr-
vice routines.
Figure 18 shows the case in which thommand
while the LM8322 is in Halt mode (Inten clock is
stopped). Any activity on the ACCESS.es up the
LM8322, but it cannot acknowfirst bcycle imme-
diately after wake-up.
The host drives a Start conby seven address
bits and a R/W bit. The host tSDA for one clock
period, so that it can be driven bM8322.
If the LM8322 does not drive SDA low during the high phase
of the clock period immediately after the R/W bit, the bus cycle
27
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
30013618
FIGURE 18. LM8322 Responds with NACK, Host Retries Command
www.national.com
28
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
17.0 Host Commands
Function
Cmd
0x80
0x81
Dir
R
Data Bytes
nnnn nnnn
pppp pppp
nnnn nnnn
Description
Read the manufacturer code (nnnn nnnn) and the device
revision number (pppp pppp).
READ_ID
WRITE_CFG
W
Write the hardware configuration register.
Read the interrupt code, deassert the IRQ output, and clear
the code. (If the NOINIT bit is set, it remains set and IRQ
remains asserted until a WRITE_CFG command is received.
READ_INT
RESET
0x82
R
nnnn nnnn
0x83
0x84
W
W
nnnn nnnn
nnnn nnnn
pppp pppp
nnnn nnnn
pppp pppp
nnnn nnnn
Reset the LM8322. Error if nnnn nnnn is not 0xAA.
WRITE_PULL_DO
WN
Select pullup (0) or pulldown (1) direction for the
corresponding general-purpose I/O (GPIO) port pins.
WRITE_PORT_SE
L
Select input (0) or output (1) for the corresponding general-
purpose I/O (GPIO) port pins.
0x85
0x86
W
W
For pins configured s inputs, 0 selects high-impedance
mode and 1 enaba ak pullup. For pins configured as
outputs, each t spethgic level driven on the pin.
WRITE_PORT_ST
ATE
pppp pppp
nnnn nnnn
pppp pppp
nnnn nnnn
pppp pppp
READ_PORT_SEL
0x87
0x88
0x89
0x8A
R
R
R
R
Read the n of the corresponding GPIO port pins.
Read e state on the corresponding GPIO port pins.
READ_PORT_STA
TE
Revent m the FIFO.
Up to 15 event
codes
READ_FIFO
Maximuevent codes stored in the FIFO.
Up to 15 evenRepeats a FIFO read without advancing the FIFO pointer,
RPT_READ_FIFO
codes
r exame to retry a read after an error.
Sime during which the LM8322 stays active before
entering Halt mode. The active time must be greater than the
ebounce time. The default time is 500 milliseconds. The
alid range is 1255. Active time = n × 4 milliseconds.
SET_ACTIVE
READ_ERROR
SET_DEBOUNCE
0x8B
0x8C
0x8F
W
R
nnn
nnnn n
nnnn nn
Read and clear the error code.
Set the time for rescanning the keypad after detecting a key-
press or key-release event to verify the event. The default
time is 12 milliseconds. The valid range is 1255. Debounce
time = n × 4 milliseconds and must not exceed active time.
W
SET_KEY_SIZE
READ_KEY_SIZE
READ_CFG
0x90
0x91
0x
0
nnn pppp
nnnn pppp
nnnn nnnn
nnnn nnnn
nnnn nnnn
aaaa aann
pppp pppp
qqqq qqqq
Set keypad size. nnnn = KP-Xx pins, pppp = KP-Yx pins
Read keypad size. nnnn = KP-Xx pins, pppp = KP-Yx pins
Read the hardware configuration register.
R
WRITE_CLOCK
READ_CLOCK
Write the clock configuration register.
Read the clock configuration register.
Write a command to the PWM script command file.
nn = PWM channel number (01, 10, or 11)
aaaaaa = address in script command file (059)
pppp pppp = high byte of script command
PWM_WRITE
0x95
W
qqqq qqqq = low byte of script command
PWM_START
PWM_STOP
0x96
0x97
W
W
aaaa aann
0000 00nn
Start script on channel nn (01, 10, or 11) at address aaaaaa.
Stop script on channel nn (01, 10, or 11).
29
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
Please note: The data bytes which follow the command can
be reads (toward the host) or writes (toward the LM8322). In
the case of the READ_FIFO and RPT_READ_FIFO com-
mands, the number of data bytes is variable, with the last
transaction indicated by returning a negative acknowledge-
ment (NACK).
17.1 READ_ID COMMAND
The READ_ID command consists of a command byte (0x80)
from the host and two data bytes from the LM8322.
The first data byte returns the manufacturer code, and the
second byte returns the device revision level.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
MANUFACTURER
REVISION
17.2 WRITE_CFG COMMAND
into the hardware configuration register. The default state of
this register is 0x80.
The WRITE_CFG command consists of a command byte
(0x81) and a data byte from the host. The data byte is loaded
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
1
IRQPST
0
0
0
MUX2EN MUX2SEL MUX1EN MUX1SEL
Bit
Value
Descripti
0
1
0
1
0
1
0
1
0
1
IRQ is an open-drain output.
IRQ is a push-pull output.
MUX2_OUT output disabled.
IRQPST
MUX2EN
MUX2SEL
MUX1EN
MUX1SEL
MUX2_OUT output enabled. This ovidey other function available on this pin.
If the MUX2 EN bit is 1, the MUXN1 input drthe MUX2_OUT output.
If the MUX2 EN bit is 1, the MU_INnput drives the MUX2_OUT output.
MUX1_OUT output disabled.
MUX1_OUT output enabled. This ovany other function available on this pin.
If the MUX1 EN bit is 1e MUX1_IN1 input drives the MUX1_OUT output.
If the MUX1 EN bit is 1, thUX12 input drives the MUX1_OUT output.
Please note: The WRITE_CFG COMMAND defines
hardware operation characteristics. It should be place
beginning of the initialization sequence driven from t
device after power on. It is not recommended to chan
configuration during run time. Anytime this comnd is us
it iializes important operating characteristics such as the
the GPIO port. This means that the GPIO pins must be re-
established
via
WRITE_PORT_SEL
and
WRITE_PORT_STATE commands in this case.
www.national.com
30
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
17.3 READ_INT COMMAND
interrupt code. An exception to this behavior occurs if the
NOINIT bit is set, in which case IRQ will not be deasserted
and the interrupt code will not be cleared until a WRITE_CFG
command is received.
The READ_INT command consists of a command byte (0x82)
from the host and a data byte from the LM8322. The data byte
is the interrupt code. Reading the interrupt code acknowl-
edges the interrupt (which deasserts IRQ) and clears the
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
PWM2END PWM1END PWM0END NOINIT ERROR
0
0
KEYPAD
Bit
Value
Description
No interrupt from PWM channel 2.
0
1
0
1
0
1
0
1
0
1
0
1
PWM2END
PWM1END
PWM0END
NOINIT
An END script command was executed by PWM channel 2.
No interrupt from PWM channel 1.
An END script command was executed by PWM channel 1.
No interrupt from PWM channel 0.
An END script command was executed by M channel 0.
Normal operation.
LM8322 is waiting for the initialization quen
No error condition is indicated.
ERROR
An error condition occurred.
No key-press or key-release ent is indica
A key-press or key-release ent curred.
KEYPAD
17.4 RESET COMMAND
set, ticaan external reset. The data byte must be
0xAA, ise no reset will occur and an error condition will
be signalled.
The RESET command consists of a command byte (0x83)
and one data byte from the host. The command causes a re-
7
6
5
4
3
2
1
0
7
5
4
3
2
1
0
1
0
0
0
0
0
1
1
0
1
0
1
0
1
0
31
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
17.5 WRITE_PULL_DOWN COMMAND
responding general-purpose I/O ports as pullups (0) or pull-
downs (1). The first data byte controls ports GPIO_15 through
GPIO_08, and the second byte controls ports GPIO_07
through GPIO_00.
The WRITE_PORT_SEL command consists of a command
byte (0x84) and two data bytes from the host. The data bytes
configure the pullup/pulldown device (if enabled) for the cor-
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
0
1
0
1
Bit
GPIO_xx
Value
Description
GPIO port pin pullup/pulldown device is a pullup.
GPIO port pin pullup/pulldown device is a pulldown.
0
1
17.6 WRITE_PORT_SEL COMMAND
puts (0) or outputs (1). The first data byte controls ports
GPIO_15 through GPIO_08, and the second byte controls
ports GPIO_07 thgh GPIO_00.
The WRITE_PORT_SEL command consists of a command
byte (0x85) and two data bytes from the host. The data bytes
configure the corresponding general-purpose I/O ports as in-
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
4
3
2
1
0
1
0
0
0
0
1
0
1
0
Bit
GPIO_xx
Value
Desiption
0
1
GPIO port pin is an input.
GPIO port pin is an utput.
The GPIO_09 port pin can only be configured as an input with
weak pullup/pulldown device.
www.national.com
32
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
17.7 WRITE_PORT_STATE COMMAND
have a weak pullup (1). For ports configured as outputs, the
data bytes control the state driven on the output. The first data
byte controls ports GPIO_15 through GPIO_08, and the sec-
ond byte controls ports GPIO_07 through GPIO_00.
The WRITE_PORT_STATE command consists of a com-
mand byte (0x86) and two data bytes from the host. For
general-purpose I/O ports configured as inputs, the data
bytes select whether the inputs are high-impedance (0) or
Bit
Value
Description
If the GPIO port pin is an input, pullup/pulldown device is disabled. If the GPIO port
pin is an output, it is driven low.
0
GPIO_xx
If the GPIO port pin is an input, pullup/pulldown device is enabled. If the GPIO port
pin is an output, it is driven high.
1
17.8 READ_PORT_SEL COMMAND
the corresponding ports, either input (0) or output (1). The first
data byte controls ports GPIO_15 through GPIO_08, and the
second byte controls ports GPIO_07 through GPIO_00.
The READ_PORT_SEL command consists of a command
byte (0x87) from the host and two data bytes from the
LM8322. The data bytes indicate the direction configured for
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
1
0
0
0
0
1
1
1
Bit
Value
Desion
0
1
GPIO port pin is an input
GPIO port pin is an ou
GPIO_xx
33
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
17.9 READ_PORT_STATE COMMAND
sponding ports. The first data byte controls ports GPIO_15
through GPIO_08, and the second byte controls ports
GPIO_07 through GPIO_00.
The READ_PORT_STATE command consists of a command
byte (0x88) from the host and two data bytes from the
LM8322. The data bytes indicate the states on the corre-
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
GP
IO_
07
1
0
0
0
1
0
0
0
Bit
Value
Description
If the GPIO port pin is an input, pullup is disabled. If the GPIO port pin is an
output, it is driven low.
0
GPIO_xx
If the GPIO port pin is an input, pullup is enabled. If the GPIO port pin is an
output, it is driven high.
1
17.10 READ_FIFO COMMAND
the FIFO is empthe last data byte is indicated by its value
(0x00) and a ativacknowledgement (NACK) on the
ACCESS.bus inteThata bytes correspond to key-
press and -releass, as described in Table 5.
The READ_FIFO command consists of a command byte
(0x89) sent from the host and a variable number of data bytes
received from the LM8322. The LM8322 will provide data until
7
6
5
4
3
2
1
0
7
6
5
4
3
2
0
7
6
5
4
3
2
1
0
1
0
0
0
1
0
0
1
FIFODTA
0x00
Field
Value
Dcription
0xxxxxxx
1xxxxxxx
Key-release event.
Key-press eve.
FIFODATA
17.11 RPT_READ_FIFO COMMAND
ata a previous READ_FIFO command, but without ad-
vng the FIFO pointer. It may be used to recover from an
error encountered during a READ_FIFO command.
The RPT_READ_FIFO command consists of a comm
byte (0x8A) and from the host and a variable number
bytes from the LM8322. This command provides th
7
6
5
4
3
2
1
0
7
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
1
0
1
FIFODATA
0x00
Field
Value
Description
0xxx
1xx
Keyelease event.
ey-press event.
FIFODATA
www.national.com
34
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
17.12 SET_ACTIVE COMMAND
press or key-release event before entering Halt mode. The
default active time is 500 milliseconds. The host can program
ACTIVETIME from 4–1020 milliseconds with a granularity of
4 milliseconds.
The SET_ACTIVE command consists of a command byte
(0x8B) and a data byte from the host. This command sets the
time that the LM8322 stays active without detecting a key-
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
1
0
1
1
ACTIVETIME
Field
Value
Description
0
Halt mode is disabled.
Active time = n × 4 milliseconds.
ACTIVETIME
1–255
17.13 READ_ERROR COMMAND
reading an interrupt code that indicates an error condition, this
command is used to read an error code that indicates the
cause of the error condition.
The READ_ERROR command consists of a command byte
(0x8C) from the host and a data byte from the LM8322. After
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
1
1
0
0
0
FIFOOVR
0
0
KOVR CMDUNK
BADPAR
Bit
Value
escripti
0
1
0
1
0
1
0
1
No FIFO overrun occurred.
FIFOOVR
KEYOVR
CMDUNK
BADPAR
Event occurred while the FIFO was
No keypad overrun ocred.
More than two keys e psed simultaneously.
No invalid command waoured.
Not a valid command.
No bad paramwas enuntered.
Bad command par
35
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
17.14 SET_DEBOUNCE COMMAND
bounce time is 12 milliseconds. The host can program DE-
BOUNCETIME from 4–1020 milliseconds with a granularity
of 4 milliseconds. The DEBOUNCETIME must not exceed the
active time set with the SET_ACTIVE command.
The SET_DEBOUNCE command consists of a command
byte (0x8F) and a data byte from the host. This command sets
the time that the LM8322 waits before rescanning the keypad
to confirm a key-press or key-release event. The default de-
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
1
1
1
1
DEBOUNCETIME
Field
Value
Description
DEBOUNCETIME
1–255
Active time = n × 4 milliseconds.
17.15 SET_KEY_SIZE COMMAND
value for either field is 3, which corresponds to a keypad con-
figuration that supports 3 × 3 + 3 SF keys (total of 12 keys).
The SET_KEY_SIZE command consists of a command byte
(0x90) and a data byte from the host. This command specifies
the keypad size in terms of the number of KP-Xx inputs and
KP-Yx outputs which are used. Any unused KP-Xx and KP-
Yx pins may be used for general-purpose I/O. The minimum
The maximum number of KP-Xx inputs is 8, and the maximum
number of KP-Yx outputs is 12. If the digital multiplexer MUX2
is used, the maximm number of KP-Yx outputs is 9. If the
SLOWCLKOUT is ued, the maximum number is 8.
7
6
5
4
3
2
1
0
7
6
5
2
1
0
1
0
0
1
0
0
0
0
K
KP-Y
Field
KP-X
KP-Y
Value
3–8
Destion
Number of KP-Xx inputs
Number of KP-Yx out.
3–12
17.16 READ_KEY_SIZE COMMAND
The hssue the command at any time to read the con-
figuration the keypad.
The READ_KEY_SIZE command consists of a command
byte (0x91) from the host and a data byte from the LM8322.
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
KP-X
KP-Y
Field
KP-X
KP-Y
Value
3–8
Description
umber of KP-Xx inputs.
uKP-Yx outputs.
3–12
www.national.com
36
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
17.17 READ_CFG COMMAND
data byte returns the settings in the hardware configuration
register. The default state of this register is 0x80.
The READ_CFG command consists of a command byte
(0x92) from the host and a data byte from the LM8322. The
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
1
0
0
1
0
0
0
0
0
Bit
Value
Description
0
1
0
1
0
1
0
1
MUX2_OUT output disabled.
MUX2EN
MUX2_OUT output enabled. This overrides any other function available on this pin.
If the MUX2 EN bit is 1, the MUX2_IN1 input drives the MUX2_OUT output.
If the MUX2 EN bit is 1, the MUX2_IN2 input drives the MUX2_OUT output.
MUX1_OUT output disabled.
MUX2SEL
MUX1EN
MUX1SEL
MUX1_OUT output enabled. This overrides y otfunction available on this pin.
If the MUX1 EN bit is 1, the MUX1_IN1 input the UX1_OUT output.
If the MUX1 EN bit is 1, the MUX1_INput driveMUX1_OUT output.
17.18 WRITE_CLOCK COMMAND
clock cfigon, as described in Table 2, Section 9.3
CLOCK CONFIATION.
The WRITE_CLOCK command consists of a command byte
(0x93) and a data byte from the host. This command sets the
7
6
5
4
3
2
1
0
7
4
3
2
1
0
1
0
0
1
0
0
1
1
CONFIGURATION
17.19 READ_CLOCK COMMAND
command reads bits 7:2 of the clock configuration, as de-
cribin Table 2 , Section 9.3 CLOCK CONFIGURATION.
The READ_CLOCK command consists of a command byte
(0x94) from the host and a data byte from the LM8322. T
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
1
0
0
1
0
1
0
CONFIGURATION
1
0
37
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
www.national.com
17.20 PWM_WRITE COMMAND
writes a 16-bit script command into a specified address in the
script command file of the specified PWM channel.
The PWM_WRITE command consists of a command byte
(0x95) and three data bytes from the host. The command
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5 4 3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
1
0
1
0
1
ADDRESS
CH
COMMAND
Bit
Value
Description
ADDRESS
0–59
01
Location in the PWM script command file.
PWM channel 0.
CH
10
PWM channel 1.
11
PWM channel 2.
17.21 PWM_START COMMAND
execution of the script command file at the specified address
for the specified channel.
The PWM_START command consists of a command byte
(0x96) and a data byte from the host. This command starts
7
6
5
4
3
2
1
0
7
6
5
3
2
1
0
1
0
0
1
0
1
1
0
ADDS
CH
Bit
Value
0–59
01
cription
ADDRESS
Start address in the PWM script comnd file.
PWM channel 0.
CH
10
PWM channel 1.
11
PWM channel 2.
17.22 PWM_STOP COMMAND
The PWM_STOP command consists of a command byte
(0x97) and a data byte from the host. This command stop
execution of the script command file for the specified ch
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
CH
Bit
Value
01
Description
PWM cnnel 0.
PWM hannel 1.
M channel 2.
CH
1
www.national.com
38
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
ESD Protection Level
(Human Body Model)
(Machine Model)
18.0 Absolute Maximum Ratings (Note
1)
2 kV
200V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Charge Device Model)
750V
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
100 mA
100 mA
−65°C to +140°C
Supply Voltage (VCC
Voltage at Any Pin
)
2V
-0.3V to VCC +0.3V
Maximum Input Current Without
Latchup
±100 mA
19.0 DC Electrical Characteristics
(Temperature: -40°C ≤ TA ≤ +85°C)
Data sheet specification limits are guaranteed by design, test, or statistical analysis.
Symbol
VCC
Parameter
Conditions
Min
Typ
Max
Units
Operating Voltage
1.62
1.98
V
IDD
Supply Current (Note 2)
Internal Clock,
No loads on pins,
1.9
<9
3.0
40
mA
VCC = 1.9V, TC = 0µs te 4)
IHALT
Standby Mode Current (Note 5)
Typical:
VCC = 1.9V, T= 25°C
µA
VIL
VIH
Logical 0 Input Voltage (Note 5)
0.3 x VCC
V
Logical 1 Input Voltage (Note 5)
0.7 x VCC
2
V
Hi-Z Input Leakage (TRI-STATE Output)
Port Input Hysteresis (Note 5, Note 6)
Weak Pull-Up/Pull-Down Current
Output Current Source (Push-Pull Mode)
Output CurrentSink (Push-Pull Mode)
VCC 1.8V
-2
µA
mA
µA
mA
mA
100
400
VCC<
150
-16
2V, VOH = 0.7 x VCC
V, VOL = 0.3 x VCC
16
Allowable Sink and Source Current per P(Note
7)
16
5
mA
pF
CPAD
Input Capacitance (Note 7)
Note 1: Absolute Maximum Ratings indicate limind which dge to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performaganteed. For guaranteed specifications and test conditions, see the Electrical Characteristics tables.
Note 2: Supply current is measured with inpC and outputs driven low but not connected to a load.
Note 3: TC = instruction cycle time (min. 0.7 µs).
Note 4: In standby mode, the internal cwitcheupply current in standby mode is measured with inputs connected to VCC and outputs driven low but
not connected to a load.
Note 5: Applied to all digital pins (except for SLOWCLK when configured for an external clock..
Note 6: Guaranteed by design, no
Note 7: The sum of all I/O sink/sourcst not e4xceed the maximum total current into VCC and out of GND as specified in the absolute maximem
ratings.
39
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
20.0 AC Electrical Characteristics
(Temperature: -40°C ≤ TA ≤ +85°C)
Data sheet specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
Typ Max Units
System Clock (mclk) (Note 8)
Internal RC
21
MHz
1.62V ≤ VCC ≤ 1.98V
1.62V ≤ VCC ≤ 1.98V
Processing and Command Execution Cycle (tC)
(Note 8)
0.5
μs
System Clock, Processing and Command
Execution Cycle Variation(Note 8)
7
%
General-Purpose I/O (GPIO)
Output Rise Time(Note 8)
Output Fall Time(Note 8)
CLOAD = 50 pF
15
15
ns
ns
ACCESS.bus Input Signals(Note 9)
Bus Free Time Between Stop and Start
Condition (tBUFi) (Note 8)
tLhigho
SCL Setup Time (tCSTOsi) (Note 8)
SCL Hold Time (tCSTRhi) (Note 8)
SCL Setup Time (tCSTRsi) (Note 8)
Data High Setup Time (tDHCsi) (Note 8)
Data Low Setup Time (tDLCsi) (Note 8)
SCL Low Time (tSCLlowi) (Note 8)
SCL High Time (tSCLhighi) (Note 8)
SDA Hold Time (tSDAhi) (Note 8)
SDA Setup Time (tSDAsi) (Note 8)
Before Stop Condition k
After Start Condition
Before Start Condition
Before SCL Rising Ee (R)
Before SCL RE
8
8
mclk
mclk
mclk
mclk
mclk
mclk
mclk
mclk
mclk
8
2
2
After SCL Falling Edge (
After SCL RE
12
12
0
After SCL FE
Before SCL RE
2
ACCESS.bus Output Signals (Note 9)
Bus Free Time Between Stop and Start
Condition (tBUFo)(Note 9)
tSCLhigho
SCL Setup Time (tCSTOso) (Note 8)
efore Sndition
Afteart Condition
fore art Condition
BefoSCL RE
efore SCL RE
ter SCL FE
tSCLhigho
tSCLhigho
tSCLhigho
tSCLhigho
tSCLhigho
16
SCL Hold Time (tCSTRho) (Note 8)
SCL Setup Time (tCSTRso) (Note 8)
Data High Setup Time (tDHCso) (Note
Data Low Setup Time (tDLCso) (Not
SCL Low Time (tSCLlowo) (Note 8)
SCL High Time (tSCLhigho) (Note 8)
SDA Hold Time (tSDAho) (N
SDA Valid Time (tSDAso) (
mclk
mclk
mclk
mclk
After SCL RE
16
After SCL FE
7
Before SCL RE
7
Note 8: Guaranteed by design, not te
Note 9: The ACCESS.bus interface implements and meets the timing necessary for interface to the I2C and SMBus protocol at logic levels. The bus drivers are
designed with open-drain output for bidirectional operation. The will not meet the AC timing and current/voltage requirements of the full bus specification.
www.national.com
40
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
30013619
FIGURE 19. ACB Start and Stop Condin Timing
41
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
21.0 Physical Dimensions inches (millimeters) unless otherwise noted
Micro Array Packag
Order Number LM8322GGR
NS Package mber GRA36A
www.national.com
42
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
Notes
43
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:29
Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
www.national.com
Products
www.national.com/amplifiers
Design Support
www.national.com/webench
Amplifiers
WEBENCH® Tools
App Notes
Audio
www.national.com/audio
www.national.com/timing
www.national.com/adc
www.national.com/interface
www.national.com/lvds
www.national.com/power
www.national.com/appnotes
www.national.com/refdesigns
www.national.com/samples
www.national.com/evalboards
www.national.com/packaging
www.national.com/quality/green
www.national.com/contacts
www.national.com/quality
www.national.com/feedback
www.national.com/easy
Clock and Timing
Data Converters
Interface
Reference Designs
Samples
Eval Boards
LVDS
Packaging
Power Management
Green Compliance
Distributors
Switching Regulators www.national.com/switchers
LDOs
www.national.com/ldo
www.national.com/led
www.national.com/vref
www.national.com/powerwise
Quality and Reliability
Feedback/Support
Design Made Easy
Applications & Markets
Mil/Aero
LED Lighting
Voltage References
PowerWise® Solutions
www.national.com/solutions
www.national.com/milaero
www.national.com/solarmagic
www.national.com/training
Serial Digital Interface (SDI) www.national.com/sdi
Temperature Sensors
PLL/VCO
www.national.com/tempsensors SolarMagic™
www.national.com/wireless
PowerWise® Design
University
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2011 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
National Semiconductor Europe
Technical Support Center
Email: europe.support@nsc.com
National Semiconductor Asia
Pacific Technical Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Technical Support Center
Email: jpn.feedback@nsc.com
Email: support@nsc.com
Tel: 1-800-272-9959
www.national.com
300136 Version 7 Revision 2 Print Date/Time: 2011/10/04 16:24:30
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Transportation and Automotive www.ti.com/automotive
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
相关型号：
LM8323
LM8323 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
TI
LM8325-1
LM8325-1 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
TI
LM8327
LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
TI
LM8327JGR8
LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
TI
LM8327JGR8X
LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
TI
LM8328
LM8328 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
TI
LM8328TME
LM8328 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
TI
LM8328TMX
LM8328 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface
TI
©2020 ICPDF网 联系我们和版权申明