LM98714CCMTX/NOPB [TI]
LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output; LM98714三通道， 16位， 45 MSPS模拟前端与LVDS / CMOS输出
| 型号： | LM98714CCMTX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output |
| 文件： | 总114页 (文件大小：6945K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM98714
www.ti.com
SNAS254A –OCTOBER 2006–REVISED JANUARY 2014
LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output and
Integrated CCD/CIS Sensor Timing Generator
Check for Samples: LM98714
1
FEATURES
DESCRIPTION
The LM98714 is a fully integrated, high performance
16-Bit, 45 MSPS signal processing solution for digital
color copiers, scanners, and other image processing
applications. High-speed signal throughput is
achieved with an innovative architecture utilizing
Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold
(S/H) inputs (for Contact Image Sensors and CMOS
2
•
LVDS/CMOS Outputs
•
•
•
•
LVDS/CMOS Pixel Rate Input Clock or ADC
Input Clock
CDS or S/H Processing for CCD or CIS
Sensors
Independent Gain/Offset Correction for Each
Channel
image sensors). The signal paths utilize
8 bit
Digital Black Level Correction Loop for Each
Channel
Programmable Gain Amplifiers (PGA), a ±9-Bit offset
correction DAC and independently controlled Digital
Black Level correction loops for each input. The PGA
and offset DAC are programmed independently
allowing unique values of gain and offset for each of
the three inputs. The signals are then routed to a
45MHz high performance analog-to-digital converter
(ADC). The fully differential processing channel
shows exceptional noise immunity, having a very low
noise floor of –74dB. The 16-bit ADC has excellent
dynamic performance making the LM98714
transparent in the image reproduction chain.
•
•
Programmable Input Clamp Voltage
Flexible CCD/CIS Sensor Timing Generator
APPLICATIONS
•
•
•
•
Multi-Function Peripherals
Facsimile Equipment
Flatbed or Handheld Color Scanners
High-Speed Document Scanner
CCD/CIS Sensor
KEY SPECIFICATIONS
Analog Front End
SPI
•
Maximum Input Level: 1.2 or 2.4 Volt Modes
(Both with + or - Polarity Option)
–
Image Processor/ASIC
LM98714
Data Output
•
•
•
•
•
•
•
•
•
•
•
•
ADC Resolution: 16-Bit
Motor
Controllers
ADC Sampling Rate: 45 MSPS
INL: ±23 LSB (Typ)
CCD Timing
Generator
Sensor Drivers
Figure 1. System Block Diagram
Channel Sampling Rate: 15/22.5/30 MSPS
PGA Gain Steps: 256 Steps
PGA Gain Range: 0.7 to 7.84x
Analog DAC Resolution: ±9 Bits
Analog DAC Range: ±300mV or ±600mV
Digital DAC Resolution: ±6 Bits
Digital DAC Range: -1024 LSB to + 1008 LSB
SNR: -74dB (@ 0 dB PGA Gain)
Power Dissipation: 505 mW (LVDS) 610 mW
(CMOS)
•
•
Operating Temp: 0 to 70°C
Supply Voltage: 3.3 V Nominal (3.0 V to 3.6 V
Range)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2014, Texas Instruments Incorporated
LM98714
SNAS254A –OCTOBER 2006–REVISED JANUARY 2014
www.ti.com
LM98714 Overall Chip Block Diagram
Figure 2. Chip Block Diagram
2
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LM98714 Pin Out Diagram
CLK3
CLK2
CLK1
SH
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK4
2
V
C
3
DGND
CLK5
4
RESET
SH_R
SDIO
SCLK
5
CLK6
6
CLK7
7
CLK8
8
CLK9
9
CLKOUT/CLK10
SEN
AGND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
D
DGND
V
A
VREFB
VREFT
DOUT0/TXOUT0-
DOUT1/TXOUT0+
DOUT2/TXOUT1-
DOUT3/TXOUT1+
DOUT4/TXOUT2-
DOUT5/TXOUT2+
DOUT6/TXCLK-
DOUT7/TXCLK+
INCLK-
48 Pin TSSOP
(not to scale)
V
A
AGND
VCLP
V
A
AGND
OS
R
AGND
OS
INCLK+
G
AGND
OS
DVB
V
R
B
AGND
DGND
Figure 3. LM98714 Pin Out Diagram
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Typical Application Diagram
5
4
3
2
1
D
D
C
B
A
Serial Interface and device
Flexible CCD Timing Gener
control bus
ator Outputs
+3.3V
0.1uF
CLK3
CLK2
CLK1
SH
LM98714
CLK4
48
1
2
3
4
CLK3
CLK2
CLK1
SH
CLK4
47
46
45
44
43
42
41
40
VC
DGND
CLK5
CLK6
CLK7
CLK8
CLK9
+3.3V
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CCD Clock
Driver(s)
Connector
Connector
5
6
7
8
9
RESET
SH_R
SDIO
SCLK
SEN
4.7uF
Ribbon
Cable
C
CLKOUT_CLK10
+3.3V
0.1uF
39
38
**
VD
DGND
TXOUT0-
TXOUT0+
0.1uF
0.1uF
10
11
12
13
14
15
16
17
AGND
VA
VREFB
VREFT
VA
AGND
VCLP
VA
0.1uF
TXOUT1-
TXOUT1+
37
36
35
34
33
32
31
30
D0_TXOUT0-
D1_TXOUT0+
D2_TXOUT1-
D3_TXOUT1+
D4_TXOUT2-
D5_TXOUT2+
D6_TXCLK-
Image
Sensor
Clock
0.1uF
LVDS
TXOUT2-
TXOUT2+
Deserial izer
(DS90CR218A
or equiv.)
0.1uF
ASIC
Inputs
TXCLK-
TXCLK+
0.1uF
D7_TXCLK+
+3.3V
R_cmos_clk
0 Ohm
*
29
28
INCLK-
INCLK+
18
19
20
21
22
23
24
AGND
OSr
AGND
OSg
AGND
OSb
AGND
R_lvds_clk
100 Ohm
*
27
26
25
**
DVB
VR
DGND
INCLK-
+3.3V
INCLK+
B
CLOCK Gen
0.1uF
0.1uF
CCD or CIS
Image Sensor
*
If using an LVDS input clock, temi
pins with a 100 Ohm resistor and rem
from INCLK- to ground.
nate clock at the
ove 0 Ohm resistor
If using a CMOS input clock, short
ground and remove the 100 Ohm L
resistor.
the INCLK- pin to
VDS termination
A
National Semiconductor Corporation
East Coast Labs Design Center
Maintain 100 Ohm Impedance for all
pair paths.
LVDS differential
**
Title
LM98714 Typical Application Diagram
Size
B
Document Number
<Doc>
Rev
A
Date:
Friday, January 27, 2006
Sheet
1
1
of
1
5
4
3
2
Figure 4. Typical Application Diagram
4
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Pin
SNAS254A –OCTOBER 2006–REVISED JANUARY 2014
PIN DESCRIPTIONS(1)
Name
CLK3
CLK2
I/O
Typ
Res
PU
Description
1
O
O
O
O
I
D
Configurable sensor control output.
Configurable sensor control output.
Configurable sensor control output.
2
D
D
D
D
D
D
D
D
P
P
A
A
P
P
A
PD
PU
PD
PU
PD
3
CLK1
SH
4
Sensor - Shift or transfer control signal for CCD and CIS sensors.
Active-low master reset. NC when function not being used.
External request for an SH pulse.
5
RESET
SH_R
SDIO
SCLK
SEN
6
I
7
I/O
Serial Interface Data Input
8
I
I
PD
PU
Serial Interface shift register clock.
9
Active-low chip enable for the Serial Interface.
10
11
12
13
14
15
16
AGND
VA
Analog ground return.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.
Top of ADC reference. Bypass with a 0.1μF capacitor to ground.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Analog ground return.
VREFB
VREFT
VA
O
O
AGND
VCLP
IO
IO
Input Clamp Voltage. Normally bypassed with a 0.1μF, and a 4.7μF capacitor to AGND.
An external reference voltage may be applied to this pin.
16
VCLP
A
Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 10μF capacitor to AGND.
An external reference voltage may be applied to this pin.
17
18
19
20
21
22
23
24
25
26
VA
P
P
A
P
A
P
A
P
P
P
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Analog ground return.
AGND
OSR
I
I
I
Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.
Analog ground return.
AGND
OSG
Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.
Analog ground return.
AGND
OSB
Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.
Analog ground return.
AGND
DGND
VR
Digital ground return.
Power supply input for internal voltage reference generator. Bypass this supply pin with a
0.1μF capacitor.
27
28
DVB
O
I
D
D
Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND.
INCLK+
Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is
selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation.
29
30
INCLK-
I
D
D
Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.
DOUT7/
TXCLK+
DOUT6/
TXCLK-
DOUT5/
TXOUT2+
DOUT4/
TXOUT2-
DOUT3/
TXOUT1+
DOUT2/
TXOUT1-
O
Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode.
31
32
33
34
35
O
O
O
O
O
D
D
D
D
D
Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode.
Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode.
Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.
Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode.
Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.
(1) (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down
with an internal resistor.).
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PIN DESCRIPTIONS(1) (continued)
Pin
36
Name
DOUT1/
I/O
Typ
Res
Description
O
O
D
Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode.
Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode.
Digital ground return.
TXOUT0+
DOUT0/
TXOUT0-
DGND
37
D
38
39
P
P
VD
Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A single
4.7μF capacitor should be used between the supply and the VD, VR and VC pins.
40
CLKOUT/
CLK10
O
D
PD
Output clock for registering output data when using CMOS outputs, or configurable
sensor control output.
41
42
43
44
45
46
47
48
CLK9
CLK8
CLK7
CLK6
CLK5
DGND
VC
O
O
O
O
O
D
D
D
D
D
P
P
D
PD
PD
PD
PU
PD
Configurable sensor control output.
Configurable sensor control output.
Configurable sensor control output.
Configurable sensor control output.
Configurable sensor control output.
Digital ground return.
Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor.
Configurable sensor control output.
CLK4
O
PD
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VA,VR,VD,VC)
4.2 V
−0.3 V to (VA + 0.3 V)
−0.3 V to (VA + 0.3 V)
2.0V
Voltage on Any Input Pin (Not to exceed 4.2 V)(3)
Voltage on Any Output Pin (execpt DVB and not to exceed 4.2 V)
DVB Output Pin Voltage
Input Current at any pin other than Supply Pins(4)
Package Input Current (except Supply Pins)(4)
Maximum Junction Temperature (TA)
±25 mA
±50 mA
150°C
Thermal Resistance (θJA
)
66°C/W
Package Dissipation at TA = 25°C(5)
1.89 W
Human Body Model
Machine Model
2500 V
ESD Rating(6)
250 V
Storage Temperature
−65°C to +150°C
Soldering process must comply with Texas Instruments’ Reflow Temperature Profile specifications. Refer to www.ti.com/packaging(7)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not
recommended.
(2) All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified.
(3) The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided
the current is limited per note 3. However, input errors will be generated If the input goes above VA and below AGND.
VA
I/O
To Internal Circuitry
AGND
(4) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the
power supplies with an input current of 25 mA to two.
(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature,
TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation
listed above will be reached only when the device is operated in a severe fault condition (for example, when input or output pins are
driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0 Ω.
(7) Reflow temperature profiles are different for lead-free and non-lead-free packages.
Operating Ratings(1)(2)
Operating Temperature Range
0°C ≤ TA ≤ +70°C
All Supply Voltage
+3.0 V to +3.6 V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not
recommended.
(2) All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified.
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Electrical Characteristics
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb)
VIH
VIL
Logical “1” Input Voltage
Logical “0” Input Voltage
2.0
V
V
0.8
VIH = VD
RESET
235
70
nA
μA
nA
IIH
Logical “1” Input Current
Logical “0” Input Current
SH_R, SCLK
SEN
130
VIL = DGND
RESET
70
235
70
μA
nA
μA
IIL
SH_R, SCLK
SEN
CMOS Digital Output DC Specifications (SH, CLK1 to CLK10, CMOS Data Outputs)
VOH
VOL
Logical “1” Output Voltage
Logical “0” Output Voltage
IOUT = -0.5mA
IOUT = 1.6mA
VOUT = DGND
VOUT= VD
2.95
V
V
0.25
16
-20
20
IOS
Output Short Circuit Current
mA
nA
VOUT = DGND
VOUT = VD
IOZ
CMOS Output TRI-STATE Current
-25
CMOS Digital Input/Output DC Specifications (SDIO)
IIH
IIL
Logical “1” Input Current
Logical “0” Input Current
VIH = VD
90
90
nA
nA
VIL = DGND
LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins)
Differential LVDS Clock
VIHL
100
0.8
mV
mV
V
High Threshold Voltage
RL = 100W, VCM (LVDS Input
Common Mode Voltage)= 1.25V
Differential LVDS Clock
Low Threshold Voltage
VILL
VIHC
VILC
-100
2.0
CMOS Clock
High Threshold Voltage
INCLK- = DGND
CMOS Clock
V
Low Threshold Voltage
IIHL
IILC
CMOS Clock Input High Current
CMOS Clock Input Low Current
280
μA
μA
-150
LVDS Output DC Specifications
VOD
VOS
IOS
Differential Output Voltage
180
328
1.23
7.9
450
1.3
mV
V
RL = 100Ω
LVDS Output Offset Voltage
Output Short Circuit Current
1.17
VOUT = 0V, RL = 100Ω
mA
(1) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
Power Supply Specifications
VA Normal State
60
12
97
23
125
32
IA
IR
VA Analog Supply Current
mA
VA Low Power State
(Powerdown)
VR Normal State
(LVDS Outputs)
30
15
64
47
75
55
mA
mA
mA
mA
VR Digital Supply Current
CMOS Output Data Format
LVDS Output Data Format with
Data Outputs Disabled
47
LVDS Output Data Format
0.05
VD Digital Output Driver Supply
Current
CMOS Output Data Format
(ATE Loading of CMOS Outputs
> 50pF)
ID
IC
12
40
12
mA
Typical sensor outputs: SH,
CLK1=Φ1A, CLK2=Φ2A,
CLK3=ΦB, CLK4=ΦC,
CLK5=RS, CLK6=CP
(ATE Loading of CMOS Outputs
> 50pF)
VC CCD Timing Generator Output
Driver Supply Current
0.5
mA
LVDS Output Data Format
350
380
505
610
650
700
mW
mW
CMOS Output Data Format (ATE
Loading of CMOS Outputs >
50pF)
PWR
Average Power Dissipation
Input Sampling Circuit Specifications
CDS Gain=1x, PGA Gain=1x
CDS Gain=2x, PGA Gain= 1x
2.3
VIN
Input Voltage Level
Vp-p
1.22
Source Followers Off
CDS Gain = 1x
OSX = VA (OSX = AGND)
50
(-70)
75
70
μA
(-40)
105
Source Followers Off
CDS Gain = 2x
OSX = VA (OSX = AGND)
Sample and Hold Mode Input Leakage
Current
IIN_SH
μA
nA
pF
(-105)
(-75)
Source Followers On
CDS Gain = 2x
OSX = VA (OSX = AGND)
-10
-16
2.5
4
-200
200
Sample/Hold Mode
Equivalent Input Capacitance
(see Figure 12)
CDS Gain = 1x
CDS Gain = 2x
CSH
7
Source Followers Off
OSX = VA (OSX = AGND)
IIN_CDS
RCLPIN
CDS Mode Input Leakage Current
-300
300
50
nA
(-25)
CLPIN Switch Resistance
(OSX to VCLP Node in Figure 9)
16
Ω
VCLP Reference Circuit Specifications
VCLP DAC Resolution
4
Bits
V
VCLP DAC Step Size
0.16
VCLP Config.
Register = 0001 0000b
VCLP DAC Voltage Min Output
0.14
2.38
1.54
0.26
2.68
VA / 2
30
0.43
2.93
1.73
V
V
VCLP Config.
Register = 0001 1111b
VVCLP
VCLP DAC Voltage Max Output
Resistor Ladder Enabled
VCLP Config.
Register = 0010 xxxxb
V
VCLP DAC Short Circuit Output
Current
VCLP Config.
Register = 0001 xxxxb
ISC
mA
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
Black Level Offset DAC Specifications
Resolution
10
Bits
Monotonicity
Ensured by characterization
CDS Gain = 1x
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
-614
614
mV
Offset Adjustment Range Referred to
AFE Input
CDS Gain = 2x
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
-307
307
mV
-16000
16000
-18200
18200
1.2
Offset Adjustment Range Referred to
AFE Output
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
LSB
mV
(LSB)
LSB
CDS Gain = 1x
Referred to AFE Output
DAC LSB Step Size
(32)
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
-0.95
-3.1
3.25
2.65
LSB
PGA Specifications
Gain Resolution
Monotonicity
8
Bits
Ensured by characterization
CDS Gain = 1x
CDS Gain = 1x
CDS Gain = 1x
CDS Gain = 1x
7.18
17.1
0.56
-5
7.9
17.9
0.7
-3
8.77
18.9
0.82
-1.72
V/V
dB
Maximum Gain
Minimum Gain
PGA Function
V/V
dB
Gain (V/V) = (196/(280-PGA Code))
Gain (dB) = 20LOG10(196/(280-PGA Code))
Minimum PGA Gain
3
Channel Matching
%
Maximum PGA Gain
12.7
ADC Specifications
VREFT
Top of Reference
2.07
0.89
V
V
VREFB
Bottom of Reference
VREFT
VREFB
-
Differential Reference Voltage
1.07
1.18
1.29
V
Overrange Output Code
Underrange Output Code
65535
0
Digital Offset “DAC” Specifications
Resolution
7
16
Bits
Digital Offset DAC LSB Step Size
Referred to AFE Output
Min DAC Code =7b0000000
Mid DAC Code =7b1000000
Max DAC Code = 7b1111111
LSB
-1024
0
Offset Adjustment Range
Referred to AFE Output
LSB
1008
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
Full Channel Performance Specifications
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
-0.99
-73
0.8/-0.6
+/-23
-79
2.55
78
LSB
LSB
dB
Minimum PGA Gain
PGA Gain = 1x
7.2
LSB RMS
dB
-74
Noise Floor
13
30
LSB RMS
dB
-56
Maximum PGA Gain
104
47
LSB RMS
Mode 3
Mode 2
Channel to Channel Crosstalk
LSB
16
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AC Timing Specifications
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
Input Clock Timing Specifications
15 (Mode 3)
22.5 (Mode 2)
30 (Mode 1)
45 (Mode 3)
45 (Mode 2)
30 (Mode 1)
60/40
INCLK = PIXCLK
(Pixel Rate Clock)
MHz
fINCLK
Input Clock Frequency
Input Clock Duty Cycle
INCLK = ADCCLK
(ADC Rate Clock)
5
MHz
%
Tdc
40/60
50/50
Full Channel Latency Specifications
SH out to First Sampled Pixel
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
Mode 3
3
3 3/7
4
Figure 19 (Mode 3)
tSHFP
TADC
TADC
TADC
Figure 20 (Mode 2)
Figure 21 (Mode 1)
4 3/7
19
3 Channel Mode Pipeline Delay
18 4/7
18
tLAT3
Figure 53 (LVDS)
Figure 58 (CMOS)
17 4/7
18
2 Channel Mode Pipeline Delay
Figure 54 (LVDS)
17 4/7
17
tLAT2
Figure 59(CMOS)
16 4/7
16
1 Channel Mode Pipeline Delay
Figure 55 (LVDS)
15 4/7
15
tLAT1
TADC
Figure 60(CMOS)
14 4/7
22
SH out to First Valid Data
tSHFD
Mode 2
21
TADC
(tSHFP + tLATx
)
Mode 1
19
SH_R Timing Specifications (Figure 49)
tSHR_S
tSHR_H
SH_R Setup Time
SH_R Hold Time
1.28
2.25
ns
ns
LVDS Output Timing Specifications (Figure 52)
fINCLK = 45MHz
INCLK = ADCCLK
(ADC Rate Clock)
TXvalid
TX Output Data Valid window
2
ns
TXpp0
TXpp1
TXpp2
TXpp3
TXpp4
TXpp5
TXpp6
TXCLK to Pulse Position 0
TXCLK to Pulse Position 1
TXCLK to Pulse Position 2
TXCLK to Pulse Position 3
TXCLK to Pulse Position 4
TXCLK to Pulse Position 5
TXCLK to Pulse Position 6
0.013
3.093
ns
ns
ns
ns
ns
ns
ns
LVDS Output
Specifications not tested in
production.
Min/Max ensured by design,
characterization and statistical
analysis.
6.238
9.613
12.663
15.762
18.982
(1) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
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AC Timing Specifications (continued)
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified.
Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
CMOS Output Timing Specifications
fINCLK = 45MHz
INCLK = ADCCLK
(ADC Rate Clock)
CLKOUT Rising Edge to CMOS
tCRDO
-2.83
-2.83
2.7
2.7
ns
ns
Output Data
fINCLK = 45MHz
INCLK = ADCCLK
(ADC Rate Clock)
CLKOUT Falling Edge to CMOS
tCFDO
Output Data
Serial Interface Timing Specifications
fSCLK <= fINCLK
INCLK = PIXCLK
(Pixel Rate Clock)
Mode 3/2/1
15/22.5/30
45/45/30
MHz
MHz
fSCLK
Input Clock Frequency
fSCLK <= fINCLK
INCLK = ADCCLK
(ADC Rate Clock)
Mode 3/2/1
SCLK Duty Cycle
Input Hold Time
50/50
ns
ns
ns
ns
tIH
tIS
1
4
Input Setup Time
tSENSC
SCLK Start Time After SEN Low
1.25
SEN High after last SCLK Rising
Edge
tSCSEN
tSENW
2.82
4
ns
INCLK must be active during
serial interface commands.
SEN Pulse Width
TINCLK
tOD
tHZ
Output Delay Time
11
14.6
0.5
ns
Data Output to High Z
TSCLK
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System Overview
INTRODUCTION
The LM98714 is a 16-bit, three-input, complete Analog Front End (AFE) for digital color copier and Multi-Function
Peripheral (MFP) applications. The system block diagram of the LM98714, shown in Figure 2 highlights the main
features of the device. Each input has its own Input Bias and Clamping Network which are routed through a
selectable Sample/Hold (S/H) or Correlated Double Sampler (CDS) amplifier. A +/-9-Bit Offset DAC applies
independent offset correction for each channel. A -3 to 17.9dB Programmable Gain Amplifier (PGA) applies
independent gain correction for each channel. The LM98714 also provides independent Digital Black Level
Correction Feedback Loops for each channel. The Black Level Correction Loop can be configured to run in
Manual Mode (where the user inputs their own values of DAC offset) or in Automatic Mode where the LM98714
calculates each channel’s Offset DAC value during optical black pixels and then adjusts the Offset register
accordingly. The signals are routed to a single high performance 16-bit, 45MHz analog-to-digital converter.
MODES OF OPERATION INTRODUCTION
The LM98714 can be configured to operate in several different operating modes. The following sections are a
brief introduction to these modes of operation. A more rigorous explanation of the operating modes is contained
in the Modes of Operation section. including input sampling diagrams for each mode as well as a description of
the operating conditions.
Mode 3 - Three Channel Input/Synchronous Pixel Sampling
OSB, OSG, and OSR inputs are sampled synchronously at a pixel rate. The sampled signals are processed with
each channel’s offset and gain adjusted independently via the control registers. The order in which pixels are
processed from the input to the ADC is fully programmable and is synchronized by the SH pulse. In this mode,
the maximum channel speed is 15MSPS per channel with the ADC running at 45MSPS yielding a three color
throughput of 45MSPS.
Mode 2 - Two Channel Input/Synchronous Pixel Sampling
Mode 2 is useful for CCD sensors with a Black and White mode with Even and Odd outputs. In its default
configuration, Mode 2 samples the Even output via the OSB channel input, and the Odd output via the OSG
channel input. Sampling of the Even and Odd pixels is performed synchronously at a maximum sample rate of
22.5MSPS per input with the ADC running at 45MSPS.
Mode 1a - One Channel Input/One, Two, Three, Four, or Five Color Sequential Line Sampling
In Mode 1a, all pixels are processed through a single input (OSR, OSG, or OSB) chosen through the control
register setup. This mode is useful in applications where only one input channel is used. The selected input is
programmable through the control register. If more than one color is being sent to the input, the user can
configure the OSR channel to utilize up to five offset and gain coefficients for up to five different lines of color
pixels. The SH pulse at the beginning of each line sequences the DAC and PGA coefficients as configured in the
control registers. In this mode, the maximum channel speed is 30MSPS per channel with the ADC running at
30MSPS.
Mode 1b - One Channel Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
In Mode 1b the OSR, OSG, and OSB inputs are sampled one input per line with the input selection being
sequenced to the next color by an SH pulse. This mode is useful with sensors that output whole lines of pixels of
a single color. The order in which the inputs are sampled is fully programmable. Sequencing from one channel to
the next is triggered by the SH pulse. The first SH pulse after this mode is set (or reset) sets up the first
programmed input for gain and offset and initiates sampling through that input alone. The next SH pulse switches
the active input to the second channel indicated by the configuration registers. This sequencing with SH pulses
continues to the third input and then continuously loops through the inputs. In this mode, the maximum channel
speed is 30MSPS per channel with the ADC running at 30MSPS.
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INPUT CLOCK INTRODUCTION
The clock input to the LM98714 can be a differential LVDS clock on the INCLK+ and INCLK- pins or a CMOS
level clock applied to the INCLK+ pin with the INCLK- pin connected to DGND. The external clock signal format
is auto sensed internally. In addition to the two available level formats, the input clock can be applied at the Pixel
frequency (PIXCLK) or at the ADC frequency (ADCCLK). The LM98714 can perform internal clock multiplication
when a Pixel frequency clock is applied, or no multiplication when an ADC frequency clock is applied. The
internal configuration registers need to be written to perform the proper setup of the input clock. The available
input clock configurations for each operating mode is outlined in the following table.
Internal
Multiplier Max Freq.
INCLK
AFE Mode
Input Clock Type
Configuration Register Settings
INCLK = Pixel Freq. (PIXCLK)
INCLK = ADC Freq. (ADCCLK)
INCLK = Pixel Freq. (PIXCLK)
INCLK = ADC Freq. (ADCCLK)
3x
1x
2x
1x
15MHz
45MHz
22.5MHz
45MHz
PIXCLK Configuration: Main Config Reg 1, Bit[2] = 1'b1
ADCCLK Configuration: Main Config Reg 1, Bit[2] = 1'b0
PIXCLK Configuration: Main Config Reg 1, Bit[2] = 1'b1
ADCCLK Configuration: Main Config Reg 1, Bit[2] = 1'b0
Mode 3
Mode 2
Mode 1
INCLK = Pixel Freq. = ADC Freq
(ADCCLK = PIXCLK in Mode 1)
1x
30MHz
Main Config Reg 1, Bit[2] = 1'bx
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Modes of Operation
MODE 3 - THREE CHANNEL INPUT/SYNCHRONOUS PIXEL SAMPLING
In Mode 3, the OSR, OSG, and OSB input channels are sampled synchronously. The sampled input signals are
then processed in parallel through their respective channels with each channel offset and gain adjusted by their
respective control registers. The signals are then routed through a 3-1 MUX to the ADC. The order in which
pixels are processed through the MUX to the ADC is programmable (OSR-OSG-OSB, or OSB-OSG-OSR) and is
synchronized by the SH pulse.
COLOR1DAC[9:0]
COLOR2DAC[9:0]
COLOR3DAC[9:0]
COLOR4DAC[9:0]
COLOR5DAC[9:0]
COLOR1PGA[7:0]
COLOR2PGA[7:0]
COLOR3PGA[7:0]
COLOR4PGA[7:0]
COLOR5PGA[7:0]
Black
Level
Offset
DAC
5:1
MUX
5:1
MUX
CDS
or
Sample/Hold
Amplifier
Input Bias/
Clamping
OSR
OSG
OSB
PGA
PGA
PGA
Black
COLOR2PGA[7:0]
Level
Offset
DAC
COLOR2DAC[9:0]
CDS
or
Input Bias/
Clamping
3:1
MUX
Sample/Hold
Amplifier
Black
COLOR3PGA[7:0]
Level
Offset
DAC
COLOR3DAC[9:0]
CDS
or
Input Bias/
Clamping
Sample/Hold
Amplifier
Figure 5. Synchronous Three Channel Pixel Mode Signal Routing
Table 1. Mode 3 Operating Details
Detail
Channels Active
OSB & OSG & OSR
15
3 channel synchronous pixel sampling.
MSPS per Channel (max)
MSPS (max)
Channel Sample Rate
ADC Sample Rate
45
Internal 3x Clock Selected
Internal 1x Clock Selected
SH Signal --> R-G-B-R-G-B-R-G-B→
or
3:01
1:01
fINCLK = 15MHz (max)
fADC: fINCLK
fINCLK = 45MHz (max)
Output Sequencing
SH Signal --> B-G-R-B-G-R-B-G-R→
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MODE 2 - TWO CHANNEL INPUT/SYNCHRONOUS PIXEL SAMPLING
Mode 2 is useful for CCD sensors with a Black and White line with Even and Odd pixels. In its default
configuration, Mode 2 samples Even sensor pixels via the Blue Channel Input, and Odd sensor pixels via the
Green Channel Input. The selection of Even/Odd inputs can be changed through the serial interface registers.
Sampling of the Even and Odd inputs is performed synchronously.
Figure 6. Mode 2 Signal Routing
Table 2. Mode 2 Operating Details
Detail
OSG and OSB (Default)
or
Two inputs synchronously processed as Even and Odd
Channels Active
OSR and OSG
or
Pixels. Channel inputs are configurable.
OSB and OSR
Channel Sample Rate
ADC Sample Rate
22.5
MSPS per Channel (max)
MSPS (max)
45
Internal 2x Clock Selected
Internal 1x Clock Selected
2:01
1:01
fINCLK = 22.5MHz (max)
fINCLK = 45MHz (max)
fADC: fINCLK
SH Signal --> Even-Odd-Even-Odd-Even-Odd-Even→
Output Sequencing
or
SH Signal --> Odd-Even-Odd-Even-Odd-Even-Odd→
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MODE 1A - ONE CHANNEL INPUT/ONE, TWO, THREE, FOUR, OR FIVE COLOR SEQUENTIAL LINE
SAMPLING
In Mode 1a, all pixels are processed through a single input (OSR, OSG, or OSB) chosen through the control
register setup. This mode is useful in applications where only one input channel is used. The selected input is
programmable through the control register. If more than one color is being sent to the input, the user can
configure the OSR channel to utilize up to five offset and gain coefficients for up to five different lines of color
pixels. The SH pulse at the beginning of each line sequences the DAC and PGA coefficients as configured in the
control registers. In this mode, the maximum channel speed is 30MSPS per channel with the ADC running at
30MSPS.
COLOR1DAC[9:0]
COLOR2DAC[9:0]
COLOR3DAC[9:0]
COLOR4DAC[9:0]
COLOR5DAC[9:0]
COLOR1PGA[7:0]
COLOR2PGA[7:0]
COLOR3PGA[7:0]
COLOR4PGA[7:0]
COLOR5PGA[7:0]
Black
Level
Offset
DAC
5:1
MUX
5:1
MUX
CDS
or
Input Bias/
Clamping
OSR
OSG
OSB
PGA
PGA
PGA
Sample/Hold
Amplifier
Black
COLOR2PGA[7:0]
Level
Offset
DAC
COLOR2DAC[9:0]
CDS
or
Input Bias/
Clamping
3:1
MUX
Sample/Hold
Amplifier
Black
COLOR3PGA[7:0]
Level
Offset
DAC
COLOR3DAC[9:0]
CDS
or
Input Bias/
Clamping
Sample/Hold
Amplifier
Up to “Five Color” line sequences shown thru OSR input. “Single Color” sequences also selectable
thru the OSG and OSB inputs.
Figure 7. Mode 1a Signal Routing
Table 3. Mode 1a Operating Details
Detail
Channels Active
OSR
30
One color active per line.
MSPS per Channel (max)
MSPS (max)
Channel Sample Rate
ADC Sample Rate
fADC: fINCLK
30
Internal 1x Clock Selected
1:01
fINCLK = 30MHz (max)
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Table 3. Mode 1a Operating Details (continued)
Detail
SH Signal → Color 1→Color 1→Color 1→Color 1→Color 1→
→SH Signal → Color 2→Color 2→Color 2→Color 2→Color 2→
→SH Signal → Color 3→Color 3→Color 3→Color 3→Color 3→
→SH Signal → Color 4→Color 4→Color 4→Color 4→Color 4→
→SH Signal → Color 5→Color 5→Color 5→Color 5→Color 5→
or
Output Sequencing
SH Signal → Color 5→Color 5→Color 5→Color 5→Color 5→
→SH Signal → Color 4→Color 4→Color 4→Color 4→Color 4→
→SH Signal → Color 3→Color 3→Color 3→Color 3→Color 3→
→SH Signal → Color 2→Color 2→Color 2→Color 2→Color 2→
→SH Signal → Color 1→Color 1→Color 1→Color 1→Color 1→
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MODE 1B - ONE CHANNEL COLOR INPUT PER LINE/SEQUENTIAL LINE (INPUT) SAMPLING/THREE
CHANNEL PROCESSING
In Mode 1b, the OSR, OSG, and OSB inputs are sampled sequentially and processed through their respective
channels. This mode allows an entire line of Red, Green, or Blue Pixels to be sampled before sequencing to the
next input. This mode is useful with sensors that output whole lines of pixels of a single color. The order in which
the channels are sampled is fully programmable. Actual switching from channel to channel is triggered by an SH
pulse. The first SH pulse after this mode is set (or reset) sets up the first programmed channel for gain and offset
and initiates sampling through that channel alone. The next SH pulse switches the active channel to the second
channel indicated by the configuration registers. This sequencing with SH pulses continues to the third channel
and then continuously loops through the channels.
COLOR1DAC[9:0]
COLOR2DAC[9:0]
COLOR3DAC[9:0]
COLOR4DAC[9:0]
COLOR5DAC[9:0]
COLOR1PGA[7:0]
COLOR2PGA[7:0]
COLOR3PGA[7:0]
COLOR4PGA[7:0]
COLOR5PGA[7:0]
Black
Level
Offset
DAC
5:1
MUX
5:1
MUX
CDS
or
Sample/Hold
Amplifier
Input Bias/
Clamping
OSR
OSG
OSB
PGA
PGA
PGA
Black
COLOR2PGA[7:0]
Level
Offset
DAC
COLOR2DAC[9:0]
CDS
or
Input Bias/
Clamping
3:1
MUX
Sample/Hold
Amplifier
Black
COLOR3PGA[7:0]
Level
Offset
DAC
COLOR3DAC[9:0]
CDS
or
Input Bias/
Clamping
Sample/Hold
Amplifier
Figure 8. Mode 1b Signal Routing
Table 4. Mode 1b Operating Details
Detail
One channel active per line. Active channel is sequenced by
SH pulse at start of new line.
Channels Active
OSB or OSG or OSR
Channel Sample Rate
ADC Sample Rate
fADC: fINCLK
30
MSPS per Channel (max)
MSPS (max)
30
Internal 1x Clock Selected
1:01
fINCLK = 30MHz (max)
SH Signal → R-R-R-R-R-R-R-R-R-R-R-R-R→
→SH Signal → G-G-G-G-G-G-G-G-G-G-G-G-G→
→SH Signal → B-B-B-B-B-B-B-B-B-B-B-B-B-B→
or
Output Sequencing
SH Signal → B-B-B-B-B-B-B-B-B-B-B-B-B-B→
→SH Signal → G-G-G-G-G-G-G-G-G-G-G-G-G→
→SH Signal → R-R-R-R-R-R-R-R-R-R-R-R-R→
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MODES OF OPERATION REGISTER SETTINGS TABLE
Table 5.
Main
Config.
Main Config. Register 0
Output Sequencing
Signal
Path(s)
Operating Mode
Sampling Input(s)
Mode 3 and 2 = Pixel Seq
Mode 1 = Color Line Seq
Reg. 3
Mode
Color
Order
Color Seq. Length
Bit [3]
Bit[7]
Bit[6]
1
Bit[5]
Bit[4]
1
Bit[3] Bit[2] Bit[1]
Bit[0]
Mode3-RGB Forward
Mode3-RGB Reverse
Mode2-RG Forw.
OSR||OSG||OSB
OSR||OSG||OSB
OSR||OSG
OSR||OSG
OSG||OSB
OSG||OSB
OSR||OSB
OSR||OSB
OSR
RGB
RGB
RG
RG
GB
GB
RB
RB
R
PixelR→PixelG→PixelB→
PixelB→PixelG→PixelR→
PixelR→PixelG→
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
x
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
x
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
x
1
1
0
0
Mode2-RG Rev.
PixelG→PixelR→
0
0
Mode2-GB Forw.
PixelG→PixelB→
0
1
Mode2-GB Rev.
PixelB→PixelG→
0
1
Mode2-RB Forw.
PixelR→PixelB→
0
0
Mode2-RB Rev.
PixelB→PixelR→
0
0
Mode1-R Mono
Color Line Seq: 1→1→1→1→1→
Color Line Seq: 1→2→1→2→1→
Color Line Seq: 2→1→2→1→2→
Color Line Seq: 1→2→3→1→2→
Color Line Seq: 3→2→1→3→2→
Color Line Seq: 1→2→3→4→1→
Color Line Seq: 4→3→2→1→4→
Color Line Seq: 1→2→3→4→5→
Color Line Seq: 5→4→3→2→1→
Color Line Seq: 1→1→1→1→1→
Color Line Seq: 1→1→1→1→1→
LineR→LineG→LineB→
1
0
Mode1a-R 2 Color For.
Mode1a-R 2 Color Rev
Mode1a-R 3 Color For.
Mode1a-R 3 Color Rev
Mode1a-R 4 Color For.
Mode1a-R 4 Color Rev
Mode1a-R 5 Color For.
Mode1a-R 5 Color Rev
Mode1a-G Mono
OSR
R
1
0
OSR
R
1
0
OSR
R
1
0
OSR
R
1
0
OSR
R
1
0
OSR
R
1
0
OSR
R
1
0
OSR
R
1
0
OSG
G
1
1
Mode1a-B Mono
OSB
B
1
0
Mode1b-RGB Forward
Mode1b-RGB Reverse
OSR→OSG→OSB
OSB→OSG→OSR
RGB
RGB
0
1
LineR→LineG→LineB→
0
1
x
x
x
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Input Bias and Clamping
VA
VA
VBIAS
Input Bias Enable
Main Configuration 1, Bit[6]
SAMPLE
20kΩ
OSR or
OSG or
OSB
Source Follower Enable
Main Configuration 1, Bit[7]
CS
20kΩ
Auto CLPIN Enable
Input Clamp Control, Bit[1]
SAMPLE
CLPIN
AGND
HOLD
VA
VA
VBIAS
CLPIN Gating Enable
Input Clamp Control, Bit[0]
CLAMP
1kΩ
1kΩ
VCLP
CS
VCLP
DAC
Sampling Mode Select
(CDS or Sample/Hold Mode)
Main Configuration 1, Bit[4]
Pixel rate switches to sample OS signal and reference voltages.
Optional line rate switch to clamp OS input to VCLP node.
Static switches controlled by Configuration Registers
AGND
VCLP Reference Select
VCLP Configuration, Bits[5:4]
SAMPLE, CLAMP, HOLD, CLPIN are internally generated timing signals.
Figure 9. Input Bias and Clamping Diagram
The inputs to the LM98714 are typically AC coupled through a film capacitor and can be sampled in either
Sample and Hold Mode (S/H Mode) or Correlated Double Sampling Mode (CDS Mode). In either mode, the DC
bias point for the LM98714 side of the AC coupling capacitor is set using the circuit of Figure 9 which can be
configured to operate in a variety of different modes.
A typical CCD waveform is shown in Figure 10. Also shown in Figure 10 is an internal signal “SAMPLE” which
can be used to “gate” the CLPIN signal so that it only occurs during the “signal” portion of the CCD pixel
waveform.
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SH
Invalid
Dummy Pixels
Optical Black Pixels
Valid Pixels
Pixels
OSX
Input Clamp Control Register
Page 0, Reg. 5, Bits[3:2]
(Auto CLPIN Width)
Auto CLPIN Position Register
Page 0, Reg. 6, Bits[7:0]
CLPIN
SAMPLE
CLPINGATED
Figure 10. Typical CCD Waveform and LM98714 Input Clamp Signal (CLPIN)
SAMPLE
OSR or
OSG or
OSB
CS
CPAR
HOLD
CLAMP
VCLP
CS
CPAR
Figure 11. Sample and Hold Mode Simplified Input Diagram
Proper DC biasing of the CCD waveform in Sample and Hold mode is critical for realizing optimal operating
conditions. In Sample/Hold mode, the Signal Level of the CCD waveform is compared to the DC voltage on the
VCLP pin. In order to fully utilize the range of the input circuitry, it is desirable to cause the Black Level signal
voltage to be as close to the VCLP voltage as possible, resulting in a near zero scale output for Black Level
pixels.
In Sample/Hold Mode, the DC bias point of the input pin is typically set by actuating the input clamp switch (see
Figure 9) during optical black pixels which connects the input pins to the VCLP pin DC voltage. The signal
controlling this switch is an auto-generated pulse, CLPIN. CLPIN is generated with a programmable pixel delay
with respect to SH and a programmable pixel width. These parameters are available through the serial interface
control registers.
Actuating the input clamp will force the average value of the CCD waveform to be centered around the VCLP DC
voltage. During Optical Black Pixels, the CCD output has roughly three components. The first component of the
pixel is a “Reset Noise” peak followed by the Reset (or Pedestal) Level voltage, then finally the Black Level
voltage signal. Taking the average of these signal components will result in a final “clamped” DC bias point that
is close to the Black Level signal voltage.
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To provide a more precise DC bias point (i.e. a voltage closer to the Black Level voltage), the CLPIN pulse can
be “gated” by the internally generated SAMPLE clock. This resulting CLPINGATED signal is the logical “AND” of
the SAMPLE and CLPIN signals as shown in Figure 10. By using the CLPINGATED signal, the higher Reset Noise
peak will not be included in the clamping period and only the average of the Reset Level and Black Level
components of the CCD waveform will be centered around VCLP.
OSR or
OSG or
OSB
fPIXEL
CSH
VCLP
Figure 12. Equivalent Input Switched Capacitance S/H Mode
In Sample and Hold Mode, the impedance of the analog input pins is dominated by the switched capacitance of
the CDS/Sample and Hold amplifier. The amplifier switched capacitance, shown as CS in Figure 11, and internal
parasitic capacitances can be estimated by a single capacitor switched between the analog input and the VCLP
reference pin for Sample and Hold mode. During each pixel cycle, the modeled capacitor, CSH, is charged to the
OSX-VCLP voltage then discharged. The average input current at the OSX pin can be calculated knowing the
input signal amplitude and the frequency of the pixel. If the application requires AC coupling of the CCD output to
the LM98714 analog inputs, the Sample and Hold Mode input bias current may degrade the DC bias point of the
coupling capacitor. To overcome this, Input Source Follower Buffers are available to isolate the larger Sample
and Hold Mode input bias currents from the analog input pin (as discussed in the following section). As shown in
CDS MODE, the input bias current is much lower for CDS mode, eliminating the need for the source follower
buffers.
CDS MODE
SAMPLE
OSR or
OSG or
OSB
CS
CPAR
HOLD
CLAMP
CS
CPAR
Figure 13. CDS Mode Simplified Input Diagram
Correlated Double Sampling mode does not require as precise a DC bias point as does Sample and Hold mode.
This is due mainly to the nature of CDS itself, that is, the Video Signal voltage is referenced to the Reset Level
voltage instead of the static DC VCLP voltage. The common mode voltage of these two points on the CCD
waveform have little bearing on the resulting differential result. However, the DC bias point does need to be
established to ensure the CCD waveform’s common mode voltage is within rated operating ranges.
The CDS mode biasing can be performed in the same way as described in the Sample/Hold Mode Biasing
section, or, an alternative method is available which precludes the need for a CLPIN pulse. Internal resistor
dividers can be switched in across the OSR, OSG, and/or OSB inputs to provide the DC bias voltage.
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SAMPLE
IBIAS
OSR or
OSG or
OSB
CS
CPAR
HOLD
CLAMP
CS
CPAR
Figure 14. CDS Mode Input Bias Current
Unlike in Sample and Hold Mode, the input bias current in CDS Mode is relatively small. Due to the architecture
of CDS switching, the average charge loss or gain on the input node is ideally zero over the duration of a pixel.
This results in a much lower input bias current, whose main source is parasitic impedances and leakage
currents. As a result of the lower input bias current in CDS Mode, maintaining the DC Bias point the input node
over the length of a line will require a much smaller AC input coupling capacitor.
INPUT SOURCE FOLLOWER BUFFERS
The OSR, OSG, OSB inputs each have an optional Source Follower Buffer which can be selected with Main
Configuration Register 1, Bit[7]. These source followers provide a much higher impedance seen at the inputs. In
some configurations, such as Sample and Hold Mode with AC coupled inputs, the DC bias point of the input
nodes must remain as constant as possible over the entire length of the line to ensure a uniform comparison to
reference level (VCLP in this case). The Source Followers effectively isolate the AC input coupling capacitor from
the switched capacitor network internal to the LM98714’s Sample and Hold/CDS Amplifier. This results in a
greatly reduced charge loss or gain on the AC Input coupling capacitor over the length of a line, thereby
preserving its DC bias point.
The Source Followers should only be used in the 1.2V input range (i.e. Main Configuration Register 2, Bit[4] = 1,
CDS Gain = 2x). Using the Source Followers in the 2.4V (i.e. Main Configuration Register 2, Bit[4] = 0, CDS Gain
= 1x). input range will result in a loss of performance (mainly linearity performance at the high and low ends of
the input range).
VCLP DAC
The VCLP pin provides the reference level for incoming signals in Sample and Hold Mode. The pin’s voltage can
be set by one of three sources by writing to the VCLP Configuration Register on register page 0. By default, the
VCLP pin voltage is established by an internal resistor divider which sets the voltage to VA/2. The resistor ladder
can be disconnected and the pin driven externally by the application.
The most flexible method of setting the VCLP voltage is using the internal VCLP DAC buffer. The DAC is
connected by setting the VCLP Configuration register Bit[5:4] to 2b’01. The DAC has a four bit “offset binary”
format which is summarized in Table 6. The DAC output has an approximate swing of +/-1.2V.
Table 6. VCLP DAC Format
VCLP Configuration [3:0]
Typical VCLP Output
-Full Scale
0
0111
1000
1001
1111
Mid Scale - LSB
Mid Scale
Mid Scale + 1 LSB
+Full Scale
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PGA Gain Plots
18
17
16
15
14
13
12
11
10
9
Gain (V/V) =
(196/(280-PGA Code))
Gain (dB) =
20LOG10(196/(280-PGA Code))
8
7
6
5
4
3
2
1
0
0
32
64
96
128
160
192
224
-1
-2
-3
-4
PGA Register Value
Overall Gain (dB) Overall Gain (V/V)
Figure 15. PGA Gain vs. PGA Gain Code
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Coarse Pixel Phase Alignment
Precise placement of the CCD video signal sampling point is a critical aspect in any typical imaging application.
Many factors such as logic gate propagation delays and signal skew increase the difficulty in properly aligning
the CCD pixel output signals with the AFE input sampling points. The LM98714 provides two powerful features to
aid the system level designer in properly sampling the CCD video signal under a large range of conditions. The
first feature, discussed in this section, is the Coarse Pixel Phase Alignment block. As the name implies, this block
provides a very coarse range of timing adjustment to align the phase of the CCD Pixel output with the phase of
the LM98714 sample circuit. The second feature, discussed on the Internal Sample Timing, is the block which is
designed for fine tuning of the sampling points within the selected Coarse Pixel Alignment Phase. A small portion
of a typical imaging application is shown in Figure 16.
SH
φ1Α
LM98714 CCD
Timing Generator
Outputs
φ2Α
OS3
CCD/CIS
Sensor
OS2
LM98714
Output Data Bus
OS1
Input Clock
(INCLK)
Figure 16. Typical AFE/CCD Interface
As shown in the diagram, the LM98714 provides the timing signals to drive the CCD using external logic gates to
drive the high capacitance CCD clock pins. The pixels are shifted out of the CCD, thru the emitter follower
buffers and received by the LM98714 inputs for processing.
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In an ideal application, depicted in Figure 17, the Pixel output signal would be in phase with the timing signals
that drove the CCD. The LM98714 input sampling clocks (CLAMP and SAMPLE) are adjustable within a pixel
period. By default, the pixel period (or pixel “phase”) is defined to be in line with the input clock. As shown in the
ideal case in Figure 17, CLAMP and SAMPLE can be properly adjusted to their ideal positions within the pixel
phase, shown below at the stable region near the end of the pedestal and data phases.
INCLK (Pixel Rate)
In an ideal application, the LM98714 CCD Timing generator outputs would be phase aligned
with the input clock;
φ1A output from LM98714
CCD Timing generator
the output of discrete logic on the application board would have no signal skew or delay;
φ1A input at CCD
(after inverter)
and the CCD pixel output would have no delay with respect to
its input clock.
Pixel output from CCD
Ideal CCD reference
level sample point
Ideal CCD data level
sample point
CLAMP
(internal pixel reference
level sampling clock)
SAMPLE
(internal pixel data level
sampling clock)
CLAMP and SAMPLE fine adjust window
PIXPHASE0
(default “coarse’ pixel phase)
By default, the LM98714's internal sampling clocks (CLAMP and SAMPLE) are adjustable
within PIXPHASE0, an internal pixel rate clock which is in phase with the input clock.
Figure 17. Clock Alignment in an Ideal Application
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In a real system however, propagation delays exist in all stages of the signal chain. These propagation delays
will lead to a shift in the CCD Pixel outputs with respect to the LM98714 input clock. The phase shift of the CCD
Pixel output, demonstrated in Figure 18, can lead to significant sample timing issues if not properly corrected.
INCLK (Pixel Rate)
The LM98714 internal clock tree creates a small amount of
delay in the CCD Timing generator outputs.
φ1A output from LM98714
CCD Timing generator
Application board discrete logic also creates propagation delay
with respect to the input clock.
φ1A input at CCD
(after inverter)
Finally, the CCD propagation delay further shifts the Pixel
signal input to the LM98714 from the input clock.
Pixel output from CCD
Maximum fine adjust
not good enough for
default PIXPHASE,
CLAMP and SAMPLE
CLAMP
(internal pixel reference
level sampling clock)
are too early due to
propagation delays.
SAMPLE
(internal pixel data level
sampling clock)
PIXPHASE0
(default “coarse’ pixel phase)
Default CLAMP fine
adjust window
Default SAMPLE
fine adjust window
Default CLAMP fine
adjust window
Figure 18. CCD Output Phase Shift in a Real Application
In the default mode, the LM98714 sampling is performed during a clock period whose phase is aligned with the
input clock (ignoring any clock tree skew for the moment). The actual sampling clocks are adjustable within the
clock period, as shown in Figure 18 (shown for CDS mode in the diagram) and further described in the Internal
Sample Timing section. As shown in the diagram, the delay of the CCD Pixel output is shifted far enough that the
fine CLAMP and SAMPLE clocks cannot be placed in a stable portion of the waveform. To remedy this situation,
the LM98714’s Coarse Pixel Phase Alignment feature allows the designer to shift the entire phase of the analog
front end with respect to the input clock. This allows the designer to choose one of four sampling phases which
best matches the delay in the external circuitry. Once the “Coarse Pixel Phase” has been chosen, the designer
can then fine tune the sampling clocks using the fine adjustment (see Internal Sample Timing)
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The four available Coarse Pixel Phases (PIXPHASE0 - PIXPHASE3) are depicted in Figure 19 (Mode 3),
Figure 20 (Mode 2) and Figure 21 (Mode 1). Also shown in the diagrams are the external input clock (INCLK)
and a typical CCD output delayed from the input clock.
TADCCLK
INCLK = ADCCLK
TPIXCLK
INCLK = PIXCLK
tSHFP
SH
(Output from CCD
Timing Generator)
fSYSCLK = 7 * fADCCLK = 21 * f
(In Mode 3)
PIXCLK
SYSCLK
(Internal system clock)
tPIXPHASE0 = TSYSCLK * 0
PIXPHASE0 (default)
Main Configutation Reg 1
Bit[1:0] = 2'b00
tPIXPHASE1 = TSYSCLK * 3
PIXPHASE1
Main Configutation Reg 1
Bit[1:0] = 2'b01
tPIXPHASE2 = TSYSCLK * 7
PIXPHASE2
Main Configutation Reg 1
Bit[1:0] = 2'b10
tPIXPHASE3 = TSYSCLK * 10
PIXPHASE3
Main Configutation Reg 1
Bit[1:0] = 2'b11
tCCD Output= ?
CCD Output
(Input to AFE)
The CCD output will usually have a measurable delay with respect to the input clock to the AFE. The AFE’s internal samplingoclks are based on one of four PIXPHASE clocks. These
PIXPHASE settings provide coarse adjustment of the internal AFE clock domain to best match the phase of the incoming CCD sig.naFline adjustment of the sampling clocks is discussed
in another section. In this example above, PIXPHASE2 appears to provide the closest match for the incoming CCD signal.
Figure 19. Mode 3 Coarse Pixel Adjustment
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Figure 20. Mode 2 Coarse Pixel Phase Adjustment
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Figure 21. Mode 1 Coarse Pixel Phase Adjustment
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Internal Sample Timing
A typical CCD input signal is depicted in Figure 22 and Figure 23. Also shown are the internally generated
SAMPLE and CLAMP pulses. These signals provide the sampling points of the input signal (OSX). The timing of
SAMPLE and CLAMP is derived from an internal system clock (SYSCLK).
The pixel’s reference level input (depicted as VREF) is captured by the falling edge of the CLAMP pulse. In
Sample/Hold Mode the VREF input is a sample of the VCLP DC voltage. In CDS Mode the CLAMP pulse samples
the pedestal Level of the CCD output waveform.
The pixel’s signal level input (depicted as VSIG) is captured by the SAMPLE pulse. In either Sample/Hold or CDS
Mode, the VSIG input is the signal level of the CCD output waveform.
The LM98714 provides fine adjustment of the CLAMP and SAMPLE pulse placement within the pixel period. This
allows the user to program the optimum location of the CLAMP and SAMPLE falling edges. In CDS mode, both
CLAMP and SAMPLE are independently adjustable for each channel in use. In Sample/Hold mode, CLAMP is
coincident with SAMPLE by default, but is also independently adjustable. The available fine tuning locations for
CLAMP and SAMPLE are shown in Figure 24 through Figure 29 for each sampling mode (CDS or S/H) and
channel mode (3, 2, or 1 Channel).
Figure 22. Pixel Sampling in CDS Mode
Figure 23. Pixel Sampling in S/H Mode
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Figure 24. 3 Channel (Mode 3) CLAMP Timing
Figure 25. 3 Channel (Mode 3) SAMPLE Timing
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Figure 26. 2 Channel (Mode 2) CLAMP Timing
Figure 27. 2 Channel (Mode 2) SAMPLE Timing
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Figure 28. 1 Channel (Mode 1) CLAMP Timing
Figure 29. 1 Channel (Mode 1) SAMPLE Timing
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Automatic Black Level Correction Loop
CCD signal processors require a reference level for the proper handling of input signals; this reference level is
commonly referred to as the black level. The LM98714 provides an Automatic Black Level Correction Loop as
shown in Figure 30. The timing for this function is shown in Figure 31. The loop can be disabled and the Black
Level Offset DAC registers programmed manually if desired.
Figure 30. Black Level Correction Loop
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The loop is intended to be used prior to scanning the page or during the first several lines at the beginning of a
scan. The loop calibrates the channel offset such that the ADC outputs the desired code for Optical Black Pixels.
In automatic mode, the pixels used to calibrate the offset should be Optical Black pixels represented by the
internal “BLKCLP” pulse in Figure 31.
BLACK LEVEL OFFSET DAC
The offset level registers store the DAC value required to meet the respective channel’s black level output. While
using the Auto Black Level Correction Loop, the DAC registers are re-written as required every line the loop is
enabled.
BLACK LEVEL CLAMP (BLKCLP)
The BLKCLP pulse can be synchronized by either the falling edge of the SH pulse or the CLPIN pulse (both
shown in Figure 31). The automatic BLKCLP pulse will begin “n” number of pixel periods after the falling edge of
the reference pulse where “n” is the Auto Black Level Clamp Position register. The reference point is
programmed by the BLKCLP Mode Select Bits[1:0] within the Black Level Clamp Control register. The BLKCLP
pulse should not be programmed coincident to the CLPIN pulse (if the CLPIN pulse is being used).
Figure 31. Black Level Correction Timing
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PIXEL AVERAGING
In order to obtain a snapshot of the current value for black (for comparison with the desired level of black) the
ADC output is sampled upon activation of BLKCLP. Since a single optical black pixel is unlikely to be an accurate
representation of the black level, a number of adjacent pixels are averaged. The number of pixels sampled is
programmable by the Pixel Averaging Bit[5:4] within the Black Level Clamp Control register. The ability to select
the number of pixels to be averaged (4, 8, 16, or 32 per line) provides greater flexibility allowing the LM98714 to
be used with different CCDs having differing number of black pixels.
TARGET BLACK LEVEL
The Target Black Level registers define a 10-bit word that specifies an ADC output (on the 12 bit level)
corresponding to the desired optical black output code (ignoring the four LSBs of the 16 Bit ADC output). In other
words, one Target Black Level LSB corresponds to sixteen ADC LSBs. Assertion of the BLKCLP signal activates
the digital black clamp loop and the black level is steered toward the value stored in the output black level
register. The digital black clamp loop is only limited in it’s range by the offset DAC’s range.
Once the correct number of pixels have been averaged, the value is subtracted from the Target Black Level and
an error value is produced.
OFFSET INTEGRATION
Each time the BLKCLP signal is activated, the average ADC output of several black pixels is compared to the
Target Black Level producing an error value. This error value is not directly added (or subtracted) to the Black
Level Offset register, rather, the value applied is a programmable fraction of this error. This has the effect of
slowing down the offset convergence resulting in a calculation for offset that is less susceptible to noise. The
scaling factor is stored in the Offset integration Bits[3:2] of the Black Level Clamp Control register. The scaling
values are divided-by-8, 16, 32, or 64. Divide-by-8 provides the quickest convergence of the loop (for use when
the number of lines available for calibration is limited) and Divide-by-64 the longest (for use when using an large
number of lines to converge).
LINE AVERAGING
The Auto Black level Correction Loop can be run for 15 lines, 31 lines, 63 lines, or infinite (every line). The Line
Averaging Bits[7:6] found in the lack Level Clamp Control register set the number of lines that the loop will run
after the Start of Scan. The recommended use of the Auto Black Level Correction Loop is in a calibration period
prior to moving the sensor down the page or during the first several lines of the page. By experimenting with the
Line Averaging and Offset Integration bits with no sensor illumination (black pixels), the proper settings for the
Auto Black Level Correction Loop are determined when the ADC output converges to the Target Black Level
value. If the loop converges with the 15, 31, or 63 line setting, the loop can remain enabled. The loop does not
update the Black Level Offset DAC once the number of lines since “Start of Scan” has passed. If the loop
requires more than 63 lines to converge (i.e. requires Line Averaging = infinite), it is recommended to disable the
loop after convergence has been reached. In the “infinite” setting, the loop will continuously update the Black
Level Offset registers as long as the loop is enabled throughout the entire scan.
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Internal Timing Generation
A flexible internal timing generator is included to provide clocking signals to CCD and CIS sensors. A block
diagram of the CCD Timing Generator is shown in Figure 32.
Figure 32. CCD Timing Generator Block Diagram
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Examples of the various operating modes and settings are shown following. The detailed pixel timing is
somewhat dependent on the operating modes of the AFE circuitry regarding the number of adjustment points for
the on and off points of the different timing outputs.
NOTE
In addition to the timing adjustments shown, the polarity of all sensor clock signals can be
adjusted by register control.
Figure 33. Sensor Timing Control - Pixel Details - 1 Pixel per Phi
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Figure 34. Sensor Timing Control - Pixel Details - 2 Pixels per Phi
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Figure 35. Sensor Timing SH Pulse Details
Figure 36. Sensor Timing Mode Pin Output Details - Static High/Low
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Figure 37. Sensor Timing Mode Pin Output Details - Active Programmed Transition
Figure 38. Lamp Control Timing - 1 Line Mode (Monochrome)
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Figure 39. Lamp Control Timing - 1 Line Mode
Figure 40. Lamp Control Timing - 2 Line Sequence
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Figure 41. Lamp Control Timing - 3 Line Sequence
Figure 42. Lamp Control Timing - 3 Line Sequence - IR Enhancement Example
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Figure 43. Lamp Control Timing - 4 Line Sequence
Color + IR1 Example
Figure 44. Lamp Control Timing - 4 Line Sequence
Color + IR2 Example
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Figure 45. Lamp Control Timing - 5 Line Sequence
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PIX SIGNAL GENERATOR OR/NOR MODES
As shown in Figure 32, the PIX signal generators outputs can be used in their normal form and sent to the
LM98714 output pins, or, they can be sent through an additional layer of OR and NOR logic to provide a number
of clocking variations. The OR and NOR combinations of multiple PIX signals can be useful for such modes as
pixel lumping, or other modes where more complicated phi clocks are required.
The OR and NOR functions are chosen through the PIX OR/NOR Control 1 and PIX OR/NOR Control 2 registers
on Page 4 of the serial interface register map. When all of the OR/NOR control bits are 0 (default) the PIX
signals are sent directly from the pix signal generators to the output pins configured by the Output Mapping
Control registers (register Page 3). When an OR/NOR control bit is set to 1, the OR or NOR product of multiple
pix signal generators is routed to the output pin described in the register details.
SH2 AND SH3 GENERATION
In some sensors, there is a requirement for up to three “SH” type signals. The LM98714 CCD Timing Generator
can be configured to produce optional SH signals as shown in Figure 46, these SH signals (SH2 and SH3) toggle
every other line and are coincident with the original SH pulse.
Figure 46. SH2 and SH3 Generation
The “Start Scan (BOS)” request bit is used to begin the proper sequence of CCD Timing outputs at the beginning
of a scan. The first line of pixels are being processed by the CCD during the first integration period (after the first
SH). The BOS signal (internal to the LM98714) occurs at the second SH to signal when the first line of pixels are
actually shifting out of the CCD and in to the AFE. The SH2 pulse is synchronized with the BOS signal and
continues to toggle on an every other line basis. The SH3 signal occurs on opposite lines from SH2.
The SH2 and SH3 signals are available in place of the Lamp IR1 and Lamp IR2 outputs respectively. The routing
of SH2 and SH3 is depicted in Figure 32. The use of SH2 and SH3 is selected by the SH2/SH3 Control register
(0x0F) on Page 4 of the register map.
Figure 47. Sensor Control Outputs
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Table 7 shows a number of example mappings of the sensor timing signals to the sensor control CLKn outputs.
Several typical timings are shown here, but any timing generator signal can be mapped to any of the CLKn
outputs, providing maximum flexibility.
Table 7. Sensor Timing Mappings Examples
Sensor Control Output
Example A
SH
Example B
SH
Example C
SH
Example D
SH
Example E
SH
Example F
SH
SH
CLK1
PIX1(PHI1)
PIX2(PHI2)
PIX3(RS)
PIX4(CP)
LAMPR
PIX1(PHI1)
PIX2(PHI2)
PIX3(RS)
PIX4(CP)
LAMPR
PIX1(PHI1)
PIX2(PHI2)
PIX3(RS)
LAMPR
PIX1(PHI1)
PIX2(PHI2)
PIX3(RS)
PIX4(CP)
LAMPR
PIX1(PHI1)
PIX2(PHI2)
PIX3(PHI3)
PIX4(PHI4)
PIX5(PHI5)
PIX6(PHI6)
PIX7(RS)
PIX8(CP)
MODE
PIX1(PHI1)
PIX2(PHI2)
PIX3(RS)
PIX4(CP)
CB[0]
CLK2
CLK3
CLK4
CLK5
LAMPG
CLK6
LAMPG
LAMPG
LAMPB
LAMPG
CB[1]
CLK7
LAMPB
LAMPB
LAMPIR1
LAMPIR2
MODE
LAMPB
CB[2]
CLK8
MODE
LAMPIR1
LAMPIR2
(MODE)
LAMPIR1
LAMPIR2
PIX5(PHI3)
CB[3]
CLK9
PIX5(PHI3)
CB[4]
CLKOUT/CLK10
CLKOUT
These examples can be used for any customer need, but typical applications would be as follows:
In Examples A, B and C, only 10 sensor control outputs are used. This is to allow the CLKOUT/CLK10 pin to be
used as a timing reference for the image output data when the outputs are in CMOS mode.
Example A: Used with most CCD or CIS sensors, including new sensors with 3 PHI clock inputs. Will support up
to 3 color LED lamps. Supports CCD sensors with switchable resolution through the MODE control output.
Example B: Used in applications where up to 2 additional IR lamps are used in addition to the R, G, B lamps. No
resolution MODE output is available.
Example C: Used where no CP pulse is needed, but 5 lamp outputs are needed as well as a MODE sensor
resolution control pin.
In Examples D and E, the CLK10 output is also used. These modes are not available when the image data
outputs are operating in CMOS mode.
Example D: Provides both PHI3 output and 5 LED lamp outputs. Does not provide MODE output for resolution
control.
Example E: Provides 5 LED lamp outputs, and the MODE output for sensor resolution control.
CCD Timing Generator Master/Slave Modes
The internal CCD Timing generator is capable of operating in Master Mode or in Slave Mode. The Master/Slave
operation is configured with the SH Mode Register (Register 0x00 on Page 2). In either Master or Slave Mode,
control bit data can be sent to the output of the LM98714 to indicate when each new scan is starting as well as
pixel information such as color, type (active, black, dummy, etc.), and the beginning of each line.
MASTER TIMING GENERATOR MODE
In Master Timing Mode, the LM98714 controls the entire CCD Timing Generator based on a Start Scan Bit (Main
Configuration Register 2, Bit[0] is the “Start Scan” or “BOS/Beginning of Scan” bit). The Start Scan bit is set by
the user to request a new scan. This bit is a self clearing register bit written to the serial interface. When
received, the LM98714 controls where and when each new line of the scan begins and ends based on the CCD
Timing Generator register settings. The scan is enabled as long as the Active/Standby bit is low. The period of
the line (integration time) is controlled by the SH Width setting (SH Pulse Width Register) and the Line End
setting (Line End MSB and Line End LSB registers).
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SLAVE TIMING GENERATOR MODE
In Slave Timing Mode, the LM98714 CCD Timing Generator is controlled by the external SH_R pin. Each new
line of a scan is initiated by an SH_R pulse. The period of the line (integration time) is mainly controlled by the
period of the incoming SH_R signal.
Figure 48. SH_R Input to SH Output Latency Diagram
Figure 49. SH_R to INCLK (PIXCLK or ADCCLK) Timing
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CCD Timing Generator Pixel Position Definition
Figure 50.
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LVDS Output Mode
LVDS OUTPUT FORMAT
Figure 51. LVDS Output Bit Alignment and Data Format
LVDS Output Timing Details
Figure 52. LVDS Data Output Mode Specification Diagram
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LVDS CONTROL BIT CODING
The 5 control bits included in the LVDS data stream are coded as follows:
The "active" and "black" pixel tags are programmable tags that the LM98714 provides in order to identify how
many pixels have been processed since the falling edge of SH.
Which pixels are given "active" and "black" CB tags is controlled by Page 4, registers 0x08 through 0x0D (Optical
Black Pixels Start, Optical Black Pixels End, Start of Valid Pixels, and End of Valid Pixels).
The LM98714 counts the number of pixel periods after the falling edge of SH: If the number of pixel periods after
the falling edge of SH is between "optical black pixels start" and "optical black pixels end" the CB bits will indicate
that the pixel is a black pixel. If the number of pixel periods after the falling edge of SH is between "start of valid
pixels" and "end of valid pixels" the CB bits will indicate that the pixel is an active pixel.
Table 8.
CB[4]
Description
Not the beginning of line
0
Beginning of Line
1
(This bit is high for as many pixels as SH pulse is active)
Table 9.
CB[3:0]
0
Description
Dummy Pixels
1
Red Active Pixels
Green Active Pixels
Blue Active Pixels
IR1 Active Pixels
IR2 Active Pixels
Red Black Pixels
Green Black Pixels
Blue Black Pixels
IR1 Black Pixels
IR2 Black Pixels
Beginning of Scan
10
11
100
101
110
111
1000
1001
1010
1111
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LVDS DATA LATENCY DIAGRAMS
Figure 53. Mode 3 LVDS Data Latency
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Figure 54. Mode 2 LVDS Data Latency
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Figure 55. Mode 1 LVDS Data Latency
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LVDS TEST MODES
The LVDS test modes present several different data patterns to the input of the LVDS serializer block. All 21 bits
are used and there is no control bit coding present. The SH signal resets the LVDS test pattern and the pattern
will resume only after SH is deasserted. If no SH signal is sent, the pattern continues indefinitely.
Test Mode 1 - Worst Case Transitions
This test mode provides an LVDS output with the maximum possible transitions. This mode is useful for system
EMI evaluations, and for ATE timing tests.
The effective data values are an alternating pattern between 21’b101010101010101010101 (0x155555) and
21’b010101010101010101010 (0x0AAAAA). This test pattern resets to 0x155555 after the SH signal.
Figure 56. LVDS Test Pattern
Test Mode 2 - Ramp
This mode provides LVDS data that progresses from 0x00000 to the full scale output 0x1FFFFF incrementing by
1 per LVDS Clock. When the LVDS ramp test pattern is selected, the ramp begins immediately and counts from
zero to the full scale value, and then repeats.
Test Mode 3 - Fixed Output Data
This mode allows a fixed data value to be output. The value is set via. Upcounter Register 1, 2 and 3. The 21 bit
value taken from these registers is repetitively sent out over the LVDS link. This is useful for system debugging
of the LVDS link and receiver circuitry.
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CMOS Output Mode
CMOS Output Data Format
Figure 57. CMOS Data Output Format (Mode 3 Shown)
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CMOS Output Data Latency Diagrams
Figure 58. Mode 3 CMOS Output Latency
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Figure 59. Mode 2 CMOS Output Latency
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Figure 60. Mode 1 CMOS Output Latency
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Serial Interface
A serial interface is used to write and read the configuration registers. The interface is a three wire interface
using SCLK, SEN, and SDIO connections. The main input clock (INCLK) to the LM98714 must be active during
all Serial Interface commands.
WRITING TO THE SERIAL REGISTERS
To write to the serial registers, the timing diagram shown in Figure 61 must be met. First, SEN is toggled low.
The LM98714 assumes control of the SDIO pin during the first eight clocks of the command. During this period,
data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the
previously addressed register, regardless if the previous command was a read or a write. At the rising edge of
ninth clock, the LM98714 releases control of the SDIO pin. At the falling edge of the ninth clock period, the
master should assume control of the SDIO pin and begin issuing the new command. SDIO is clocked into the
LM98714 at the rising edge of SCLK. The remaining bits are composed of the “write” command bit (a zero), two
device address bits (zeros for the LM98714), five bit register address to be written, and the eight bit register
value to be written. When SEN toggles high, the register is written to, and the LM98714 now functions with this
new data.
Figure 61. Serial Write
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READING THE SERIAL REGISTERS
To read to the serial registers, the timing diagram shown in Figure 62 must be met. First, SEN is toggled low.
The LM98714 assumes control of the SDIO pin during the first eight clocks of the command. During this period,
data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the
previously addressed register, regardless if the previous command was a read or a write. At the rising edge of
ninth clock, the LM98714 releases control of the SDIO pin. At the falling edge of the ninth clock period, the
master should assume control of the SDIO pin and begin issuing the new command. SDIO is clocked into the
LM98714 at the rising edge of SCLK. The remaining bits are composed of the “read” command bit (a one), two
device address bits (zeros for the LM98714), five bit register address to be read, and the eight bit “don’t care”
bits. When SEN toggles high, the register is not written to, but its contents are staged to be outputted at the
beginning of the next command.
Figure 62. Serial Read
Serial Interface Timing Details
Figure 63. Serial Interface Specification Diagram
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Configuration Registers
The LM98714 operation is very flexible to support a wide variety of sensors and system designs. This flexibility is
controlled through configuration registers which are first summarized, then described in full in the following
tables. Because the serial interface only allows 5 address bits, a register paging system is used to support the
larger number of required registers.
A page register is present at the highest address (1Fh or 11111b). The power on default setting of the page
register is 00. Writing other values to this register allows the other pages to be accessed. The page register is
mirrored, and is accessible at the highest address on each page.
Figure 64 shows the proper sequence of operation for the LM98714.
Figure 64. LM98714 Proper Sequence of Operation
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PAGE 0 REGISTER TABLE - MAIN ANALOG FRONT END CONFIGURATION
Table 10.
Register/Bit Description
Bit 4 Bit 3
Address
(Binary)
Register Title
(Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page Register 1F = 0000 0000
Page 0
00000
Main Configuration 0
1111 0001
Operating Mode Select
Source
Follower
Enable
PIXCLK/
ADCCLK
Config.
Input Bias
Enable
Sampling
Mode Select
Output
Format
00001
00010
00011
Main Configuration 1
0101 0000
Input Polarity
Pixel Phase Clock Select
Active/
Standby
Gain Mode
Select
Output
Enable
Main Configuration 2
Main Configuration 3
0000 0000
0000 0111
Not Used
Power-down
Soft Reset
Reserved
Start Scan
Processing
Channel
Override
Upcount
Enable
00100
00101
Main Configuration 4
Input Clamp Control
0000 0000
0000 0000
Not Used
Not Used
LVDS Test Mode
Auto CLPIN
Enable
CLPIN
Gating
Auto CLPIN Width
00110
00111
01000
Auto CLPIN Position
VCLP Configuration
0010 0111
0010 0000
0000 0000
MSB
LSB
Not Used
Line Averaging
VCLP Reference Select
Pixel Averaging
VCLP DAC Bits
Offset Integration BLKCLP Mode Select
Black Level Clamp Control
Auto Black Level Clamp
Position
01001
0000 0000
Not Used
MSB
LSB
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
Target Black Level MSB
Target Black Level LSB
OSR CLAMP Control
OSG CLAMP Control
OSB CLAMP Control
OSR SAMPLE Control
OSG SAMPLE Control
OSB SAMPLE Control
Upcounter Register 1
Upcounter Register 2
Upcounter Register 3
0010 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
MSB
LSB+2
LSB
Not Used
LSB+1
Not Used
Not Used
Not Used
CLAMPR Position
CLAMPG Position
CLAMPB Position
Not Used
Not Used
Not Used
SAMPLER Position
SAMPLEG Position
SAMPLEB Position
Count Value LSBs
Count Value Middle 8 Bits
Not Used
Count Value MSBs
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Table 10. (continued)
Register/Bit Description
Bit 4 Bit 3
Address
(Binary)
Register Title
(Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
11000
11001
11010
11011
11100
11101
11110
11111
0000 0100
0000 0000
Page Register
Reserved (program all zeros)
LSB+2
LSB+1
LSB
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PAGE 1 REGISTER TABLE - OFFSET AND GAIN SETTINGS
Table 11.
Register/Bit Description
Bit 4 Bit 3
Address
(Binary)
Default
(Binary)
Register Title (Mnemonic)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page Register 1F = 0000 0001
Page 1
00000
00001
00010
00011
00100
Color 1 PGA
Color 2 PGA
Color 3 PGA
Color 4 PGA
Color 5 PGA
0101 0100
0101 0100
0101 0100
0101 0100
0101 0100
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
Color 1 Black Level Offset
DAC MSB
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
1000 0000
0000 0000
1000 0000
0000 0000
1000 0000
0000 0000
1000 0000
0000 0000
1000 0000
0000 0000
MSB
MSB
MSB
MSB
MSB
LSB+2
LSB
Color 1 Black Level Offset
DAC LSB
Not Used
Not Used
Not Used
Not Used
Not Used
LSB+1
LSB+1
LSB+1
LSB+1
LSB+1
Color 2 Black Level Offset
DAC MSB
LSB+2
LSB
Color 2 Black Level Offset
DAC LSB
Color 3 Black Level Offset
DAC MSB
LSB+2
LSB
Color 3 Black Level Offset
DAC LSB
Color 4 Black Level Offset
DAC MSB
LSB+2
LSB
Color 4 Black Level Offset
DAC LSB
Color 5 Black Level Offset
DAC MSB
LSB+2
LSB
Color 5 Black Level Offset
DAC LSB
01111
10000
10001
10010
10011
10100
10101
Color 1 Digital Offset
Color 2 Digital Offset
Color 3 Digital Offset
Color 4 Digital Offset
Color 5 Digital Offset
0100 0000
0100 0000
0100 0000
0100 0000
0100 0000
Not Used
Not Used
Not Used
Not Used
Not Used
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
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Table 11. (continued)
Register/Bit Description
Bit 4 Bit 3
Address
(Binary)
Default
(Binary)
Register Title (Mnemonic)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0000 0100
0000 0000
Page Register
Reserved (program all zeros)
LSB+2
LSB+1
LSB
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PAGE 2 REGISTER TABLE - CCD/CIS TIMING GENERATOR CONTROL 1
Table 12.
Register/Bit Description
Bit 4 Bit 3
Address
(Binary)
RegisterTitle
(Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page Register 1F = 0000 0010
Page 2
00000
00001
00010
SH Output
Enable
SH Source
Select
SH Mode
0000 0000
0010 0111
1100 1000
SH Mode
SH Delay
SH Pulse Width
PIX1/2 Control
SH Pulse Width
PIX1 Activity
PIX1
PIX2
PIX2 Activity
During SH
PIX1 Activity
PIX3 Activity
PIX5 Activity
PIX7 Activity
PIX1 Polarity
PIX3 Polarity
PIX5 Polarity
PIX2 Activity
PIX4 Activity
PIX6 Activity
PIX2 Polarity
PIX4 Polarity
PIX6 Polarity
PIX8 Polarity
Frequency
During SH
Frequency
PIX3
PIX3 Activity
During SH
PIX4
PIX4 Activity
During SH
00011
00100
00101
00110
PIX3/4 Control
PIX5/6 Control
1000 1000
0000 0000
0000 0000
0000 0000
Frequency
Frequency
PIX5
PIX5 Activity
During SH
PIX6
PIX6 Activity
During SH
Frequency
Frequency
PIX7
PIX7 Activity
During SH
PIX8
Frequency
PIX8 Activity
During SH
PIX7/8 Control
PIX7 Polarity
PIX7 Line
PIX8 Activity
PIX4 Line
Frequency
PIX8 Line Clamp
Enable
PIX6 Line
PIX5 Line
PIX3 Line Clamp
Enable
PIX2 Line
Clamp Enable Clamp Enable
PIX1 Line
Line Clamp Enable
Clamp Enable Clamp Enable Clamp Enable Clamp Enable
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
PIX1 Start
PIX1 End
0000 0000
0001 0101
Reserved
Reserved
MSB
MSB
LSB
LSB
PIX2 Start
PIX2 End
0000 0000
0001 0101
Reserved
Reserved
MSB
MSB
LSB
LSB
PIX3 Start
PIX3 End
0000 1011
0000 1101
Reserved
Reserved
MSB
MSB
LSB
LSB
PIX4 Start
PIX4 End
0001 0000
0001 0011
Reserved
Reserved
MSB
MSB
LSB
LSB
PIX5 Start
PIX5 End
0000 0000
0000 0000
Reserved
Reserved
MSB
MSB
LSB
LSB
PIX6 Start
PIX6 End
0000 0000
0000 0000
Reserved
Reserved
MSB
MSB
LSB
LSB
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Table 12. (continued)
Register/Bit Description
Address
(Binary)
RegisterTitle
(Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSB
LSB
11001
11010
11011
11100
11101
PIX7 Start
PIX7 End
0000 0000
0000 0000
Reserved
Reserved
MSB
MSB
PIX8 Start
PIX8 End
0000 0000
0000 0000
Reserved
Reserved
MSB
MSB
LSB
LSB
CMOS Data Mode
Status Bit Enable
Page Register
CLK10/
CLKOUT
11110
11111
0000 0000
0000 0000
Reserved
CLK9/ CB[4]
CLK8/ CB[3]
CLK7/ CB[2]
LSB+2
CLK6/ CB[1]
LSB+1
CLK5/ CB[0]
LSB
Reserved (program all zeros)
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PAGE 3 REGISTER TABLE - CCD/CIS TIMING GENERATOR CONTROL 2
Table 13.
Register/Bit Description
Bit 4 Bit 3
Address
(Binary)
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page 3
00000
Page Register 1F = 0000 0011
Output Mapping
CLK1/CLK2
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Output Mapping for CLK1 Pin
Output Mapping for CLK3 Pin
Output Mapping for CLK5 Pin
Output Mapping for CLK7 Pin
Output Mapping for CLK9 Pin
Output Mapping for CLK2 Pin
Output Mapping for CLK4 Pin
Output Mapping for CLK6 Pin
Output Mapping for CLK9 Pin
Output Mapping
CLK3/CLK4
00001
00010
00011
00100
Output Mapping
CLK5/CLK6
Output Mapping
CLK7/CLK8
Output Mapping
CLK9/(CLKOUT/ CLK10)
Output Mapping for CLKOUT/CLK10 Pin
LampIR2 SH/LAMP
LAMPR
Normal
State
LAMPG
Normal
State
LAMPB
Normal
State
LampIR1
Normal
State
00101
Illumination Mode
0000 0000
Normal
State
Reserved
Overlap
Enable
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp
Enable
IR2 Lamp
Enable
00110
00111
01000
01001
01010
01011
Line 1 Lamp Selection
Line 2 Lamp Selection
Line 3 Lamp Selection
Line 4 Lamp Selection
Line 5 Lamp Selection
LAMPR On - MSB
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp
Enable
IR2 Lamp
Enable
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp
Enable
IR2 Lamp
Enable
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp
Enable
IR2 Lamp
Enable
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp
Enable
IR2 Lamp
Enable
SH_OR
Enable
Reserved
MSB
MSB
MSB
MSB
01100
01101
01110
LAMPR On - LSB
LAMPR Off - MSB
LAMPR Off - LSB
0001 0001
0000 0011
0000 0110
LSB
LSB
Reserved
SH_OR
Enable
01111
LAMPG On - MSB
0000 0000
Reserved
010000
10001
10010
LAMPG On - LSB
LAMPG Off - MSB
LAMPG Off - LSB
0001 0010
0000 0011
0000 0000
LSB
LSB
Reserved
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Table 13. (continued)
Register/Bit Description
Address
(Binary)
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SH_OR
Enable
10011
LAMPB On - MSB
0000 0000
Reserved
MSB
10100
10101
10110
LAMPB On - LSB
LAMPB Off - MSB
LAMPB Off - LSB
0001 0011
0000 0011
0011 0000
LSB
LSB
Reserved
MSB
MSB
MSB
MSB
MSB
SH_OR
Enable
10111
LAMPIR1 On - MSB
0000 0000
Reserved
11000
11001
11010
LAMPIR1 On - LSB
LAMPIR1 Off - MSB
LAMPIR1 Off - LSB
0001 0100
0000 0011
0011 0000
LSB
LSB
Reserved
SH_OR
Enable
11011
LAMPIR2 On - MSB
0000 0000
Reserved
11100
11101
11110
11111
LAMPIR2 On - LSB
LAMPIR2 Off - MSB
LAMPIR2 Off - LSB
Page Register
0001 0101
0000 0011
0011 0000
0000 0000
LSB
Reserved
LSB
LSB
Reserved (program all zeros)
LSB+2
LSB+1
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PAGE 4 REGISTER TABLE - CCD/CIS TIMING GENERATOR CONTROL 3
Table 14.
Register/Bit Description
Bit 4 Bit 3
Address
(Binary)
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page Register 1F = 0000 0100
Page 4
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
11111
Mode On - MSB
Mode On - LSB
0000 0010
0000 0000
0000 0011
0000 0001
0000 0000
0000 0000
0000 0000
0000 0001
0011 1111
1111 1110
0011 1111
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
Reserved
MSB
LSB
Mode Off - MSB
Reserved
MSB
Mode Off - LSB
LSB
LSB
LSB
Optical Black Pixels Start
Optical Black Pixels End
Start of Valid Pixels - MSB
Start of Valid Pixels - LSB
End of Valid Pixels - MSB
End of Valid Pixels - LSB
Line End - MSB
MSB
MSB
Reserved
Reserved
Reserved
MSB
LSB
LSB
LSB
MSB
MSB
Line End - LSB
Sample Timing Monitor 1
Sample Timing Monitor 2
Sample Timing Monitor 3
SH2/SH3 Control
SH3 Select
SH2 Select
LSB+2
PIX OR/NOR Control 1
PIX OR/NOR Control 2
Page Register
Reserved (program all zeros)
LSB+1
LSB
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PAGE 5 REGISTER TABLE - CCD/CIS TIMING GENERATOR CONTROL 4
Table 15.
Register/Bit Description
Bit 4 Bit 3
Address
(Binary)
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page Register 1F = 0000 0101
Page 5
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
11111
PIX1/SH On Guardbands
PIX1/SH Off Guardbands
PIX2/SH On Guardbands
PIX2/SH Off Guardbands
PIX3/SH On Guardbands
PIX3/SH Off Guardbands
PIX4/SH On Guardbands
PIX4/SH Off Guardbands
PIX5/SH On Guardbands
PIX5/SH Off Guardbands
PIX6/SH On Guardbands
PIX6/SH Off Guardbands
PIX7/SH On Guardbands
PIX7/SH Off Guardbands
PIX8/SH On Guardbands
PIX8/SH Off Guardbands
Page Register
0000 1111
0000 0111
0000 1111
0000 0111
0000 1111
0000 0111
0000 1111
0000 0111
0000 1111
0000 0111
0000 1111
0000 0111
0000 1111
0000 0111
0000 1111
0000 0111
0000 0000
PIX1 On Guardband
PIX1 Off Guardband
PIX2 On Guardband
PIX2 Off Guardband
PIX3 On Guardband
PIX3 Off Guardband
PIX4 On Guardband
PIX4 Off Guardband
PIX5 On Guardband
PIX5 Off Guardband
PIX6 On Guardband
PIX6 Off Guardband
PIX7 On Guardband
PIX7 Off Guardband
PIX8 On Guardband
PIX8 Off Guardband
Reserved (program all zeros)
LSB+2
LSB+1
LSB
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REGISTER DEFINITION
Table 16.
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
Registers below are in register page 0.
[7:0] Main Configuration Register 0
Mode Select Bits.
11 Mode 3 (Default) (3 Channel Mode)
[7:6] 10 Mode 2 (2 Channel Mode)
01 Mode 1a (1 Channel Mode, 1 Channel sampled for all lines)
00 Mode 1b (3 Channel Line rate mode, 1 Channel sampled per line)
Color Select Bits. Used to determine the inputs sampled during a scan.
11 All three channels sampled (Default)
[5:4] 10 Mode 2 = OSR & OSB Mode 1 = OSB
01 Mode 2 = OSG & OSB Mode 1 = OSG
00 Mode 2 = OSR & OSG Mode 1 = OSR
Main
Configurati
on 0
1111
0001
Color Order. Configures the sequence of the pixel processing.
0
0 0000
[3]
0 Forward (default)
1 Reverse
Color Sequence Length. Used in Mode 1a only to determine the number of lines of colors sequenced during a
scan.
111 Not valid
110 Not Valid
101 Five color (line) sequence
100 Four color (line) sequence
011 Three color (line) sequence
010 Two color (line) sequence
001 One color (line) sequence (Default)
000 Not Valid
[2:0]
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:0] Main Configuration Register 1
Source Follower Enable.
[7]
[6]
[5]
[4]
[3]
0 Disable (Default)
1 Enable
Input Bias Enable. Enables the Input Bias Resistor ladder.
0 Disable
1 Enable (Default)
Input Polarity. Configures the polarity mode of the input signal.
0 Negative going input relative to reference (Default)
1 Positive going input relative to reference
Sampling Mode Select.
0 Sample and Hold Mode
1 Correlated Double Sampling Mode (Default)
Output Format.
0 LVDS (Default)
Main
Configurati
on 1
0101
0000
0
0 0001
1 CMOS
PIXCLK/ADCCLK Configuration. Selects appropriate multiplier for given input clock frequency.
Mode 3: ADC Frequency = 3x Pixel Frequency
Mode 2: ADC Frequency = 2x Pixel Frequency
Mode 1: ADC Frequency = 1x Pixel Frequency
[2]
0 ADCCLK User supplies ADC rate clock, LM98714 performs no multiplication
1 PIXCLK User supplies Pixel rate clock, LM98714 performs clock multiplication
Mode 3: PIXCLK internally multiplied by 3 to get ADC clock
Mode 2: PIXCLK internally multiplied by 2 to get ADC clock
Mode 1: PIXCLK = ADCCLK. This bit is not used for Mode 1
[1:0] Pixel Phase Clock Select. Coarse adjustment for Pixel phase relative to INCLK. Useful in systems where Pixel
inputs arrive with significant delay relative to INCLK.
00 PIXPHASE0. Pixel phase aligned with INCLK
01 PIXPHASE1. Pixel phase delayed by (TADC Clock* 3/7)
10 PIXPHASE2. Pixel phase delayed by (TADC Clock
)
11 PIXPHASE3. Pixel phase delayed by (TADC Clock * (1 + 3/7))
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:0] Main Configuration 2
[7:6] Not Used
[5]
Active/Standby
Gain Mode Select. Selects either a 1x or 2x gain mode in the CDS/Sample/Hold Block.
0 1x Gain in the CDS/Sample/Hold Block (Default)
1 2x Gain in the CDS/Sample/Hold Block
Output Enable. Enables the Data Output pins.
0 Disabled (Default)
[4]
Main
Configurati
on 2
[3]
0000
0000
0
0 0010
1 Enable
Powerdown
[2]
[1]
[0]
0 Device fully powered (Default)
1 Powerdown. Power down of major analog blocks
Software Reset. Performs a system reset when set to a 1. Self clearing.
Start Scan (BOS)
0 Ready (Default)
1 Start Scan. Control bit is self clearing
[7:0] Main Configuration 3
[7:4] Not Used
Processing Channel Override. Used in Mode 1 to determine the analog processing path for the selected inputs.
Main
Configurati
on 3
0000
0111
0
0 0011
[3]
0 Multiplex all selected inputs into the Red Channel analog path (Default)
1 Process each selected input thru its respective analog path
Reserved
Set to 111
[2:0]
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:0] Main Configuration 4
[7:4] Not Used
[3]
Upcount Enable
LVDS Test Mode. Activates LVDS test pattern output (when in LVDS output mode only).
000 Normal operation, no test pattern output (Default)
Main
Configurati
on 4
0000
0000
001 Test pattern 1: Alternating pattern between 0x155555 and 0x0AAAAA
010 Test pattern 2: If Upcount Enable Bit set, count from 21h000000 to 21h 1FFFFF
0
0 0100
[2:0]
011 Test pattern 3. Output Static Count value found represented by the three Upcounter Registers found on page
0
Reg 0x14 Bits[4:0] = Count Values 5 MSBs
Reg 0x13 Bits[7:0] = Count Values 8 Middle Bits
Reg 0x12 Bits[7:0] = Count Values 8 LSBs
[7:0] Input Clamp Control (CLPIN) Configuration Register
[7:4] Reserved
Auto CLPIN Width. Width in Pixels of the Auto generated CLPIN pulse.
00 4 Pixels (Default)
[3:2] 01 8 Pixels
10 16 Pixels
11 32 Pixels
Input
Clamp
Control
0000
0000
0
0 0101
Auto CLPIN Enable.
0 Auto CLPIN Disabled
[1]
[0]
CLPIN Pulse generation Disabled (Default)
1 Auto CLPIN
CLPIN generated internally with a programmable delay from SH
CLPIN Gating Enable.
0 Auto CLPINGATED not gated by SAMPLE (default)
1 Auto CLPINGATED gated by SAMPLE (= logical and of CLPIN and SAMPLE)
[7:0] Auto CLPIN Pulse Position Register
Auto
CLPIN
Position
0010
0111
0
0 0110
Auto CLPIN Pulse Position. Number of pixels in which Auto CLPIN pulse is delayed, relative to the falling edge of
[7:0]
SH.
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:0] VCLP Configuration Register
[7:6] Reserved
VCLP Reference Select.
VCLP
Configurati
on
00 External Bias (No Internal Connection to Ladder Resistors or DAC)
[5:4] 01 Internal VCLP DAC connection only
10 Internal Resistor Ladder connection only (Default)
11 Reserved
0010
0000
0
0 0111
[3:0] 4 Bit nibble for VCLP Reference DAC value.
[7:0] Black Level Correction Circuitry Configuration Register
Line Averaging. Number of Lines that the correction loop will run. Line Counter is reset during any write to this
register. A line beginning is defined by the SH pulse.
00 Infinite (Default)
[7:6]
01 15 Lines
10 31 Lines
11 63 Lines
Pixel Averaging. Number of Black Level Pixels averaged by the correction loop.
00 4 Pixels
[5:4] 01 8 Pixels
Black Level
Clamp
Control
10 16 Pixels
0000
0000
0
0 1000
11 32 Pixels
Offset Integration.
00 Divide by 8
[3:2] 01 Divide by 16
10 Divide by 32
11 Divide by 64
BLKCLP Mode Select. If Auto Black Clamp pulse is enabled, Offset DAC registers are read only.
00 Auto Black Clamp Circuitry Disabled (default)
[1:0] 01 Auto Black Clamp pulse delayed from falling edge of SH pulse
10 Auto Black Clamp pulse delayed from falling edge of CLPIN pulse
11 Reserved
[7:0] Auto Black Level Clamp Position Register
Auto Black
Level
Clamp
0000
0000
[7]
Reserved
0
0 1001
Black Level Clamp Position. Number of pixels in which Auto Black pulse is delayed, relative to selected trigger
source.
[6:0]
Position
80
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
Target
0 1010 Black Level
MSB
0010
0000
0
[7:0] The 8 MSBs of the 10 Bit target output code for black pixels when using the Auto Black Level Correction loop.
[7:0] The target output code for black pixels when using the Auto Black Level Correction loop
Target
0 1011 Black Level
LSB
0000
0000
0
0
0
0
0
0
[7:2] Reserved
[1:0] The 2 LSBs of the 10 Bit target output code for black pixels when using the Auto Black Level Correction loop.
[7:0]
OSR
CLAMP
Control
0000
0000
0 1100
0 1101
0 1110
0 1111
1 0000
[7:5] Not Used
[4:0] CLAMPR Position. A value of 0 will force the position of this pulse to be at the mode dependant default.
[7:0]
OSG
CLAMP
Control
0000
0000
[7:5] Not Used
[4:0] CLAMPG Position. A value of 0 will force the position of this pulse to be at the mode dependant default.
[7:0]
OSB
CLAMP
Control
0000
0000
[7:5] Not Used
[4:0] CLAMPB Position. A value of 0 will force the position of this pulse to be at the mode dependant default.
[7:0]
OS R
SAMPLE
Control
0000
0000
[7]
Not Used
[6:0] SAMPLER Position. A value of 0 will force the position of this pulse to be at the mode dependant default.
[7:0]
OSG
SAMPLE
Control
0000
0000
[7]
Not Used
[6:0] SAMPLEG Position. A value of 0 will force the position of this pulse to be at its mode dependant default.
[7:0]
OSB
SAMPLE
Control
0000
0000
0
0
1 0001
1 1111
[7]
Not Used
[6:0] SAMPLEB Position. A value of 0 will force the position of this pulse to be at its mode dependant default.
Page
Register
0000
0000
[7:0] Used to select desired page of registers being accessed.
Registers below are in register page 1.
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 1 lines.
Color 1
PGA
0101
0100
1
1
1
0 0000
0 0001
0 0010
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the PGA setting for the OSR input.
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 2 lines.
Color 2
PGA
0101
0100
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the PGA setting for the OSG input.
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 3 lines.
Color 3
PGA
0101
0100
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the PGA setting for the OSB input.
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 4 lines.
Not used in Mode 1b, Mode 2 or Mode 3.
Color 4
PGA
0101
0100
1
0 0011
0 0100
[7:0]
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 5 lines.
Not used in Mode 1b, Mode 2 or Mode 3.
Color 5
PGA
0101
0100
1
1
[7:0]
[7:0]
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 1 lines.
Color 1
0 0101 Black Level
DAC MSB
1000
0000
In Mode 1b/c, Mode 2 or Mode 3, the register used to define the DAC setting for the OSR input. The DAC value is
in offset Binary format.
[7:0] Color 1 Black Level DAC LSB
[7:2] Not Used
Color 1
0 0110 Black Level
DAC LSB
0000
0000
1
1
1
1
1
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 1 lines.
[1:0]
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSR input. The DAC value is in
offset Binary format.
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 2 lines.
Color 2
0 0111 Black Level
DAC MSB
1000
0000
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSG input. The DAC value is in
offset Binary format.
[7:0] Color 2 Black Level DAC LSB
[7:2] Not Used
Color 2
0 1000 Black Level
DAC LSB
0000
0000
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 2 lines.
[1:0]
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSG input. The DAC value is in
offset Binary format.
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 3 lines.
Color 3
0 1001 Black Level
DAC MSB
1000
0000
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSB input. The DAC value is in
offset Binary format.
[7:0] Color 3 Black Level DAC LSB
[7:2] Not Used
Color 3
0 1010 Black Level
DAC LSB
0000
0000
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 3 lines.
[1:0]
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSB input. The DAC value is in
offset Binary format.
Color 4
0 1011 Black Level
DAC MSB
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 4 lines.
1000
0000
1
1
Not used in Mode 1b, Mode 2 or Mode 3. The DAC value is in offset Binary format.
[7:0] Color 4 Black Level DAC LSB
[7:2] Not Used
Color 4
0 1100 Black Level
DAC LSB
0000
0000
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 4 lines.
[1:0]
Not used in Mode 1b, Mode 2 or Mode 3. The DAC value is in offset Binary format.
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
Color 5
0 1101 Black Level
DAC MSB
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 5 lines.
1000
0000
1
[7:0]
Not used in Mode 1b, Mode 2 or Mode 3. The DAC value is in offset Binary format.
[7:0] Color 5 Black Level DAC LSB
[7:2] Not Used
Color 5
0 1110 Black Level
DAC LSB
0000
0000
1
1
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 5 lines.
[1:0]
Not used in Mode 1b/c, Mode 2 or Mode 3. The DAC value is in offset Binary format.
[7:0] Color 1 Digital Offset
[7]
Not Used
Color 1
0100
0000
0 1111
1 0000
Digital
Offset
The Digital Offset applied to the ADC result in Mode 1a during Color 1 lines.
[6:0]
In Mode 1b/c, Mode 2 or Mode 3, the register used to define the Digital Offset setting for the OSR input. The DAC
value is in offset Binary format.
[7:0] Color 2 Digital Offset
[7]
Not Used
Color 2
Digital
Offset
0100
0000
1
The Digital Offset applied to the ADC result in Mode 1a during Color 2 lines.
[6:0]
In Mode 1b/c, Mode 2 or Mode 3, the register used to define the DAC setting for the OSG input. The DAC value is
in offset Binary format.
[7:0] Color 3 Digital Offset
[7]
Not Used
Color 3
Digital
Offset
0100
0000
1
1
1 0001
1 0010
The Digital Offset applied to the ADC result in Mode 1a during Color 3 lines.
[6:0]
In Mode 1b/c, Mode 2 or Mode 3, the register used to define the DAC setting for the OSB input. The DAC value is
in offset Binary format.
[7:0] Color 4 Digital Offset
Color 4
Digital
Offset
[7]
Not Used
0100
0000
The Digital Offset applied to the ADC result in Mode 1a during Color 4 lines.
Not used in Mode 1b/c, Mode 2 or Mode 3. The DAC value is in offset Binary format.
[6:0]
[7:0] Color 5 Digital Offset
Color 5
Digital
Offset
[7]
Not Used
0100
0000
1
1
1 0011
1 1111
The Digital Offset applied to the ADC result in Mode 1a during Color 5 lines.
Not used in Mode 1b/c, Mode 2 or Mode 3. The DAC value is in offset Binary format.
[6:0]
Page
Register
0000
0000
[7:0] Used to select desired page of registers being accessed.
Registers below are in register page 2.
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
SH Output Enable.
[7]
0 Enable SH Output
1 SH Output Tristate
SH Master/Slave Select.
0 External SH_R input. CCD Timing Generator runs in Slave mode, with SH triggered by an external pulse on the
SH_R pin.
[6]
1 Auto generated SH. CCD Timing Generator runs in Master mode, with SH generated internally with a
programmable period and width.
0000
0000
2
0 0000
SH Mode
SH Output Mode.
00 SH Output = SH
[5:4] 01 SH Output = SH
10 SH Output = 0
11 SH Output = 1
SH Delay from SH_R
[3:0]
Additional delay
SH Pulse Width
[7:0]
SH Pulse
Width
0010
0111
2
0 0001
SH Pulse Width = (2 * [7:0]) + 1
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
PIX1 Activity
[7]
0 Disabled
1 Enabled
PIX1 Polarity
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0 Normal - Low when off
1 Inverted - High when off
PIX1 Frequency
0 Pixel Rate
1 1/2 Pixel Rate
PIX1 Activity During SH
0 Inactive
1 Active
PIX1/2
Control
1100
1000
2
0 0010
PIX2 Activity
0 Disabled
1 Enabled
PIX2 Polarity
0 Normal - Low when off
1 Inverted - High when off
PIX2 Frequency
0 Pixel Rate
1 1/2 Pixel Rate
PIX2 Activity During SH
0 Inactive
1 Active
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
PIX3 Activity
[7]
0 Disabled
1 Enabled
PIX3 Polarity
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0 Normal - Low when off
1 Inverted - High when off
PIX3 Frequency
0 Pixel Rate
1 1/2 Pixel Rate
PIX3 Activity During SH
0 Inactive
1 Active
PIX3/4
Control
1000
1000
2
0 0011
PIX4 Activity
0 Disabled
1 Enabled
PIX4 Polarity
0 Normal - Low when off
1 Inverted - High when off
PIX4 Frequency
0 Pixel Rate
1 1/2 Pixel Rate
PIX4 Activity During SH
0 Inactive
1 Active
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
PIX5 Activity
[7]
0 Disabled
1 Enabled
PIX5 Polarity
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0 Normal - Low when off
1 Inverted - High when off
PIX5 Frequency
0 Pixel Rate
1 1/2 Pixel Rate
PIX5 Activity During SH
0 Inactive
1 Active
PIX5/6
Control
0000
0000
2
0 0100
PIX6 Activity
0 Disabled
1 Enabled
PIX6 Polarity
0 Normal - Low when off.
1 Inverted - High when off.
PIX6 Frequency
0 Pixel Rate
1 1/2 Pixel Rate
PIX6 Activity During SH
0 Inactive
1 Active
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
PIX7 Activity
[7]
0 Disabled
1 Enabled
PIX7 Polarity
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0 Normal - Low when off
1 Inverted - High when off
PIX7 Frequency
0 Pixel Rate
1 1/2 Pixel Rate
PIX7 Activity During SH
0 Inactive
1 Active
PIX7/8
Control
0000
0000
2
0 0101
PIX8 Activity
0 Disabled
1 Enabled
PIX8 Polarity
0 Normal - Low when off
1 Inverted - High when off
PIX8 Frequency
0 Pixel Rate
1 1/2 Pixel Rate
PIX8 Activity During SH
0 Inactive
1 Active
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
PIX8 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX8.
0 Disabled. PIX generator functions as normal.
[7]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX7 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX7.
0 Disabled. PIX generator functions as normal.
[6]
[5]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX6 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX6.
0 Disabled. PIX generator functions as normal.
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX5 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX5.
0 Disabled. PIX generator functions as normal.
[4]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX4 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX4.
0 Disabled. PIX generator functions as normal.
Line Clamp
Enable
0000
0000
2
0 0110
[3]
[2]
[1]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX3 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX3.
0 Disabled. PIX generator functions as normal.
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX2 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX2.
0 Disabled. PIX generator functions as normal.
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX1 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX1.
0 Disabled. PIX generator functions as normal.
[0]
[7]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
Reserved. Set to 0.
0000
0000
2
2
2
0 0111
0 1000
0 1010
PIX1 Start
PIX1 End
PIX2 Start
[6:0] PIX1 on point. Defines when the PIX1 signal turns on within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0001
0101
[6:0] PIX1 off point. Defines when the PIX1 signal turns off within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
0000
[6:0] PIX2 on point. Defines when the PIX2 signal turns on within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7]
Reserved. Set to 0.
0001
0101
2
0 1011
0 1101
0 1110
1 0000
1 0001
1 0011
1 0100
1 0110
1 0111
1 1001
1 1010
1 1100
PIX2 End
PIX3 Start
PIX3 End
PIX4 Start
PIX4 End
PIX5 Start
PIX5 End
PIX6 Start
PIX6 End
PIX7 Start
PIX7 End
PIX8 Start
[6:0] PIX2 off point. Defines when the PIX2 signal turns off within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
1011
2
2
2
2
2
2
2
2
2
2
2
[6:0] PIX3 on point. Defines when the PIX3 signal turns on within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
1101
[6:0] PIX3 off point. Defines when the PIX3 signal turns off within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0001
0000
[6:0] PIX4 on point. Defines when the PIX4 signal turns on within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0001
0011
[6:0] PIX4 off point. Defines when the PIX4 signal turns off within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
0000
[6:0] PIX5 on point. Defines when the PIX5 signal turns on within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
0000
[6:0] PIX5 off point. Defines when the PIX5 signal turns off within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
0000
[6:0] PIX6 on point. Defines when the PIX6 signal turns on within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
0000
[6:0] PIX6 off point. Defines when the PIX6 signal turns off within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
0000
[6:0] PIX7 on point. Defines when the PIX7 signal turns on within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
0000
[6:0] PIX7 off point. Defines when the PIX7 signal turns off within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
[7]
Reserved. Set to 0.
0000
0000
[6:0] PIX8 on point. Defines when the PIX8 signal turns on within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7]
Reserved. Set to 0
0000
0000
2
1 1101
PIX8 End
[6:0] PIX8 off point. Defines when the PIX8 signal turns off within the pixel period. Can be set to any available edge
within the pixel period. (For 1/2 frequency signals, the count can be any available edge within 2 pixel periods)
Reserved. Set to 000
[7:6]
When mapping the CLK5 to CLK10 pins as either CLKOUT or CB outputs, the Sample Timing Monitor 1 (Page 4,
Register 0x0C) cannot be used.
[5]
[4]
[3]
[2]
[1]
[0]
0 - CLK10 mapped normally, 1- CLK10 = CLKOUT
0 - CLK9 mapped normally, 1- CLK9 = CB[4] status bit
0 - CLK8 mapped normally, 1- CLK8 = CB[3] status bit
0 - CLK7 mapped normally, 1- CLK7 = CB[2] status bit
0 - CLK6 mapped normally, 1- CLK6 = CB[1] status bit
0 - CLK5 mapped normally, 1- CLK5 = CB[0] status bit
CMOS
Data Mode
Status Bit
Enable
0000
0000
2
2
1 1110
1 1111
Page
Register
0000
0000
[7:0] Used to select desired page of registers being accessed.
Registers below are in register page 3.
These registers set which timing signal is present on the respective CLKn output pin.
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:4]
CLK 0011 PIX3
1
0100 PIX4
0101 PIX5
0110 PIX6
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
Output
Mapping
CLK1/CLK
2
0000
0000
3
0 0000
[3:0]
CLK
1011 LAMPB
1100 LAMPIR1
2
1101 LAMPIR2
1110 MODE
1111 SH
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
These registers set which timing signal is present on the respective CLKn output pin.
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:4]
CLK 0011 PIX3
3
0100 PIX4
0101 PIX5
0110 PIX6
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
Output
Mapping
CLK3/CLK
4
0000
0000
3
0 0001
[3:0]
CLK
1011 LAMPB
1100 LAMPIR1
4
1101 LAMPIR2
1110 MODE
1111 SH
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
These registers set which timing signal is present on the respective CLKn output pin.
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:0]
CLK 0011 PIX3
5
0100 PIX4
0101 PIX5
0110 PIX6
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
Output
Mapping
CLK5/CLK
6
0000
0000
3
0 0010
[3:0]
CLK
1011 LAMPB
1100 LAMPIR1
6
1101 LAMPIR2
1110 MODE
1111 SH
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
These registers set which timing signal is present on the respective CLKn output pin.
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:0]
CLK 0011 PIX3
7
0100 PIX4
0101 PIX5
0110 PIX6
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
Output
Mapping
CLK7/CLK
8
0000
0000
3
0 0011
[3:0]
CLK
1011 LAMPB
1100 LAMPIR1
8
1101 LAMPIR2
1110 MODE
1111 SH
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
These registers set which timing signal is present on the respective CLKn output pin.
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:4]
CLK 0011 PIX3
9
0100 PIX4
0101 PIX5
0110 PIX6
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
Output
Mapping
CLK9/CLK
10
0000
0000
3
0 0100
[3:0]
CLK
1011 LAMPB
1100 LAMPIR1
10
1101 LAMPIR2
1110 MODE
1111 SH
LAMPR Normal State
[7]
0 = Low, 1 = High
LAMPG Normal State
[6]
0 = Low, 1 = High
LAMPB Normal State
[5]
0 = Low, 1 = High
Illumination
Mode (see
also AFE
color
LampIR1 Normal State
0000
0000
3
0 0101
[4]
0 = Low, 1 = High
modes)
LampIR2 Normal State
[3]
0 = Low, 1 = High
[2:1] Reserved
SH/LAMP Overlap Enable
[0]
0 Disabled
1 Overlap Enabled
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:5] Reserved. Set to 000
Red Lamp Enable
[4]
[3]
[2]
[1]
[0]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
0 IR1 Disabled
1 IR1 Enabled
Line 1
Lamp
Selection
0000
0000
3
0 0110
IR2 Lamp Enable
0 IR2 Disabled
1 IR2 Enabled
[7:5] Reserved. Set to 000
Red Lamp Enable
[4]
[3]
[2]
[1]
[0]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
0 IR1 Disabled
1 IR1 Enabled
Line 2
Lamp
Selection
0000
0000
3
0 0111
IR2 Lamp Enable
0 IR2 Disabled
1 IR2 Enabled
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:5] Reserved. Set to 000
Red Lamp Enable
[4]
[3]
[2]
[1]
[0]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
0 IR1 Disabled
1 IR1 Enabled
Line 3
Lamp
Selection
0000
0000
3
0 1000
IR2 Lamp Enable
0 IR2 Disabled
1 IR2 Enabled
[7:5] Reserved. Set to 000
Red Lamp Enable
[4]
[3]
[2]
[1]
[0]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
0 IR1 Disabled
1 IR1 Enabled
Line 4
Lamp
Selection
0000
0000
3
0 1001
IR2 Lamp Enable
0 IR2 Disabled
1 IR2 Enabled
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:5] Reserved. Set to 000
Red Lamp Enable
[4]
[3]
[2]
[1]
[0]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
0 IR1 Disabled
1 IR1 Enabled
Line 5
Lamp
Selection
0000
0000
3
0 1010
IR2 Lamp Enable
0 IR2 Disabled
1 IR2 Enabled
[7:5] Reserved. Set to 000
LAMPR SH_OR Enable
[4]
0 No ORing
LAMPR On
MSB
0000
0000
3
0 1011
1 LAMPR uses SH_OR function
LAMPR On Time Most Significant Bits
[3:0]
[7:0]
This selects the pixel count at which the LAMPR output goes high.
LAMPR On Time Least Significant Byte
LAMPR On
LSB
0001
0001
3
3
3
0 1100
0 1101
0 1110
This selects the pixel count at which the LAMPR output goes high.
[7:4] Reserved. Set to 0000
LAMPR Off
MSB
0000
0011
LAMPR Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the LAMPR output goes low.
LAMPR Off Time Least Significant Byte
LAMPR Off
LSB
0000
0110
[7:0]
This selects the pixel count at which the LAMPR output goes low.
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:5] Reserved. Set to 000
LAMPG SH_OR Enable.
[4]
0 No ORing
LAMPG On
MSB
0000
0000
3
0 1111
1 LAMPG uses SH_OR function
LAMPG On Time Most Significant Bits.
[3:0]
[7:0]
This selects the pixel count at which the LAMPR output goes high.
LAMPG On Time Least Significant Byte
LAMPG On
LSB
0001
0010
3
3
3
1 0000
1 0001
1 0010
This selects the pixel count at which the LAMPR output goes high.
[7:4] Reserved. Set to 0000
LAMPG Off
MSB
0000
0011
LAMPG Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the LAMPR output goes low.
LAMPG Off Time Least Significant Byte
LAMPG Off
LSB
0000
0000
[7:0]
This selects the pixel count at which the LAMPR output goes low.
[7:5] Reserved. Set to 000
LAMPB SH_OR Enable
[4]
0 No ORing
LAMPB On
MSB
0000
0000
3
1 0011
1 LAMPB uses SH_OR function
LAMPB On Time Most Significant Bits
[3:0]
[7:0]
This selects the pixel count at which the LAMPR output goes high.
LAMPB On Time Least Significant Byte
This selects the pixel count at which the LAMPR output goes high.
LAMPB On
LSB
0001
0011
3
3
3
1 0100
1 0101
1 0110
[7:4] Reserved. Set to 0000
LAMPB Off
MSB
0000
0011
LAMPB Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the LAMPR output goes low.
LAMPB Off Time Least Significant Byte
LAMPB Off
LSB
0011
0000
[7:0]
This selects the pixel count at which the LAMPR output goes low.
[7:5] Reserved. Set to 000
LAMPIR1 SH_OR Enable
[4]
0 No ORing
LAMPIR1
On MSB
0000
0000
3
1 0111
1 LAMPIR1 uses SH_OR function
LAMPIR1 On Time Most Significant Bits
This selects the pixel count at which the LAMPR output goes high.
[3:0]
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
LAMPIR1 On Time Least Significant Byte
This selects the pixel count at which the LAMPR output goes high.
LAMPIR1
On LSB
0001
0100
3
1 1000
1 1001
1 1010
[7:0]
[7:4] Reserved. Set to 0000
LAMPIR1
Off MSB
0000
0011
3
3
LAMPIR1 Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the LAMPR output goes low.
LAMPIR1 Off Time Least Significant Byte
LAMPIR1
Off LSB
0011
0000
[7:0]
This selects the pixel count at which the LAMPR output goes low.
[7:5] Reserved. Set to 000
LAMPIR2 SH_OR Enable.
[4]
0 No ORing
LAMPIR2
On MSB
0000
0000
3
1 1011
1 LAMPIR2 uses SH_OR function
LAMPIR2 On Time Most Significant Bits.
This selects the pixel count at which the LAMPR output goes high.
LAMPIR2 On Time Least Significant Byte
This selects the pixel count at which the LAMPR output goes high.
[3:0]
[7:0]
LAMPIR2
On LSB
0001
0101
3
3
1 1100
1 1101
[7:4] Reserved. Set to 0000
LAMPIR2
Off MSB
0000
0011
LAMPIR2 Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the LAMPR output goes low.
LAMPIR2 Off Time Least Significant Byte
LAMPIR2
Off LSB
0011
0000
3
3
1 1110
1 1111
[7:0]
This selects the pixel count at which the LAMPR output goes low.
Page
Register
0000
0000
Used to select desired page of registers being accessed.
[7:0]
Registers below are in register page 4.
[7:4] Reserved. Set to 0000
Mode On
MSB
0000
0010
4
4
4
4
0 0000
0 0001
0 0010
0 0011
Mode On Time Most Significant Bits
[3:0]
This selects the pixel count at which the Mode output goes high.
Mode On Time Least Significant Byte
Mode On
LSB
0000
0000
[7:0]
This selects the pixel count at which the Mode output goes high.
[7:4] Reserved. Set to 0000
Mode Off
MSB
0000
0011
Mode Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the Mode output goes low.
Mode Off Time Least Significant Byte
Mode Off
LSB
0000
0001
[7:0]
This selects the pixel count at which the Mode output goes low.
100
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
Optical
Black
Pixels Start
Starting point for optical black clamping
0000
0000
4
0 0100
[7:0]
nnnnnnnn - n pixels (0-255)
Optical
Black
Pixels End
End point for optical black clamping
nnnnnnnn - n pixels (0-255)
0000
0000
4
4
0 0101
0 0110
[7:0]
Start of
Valid
Pixels -
MSB
[7:6] Reserved. Set to 00
Start of Valid Pixels - Most Significant Bits.
0000
0000
[5:0]
Selects the pixel count where the data status bits begin to indicate valid pixels.
Start of Valid Pixels - Least Significant Bits.
Start of
Valid
Pixels -
LSB
0000
0000
Selects the pixel count where the data status bits begin to indicate valid pixels.
4
4
4
0 0111
0 1000
0 1001
[7:0]
End of
Valid
Pixels -
MSB
[7:6] Reserved. Set to 00
End of Valid Pixels - Most Significant Bits.
0011
1111
[5:0]
Selects the pixel count where the data status bits stop indicating valid pixels.
End of Valid Pixels - Least Significant Bits.
End of
Valid
Pixels -
LSB
1111
1110
Selects the pixel count where the data status bits stop indicating valid pixels.
[7:0]
[7:6] Reserved. Set to 00.
Line End -
MSB
0011
1111
Line End Value - Most Significant 6 Bits
4
4
0 1010
0 1011
[5:0]
Selects the pixel count where the current line is ended and the next one begins. Con trols the integration time of
one line and the period between SH pulses.
Line End Value Least Significant Byte
Line End -
LSB
1111
1111
Selects the pixel count where the current line is ended and the next one begins. Con trols the integration time of
one line and the period between SH pulses.
[7:0]
n pixels (0 - 16383)
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
Enables Sample and Clamp timing signals to be observed on one of the sensor timing control outputs. This
function overrides any other settings for sensor control signal mapping.
[7:0]
Important Note: Sample Timing Monitor 1 cannot be used if the CMOS Data Mode Status Bit Enable
Register (Page 2, Register 0x1E) is being programmed to map CLKOUT to CLK10 or any Control Bit to
CLK5-CLK9. Sample Timing Monitors 2 and 3 are not effected by this limitation.
Upper 4 bits select timing signal to be monitored.
0000 Sample Red
0001 Clamp Red
0010 Sample Green
0011 Clamp Green
0100 Sample Blue
0101 Clamp Blue
[7:4]
Sample
Timing
Monitor 1
1111 No signal monitored
Lower 4 bits select which output pin is used as a monitor.
0000 CLK1
1111
1111
4
0 1100
0001 CLK2
0010 CLK3
0011 CLK4
0100 CLK5
[3:0]
0101 CLK6
0110 CLK7
0111 CLK8
1000 CLK9
1001 CLKOUT/CLK10
1111 All outputs normal
102
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
Enables Sample and Clamp timing signals to be observed on one of the sensor timing control outputs. This
function overrides any other settings for sensor control signal mapping.
[7:0]
Upper 4 bits select timing signal to be monitored.
0000 Sample Red
0001 Clamp Red
0010 Sample Green
0011 Clamp Green
0100 Sample Blue
0101 Clamp Blue
[7:4]
1111 No signal monitored
Lower 4 bits select which output pin is used as a monitor.
0000 CLK1
Sample
Timing
Monitor 2
1111
1111
4
0 1101
0001 CLK2
0010 CLK3
0011 CLK4
0100 CLK5
[3:0]
0101 CLK6
0110 CLK7
0111 CLK8
1000 CLK9
1001 CLKOUT/CLK10
1111 All outputs normal
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
Enables Sample and Clamp timing signals to be observed on one of the sensor timing control outputs. This
function overrides any other settings for sensor control signal mapping.
[7:0]
Upper 4 bits select timing signal to be monitored.
0000 Sample Red
0001 Clamp Red
0010 Sample Green
0011 Clamp Green
0100 Sample Blue
0101 Clamp Blue
[7:4]
1111 No signal monitored
Lower 4 bits select which output pin is used as a monitor.
0000 CLK1
Sample
Timing
Monitor 3
1111
1111
4
0 1110
0001 CLK2
0010 CLK3
0011 CLK4
0100 CLK5
[3:0]
0101 CLK6
0110 CLK7
0111 CLK8
1000 CLK9
1001 CLKOUT/CLK10
1111 All outputs normal
Controls the optional SH2 and SH3 output signals. These signals can override the Lamp IR1 and Lamp IR2
outputs if additional SH signals are required.
[7:0]
[7:4] Not Used.
SH3 Output Select.
[3]
0 Lamp IR2 output is programmed from Lamp IR2 Generator
1 Lamp IR2 output is SH3
SH2/SH3
Control
0000
0000
4
0 1111
SH2 Output Select.
[2]
0 Lamp IR1 output is programmed from Lamp IR1 Generator
1 Lamp IR1 output is SH2
[1:0] Not Used
104
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
[7:0] Controls the optional OR and NOR operations on the PIX generator outputs as described below. These signals
can override the normal PIX generator outputs to pro vide OR and NOR functionality for uses such as Pixel
Lumping. If multiple functions are selected, the order of priority from highest to lowest is PIX OR/NOR Control 1
Bit[0] to Bit [7], then PIX OR/NOR Control 2 Bit[0] to Bit[7] (i.e PIX OR/NOR Control 1 Bit[7] has a higher priority
on the PIX5 output than PIX OR/NOR Control 2 Bit[0] or Bit[2]).
For reference purposes, the normal, unmodified PIX generator outputs are named pix1 through pix8 (lower case)
and the final signal prior to the CLK pins are named PIX1 through PIX8 (upper case).
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0 No effect (default); 1 PIX1 = ~(pix1 || pix2)
0 No effect (default); 1 PIX2 = (pix1 || pix2)
0 No effect (default); 1 PIX2 = ~(pix2 || pix3)
0 No effect (default); 1 PIX3 = (pix2 || pix3)
0 No effect (default); 1 PIX3 = ~(pix3 || pix4)
0 No effect (default); 1 PIX4 = (pix3 || pix4)
0 No effect (default); 1 PIX4 = ~(pix4 || pix5)
0 No effect (default); 1 PIX5 = (pix4 || pix5)
PIX
OR/NOR
Control 1
0000
0000
4
1 0000
[7:0] Controls the optional OR and NOR operations on the PIX generator outputs as described below. These signals
can override the normal PIX generator outputs to pro vide OR and NOR functionality for uses such as Pixel
Lumping. If multiple functions are selected, the order of priority from highest to lowest is PIX OR/NOR Control 1
Bit[0] to Bit [7], then PIX OR/NOR Control 2 Bit[0] to Bit[7] (i.e PIX OR/NOR Control 1 Bit[7] has a higher priority
on the PIX5 output than PIX OR/NOR Control 2 Bit[0] or Bit[2]).
For reference purposes, the normal, unmodified PIX generator outputs are named pix1 through pix8 (lower case)
and the final signal prior to the CLK pins are named PIX1 through PIX8 (upper case).
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0 No effect (default); 1 PIX5 = ~(pix5 || pix6)
0 No effect (default); 1 PIX6 = (pix5 || pix6)
PIX
OR/NOR
Control 2
0000
0000
4
1 0001
0 No effect (default); 1 PIX5 = ~(pix4 || pix5 || pix6)
0 No effect (default); 1 PIX6 = (pix4 || pix5 || pix6)
0 No effect (default); 1 PIX7 = ~(pix3 || pix7 || pix8)
0 No effect (default); 1 PIX8 = (pix3 || pix7 || pix8)
0 No effect (default); 1 PIX7 = ~(pix7 || pix8)
0 No effect (default); 1 PIX8 = (pix7 || pix8)
Page
Register
0000
0000
Used to select desired page of registers being accessed.
4
5
1 1111
0 0000
[7:0]
Registers below are in register page 5.
PIX1/SH
On
Guardband
s
0000
1111
[7:0] PIX1 on guardband. Number of pixel periods from end of SH pulse to start of PIX1.
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
PIX1/SH
Off
Guardband
s
0000
0111
5
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
[7:0] PIX1 off guardband. Number of pixel periods before start of SH pulse that PIX1 stops.
[7:0] PIX2 on guardband. Number of pixel periods from end of SH pulse to start of PIX2.
[7:0] PIX2 off guardband. Number of pixel periods before start of SH pulse that PIX2 stops.
[7:0] PIX3 on guardband. Number of pixel periods from end of SH pulse to start of PIX3.
[7:0] PIX3 off guardband. Number of pixel periods before start of SH pulse that PIX3 stops.
[7:0] PIX4 on guardband. Number of pixel periods from end of SH pulse to start of PIX4.
[7:0] PIX4 off guardband. Number of pixel periods before start of SH pulse that PIX4 stops.
[7:0] PIX5 on guardband. Number of pixel periods from end of SH pulse to start of PIX5.
[7:0] PIX5 off guardband. Number of pixel periods before start of SH pulse that PIX5 stops.
[7:0] PIX6 on guardband. Number of pixel periods from end of SH pulse to start of PIX6.
PIX2/SH
On
Guardband
s
0000
1111
5
5
5
5
5
5
5
5
5
PIX2/SH
Off
Guardband
s
0000
0111
PIX3/SH
On
Guardband
s
0000
1111
PIX3/SH
Off
Guardband
s
0000
0111
PIX4/SH
On
Guardband
s
0000
1111
PIX4/SH
Off
Guardband
s
0000
0111
PIX5/SH
On
Guardband
s
0000
1111
PIX5/SH
Off
Guardband
s
0000
0111
PIX6/SH
On
Guardband
s
0000
1111
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Table 16. (continued)
Address
(Binary)
Register
Title
Default
(Binary)
Page
Bit(s)
Description
PIX6/SH
Off
Guardband
s
0000
0111
5
0 1011
[7:0] PIX6 off guardband. Number of pixel periods before start of SH pulse that PIX6 stops.
[7:0] PIX7 on guardband. Number of pixel periods from end of SH pulse to start of PIX7.
[7:0] PIX7 off guardband. Number of pixel periods before start of SH pulse that PIX7 stops.
[7:0] PIX8 on guardband. Number of pixel periods from end of SH pulse to start of PIX8.
[7:0] PIX8 off guardband. Number of pixel periods before start of SH pulse that PIX8 stops.
PIX7/SH
On
Guardband
s
0000
1111
5
5
5
5
0 1100
0 1101
0 1110
0 1111
PIX7/SH
Off
Guardband
s
0000
0111
PIX8/SH
On
Guardband
s
0000
1111
PIX8/SH
Off
Guardband
s
0000
0111
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Changes from Original (October 2006) to Revision A
Page
•
Added content to complete full data sheet. .......................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2014
PACKAGING INFORMATION
Orderable Device
LM98714BCMT/NOPB
LM98714BCMTX/NOPB
LM98714CCMT/NOPB
LM98714CCMTX
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
DGG
48
48
48
48
48
38
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Call TI
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
LM98714
BCMT
ACTIVE
ACTIVE
NRND
DGG
DGG
DGG
DGG
1000
38
Green (RoHS
& no Sb/Br)
0 to 70
LM98714
BCMT
Green (RoHS
& no Sb/Br)
0 to 70
LM98714
CCMT
1000
1000
TBD
0 to 70
LM98714
CCMT
LM98714CCMTX/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
0 to 70
LM98714
CCMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jan-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM98714BCMTX/NOPB TSSOP
LM98714CCMTX TSSOP
LM98714CCMTX/NOPB TSSOP
DGG
DGG
DGG
48
48
48
1000
1000
1000
330.0
330.0
330.0
24.4
24.4
24.4
8.6
8.6
8.6
13.2
13.2
13.2
1.6
1.6
1.6
12.0
12.0
12.0
24.0
24.0
24.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jan-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM98714BCMTX/NOPB
LM98714CCMTX
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
48
48
48
1000
1000
1000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
LM98714CCMTX/NOPB
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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