LMG1020YFFR [TI]
具有 60MHz/1ns 速度的 5V、7A/5A 低侧 GaN 驱动器 | YFF | 6 | -40 to 125;
| 型号： | LMG1020YFFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 60MHz/1ns 速度的 5V、7A/5A 低侧 GaN 驱动器 | YFF | 6 | -40 to 125 驱动 接口集成电路 驱动器 |
| 文件： | 总27页 (文件大小：1833K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
适用于 1ns 脉宽应用的 LMG1020 5V 7A/5A 低侧 GaN 和 MOSFET 驱动
器
1 特性
3 说明
1
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•
•
•
•
•
•
•
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用于 GaN 和硅质 FET 的低侧、超快栅极驱动器
LMG1020 器件是一款单通道低侧驱动器，专为在高速
应用 （包括 LiDAR、飞行时间、面部识别和任何涉及
低侧驱动器的功率转换器）中驱动 GaN FET 和逻辑电
平 MOSFET 而设计。LMG1020 设计简约，可实现
2.5 纳秒的极快传播延迟和 1 纳秒的最小脉冲宽度。通
过分别在栅极与 OUTH 和 OUTL 之间连接外部电阻
器，可针对上拉和下拉沿来独立调节驱动强度。
1ns 最小输入脉冲宽度
工作频率高达 60MHz
传播延迟：典型值 2.5ns，最大值 4.5ns
典型上升和下降时间 400ps
7A 峰值拉电流和 5A 峰值灌电流
5V 电源电压
UVLO 和过热保护
该驱动器 提供 过载或故障情况下的欠压锁定 (UVLO)
和过热保护 (OTP)。
0.8mm × 1.2mm WCSP 封装
2 应用
LMG1020 的 0.8mm × 1.2mm WCSP 封装可最大限度
地降低栅极回路电感并最大限度地提高高频功率密度
要求。
•
•
•
•
•
•
•
激光雷达
飞行时间激光驱动器
面部识别
器件信息(1)
E 类无线充电器
VHF 谐振电源转换器
基于 GaN 的同步整流器
扩增实境
器件型号
LMG1020
封装
WCSP (6)
封装尺寸（标称值）
0.80mm × 1.20mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化的激光雷达 (LiDAR) 驱动器级图
+5 V
Vbus
LMG1020
R1
R2
OUTH
VDD
IN+
OUTL
PWM
EN
GaN
INœ
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSD45
LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
Power Supply Recommendations...................... 15
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics ............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 器件和文档支持 ..................................................... 18
11.1 文档支持 ............................................................... 18
11.2 接收文档更新通知 ................................................. 18
11.3 社区资源................................................................ 18
11.4 商标....................................................................... 18
11.5 静电放电警告......................................................... 18
11.6 术语表 ................................................................... 18
12 机械、封装和可订购信息....................................... 18
7
4 修订历史记录
Changes from Original (June 2018) to Revision B
Page
•
已更改 将图 1 输入结构中的“与非门”更改为“与门” ................................................................................................................. 1
2
Copyright © 2018, Texas Instruments Incorporated
LMG1020
www.ti.com.cn
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
5 Pin Configuration and Functions
YFF Package
6-Ball WCSP
Top View
OUTH
VDD
A2
A1
OUTL
GND
B2
C2
B1
C1
IN+
IN-
0.8mm
Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
IN+
NO.
B1
—
Ground
C1
C2
I
I
Positive logic-level input
Negative logic-level input
IN–
Pulldown gate drive output. Connect through an optional resistor to the target transistor’s
gate
OUTL
B2
O
OUTH
VDD
A2
A1
O
I
Pullup gate drive output. Connect through a resistor to the target transistor’s gate
Input voltage supply. Decouple through a small size, low inductance capacitor to GND
Copyright © 2018, Texas Instruments Incorporated
3
LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.75
UNIT
V
VDD
VIN
Supply voltage
IN+, IN- pin voltage
OUTH, OUTL pin voltage
Storage Temperature
Operating Temperature
-0.3
-0.3
-55
-40
VDD + 0.3
5.75
V
VOUT
TSTG
TJ
V
150
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.75
0
NOM
MAX
5.4
UNIT
V
VDD
VINx
TJ
Supply voltage
5
IN+ or IN- input voltage
Operating Temperature
VDD
125
V
-40
°C
6.4 Thermal Information
SN1020
THERMAL METRIC(1)
YFF (WCSP)
6 PINS
133.6
1.7
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
38.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.5
YJB
38.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
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LMG1020
www.ti.com.cn
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
6.5 Electrical Characteristics
over operating free-air temperature range (VDD=5V unless otherwise noted)
PARAMETER
DC Characteristics
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVDD, Q
VDD Quiescent Current
VDD Operating Current(1)
IN+ = IN- = 0 V
75
µA
mA
mA
fsw = 30 MHz, 2 Ω, 0.1 pF load
fsw = 30 MHz, 2 Ω, 100 pF load
40
51
IVDD, op
VDD,
Under-voltage Lockout
UVLO Hysteresis
VDD rising
4.06
4.19
85
4.33
V
UVLO
ΔVDD,
UVLO
mV
Over temperature shutdown, rising edge
threshold
TOTP
170
18
°C
°C
ΔTOTP
Over temperature hysteresis
Input DC Characteristics
VIH
IN+, IN- high threshold
1.7
1.1
2.6
1.8
1
V
V
VIL
IN+, IN- low threshold
VHYST
RIN+
RIN-
CIN
IN+, IN- hysteresis
0.5
V
Positive input pull-down resistance
Negative input pull-up resistance
Input pin capacitance(1)
To GND
to VDD
100
100
150
150
1.3
250
250
kΩ
kΩ
pF
To GND
Output DC Characteristics
VOL OUTL voltage
VDD-VOH OUTH voltage
IOH
Peak source current(1)
IOL
Peak sink current(1)
IOUTL = 100 mA, IN+= IN- = 0 V
IOUTH = 100 mA, IN+= 5 V, IN- = 0 V
VOUTH = 0 V, IN+= 5 V, IN- = 0 V
VOUTL = 5 V, IN+= IN- = 0 V
36
50
mV
mV
A
7
5
A
(1) Insured by design
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5
LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
6.6 Switching Characteristics
over operating free-air temperature range (VDD=5V unless otherwise noted)
PARAMETER
Startup Time, VDD rising above UVLO
ULVO falling
TEST CONDITIONS
MIN
TYP
40
MAX
UNIT
µs
IN- = GND, IN+ = VDD , VDD rising to
4.2V to OUTH rising
tstart
70
tshut-off
IN- = GND, IN+ = VDD , VDD falling
below 4.1V to OUTH falling
1
1.9
3.1
µs
tpd, r
tpd, f
Δtpd
trise
tfall
Propagation delay, turn on
Propagation delay, turn off
IN- = 0 V, IN+ to OUTH, 100 pF load
IN- = 0 V, IN+ to OUTL, 100 pF load
1.5
1.8
2.5
2.6
230
375
350
1
4.1
4.3
ns
ns
ps
ps
ps
ns
Pulse positive distrortion (tpd, f - tpd, r
Output rise time
)
603
0Ω series 100 pF load(1)
0Ω series 100 pF load(1)
0Ω series 100 pF load(1)
Output fall time
tmin
Minimum input pulse width
(1) rise and fall calulated as a 20% to 80%
6
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LMG1020
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ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
6.7 Typical Characteristics
51
50
49
48
47
100
90
80
70
60
50
40
30
20
10
0
T=-40°C
T=0°C
T=25°C
T=85°C
T=125°C
0
5
10 15 20 25 30 35 40 45 50 55 60
Frequency (MHz)
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Figu
Figu
图 1. IVDD, op vs Frequency With 2 Ω Series 100 pF Load
图 2. IVDD, op vs Temperature At 30MHz With 2 Ω series 100
pF Load
48
3.4
3.3
3.2
3.1
3
46
44
42
40
2.9
2.8
2.7
2.6
2.5
tpd, r
tpd, f
2.4
2.3
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Figu
Figu
图 3. Quiescent Current vs Temperature
图 4. Propagation Delay vs Temperature
375
Tfall (ns)
Trise (ns)
372.5
370
367.5
365
362.5
360
357.5
355
352.5
350
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Figu
图 5. Rise And Fall Time vs Temperature With 0 Ω Series 100 pF Load
版权 © 2018, Texas Instruments Incorporated
7
LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
LMG1020 is a high-performance low-side 5-V gate driver for GaN and logic-level silicon power transistors. While
the LMG1020 is designed for high-speed applications, such as wireless power transmission and LiDAR
applications, it is a high-performance solution for any other low-side driving applications.
The LMG1020 is optimized to provide the lowest propagation delay through the driver to the power transistor.
LMG1020 is in a small 0.8×1.2mm WCSP ball-grid array package in order to minimize its parasitic inductance.
This low inductance design helps achieve high current, low ringing performance in very high frequency operation
when driving power FETs.
7.2 Functional Block Diagram
1
3
6
5
2
VDD
IN+
OUTH
OUTL
GND
UVLO
OTP
VDD
INœ
4
7.3 Feature Description
7.3.1 Input Stage
The input stage features two Schmitt-triggers at the pins IN+ and IN– to reduce sensitivity to noise on the inputs.
IN+ signal and the inverted IN– signal are both sent to an AND gate. IN+ is connected with a pull-down resistor
while IN– is connected with a pull-up resistor to prevent unintended turnon. The output signal will follow the
difference between IN+ and IN–. Both IN+ and IN– are single ended inputs, and these two pins cannot be used
as a differential input pair.
7.3.2 Output Stage
LMG1020 provides 7-A source, 5-A sink (asymmetrical drive) peak-drive current capability, and features a split
output configuration. The OUTH and OUTL outputs of the LMG1020 allow the user to use independent resistors
connecting to the gate. The two resistors allow the user to independently adjust the turnon and turnoff drive
strengths to control slew rate and EMI, and to control ringing on the gate signal. For GaN FETs, controlling
ringing is important to reduce stress on the GaN FET and driver. The output stage OUTL is also pulled down in
undervoltage condition, which prevents the unintended charge accumulation of device Ciss.
7.3.3 VDD and undervoltage lockout
LMG1020 features nominal 5V and maximum 5.25V of supply voltage, and its absolute maximum supply voltage
is 5.75 V. In the design, it is recommended to limit the variability of the power supply to be within 5% (0.25V),
and the overshoot voltage during switching transient not to exceed the absolute maximum voltage. Refer to
Section VDD and Overshoot for more the detailed design guide.
LMG1020 also features internal undervoltage lockout (UVLO) to protect the driver and circuit in case of fault
conditions. The UVLO point is setup between 4.1V and 4.2V with a hysteresis of 85mV. This UVLO level is
specifically designed to guarantee that GaN power devices can be switched at a low RDS(ON) region. During
UVLO condition, the OUTL is pulled down to ground.
8
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LMG1020
www.ti.com.cn
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
Feature Description (接下页)
7.3.4 Overtemperature Protection (OTP)
LMG1020 features overtemperature protection (OTP) function by having a rising edge trigger point at around
170°C. With a hysteresis of 20°C, the device can restart to operate when junction temperature is below 150°C.
7.4 Device Functional Modes
表 1. Truth Table
IN–
L
IN+
L
OUTH
OPEN
H
OUTL
L
L
H
OPEN
H
L
OPEN
OPEN
L
L
H
H
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9
LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To operate GaN transistors at very high switching frequencies and to reduce associated switching losses, a
powerful gate driver is employed between the PWM output of controller and the gates of the GaN transistor.
Also, gate drivers are indispensable when the outputs of the PWM controller do not meet the voltage or current
levels needed to directly drive the gates of the switching devices. With the advent of digital power, this situation
is often encountered because the PWM signal from the digital controller is often a 3.3 V logic signal, which
cannot effectively turn on a power switch. A level-shift circuit is needed to boost the 3.3 V signal to the gate-drive
voltage (such as 5 V) in order to fully turn on the power device and minimize conduction losses.
Gate drivers effectively provide the buffer-drive functions. Gate drivers also address other needs such as
minimizing the effect of high-frequency switching noise (by placing the high-current driver IC physically close to
the power switch), reducing power dissipation and thermal stress in controllers by moving gate charge power
losses from the controller into the driver.
The LMG1020 is a 60-MHz low-side gate driver for enhancement mode GaN FETs and Si FETs in a single-
ended configuration. The split-gate outputs with strong source and sink capability provides flexibility to adjust the
turnon and turnoff strength independently. As a low side driver, LMG1020 can be used in a variety of
applications, including different power converters, LiDAR, time-of-flight laser drivers, class-E wireless chargers,
synchronous rectifiers, and augmented reality. LMG1020 can also be used as a high frequency low current laser
diode driver, or as a signal buffer with very fast rise/fall time.
8.2 Typical Application
The LMG1020 is designed to be used with a single low-side, ground-referenced GaN or logic-level Si FET, as
shown in 图 6. Independent gate drive resistors, R1 and R2, are used to independently control the turnon and
turnoff drive strengths, respectively. For fast and strong turnoff, R2 can be shorted and OUTL directly connected
to the transistor’s gate. For symmetric drive strengths, it is acceptable to short OUTH and OUTL and use a single
gate-drive resistor.
TI recommends using at least a 2 Ω resistor at each OUTH and OUTL to avoid voltage overstress due to
inductive ringing. Ringing overshoot must not exceed the maximum absolute supply voltage.
For applications requiring smaller resistance values, contact TI E2E for guidance.
+5 V
Vbus
LMG1020
R1
R2
OUTH
OUTL
VDD
IN+
PWM
EN
GaN
INœ
GND
图 6. Typical Implementation of a Circuit
10
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LMG1020
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ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
Typical Application (接下页)
8.2.1 Design Requirements
When designing a multi-MHz (or nano-second pulse) application that incorporates the LMG1020 gate driver and
GaN power FETs, some design considerations must be evaluated first to make the most appropriate selection.
Among these considerations are layout optimization, circuit voltages, passive components, operating frequency,
and controller selection.
8.2.2 Detailed Design Procedure
8.2.2.1 Handling Ground Bounce
For the best switching performance and gate loop with lowest parasitics, it is recommended to connect the
ground return pin of LMG1020 as close as possible to the source of the low-side FET in a low inductance
manner. However, doing so can cause the ground of LMG1020 to bounce relative to the system or controller
ground and lead to erroneous switching logic on the input so as mis-turn on/off on the output.
First of all, LMG1020 has input hysteresis built into the input buffers to help counteract this effect. The maximum
di/dt allowed to prevent the input voltage transient from exceeding the input hysteresis is given by 公式 1
dis VHYST
=
dt
LRS
where
•
•
•
LRS is the inductance between FET source and ground,
VHYST is the hysteresis of the input pin,
and dis/ Δt is the maximum allowed current slew rate.
(1)
For an assumed parasitic inductance of 0.5 nH and a minimum hysteresis of 0.5 V, the maximum slew rate is 1
A/ns. Many applications would exhibit higher current slew rates, up to the 10 A/ns range, which would make this
approach impractical. The stability of this approach can be improved by using the IN– input for the PWM signal
and locally tying IN+ to VDD. By using the inverting input, the transient voltage applied to the input pin reinforces
the PWM signal in a positive feedback loop. While this approach would reduce the probability of false pulses or
oscillation, the transient spikes due to high di/dt may overly stress the inputs to the LMG1020. A current-limiting,
100 Ω resistor can be placed right before the IN– input to limit excessive current spikes in the device.
Secondly, for moderate ground-bounce cases, a simple R-C filter can be built with a simple resistor in series with
the inputs. By utilizing the input capacitance of LMG1020, the resistor could be close to its input pin. The addition
of a small capacitor on the input as supplement can also be helpful. A small time constant of the R-C filter can
can enough to filter out high frequency noises. This solution is acceptable for moderate cases in applications
where extra delay is acceptable and the pulse width is not extremely short such as 1ns range.
For more extreme cases, or where no delay is tolerable while pulse width is extremely short, using a common-
mode choke provides the best results.
One example application where ground-bounce is particularly challenging is when using a current sense resistor.
In configuration A LMG1020 ground is connected to the source of GaN FET, while the controller ground is
connected to the other side of the current sense resistor as shown in 图 7. Due to the fast switching and very fast
current slew rates, the high ground potential bounce induced by inductance of the sense resistor can disrupt the
operation of the circuit or even damage the part. To prevent this, a common-mode choke can be used for IN+
and IN–, respectively. Resistors can also added to the signal output line before LMG1020 depending on the input
signal pulse width to provide additional RC filtering. 图 9 presents the schematic using approach A with the
preferred filtering method. Approach B as 图 8 places the current sense resistor within the gate drive loop path.
In this case, the LMG1020 GND pin is connected to the signal ground, and with good ground plane connection,
the ground bounce issue can be less severe than approach A. However, the inductance of the current sense
resistor adds common-source inductance to the gate drive loop. The voltage generated across this parasitic
inductance will subtract from the gate-drive voltage of the FET, slowing down the turnon and turnoff di/dt of the
FET, or even cause mis-turn on and off. Additional gate resistance will have to be added to ensure the loop is
stable and ring-free. The slower rise may negate the advantage of the fast switching of the GaN FET and may
cause additional losses in the circuit. Therefore, this approach is not recommended.
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LMG1020
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Typical Application (接下页)
(a)
(b)
R1
R1
R2
OUTH
OUTH
OUTL
GND
R2
OUTL
GaN
RS
GaN
RS
GND
LMG1020
LMG1020
图 7. Source Resistor Current Sense A
图 8. Source Resistor Current Sense B
Configuration
Configuration
5V
LMG1020
R1
VDD
IN+
IN-
OUTH
OUTL
GND
RC filter
R2
GaN
RS
CM choke
Controller
图 9. Filtering For Ground Bounce Noise Handling When Using LMG1020
8.2.2.2 Creating Nanosecond Pulse With LMG1020
LMG1020 can be used to drive pulses of nano seconds duration on to a capacitive load. LMG1020 can be driven
with a equivalently short pulse on one input pin. However, this takes a sufficiently strong digital driver and careful
consideration of the routing parasitics from digital output to input of LMG1020. Two inputs and included AND
gate in LMG1020 provide an alternate method to create a short pulse at the LMG1020 output. Starting with both
IN+ and IN– at low, taking IN+ high will cause the output to go high. Now if IN– is taken high as well, output will
be pulled low. So a digital signal and its delayed version can be applied to IN+ and IN– respectively to create a
12
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LMG1020
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ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
Typical Application (接下页)
pulse at the output with width corresponding to the delay between the signals, as shown in 图 10. The delay can
be digitally controlled in the nanosecond range. This method alleviates the requirements for driving the input of
LMG1020. If a separate delayed version of the digital signal is not available, a RC delay followed by a buffer can
be used to derive the second signal. Optionally, if LMG1020 must be driven with a single short duration pulse,
that pulse can itself be generated using another LMG1020 by the above method to meet drive requirements.
IN+
IN-
OUT
图 10. Timing Diagram To Create Short Pulses
8.2.3 VDD and Overshoot
Fast switching with high current is prone to ringing with parasitic inductances, including those on PCB traces.
Overshoot associated with such ringing transients need to be evaluated and controlled as a part of the PCB
design process to limit device stress. The parameters affecting stress are how high the overshoot is above the
absolute maximum specification and the ratio of overshoot duration to the switching time period. Recommended
design practice is to limit the overshoots to the absolute maximum pin voltages. This is accomplished with carful
PCB layout to minimize parasitic inductances, choice of components with low ESL and addition of series
resistance to limit rise times. For large overshoots, limiting the variability of the power supply may be required.
For example, 0.5V of overshoot will be permissible with a maximum recommended supply of 5.25 V (5%
variability); however, for larger overshoots, a supply with lower variability will be preferred.
8.2.4 Operating at Higher Frequency
With fast rise/fall time, and capability of achieving 1 ns pulse width, depending on the capacitive load condition,
the operating frequency of LMG1020 can be increased in a burst manner. In conditions which requires very high
frequency pulsing, a pulse train with certain period of pause between each burst can be adopted to avoid
overheat of the device. This will help maintain the RMS output current similar as lower frequency operation but
boost the transient frequency to very high. In addition, higher decoupling capacitance will be needed to supply
high frequency charging of the capacitive load.
版权 © 2018, Texas Instruments Incorporated
13
LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
Typical Application (接下页)
8.2.5 Application Curves
图 12. 90 ns Pulse from Function Generator Yielding 1.5 ns
Pulse On The Input (Cyan) And Gate (Blue) After Pulse
Shortening
图 11. 90 ns Pulse from Function Generator Yielding 15 ns
Pulse On The Input (Cyan) And Gate (Blue) After Pulse
Shortening
图 13. 1.2 ns Gate Pulse Yielding 1.5 ns 30V Into 1 Ω Pulse
(500MHz Scope)
图 14. VDS for 1.5 ns Pulse With 40V of Bus Voltage
图 11 and 图 12 are the waveforms showing the pulse short pulse generation and input/output pulses. The 90ns
long pulse (in green color) and its delayed signal are sent through an AND gate, which outputs a short pulse
signal as the input of LMG1020. The output signal (in blue color) follows the input (in cyan color) with certain
propagation delay. An output pulse short as 1.5 ns can be obtained as 图 12.
图 13 is taken with a 500MHz oscilloscope and shows typical operation waveforms, including the input logic
gating signal (cyan), gate signal (blue), and drain to source signal (pink) of the switching GaN FET. On the drain
waveform of the FET, it is possible to see a 20V overshoot. This is due to the inductance in the power loop. Vg
seems to be oscillating, but this is caused by pickup noise, which is inevitable even when using a spring ground
connection.
图 14 shows the waveform of drain to source voltage of a FET driven by LMG1020 with 1.5ns pulse width and
300ps fall time, which drives maximum 60A current at 40V bus voltage.
14
版权 © 2018, Texas Instruments Incorporated
LMG1020
www.ti.com.cn
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
9 Power Supply Recommendations
A low-ESR/ESL ceramic capacitor must be connected close to the IC, between VDD and GND pins to support the
high peak current being drawn from VDD during turnon of the FETs. It is most desirable to place the VDD
decoupling capacitor on the same side of the PC board as the driver. The inductance of via holes can impose
excessive ringing on the IC pins.
TI recommends the use of a three-terminal capacitor connecting in shunt-through manner to achieve the lowest
ESL and best transient performance. This capacitor can be placed as close as possible to the IC, while another
capacitor in larger capacitance can be placed closely to the three-terminal cap to supply enough charge but with
slightly lower bandwidth. As a general practice, the combination of a 0.1 µF of 0402 or feed-through capacitor
(closest to LMG1020) and a 1 µF 0603 capacitor is recommended.
版权 © 2018, Texas Instruments Incorporated
15
LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
The layout of the LMG1020 is critical to its performance and functionality. The LMG1020 is available in a WCSP
ball-grid array package, which enables low-inductance connection to a BGA-type GaN FET. 图 15 shows the
recommended layout of the LMG1020 with a ball-grid array GaN FET. 图 16 presents a layout of LMG1020 with
a 0.1 µF feed-through capacitor and a larger 1uF capacitor.
A four-layer or higher layer count board is required to reduce the parasitic inductances of the layout to achieve
suitable performance. To minimize inductance and board space, resistors and capacitors in the 0201 package
are used here. The gate drive power loss must be calculated to ensure an 0201 resistor will be able to handle
the power level.
10.1.1 Gate Drive Loop Inductance and Ground Connection
A compact, low-inductance gate-drive loop is essential to achieving fast switching frequencies with the LMG1020.
The LMG1020 should be placed as close to the GaN FET as possible, with gate drive resistors R1 and R2
immediately connecting OUTH and OUTL to the FET gate. Large traces must be used to minimize resistance
and parasitic inductance.
To minimize gate drive loop inductance, the source return should be on layer 2 of the PCB, immediately under
the component (top) layer. Vias immediately adjacent to both the FET source and the LMG1020 GND pin
connect to this plane with minimal impedance. Finally, take care to connect the GND plane to the source power
plane only at the FET to minimize common-source inductance and to reduce coupling to the ground plane.
10.1.2 Bypass Capacitor
The VDD power terminal of the LMG1020 must by bypassed to ground immediately adjacent to the IC. Because
of the fast gate drive of the IC, the placement and value of the bypass capacitor is critical. The bypass capacitor
must be place on the top layer, as close as possible to the IC, and connected to both VDD and GND using large
power planes. This bypass capacitor has to be at least a 0.1 µF, up to 1 µF, with temperature coefficient X7R or
better. Recommended body types are Low Inductance Chip Capacitor (LICC), Inter-Digitated Capacitor (IDC),
Feed-through, and LGA. Finally, an additional 1 μF capacitor (not shown in 图 15) must be placed as close to the
IC as practical.
10.2 Layout Example
图 15 presents a typical layout of LMG1020 with a 0402 decoupling capacitor C1, which is placed as close as
possible to LMG1020. The ground return at GaN FET Kelvin source immediately flows through a via to the
closest inner layer, and overlaps with the top layer traces.
图 16 presents a layout of LMG1020 with a 0.1 µF feed-through capacitor (C1) and a larger 1uF capacitor (C3)
for decoupling. In this design, the feed-through capacitor C1 is placed in a shunt-through manner for lower noise
decoupling, and C3 is placed next to C1. 0201 resistors are used at the output of LMG1020, which brings lower
parasitic inductance than 0402 package.
16
版权 © 2018, Texas Instruments Incorporated
LMG1020
www.ti.com.cn
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
Layout Example (接下页)
图 15. Typical LMG1020 Layout With Ball-Grid GaN FET And 0402 Decoupling Capacitor
图 16. Typical Layout Of LMG1020 And A Feed-Through Decoupling Capacitor With A Capacitor Load
版权 © 2018, Texas Instruments Incorporated
17
LMG1020
ZHCSHN8B –FEBRUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
使用 LMG1020-EVM 纳秒 LiDAR EVM (SNOU150)
《LMG1020 PSpice 瞬态模型》(SNOM618)
《LMG1020 TINA-TI 参考设计》(SNOM619)
《LMG1020 TINA-TI 瞬态 Spice 模型》(SNOM620)
《LMG1020EVM Altium 设计文件》(SNOR025)
11.2 接收文档更新通知
如需接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
18
版权 © 2018, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMG1020YFFR
LMG1020YFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
6
6
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
AT
AT
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Oct-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMG1020YFFR
LMG1020YFFT
DSBGA
DSBGA
YFF
YFF
6
6
3000
250
180.0
180.0
8.4
8.4
0.96
0.96
1.36
1.36
0.69
0.69
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Oct-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMG1020YFFR
LMG1020YFFT
DSBGA
DSBGA
YFF
YFF
6
6
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0006
DSBGA - 0.625 mm max height
SCALE 10.500
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.05 C
0.30
0.12
BALL TYP
0.4 TYP
C
B
SYMM
0.8
D: Max = 1.285 mm, Min =1.225 mm
E: Max = 0.885 mm, Min =0.825 mm
TYP
0.4 TYP
A
0.3
6X
2
1
0.2
SYMM
0.015
C A B
4223785/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0006
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
6X ( 0.23)
(0.4) TYP
1
2
A
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
EXPOSED
METAL
EXPOSED
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223785/A 06/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0006
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
2
6X ( 0.25)
(0.4) TYP
(R0.05) TYP
1
A
B
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:35X
4223785/A 06/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
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