LMK03002ISQ/NOPB [TI]

具有集成 VCO 的 1566 至 1724MHz、800FS RMS 抖动、精密时钟调节器 | RHS | 48 | -40 to 85;


型号：	LMK03002ISQ/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有集成 VCO 的 1566 至 1724MHz、800FS RMS 抖动、精密时钟调节器 \| RHS \| 48 \| -40 to 85 时钟外围集成电路晶体调节器
文件：	总39页 (文件大小：547K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK03002

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SNAS414E –AUGUST 2007–REVISED APRIL 2013

LMK03002 /LMK03002C Precision Clock Conditioner with Integrated VCO

Check for Samples: LMK03002

FEATURES

TARGET APPLICATIONS

•

Integrated VCO with Very Low Phase Noise

Floor

•

Data Converter Clocking

Networking, SONET/SDH, DSLAM

Wireless Infrastructure

Medical

•

Integrated Integer-N PLL with Outstanding

Normalized Phase Noise Contribution of

-224 dBc/Hz

Test and Measurement

Military / Aerospace

•

Clock Generator Performance (10 Hz - 20 MHz)

–

LMK03002C: 200 fs RMS Jitter

Jitter Cleaner Performance Grade (12 kHz to

20 MHz)

DESCRIPTION

The

LMK03002/LMK03002C

precision

clock

conditioners combine the functions of jitter

cleaning/reconditioning, multiplication, and distribution

of a reference clock. The devices integrate a Voltage

Controlled Oscillator (VCO), a high performance

Integer-N Phase Locked Loop (PLL), a partially

integrated loop filter, and four LVPECL clock output

distribution blocks.

–

LMK03002: 800 fs RMS Jitter

LMK03002C: 400 fs RMS Jitter

•

VCO Frequency: 1566 to 1724 MHz

Clock Output Frequency Range of 1 to 862

MHz

•

4 LVPECL Clock Outputs

The VCO output is optionally accessible on the Fout

port. Internally, the VCO output goes through a VCO

Divider to feed the various clock distribution blocks.

Partially Integrated Loop Filter

Dedicated Divider and Delay Blocks on Each

Clock Output

Each

clock

distribution

block

includes

•

Pin Compatible Family of Clocking Devices

3.15 to 3.45 V Operation

programmable divider,

phase synchronization

circuit, a programmable delay, a clock output mux,

and an LVPECL output buffer. This allows multiple

integer-related and phase-adjusted copies of the

reference to be distributed to four system

components.

Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)

The clock conditioners come in a 48-pin WQFN

package and are footprint compatible with other

clocking devices in the same family.

CLKout0

Recovered

Serializer/

Deserializer

—dirty“ clock or

clean clock

LMK0300xx

CLKout1

CLKout2

CLKout3

Precision Clock

Conditioner

OSCin

LMX2531

PLL+VCO

FPGA

Fout

> 1 Gsps

Multiple —clean“ clocks at

different frequencies

DAC

ADC

Figure 1. System Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMK03002

SNAS414E –AUGUST 2007–REVISED APRIL 2013

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Functional Block Diagram

Partially

Integrated

Loop Filter

Internal

VCO

OSCin

OSCin*

R Divider

Phase

Detector

Fout

N Divider

VCO

Divider

Distribution

Path

CLKout0

CLKout0*

Divider

Mux

Delay

CLK

mWire

Port

Control

Registers

DATA

CLKout1

CLKout1*

Divider

CLKout2

CLKout2*

GOE

Device

Control

SYNC*

CLKout3

CLKout3*

Clock Buffers

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Connection Diagram

GND

Fout

Bias

Vcc1

CLKuWire

Vcc10

CPout

Vcc9

Vcc8

OSCin*

OSCin

SYNC*

Vcc7

GND

DATAuWire

LEuWire

Top Down View

Vcc2

LDObyp1

LDObyp2

GOE

DAP

Figure 2. 48-Pin WQFN Package

PIN DESCRIPTIONS

Pin #

1, 25

Pin Name

I/O

Description

GND

Ground

Fout

Internal VCO Frequency Output

3, 8, 13, 16, 19, 22, 26,

30, 31, 33, 37, 40, 43, 46

Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8,

Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14

Power Supply

CLKuWire

DATAuWire

LEuWire

MICROWIRE Clock Input

MICROWIRE Data Input

MICROWIRE Latch Enable Input

7, 14, 15, 17, 18, 20, 21,

23, 24, 34, 35

No Connection to these pins

9, 10

LDObyp1, LDObyp2

GOE

LDO Bypass

Global Output Enable

Lock Detect and Test Output

Global Clock Output Synchronization

Oscillator Clock Input; Must be AC coupled

Charge Pump Output

SYNC*

28, 29

OSCin, OSCin*

CPout

Bias

Bias Bypass

38, 39

41, 42

44, 45

47, 48

DAP

CLKout0, CLKout0*

CLKout1, CLKout1*

CLKout2, CLKout2*

CLKout3, CLKout3*

DAP

LVPECL Clock Output 0

LVPECL Clock Output 1

LVPECL Clock Output 2

LVPECL Clock Output 3

Die Attach Pad is Ground

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings^(1)(2)(3)

Parameter

Symbol

V_CC

V_IN

Ratings

-0.3 to 3.6

-0.3 to (V_CC+ 0.3)

-65 to 150

+260

Units

Power Supply Voltage

Input Voltage

Storage Temperature Range

Lead Temperature (solder 4 s)

Junction Temperature

T_STG

T_L

°C

T_J

125

(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD

protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

Recommended Operating Conditions

Parameter

Symbol

Min

-40

Typ

Max

Units

°C

Ambient Temperature

T_A

Power Supply Voltage

V_CC

3.15

3.3

3.45

Package Thermal Resistance

Package

θ_JA

27.4° C/W

θ_{J-PAD (Thermal Pad)}

(1)

48-Lead WQFN

5.8° C/W

(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These

vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in

the board layout.

(1)

Electrical Characteristics

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values

represent most likely parametric norms at Vcc = 3.3 V, T_A= 25 °C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Current Consumption

Entire device; CLKout0 & CLKout3 enabled in Bypass

Mode

175

I_CC

Power Supply Current⁽²⁾

Power Down Current

Entire device; All Outputs Off (no emitter resistors

placed)

I_CCPD

POWERDOWN = 1

Reference Oscillator

Reference Oscillator Input Frequency Range for Square

Wave

f_OSCinsquare

V_OSCinsquare

200

1.6

MHz

Vpp

AC coupled; Differential (V_OD

)

Square Wave Input Voltage for OSCin and OSCin*

0.2

(1) The Electrical Characteristics table lists ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) See CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS for more current consumption / power dissipation

calculation information.

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Electrical Characteristics ⁽¹⁾(continued)

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values

represent most likely parametric norms at Vcc = 3.3 V, T_A= 25 °C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

PLL

f_COMP

Phase Detector Frequency

MHz

V_CPout= Vcc/2, PLL_CP_GAIN = 1x

V_CPout= Vcc/2, PLL_CP_GAIN = 4x

V_CPout= Vcc/2, PLL_CP_GAIN = 16x

V_CPout= Vcc/2, PLL_CP_GAIN = 32x

V_CPout= Vcc/2, PLL_CP_GAIN = 1x

V_CPout= Vcc/2, PLL_CP_GAIN = 4x

V_CPout= Vcc/2, PLL_CP_GAIN = 16x

V_CPout= Vcc/2, PLL_CP_GAIN = 32x

0.5 V < V_CPout< Vcc - 0.5 V

100

400

I_SRCECPout

Charge Pump Source Current

µA

1600

3200

-100

-400

-1600

-3200

I_SINKCPout

Charge Pump Sink Current

I_CPoutTRI

Charge Pump TRI-STATE Current

Magnitude of Charge Pump

Sink vs. Source Current Mismatch

V_CPout= Vcc / 2

T_A= 25°C

I_CPout%MIS

Magnitude of Charge Pump

Current vs. Charge Pump Voltage Variation

0.5 V < V_CPout< Vcc - 0.5 V

T_A= 25°C

I_CPoutVTUNE

I_CPoutTEMP

Magnitude of Charge Pump Current vs. Temperature

Variation

(3)

PLL_CP_GAIN = 1x

PLL_CP_GAIN = 32x

PLL_CP_GAIN = 1x

PLL_CP_GAIN = 32x

-117

-122

-219

-224

PLL 1/f Noise at 10 kHz Offset

PN10kHz

PN1Hz

dBc/Hz

Normalized to 1 GHz Output Frequency

Normalized Phase Noise Contribution⁽⁴⁾

(3) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker

noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz =

L_{PLL_flicker}(10 kHz) - 20log(Fout / 1 GHz), where L_{PLL_flicker}(f) is the single side band phase noise of only the flicker noise's contribution to

total noise, L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency

and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the

reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of

L_{PLL_flicker}(f) and L_{PLL_flat}(f).

(4) A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, L_{PLL_flat}(f), of the PLL and is defined

as PN1Hz = L_{PLL_flat}(f) – 20log(N) – 10log(f_COMP). L_{PLL_flat}(f) is the single side band phase noise measured at an offset frequency, f, in a

1 Hz Bandwidth and f_COMPis the phase detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f). To measure

L_{PLL_flat}(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid

a substantial noise contribution from the reference and flicker noise. L_{PLL_flat}(f) can be masked by the reference oscillator performance if

a low power or noisy source is used.

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Electrical Characteristics ⁽¹⁾(continued)

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values

represent most likely parametric norms at Vcc = 3.3 V, T_A= 25 °C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

VCO

f_Fout

VCO Tuning Range

LMK03002/LMK03002C

1566

1724

125

MHz

°C

After programming R15 for lock, no changes to

output configuration are permitted to ensure

|ΔT_CL

Allowable Temperature Drift for Continuous Lock

(5)

continuous lock.

p_Fout

Output Power to a 50 Ω load driven by Fout

LMK03002/LMK03002C; T_A= 25 °C

LMK03002/LMK03002C

dBm

Fine Tuning Sensitivity

(The lower sensitivity indicates the typical sensitivity at the

lower end of the tuning range, the higher sensitivity at the

higher end of the tuning range)

K_Vtune

11 to 15

MHz/V

LMK03002

12 kHz to 20 MHz bandwidth

800

400

J_RMSFout

Fout RMS Period Jitter

LMK03002C

12 kHz to 20 MHz bandwidth

10 kHz Offset

-89

-113

-135

-155

-91

100 kHz Offset

LMK03002C

(6)

f_Fout= 1724 MHz

1 MHz Offset

10 MHz Offset

10 kHz Offset

L(f)_Fout

Fout Single Side Band Phase Noise

dBc/Hz

100 kHz Offset

LMK03002C

-115

-137

-156

(6)

f_Fout= 1566 MHz

1 MHz Offset

10 MHz Offset

Clock Distribution Section ⁽⁷⁾- LVPECL Clock Outputs

CLKoutX_MUX =

Bypass

R_L= 100 Ω

Distribution Path =

800 MHz

Bandwidth =

12 kHz to 20 MHz

±3

(7)

Jitter_ADD

Additive RMS Jitter

CLKoutX_MUX =

Divided

CLKoutX_DIV = 4

Equal loading and identical clock configuration

Termination = 50 Ω to Vcc - 2 V

(8)

t_SKEW

CLKoutX to CLKoutY

-30

V_OH

V_OL

V_OD

Output High Voltage

Output Low Voltage

Vcc - 0.98

Vcc - 1.8

810

Termination = 50 Ω to Vcc - 2 V

CLKoutX output frequency = 200 MHz

Differential Output Voltage

660

965

(5) Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction and stay in lock from the ambient

temperature and programmed state at which the device was when register R15 was programmed. The action of programming the R15

register, even to the same value, activates a frequency calibration routine. This implies that the device will work over the entire

frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to

reprogram the R15 register to ensure that the device stays in lock. Regardless of what temperature the device was initially programmed

at, the ambient temperature can never drift outside the range of -40 °C ≤ T_A≤ 85 °C without violating specifications. For this

specification to be valid, the programmed state of the device must not change after R15 is programmed.

(6) VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the

phase noise typically varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over

temperature, the phase noise typically varies by 1 to 2 dB, assuming the device is not reprogrammed. Reprogramming R15 will run the

frequency calibration routine for optimum phase noise.

(7) The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications

apply to the clock distribution section only and is in RMS form addition to the jitter from the VCO.

(8) Specification is ensured by characterization and is not tested in production.

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Electrical Characteristics ⁽¹⁾(continued)

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ T_A≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values

represent most likely parametric norms at Vcc = 3.3 V, T_A= 25 °C, and at the Recommended Operation Conditions at the

time of product characterization and are not ensured).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(9)

Digital LVTTL Interfaces

V_IH

V_IL

I_IH

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

2.0

Vcc

0.8

5.0

V_IH= Vcc

V_IL= 0

-5.0

-40.0

µA

I_IL

V_OH

V_OL

High-Level Output Voltage

Low-Level Output Voltage

I_OH= +500 µA

Vcc - 0.4

I_OL= -500 µA

0.4

(10)

Digital MICROWIRE Interfaces

V_IH

V_IL

I_IH

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

1.6

Vcc

0.4

5.0

V_IH= Vcc

-5.0

µA

I_IL

V_IL= 0

MICROWIRE Timing

See Figure 3

t_CS

Data to Clock Set Up Time

Data to Clock Hold Time

Clock Pulse Width High

Clock Pulse Width Low

t_CH

t_CWH

t_CWL

t_ES

Clock to Enable Set Up Time

Enable to Clock Set Up Time

Enable Pulse Width High

t_CES

t_EWH

(9) Applies to GOE, LD, and SYNC*.

(10) Applies to CLKuWire, DATAuWire, and LEuWire.

Serial Data Timing Diagram

MSB

D27

LSB

DATAuWire

CLKuWire

LEuWire

D26

D25

D24

D23

CWH

CES

CWL

EWH

Figure 3. Serial Data Timing Diagram

Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the

CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the

addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire,

and LEuWire signals should be returned to a low state. It is recommended that the slew rate of CLKuWire,

DATAuWire, and LEuWire should be at least 30 V/µs.

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Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at V_CPout= Vcc - ΔV

I2 = Charge Pump Sink Current at V_CPout= Vcc/2

I3 = Charge Pump Sink Current at V_CPout= ΔV

I4 = Charge Pump Source Current at V_CPout= Vcc - ΔV

I5 = Charge Pump Source Current at V_CPout= Vcc/2

I6 = Charge Pump Source Current at V_CPout= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage

Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch

Charge Pump Output Current Magnitude Variation vs. Temperature

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Typical Performance Characteristics

LVPECL Differential Output Voltage (V_OD

)

LVPECL Output Noise Floor

1000

-146

-148

-150

-152

-154

-156

-158

-160

Vboost = 1

900

800

700

600

500

Vboost = 0

400

300

200

100

Vboost = 1

200 400 600 800 10001200140016001800 2000

FREQUENCY (MHz)

Figure 4.

Figure 5.

Delay Noise Floor (Adds to Output Noise Floor)

-135

Delay = 2250 ps

Delay=1800 ps

-140

-145

-150

-155

-160

-165

-170

Delay = 900 ps

Delay = 450 ps

Delay = 0 ps

20 30 50 100

300 500 1000 2000

200

400

FREQUENCY (MHz)

Figure 6.

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FUNCTIONAL DESCRIPTION

The LMK03002/LMK03002C precision clock conditioners combine the functions of jitter cleaning/reconditioning,

multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO),

a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and four LVPECL clock

output distribution blocks.

The devices include internal 3rd and 4th order poles to simplify loop filter design and improve spurious

performance. The 1st and 2nd order poles are off-chip to provide flexibility for the design of various loop filter

bandwidths.

The LMK03002/LMK03002C includes a 1.64 GHz VCO. The VCO output is optionally accessible on the Fout

port. Internally, the VCO output goes through an VCO Divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable

delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted

copies of the reference to be distributed to four system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices

in the same family.

BIAS PIN

To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is

important for low noise performance.

LDO BYPASS

To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF

capacitor.

OSCILLATOR INPUT PORT (OSCin, OSCin*)

The purpose of OSCin is to provide the PLL with a reference signal. The OSCin port must be AC coupled, refer

to SYSTEM LEVEL DIAGRAM in Application Information. The OSCin port may be driven single endedly by AC

grounding OSCin* with a 0.1 µF capacitor.

LOW NOISE, FULLY INTEGRATED VCO

The LMK03002/LMK03002C devices contain a fully integrated VCO. In order for proper operation the VCO uses

a frequency calibration algorithm. The frequency calibration algorithm is activated any time that the R15 register

is programmed. Once R15 is programmed the temperature may not drift more than the maximum allowable drift

for continuous lock, ΔT_CL, or else the VCO is not ensured to stay in lock.

For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 is

programmed.

CLKout DELAYS

Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a

150 ps step size and range from 0 to 2250 ps of total delay.

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LVPECL OUTPUTS

Each LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be

disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0.

The duty cycle of the LVPECL clock outputs are shown in the table below.

VCO_DIV

CLKoutX_MUX

Divided, or Divided and Delayed

Any

Duty Cycle

50%

Any

2, 4, 6, 8

50%

Bypassed, or Delayed

33%

40%

43%

GLOBAL CLOCK OUTPUT SYNCHRONIZATION

The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided

outputs are also held in a logic low state. The bypassed outputs will continue to operate normally. Shortly after

the SYNC* pin goes high, the divided clock outputs are activated and will all transition to a high state

simultaneously. All the outputs, divided and bypassed, will now be synchronized. Clocks in the bypassed state

are not affected by SYNC* and are always synchronized with the divided outputs.

TThe SYNC* pin must be held low for greater than one clock cycle of the output of the VCO Divider, also known

as the distribution path. Once this low event has been registered, the outputs will not reflect the low state for four

more cycles. This means that the outputs will be low on the fifth rising edge of the distribution path. Similarly

once the SYNC* pin becomes high, the outputs will not simultaneously transition high until four more distribution

path clock cycles have passed, which is the fifth rising edge of the distribution path. See the timing diagram in

Figure 7 for further detail. The clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided,

CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4. To synchronize the outputs, after the low

SYNC* event has been registered, it is not required to wait for the outputs to go low before SYNC* is set high.

Distribution

Path

SYNC*

CLKout0

CLKout1

CLKout2

Figure 7. SYNC* Timing Diagram

The SYNC* pin provides an internal pull-up resistor as shown on the Functional Block Diagram. If the SYNC* pin

is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used, clock

output synchronization is not ensured.

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CLKout OUTPUT STATES

Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control

bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit

(EN_CLKout_Global).

All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or

EN_CLKout_Global is set to 0.

CLKoutX_EN bit

EN_CLKout_Global bit

GOE pin

Low

Clock X Output State

Low

Off

Don't care

Off

High / No Connect

Enabled

When an LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt.

GLOBAL OUTPUT ENABLE AND LOCK DETECT

The GOE pin provides an internal pull-up resistor as shown on the Functional Block Diagram. If it is not

terminated externally, the clock output states are determined by the Clock Output Enable bits (CLKoutX_EN) and

the EN_CLKout_Global bit.

By programming the PLL_MUX register to Digital Lock Detect Active High (see PLL_MUX[3:0] – Multiplexer

Control for LD Pin), the Lock Detect (LD) pin can be connected to the GOE pin in which case all outputs are set

low automatically if the synthesizer is not locked.

POWER ON RESET

When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit sets

all registers to their default values, see Table 1 for more information on default register values. Voltage should be

applied to all Vcc pins simultaneously.

DIGITAL LOCK DETECT

The PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase

detector to a RC generated delay of ε. To indicate a locked state the phase error must be less than the ε RC

delay for 5 consecutive reference cycles. Once in lock, the RC delay is changed to approximately δ. To indicate

an out of lock state, the phase error must become greater δ. The values of ε and δ are shown in the table below:

10 ns

20 ns

To utilize the digital lock detect feature, PLL_MUX must be programmed for "Digital Lock Detect (Active High)" or

"Digital Lock Detect (Active Low)." When one of these modes is programmed the state of the LD pin will be set

high or low as determined by the description above as shown in Figure 8.

When the device is in power down mode and the LD pin is programmed for a digital lock detect function, LD will

show a "no lock detected" condition which is low or high given active high or active low circuitry respectively.

The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the DIV4 word

should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to divide the

comparison frequency presented to the lock detect circuit by 4.

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YES

Lock Detected =

False

START

Phase Error < g

YES

Lock Detected =

Phase Error > *

True

Phase Error < g

Figure 8. Digital Lock Detect Flowchart

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General Programming Information

The LMK03002/LMK03002C devices are programmed using several 32-bit registers which control the device's

operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the

address field. The remaining 28 bits form the data field DATA[27:0].

During programming, LEuWire is low and serial data is clocked in on the rising edge of CLKuWire (MSB first).

When LEuWire goes high, data is transferred to the register bank selected by the address field. Only registers

R0, R4 to R8, R11, and R13 to R15 need to be programmed for proper device operation. After programming,

CLKuWire, DATAuWire, LEuWire should remain low to prevent spurious.

For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 is

programmed. Any changes to the PLL R divider or OSCin require R15 to be programmed again to activate the

frequency calibration routine.

RECOMMENDED PROGRAMMING SEQUENCE

The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to

ensure the device is in a default state. Registers are programmed in order with R15 being the last register

programmed. An example programming sequence is shown below.

•

Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state.

Program R4 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings.

Program R8 for optiumum phase noise performance.

Program R9 with Vboost setting if necessary. Optional, only needed to set Vboost = 1.

Program R11 with DIV4 setting if necessary.

Program R13 with oscillator input frequency and internal loop filter values.

Program R14 with Fout enable bit, global clock output bit, power down setting, PLL mux setting, and PLL R

divider.

•

Program R15 with PLL charge pump gain, VCO divider, and PLL N divider. Also starts frequency calibration

routine.

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LMK03002/LMK03002C Register Map

REG

Data [27:0]

CLKout0

_MUX

[1:0]

CLK

out0

_EN

CLKout0_DIV

[7:0]

CLKout0_DLY

[3:0]

CLKout1

_MUX

[1:0]

CLK

out1

_EN

CLKout1_DIV

[7:0]

CLKout1_DLY

[3:0]

CLKout2

_MUX

[1:0]

CLK

out2

_EN

CLKout2_DIV

[7:0]

CLKout2_DLY

[3:0]

CLKout3

_MUX

[1:0]

CLK

out3

_EN

CLKout3_DIV

[7:0]

CLKout3_DLY

[3:0]

Vboo

R11

R13

DIV4

OSCin_FREQ

[7:0]

VCO_R4_LF

[2:0]

VCO_R3_LF

[2:0]

VCO_C3_C4_LF

[3:0]

PLL_MUX

[3:0]

PLL_R

[11:0]

R14

R15

PLL_CP_

GAIN

VCO_DIV

[3:0]

PLL_N

[17:0]

[1:0]

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REGISTERS R0, R4 to R7

Registers R4 through R7 control the four clock outputs. Register R3 controls CLKout0, Register R4 controls

CLKout1, and so on. There is one additional bit in register R0 called RESET. The X in CLKoutX_MUX,

CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 3.

Table 1. POR Register Defaults

Default

Bit Value

Bit

Location

Bit Name

Bit State

Bit Description

RESET

No reset, normal operation

Bypassed

Reset to power on defaults

CLKoutX mux mode

18:17

CLKoutX_MUX

CLKoutX_EN

CLKoutX_DIV

CLKoutX_DLY

Vboost

Disabled

CLKoutX enable

R0 to R7

Divide by 2

CLKoutX clock divide

CLKoutX clock delay

Output Power Control

Phase Detector Frequency

OSCin Frequency in MHz

R4 internal loop filter values

R3 internal loop filter values

C3 and C4 internal loop filter values

Fout enable

15:8

7:4

0 ps

Normal Mode

PDF ≤ 20 MHz

10 MHz OSCin

Low (~200 Ω)

Low (~600 Ω)

C3 = 0 pF, C4 = 10 pF

Fout disabled

Normal - CLKouts normal

Normal - Device active

Disabled

DIV4

R11

OSCin_FREQ

VCO_R4_LF

VCO_R3_LF

VCO_C3_C4_LF

EN_Fout

21:14

13:11

10:8

7:4

R13

EN_CLKout_Global

POWERDOWN

PLL_MUX

Global clock output enable

Device power down

R14

R15

Multiplexer control for LD pin

PLL R divide value

23:20

19:8

31:30

29:26

25:8

PLL_R

R divider = 10

100 uA

PLL_CP_GAIN

VCO_DIV

Charge pump current

VCO divide value

Divide by 2

PLL_N

760

N divider = 760

PLL N divide value

RESET bit – R0 only

This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit

to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. If this bit is

set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and

RESET = 0.

CLKoutX_MUX[1:0] – Clock Output Multiplexers

These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes

changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode. The different

MUX modes and associated delays are listed below.

CLKoutX_MUX[1:0]

Mode

Bypassed (default)

Divided

Added Delay Relative to Bypass Mode

0 ps

100 ps

400 ps

Delayed

(In addition to the programmed delay)

500 ps

Divided and Delayed

(In addition to the programmed delay)

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CLKoutX_DIV[7:0] – Clock Output Dividers

These bits control the clock output divider value. In order for these dividers to be active, the respective

CLKoutX_MUX (see CLKoutX_MUX[1:0] – Clock Output Multiplexers) bit must be set to either "Divided" or

"Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all

edges of the clock outputs are aligned (see GLOBAL CLOCK OUTPUT SYNCHRONIZATION). The Clock Output

Dividers follow the VCO Divider so the final clock divide for an output is VCO Divider × Clock Output Divider. By

adding the divider block to the output path a fixed delay of approximately 100 ps is incurred.

The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.

CLKoutX_DIV[7:0]

Clock Output Divider value

Invalid

2 (default)

...

510

CLKoutX_DLY[3:0] – Clock Output Delays

These bits control the delay stages for each clock output. In order for these delays to be active, the respective

CLKoutX_MUX (see CLKoutX_MUX[1:0] – Clock Output Multiplexers) bit must be set to either "Delayed" or

"Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps

is incurred in addition to the delay shown in the table below.

CLKoutX_DLY[3:0]

Delay (ps)

0 (default)

150

300

450

600

750

900

1050

1200

1350

1500

1650

1800

1950

2100

2250

CLKoutX_EN bit – Clock Output Enables

These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (see

EN_CLKout_Global bit – Global Clock Output Enable) is set to zero or if GOE pin is held low, all CLKoutX_EN bit

states will be ignored and all clock outputs will be disabled. See CLKout OUTPUT STATES for more information

on CLKout states.

CLKoutX_EN bit

Conditions

CLKoutX State

Disabled (default)

Enabled

EN_CLKout_Global bit = 1

GOE pin = High / No Connect

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The programming of register R8 provides optimum phase noise performance.

The programming of register R9 is optional. If it is not programmed the bit Vboost will be defaulted to 0, which is

the test condition for all electrical characteristics.

Vboost – Voltage Boost

By enabling this bit, the voltage output levels for all clock outputs is increased. Also, the noise floor is improved.

Vboost

Typical LVPECL Voltage Output (mV)

810

865

This register only has one bit and only needs to be programmed in the case that the phase detector frequency is

greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to the correct values.

DIV4 – High Phase Detector Frequencies and Lock Detect

This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a reliable

output from the digital lock detect output in the case of a phase detector frequency frequency greater than

20 MHz.

DIV4

Digital Lock Detect Circuitry Mode

Not divided;

Phase Detector Frequency ≤ 20 MHz (default)

Divided by 4;

Phase Detector Frequency > 20 MHz

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VCO_C3_C4_LF[3:0] – Value for Internal Loop Filter Capacitors C3 and C4

These bits control the capacitor values for C3 and C4 in the internal loop filter.

VCO_C3_C4_LF[3:0]

Loop Filter Capacitors

C3 (pF)

C4 (pF)

10 (default)

0 (default)

110

100

110

160

100

150

110

12 to 15

Invalid

VCO_R3_LF[2:0] – Value for Internal Loop Filter Resistor R3

These bits control the R3 resistor value in the internal loop filter. The recommended setting for VCO_R3_LF[2:0]

= 0 for optimum phase noise and jitter.

VCO_R3_LF[2:0]

R3 Value (kΩ)

Low (~600 Ω) (default)

5 to 7

Invalid

VCO_R4_LF[2:0] – Value for Internal Loop Filter Resistor R4

These bits control the R4 resistor value in the internal loop filter. The recommended setting for VCO_R4_LF[2:0]

= 0 for optimum phase noise and jitter.

VCO_R4_LF[2:0]

R4 Value (kΩ)

Low (~200 Ω) (default)

5 to 7

Invalid

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OSCin_FREQ[7:0] – Oscillator Input Calibration Adjustment

These bits are to be programmed to the OSCin frequency. If the OSCin frequency is not an integral multiple of

1 MHz, then round to the closest value.

OSCin_FREQ[7:0]

OSCin Frequency

1 MHz

2 MHz

...

10 MHz (default)

...

200

200 MHz

Invalid

201 to 255

PLL_R[11:0] – R Divider Value

These bits program the PLL R Divider and are programmed in binary fashion. Any changes to PLL_R require

R15 to be programmed again to active the frequency calibration routine.

PLL_R[11:0]

PLL R Divide Value

Invalid

...

10 (default)

...

4095

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PLL_MUX[3:0] – Multiplexer Control for LD Pin

These bits set the output mode of the LD pin. The table below lists several different modes.

PLL_MUX[3:0]

Output Type

Hi-Z

LD Pin Function

Disabled (default)

Push-Pull

Logic High

Push-Pull

Logic Low

Push-Pull

Digital Lock Detect (Active High)

Digital Lock Detect (Active Low)

Analog Lock Detect

Push-Pull

Open Drain NMOS

Open Drain PMOS

Invalid

Push-Pull

N Divider Output/2 (50% Duty Cycle)

R Divider Output/2 (50% Duty Cycle)

12 to 15

"Logic High" and "Logic Low" allow the PLL_MUX pin to be used as a general purpose output. These modes are

also useful when debugging to verify programming. The Digital Lock Detect operation is covered in DIGITAL

LOCK DETECT.

Analog Lock Detect outputs the state of the charge pump on the LD pin. While the charge pump is on, the LD pin

is low. While the charge pump is off, the LD pin is high. By using two resistors, a capacitor, diode, and

comparator a lock detect circuit may be constructed. When in lock the charge pump will only turn on momentarily

once every period of the phase detector frequency. "N Divider Output/2" and "R Divider Output/2" output half the

frequency of the phase detector on the LD pin. When the device is locked, these frequencies should be the

same. These options are useful for debugging.

NOTE

For more information on lock detect circuits, see chapter 32 of PLL Performance,

Simulation and Design Handbook, Fourth Edition by Dean Banerjee.

POWERDOWN bit – Device Power Down

This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of

the state of any of the other bits or pins.

POWERDOWN bit

Mode

Normal Operation (default)

Entire Device Powered Down

EN_CLKout_Global bit – Global Clock Output Enable

This bit overrides the individual CLKoutX_EN bits (see CLKoutX_EN bit – Clock Output Enables). When this bit is

set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or pins. See CLKout

OUTPUT STATES for more information on CLKout states.

EN_CLKout_Global bit

Clock Outputs

All Off

Normal Operation (default)

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EN_Fout bit – Fout port enable

This bit enables the Fout pin.

EN_Fout bit

Fout Pin Status

Disabled (default)

Enabled

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Programming R15 also activates the frequency calibration routine.

PLL_N[17:0] – PLL N Divider

These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and

precedes the PLL phase detector. Since the VCO Divider is also in the feedback path from the VCO to the PLL

Phase Detector, the total N divide value, N_Total, is also influenced by the VCO Divider value. N_Total= PLL N

Divider × VCO Divider. The VCO frequency is calculated as, f_VCO= f_OSCin× PLL N Divider × VCO Divider / PLL R

Divider. Since the PLL N divider is a pure binary counter there are no illegal divide values for PLL_N[17:0] except

for 0.

PLL_N[17:0]

PLL N Divider Value

Invalid

...

760 (default)

...

262143

VCO_DIV[3:0] – VCO Divider

These bits program the divide value for the VCO Divider. The VCO Divider follows the VCO output and precedes

the clock distribution blocks. Since the VCO Divider is in the feedback path from the VCO to the PLL phase

detector the VCO Divider contributes to the total N divide value, N_Total. N_Total= PLL N Divider × VCO Divider. The

VCO Divider can not be bypassed. See PLL_N[17:0] – PLL N Divider (PLL N Divider) for more information on

setting the VCO frequency.

VCO_DIV[3:0]

VCO Divider Value

Invalid

2 (default)

Invalid

...

Invalid

PLL_CP_GAIN[1:0] – PLL Charge Pump Gain

These bits set the charge pump gain of the PLL.

PLL_CP_GAIN[1:0]

Charge Pump Gain

1x (default)

16x

32x

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Application Information

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SYSTEM LEVEL DIAGRAM

Vcc

1 mF

0.1 mF

OSCin

100W

OSCin*

CLKout0

CLKout0*

0.1 mF

CLKout1

CLKout1*

LEuWire

CLKout2

CLKout2*

To System

CLKuWire

DATAuWire

SYNC*

CLKout3

CLKout3*

To Host

LMK03002

(optional)

GOE

LDObyp1

LDObyp2

10 mF

0.1 mF

Figure 9. Typical Application

Figure 9 shows an LMK03000 family device used in a typical application. In this setup the clock may be

multiplied, reconditioned, and redistributed. Both the OSCin/OSCin* and CLKoutX/CLKoutX* pins can be used in

a single-ended or a differential fashion, which is discussed later in this datasheet. The GOE pin needs to be high

for the outputs to operate. One technique sometimes used is to take the output of the LD (Lock Detect) pin and

use this as an input to the GOE pin. If this is done, then the outputs will turn off if lock detect circuit detects that

the PLL is out of lock. The loop filter actually consists of seven components, but four of these components that

for the third and fourth poles of the loop filter are integrated in the chip. The first and second pole of the loop filter

are external.

BIAS PIN

To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is

important for low noise performance.

LDO BYPASS

To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF

capacitor.

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LOOP FILTER

LMK03002

Phase

Detector

Internal Loop Filter

External Loop Filter

Figure 10. Loop Filter

The internal charge pump is directly connected to the integrated loop filter components. The first and second

pole of the loop filter are externally attached as shown in Figure 10. When the loop filter is designed, it must be

stable over the entire frequency band, meaning that the changes in K_Vtunefrom the low to high band specification

will not make the loop filter unstable. The design of the loop filter is application specific and can be rather

involved, but is discussed in depth in the Clock Conditioner Owner's Manual provided by Texas Instruments.

When designing with the integrated loop filter of the LMK03000 family, considerations for minimum resistor

thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4.

Both the integrated loop filter resistors and capacitors (C3 and C4) also restrict how wide the loop bandwidth the

PLL can have. However, these integrated components do have the advantage that they are closer to the VCO

and can therefore filter out some noise and spurs better than external components. For this reason, a common

strategy is to minimize the internal loop filter resistors and then design for the largest internal capacitor values

that permit a wide enough loop bandwidth. In some situations where spurs requirements are very stringent and

there is margin on phase noise, it might make sense to design for a loop filter with integrated resistor values that

are larger than their minimum value.

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CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS

Due to the myriad of possible configurations, Table 2 serves to provide enough information to allow the user to

calculate estimated current consumption of the device. Unless otherwise noted Vcc = 3.3 V, T_A= 25 °C.

Table 2. Block Current Consumption

Power

Current

Consumption at

3.3 V (mA)

Power

Dissipated in

device (mW)

Dissipated in

LVPECL emitter

resistors (mW)

Block

Condition

Entire device,

core current

All outputs off; No LVPECL emitter resistors connected

86.0

283.8

Clock buffers

(internal)

The clock buffers are enabled anytime one of CLKout0

through CLKout3 are enabled

29.7

47.8

Fout buffer, EN_Fout = 1

14.5

LVPECL output, bypass mode (includes 120 Ω emitter

resistors)

Output buffers

LVPECL output, disabled mode (includes 120 Ω emitter

resistors)

17.4

38.3

19.1

LVPECL output, disabled mode. No emitter resistors

placed; open outputs

Divide enabled, divide = 2

5.3

8.5

5.8

9.9

175

17.5

28.0

19.1

32.7

457.5

Divide circuitry

per output

Divide enabled, divide > 2

Delay enabled, delay < 8

Delay circuitry per

output

Delay enabled, delay > 7

Entire device

CLKout0 & CLKout3 enabled in bypass mode

120

From Table 2 the current consumption can be calculated in any configuration. For example, the current for the

entire device with two LVPECL (CLKout0 and CLKout3) outputs in bypass mode can be calculated by adding up

the following blocks: core current, clock buffers, and two LVPECL output buffer currents. There will also be two

LVPECL outputs drawing emitter current, but some of the power from the current draw is dissipated in the

external 120 Ω resistors which doesn't add to the power dissipation budget for the device. If delays or divides are

switched in, then the additional current for these stages needs to be added as well.

For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device

minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter

resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of two

LVPECL (CLKout0 & CLKout3) outputs operating at 3.3 volts, we calculate 3.3 V × (86 + 9 + 40 + 40) mA =

3.3 V × 175 mA = 577.5 mW. Because two LVPECL outputs (CLKout0 and CLKout3) have the emitter resistors

hooked up and the power dissipated by these resistors is 60 mW for each clock, the total device power

dissipation is 533.9 mW - 120 mW = 457.5 mW.

When the LVPECL output is active, ~1.9 V is the average voltage on each output as calculated from the LVPECL

V_OH& V_OLtypical specification. Therefore the power dissipated in each emitter resistor is approximately (1.9 V)²/

120 Ω = 30 mW. When the LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the

power dissipated in each emitter resistor is approximately (1.07 V)²/ 120 Ω = 9.5 mW.

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THERMAL MANAGEMENT

Power consumption of the LMK03002/LMK03002C devices can be high enough to require attention to thermal

management. For reliability and performance reasons the die temperature should be limited to a maximum of

125 °C. That is, as an estimate, T_A(ambient temperature) plus device power consumption times θ_JAshould not

exceed 125 °C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent

electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal

land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the

package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A

recommended land and via pattern is shown in Figure 11. More information on soldering WQFN packages can

be obtained at www.ti.com.

5.0 mm, min

0.33 mm, typ

1.2 mm, typ

Figure 11. Recommended Land and Via Pattern

To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground

plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite

side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but

should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in

Figure 11 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat

pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively

dissipated.

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TERMINATION AND USE OF CLOCK OUTPUTS (DRIVERS)

When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:

•

Transmission line theory should be followed for good impedance matching to prevent reflections.

Clock drivers should be presented with the proper loads. For example:

–

LVDS drivers are current drivers and require a closed current loop.

LVPECL drivers are open emitter and require a DC path to ground.

•

Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage)

for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage

level. In this case, the signal should normally be AC coupled.

It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above

guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best

termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode

voltage). For example, when driving the OSCin/OSCin* input of the LMK03000 family, OSCin/OSCin* should be

AC coupled because OSCin/OSCin* biases the signal to the proper DC level, see Figure 9. This is only slightly

different from the AC coupled cases described in Termination for AC Coupled Differential Operation because the

DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains

the same, which is the receiver (OSCin/OSCin*) set the input to the optimum DC bias voltage (common mode

voltage), not the driver.

Termination for DC Coupled Differential Operation

For DC coupled operation of an LVPECL driver, terminate with 50 Ω to Vcc - 2 V as shown in Figure 12.

Alternatively terminate with a Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistor

connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) as shown in

Figure 13 for Vcc = 3.3 V.

Vcc - 2 V

CLKoutX

100W Trace

(Differential)

LVPECL

Driver

LVPECL

Receiver

CLKoutX*

Vcc - 2 V

Figure 12. Differential LVPECL Operation, DC Coupling

Vcc

CLKoutX

100W Trace

(Differential)

LVPECL

Driver

LVPECL

Receiver

CLKoutX*

Vcc

Figure 13. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent

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Termination for AC Coupled Differential Operation

AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver

standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important

to ensure the receiver is biased to its ideal DC level.

LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω emitter resistors

close to the LVPECL driver to provide a DC path to ground as shown in Figure 14. For proper receiver operation,

the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical

DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82 Ω

resistor connected to Vcc and a 120 Ω resistor connected to ground with the driver connected to the junction of

the 82 Ω and 120 Ω resistors) is a valid termination as shown in Figure 14 for Vcc = 3.3 V. Note this Thevenin

circuit is different from the DC coupled example in Figure 13.

Vcc

CLKoutX

0.1 mF

100W Trace

(Differential)

LVPECL

Reciever

LVPECL

Driver

0.1 mF

CLKoutX*

Vcc

Figure 14. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent

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Termination for Single-Ended Operation

A balun can be used with LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-

ended signal.

It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one of the

LMK03000 family clock LVPECL drivers, the termination should still be 50 ohms to Vcc - 2 V as shown in

Figure 15. Again the Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistor

connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) is a valid

termination as shown in Figure 16 for Vcc = 3.3 V.

Vcc - 2V

CLKoutX

50W Trace

LVPECL

Driver

Vcc - 2V

Load

CLKoutX*

50W

Figure 15. Single-Ended LVPECL Operation, DC Coupling

Vcc

CLKoutX

Vcc

50W Trace

LVPECL

Driver

CLKoutX*

Load

Figure 16. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent

When AC coupling an LVPECL driver use a 120 Ω emitter resistor to provide a DC path to ground and ensure a

50 ohm termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL

receivers is 2 V (see Termination for AC Coupled Differential Operation). If the other driver is not used it should

be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended

LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase

noise analyzer. When using most RF test equipment no DC bias (0 V DC) is expected for safe and proper

operation. The internal 50 ohm termination the test equipment provides correctly terminates the LVPECL driver

being measured as shown in Figure 17. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be

sure to properly terminate the unused driver.

CLKoutX

50W Trace

0.1 mF

LVPECL

Driver

0.1 mF

CLKoutX*

Load

Figure 17. Single-Ended LVPECL Operation, AC Coupling

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Conversion to LVCMOS Outputs

To drive an LVCMOS input with an LMK03000 family LVDS or LVPECL output, an LVPECL/LVDS to LVCMOS

converter such as TI's DS90LV018A, DS90LV028A, DS90LV048A, etc. is required. For best noise performance,

LVPECL provides a higher voltage swing into input of the converter.

OSCin INPUT

In addition to LVDS and LVPECL inputs, OSCin can also be driven with a sine wave. The OSCin input can be

driven single-ended or differentially with sine waves. The configurations for these are shown in Figure 18 and

Figure 19.

Figure 20 shows the recommended power level for sine wave operation for both differential and single-ended

sources over frequency. The part will operate at power levels below the recommended power level, but as power

decreases the PLL noise performance will degrade. The VCO noise performance will remain constant. At the

recommended power level the PLL phase noise degradation from full power operation (8 dBm) is less than 2 dB.

0.1 mF

50W Trace

LMK

Input

Clock Source

0.1 mF

Figure 18. Single-Ended Sine Wave Input

0.1 mF

100W Trace

(Differential)

LMK

Input

0.1 mF

Clock Source

Figure 19. Differential Sine Wave Input

Minimum Recommended

Power for Single-Ended

Operation

-5

Minimum Recommended

Power for Differential

Operation

-10

-15

-20

100

FREQUENCY (MHz)

Figure 20. Recommended OSCin Power for Operation with a Sine Wave Input

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MORE THAN EIGHT OUTPUTS WITH AN LMK03000 FAMILY DEVICE

The LMK03000 family devices include eight or less outputs. When more than 8 outputs are required the footprint

compatible LMK01000 family may be used for clock distribution. By using an LMK03000 device with eight

LMK01000 family devices up to 64 clocks may be distributed in many different LVDS / LVPECL combinations. It's

possible to distribute more than 64 clocks by adding more LMK01000 family devices. Refer to AN-1864

(SNAA060) for more details on how to do this.

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REVISION HISTORY

Changes from Revision D (April 2013) to Revision E

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 32

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMK03002CISQ/NOPB

LMK03002CISQX/NOPB

LMK03002ISQ/NOPB

LMK03002ISQX/NOPB

ACTIVE

WQFN

RHS

250

RoHS & Green

Level-3-260C-168 HR

-40 to 85

K03002CI

2500 RoHS & Green

250 RoHS & Green

2500 RoHS & Green

K03002CI

K03002 I

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMK03002CISQ/NOPB

WQFN

RHS

250

2500

250

178.0

330.0

178.0

330.0

16.4

7.3

1.3

12.0

16.0

LMK03002CISQX/NOPB WQFN

LMK03002ISQ/NOPB

LMK03002ISQX/NOPB

WQFN

2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMK03002CISQ/NOPB

LMK03002CISQX/NOPB

LMK03002ISQ/NOPB

LMK03002ISQX/NOPB

WQFN

RHS

250

2500

250

208.0

356.0

208.0

356.0

191.0

356.0

191.0

356.0

35.0

2500

Pack Materials-Page 2

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LMK03002ISQ/NOPB [TI]

相关型号：

LMK03002ISQX

LMK03002ISQX/NOPB

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LMK03033CISQ

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LMK03033CISQX

LMK03033CISQX/NOPB

LMK03033ISQ

LMK03033ISQ/NOPB

LMK03033ISQE/NOPB