LMP8350MAX/NOPB [TI]
具有可选功率模式的超低失真全差动精密 ADC 驱动器 | D | 8 | -40 to 85;
| 型号： | LMP8350MAX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可选功率模式的超低失真全差动精密 ADC 驱动器 | D | 8 | -40 to 85 驱动 光电二极管 信号电路 驱动器 模拟IC |
| 文件： | 总24页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMP8350
LMP8350 Ultra Low Distortion Fully Differential Precision ADC Driver with
Selectable Power Modes
Literature Number: SNOSB80A
February 9, 2011
LMP8350
Ultra Low Distortion Fully Differential Precision ADC Driver
with Selectable Power Modes
General Description
Features
The LMP8350 is an ultra low distortion fully differential am-
plifier designed for driving high-performance precision ana-
log-to-digital converters (ADC). As part of the PowerWise®
family, a unique mode enable pin allows the user to choose
from three different operating modes, trading power con-
sumption for dynamic performance.
Differential Input and Output
■
■
■
■
■
■
Tri-Level Power Settings with Shutdown
Ultra Low HD2/HD3 and THD+N Distortion
Adjustable Output Common Mode Level
Fully Balanced Differential Architecture
Single or Dual Supply Operation
The high power mode is optimized for highest AC perfor-
mance. The low noise, wide bandwidth and fast slew rate
makes the LMP8350 ideal for driving 24bit ADCs with input
sampling rates of 10MHz or less. The medium power mode
is optimized for precision DC performance, and can be used
to drive 24-bit ADCs with input sampling rates of 6MHz or less.
The low power mode is a trade-off between AC performance
and quiescent current for power sensitive applications. The
disable mode fully shuts-down the amplifier for further stand-
by power savings.
Key Specifications
(TA = 25°C, VS = +10V, RL = 2kΩ//20pF, typical values unless
otherwise specified)
Operating voltage range
Supply current
Total THD+N @ 1KHz
HD2 / HD3 Distortion @ 1KHz
Bandwidth
Settling to 0.1%
Low Offset Drift
Offset Voltage
Voltage Noise
4.5V to 12V
3 to 13mA
0.000097%
< –124 dBc
118 MHz
20 ns
0.4 µV/°C
80µV
■
■
■
■
■
■
■
■
■
■
The fully differential architecture of this device allows for easy
implementation of a single-ended to fully-differential output
conversion. Driving a 3Vpp, 1kHz output sine wave with the
amplifier powered by ±3.3V rails in high power mode yields
0.000098% THD+N.
The LMP8350 is part of the LMP® precision amplifier family.
It is offered in the 8-Pin SOIC package and has an operating
temperature range of −40°C to +85°C.
4.6 nV/Hz
−40°C to +85°C
Operating temperature range
Applications
High Resolution Differential ADC Driver
■
■
■
Portable instrumentation
Precision Line Driver
Typical Application
30140501
Typical Application Circuit
PowerWise® is a registered trademark of National Semiconductor.
LMP® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
301405
www.national.com
Ordering Information
Package
Part Number
LMP8350MA
LMP8350MAX
Package Marking
Transport Media
95 Units/Rail
NSC Drawing
8-Pin SOIC
LMP8350MA
M08A
2.5k Units Tape and Reel
Connection Diagram
8-Pin SOIC
30140502
Top View
Pin Descriptions
Pin
Name
Description
1
-IN
Inverting Input
Output Common Mode voltage set input. Sets output common mode voltage equal to the applied VOCM pin
VOCM
2
voltage.
3
4
5
6
7
8
V+
+OUT
-OUT
V-
Positive Power Supply Voltage
Non-Inverting Output
Inverting Output
Negative Power Supply Voltage
EN
Enable and Power Select input. Applied voltage sets power level or shutdown mode.
Non-Inverting Input
+IN
www.national.com
2
For soldering specifications:
See product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Note 1)
ESD Tolerance (Note 5)
Human Body Model
Machine Model
Charge-Device Model
Output Short Circuit Duration
V+ relative to V-
IN+, IN-, OUT, EN and VOCM Pins
Input Current
Temperature Range (TA)
−40°C to +85°C
4.5V to 12V
2500 V
200V
1250V
Supply Voltage (VS = V+ – V–)
Package Thermal Resistance (θJA) (Note 4)
8-Pin SOIC
(Note 3)
150°C/W
-0.3 to +12.9V
V+ + 0.3V, V- – 0.3V
1 mA
Storage Temperature Range
Junction Temperature (Note 4)
−65°C to +150°C
+150°C
+10V Electrical Characteristics (Note 2)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, Avcl = +1, RF = RG = 1kΩ, Fully differential input, VS = +10V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply at
the temperature extremes.
Conditions
(Note 12)
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Units
10V DC Characteristics
VOS Input Offset Voltage
(RTI)
±4
±4.05
High Power
Mid Power
Low Power
±0.6
±0.08
±0.1
±2
±2.03
mV
μV/°C
μA
±2.5
±2.52
TCVOS Input Offset Voltage vs.Temperature High Power
±0.8
±0.5
±0.4
(Note 9)
Mid Power
Low Power
IB
Input Bias Current
2
2.1
High Power
Mid Power
Low Power
2.7
3.2
3.5
3.7
AVOL
Open Loop Gain
High Power
Mid Power
Low Power
65
72
74
1.2
90
130
114
dB
V
CMVR Common Mode Voltage Range
8.8
8.8
8.8
HP @ CMRR ≥73dB
MP @ CMRR ≥83dB
LP @ CMRR ≥77dB
(Note 10)
1.2
1.2
CMRR Common Mode Rejection Ratio
DC, VOCM=0,VID=0,
ΔVcm=±0.2V
High Power
75
84
79
90
130
114
0.48
1
dB
Medium Power
Low Power
ZIND
CIND
Differential Input Resistance
Differential Input Capacitance
VCM = mid supply
VCM = mid supply
MΩ
pF
3
www.national.com
Conditions
(Note 12)
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Output Swing
Units
VO
0.75 to
9.25
High Power
Mid Power
Low Power
0.86
0.85
0.86
9.14
9.15
9.14
(Single Ended)
0.74 to
9.26
V
0.81 to
9.19
ISHORT
Short-Circuit Current
Output Shorted to mid supply
(Note 3)
High Power
+75 / -36 +108 / -65
+60 / -26 +85 / -48
mA
dB
Medium Power
Low Power
High Power
Mid Power
Low Power
VEN=8.75
+15 / -6
+36 / -20
107
PSRR
IS
Power Supply Rejection Ratio
VS ±10%
118
124
Supply Current
18
20
15
8
(Note 11)
VEN=6.25
10
11
mA
V
(Note 11)
VEN=3.75
4
5
3
(Note 11)
PD
Power Down Mode
Enable Time
Disable Voltage Threshold
(Note 11)
<1.65
0.75
0.9
0.95
Shutdown Current
mA
Enable Pin Current
High Power
100
15
μA
ten
Mid Power
20
ns
Low Power
40
10V AC Characteristics
SSBW Small Signal Bandwidth
200mVp-p Differential
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
2V Step, CL = 20pF
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
118
87
MHz
V/μs
ns
31
SR
trise
tfall
ts
Slew Rate
2Vp-p Differential
(Note 6)
507
393
178
3.0
3.9
9.7
2.8
3.8
9.6
Rise Time
2Vp-p Differential
Fall Time
2Vp-p Differential
ns
0.1% Settling Time
2Vp-p
20
ns
25
38
4.6
4.8
8
en
Input Referred Voltage Noise
@ 10KHz
nV/
www.national.com
4
Conditions
(Note 12)
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Units
In
Input Referred Current Noise
@ 10KHz
f = 10 kHz
High Power
1.7
pA/
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
1.1
0.6
THD+N Total Harmonic Distortion + Noise
3Vp-p @ 1KHz
0.000097
0.000109
0.000185
–124.7
–122.8
–117.2
–118.9
–117.6
–114.7
–139.9
–141.9
–133.3
–129.5
–132.4
–129.4
%
HD2
2nd Harmonic Distortion
3Vp-p, 1KHz
–116
–126
dBc
dBc
dBc
dBc
2nd Harmonic Distortion
6Vp-p, 1KHz
HD3
3rd Harmonic Distortion
3Vp-p, 1KHz
3rd Harmonic Distortion
6Vp-p, 1KHz
10V VOCM Input Characteristics
VOCM Small Signal Bandwidth
200mVp-p
High Power
Mid Power
Low Power
4.8
2.4
MHz
V/V
mV
0.64
VOCM Gain
1
VOCM Offset Voltage
High Power
Mid Power
Low Power
±1.62
±0.23
±0.43
1.8 to 8.2
VOCM Voltage Range
VOCM Input Resistance
All Power Levels
V
30 to mid
supply
All power levels
KΩ
+6.6V Electrical Characteristics (Note 2)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, Avcl = +1, RF = RG = 1kΩ, Fully differential input, VS = +6.6V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply at
the temperature extremes..
Conditions
(Note 12)
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Units
6.6V DC Characteristics
VOS
Input Offset Voltage
(RTI)
±3.5
±3.54
High Power
Mid Power
Low Power
±0.3
±0.1
±0.1
±2.8
±2.83
mV
±2.5
±2.52
TCVOS Input Offset Voltage vs.Temperature High Power
±0.7
±0.5
±0.4
(Note 9)
Mid Power
Low Power
μV/°C
5
www.national.com
Conditions
(Note 12)
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Input Bias Current
Units
IB
1.4
2.4
High Power
Mid Power
Low Power
2.5
3.0
μA
3.5
3.7
AVOL
Open Loop Gain
High Power
Mid Power
Low Power
65
73
72
1.2
70
76
75
dB
V
CMVR Common Mode Voltage Range
5.4
5.4
5.4
HP @ CMRR ≥68dB
MP @ CMRR ≥63dB
LP @ CMRR ≥ 79dB
(Note 10)
1.2
1.2
CMRR Common Mode Rejection Ratio
DC, VOCM=0,VID=0,
ΔVcm=±0.2V
High Power
70
86
81
85
117
113
0.48
1
dB
Mid Power
Low Power
ZIND
CIND
VO
Differential Input Resistance
Differential Input Capacitance
VCM = mid supply
VCM = mid supply
MΩ
pF
Output Swing
(Single Ended)
0.77 to
5.83
High Power
Mid Power
Low Power
0.84
0.82
0.83
5.76
5.78
5.77
0.75 to
5.83
V
0.77 to
5.83
ISHORT
Short-Circuit Current
Output Shorted to mid supply
(Note 3)
High Power
+54 / –30 +83 / –49
mA
dB
Mid Power
Low Power
High Power
Mid Power
Low Power
VEN=5.775
(Note 11)
+40 / –19 +64 / –35
+15 / –6 +27 / –15
PSRR
IS
Power Supply Rejection Ratio
VS ±10%
111
117
127
Supply Current
16
18
14
7
VEN=4.125
(Note 11)
9
10
mA
V
VEN=2.475
(Note 11)
3
4
2
PD
Power Down Mode
Enable Time
Disable Voltage Threshold
(Note 11)
<1.225
0.55
0.65
0.7
Shutdown Current
mA
Enable Pin Current
High Power
40
18
22
43
μA
ten
Mid Power
ns
Low Power
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6
Conditions
(Note 12)
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Units
6.6V AC Characteristics
SSBW Small Signal Bandwidth
200mVp-p Differential
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
116
85
MHz
V/μs
ns
29
SR
trise
tfall
ts
Slew Rate
2Vp-p Differential
(Note 6)
488
376
166
3.1
Rise Time
2Vp-p Differential
4.2
10.4
3.0
Fall Time
2Vp-p Differential
4.0
ns
10.3
0.1% Settling Time
2Vp-p
2V Step, CL = 20pF
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
19
ns
25
43
en
Input Referred Voltage Noise
@ 10KHz
4.5
4.8
nV/
8
In
Input Referred Current Noise
@ 10KHz
1.7
1.2
pA/
0.6
THD+N Total Harmonic Distortion + Noise
3Vp-p @ 1KHz
0.000098
0.00011
0.000089
–124.7
–122.8
–117.2
–118.9
–117.6
–114.7
–139.9
-141.9
–133.3
–121.4
–125.3
–124.5
%
HD2
2nd Harmonic Distortion
3Vp-p, 1KHz
dBc
dBc
dBc
dBc
2nd Harmonic Distortion
6Vp-p, 1KHz
HD3
3rd Harmonic Distortion
3Vp-p, 1KHz
3rd Harmonic Distortion
6Vp-p, 1KHz
6.6V VOCM Input Characteristics
VOCM Small Signal Bandwidth
200mVp-p
High Power
Mid Power
Low Power
4.5
2.2
MHz
V/V
mV
0.6
VOCM Gain
1
VOCM Offset Voltage
High Power
Mid Power
±0.97
±0.43
±0.89
1.2 to 5.4
Low Power
VOCM Voltage Range
VOCM Input Resistance
All Power Levels
V
30 to mid
supply
All power levels
KΩ
7
www.national.com
+5V Electrical Characteristics (Note 2)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, Avcl = +1, RF=RG = 1kΩ, Fully differential input, VS = +5V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply at
the temperature extremes.
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Conditions
Units
5V DC Characteristics
VOS
Input Offset Voltage
(RTI)
±3.2
±3.6
High Power
Mid Power
Low Power
±0.2
±0.1
±0.1
±2.0
±2.3
mV
μV/°C
μA
±2.0
±2.3
TCVOS Input Offset Voltage vs.Temperature High Power
±0.7
±0.5
±0.4
(Note 9)
Mid Power
Low Power
IB
Input Bias Current
1.5
1.6
High Power
Mid Power
Low Power
2.5
3.0
3.5
3.7
AVOL
Open Loop Gain
High Power
Mid Power
Low Power
63
71
68
75
75
dB
V
68
CMVR Common Mode Voltage Range
1.15
3.85
3.85
3.85
HP @ CMRR ≥60dB
MP @ CMRR ≥86dB
LP @ CMRR ≥80dB
(Note 10)
1.15
1.15
CMRR Common Mode Rejection Ratio
DC, VOCM=0,VID=0,
ΔVcm=±0.2V
High Power
63
87
82
79
114
114
0.48
1
dB
Mid Power
Low Power
ZIND
CIND
VO
Differential Input Resistance
Differential Input Capacitance
VCM = mid supply
VCM = mid supply
MΩ
pF
Output Swing
(Single Ended)
0.77 to
4.23
High Power
Mid Power
Low Power
0.82
0.82
0.83
4.18
4.18
4.17
0.75 to
4.25
V
0.77 to
4.23
ISHORT
Short-Circuit Current
Output Shorted to mid supply
(Note 3)
High Power
+44 / –25 +72 / –42
mA
dB
Mid Power
Low Power
High Power
Mid Power
Low Power
+34 / –16 +57 / –31
+12 / –5 +23 / –13
PSRR
Power Supply Rejection Ratio
VS ±10%
117
120
111
www.national.com
8
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Supply Current
Conditions
Units
mA
V
IS
VEN=4.375
(Note 11)
VEN=3.125
(Note 11)
VEN=1.875
(Note 11)
15
17
13
7
9
10
3
4
2
PD
Power Down Mode
Enable Time
Disable Voltage Threshold
<1.025
0.50
(Note 11)
0.85
0.90
Shutdown Current
mA
Enable Pin Current
High Power
15
20
22
50
μA
ten
Mid Power
ns
Low Power
5V AC Characteristics
SSBW Small Signal Bandwidth
200mVp-p Differential
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
2V Step, CL = 20pF
High Power
Mid Power
Low Power
114.5
84
MHz
V/μs
ns
28
SR
trIse
tfall
ts
Slew Rate
2Vp-p Differential
(Note 6)
476
366
160
3.2
Rise Time
2Vp-p Differential
4.3
10.8
3.1
Fall Time
2Vp-p Differential
4.1
ns
10.7
0.1% Settling Time
2Vp-p
19
ns
24
48
en
Input Referred Voltage Noise
Input Referred Current Noise
f = 10 kHz
High Power
4.5
nV/
Mid Power
Low Power
4.8
8
In
f = 10 kHz
High Power
1.8
pA/
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
High Power
Mid Power
Low Power
1.2
0.6
THD+N Total Harmonic Distortion + Noise
3Vp-p @ 1KHz
0.000107
0.000114
0.000192
–125.3
–122.6
–117.0
–125.5
–130.0
–128.7
%
HD2
HD3
2nd Harmonic Distortion
3Vp-p, 1KHz
dBc
dBc
3rd Harmonic Distortion
3Vp-p, 1KHz
9
www.national.com
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Symbol
Parameter
Conditions
Units
5V VOCM Input Characteristics
VOCM Small Signal Bandwidth
High Power
Mid Power
Low Power
4.4
2.2
200mVp-p
MHz
V/V
mV
0.56
1
VOCM Gain
VOCM Offset Voltage
High Power
Mid Power
Low Power
±0.46
±0.53
±0.11
VOCM Voltage Range
VOCM Input Resistance
1.15 to
3.85
All Power Levels
All power levels
V
30 to mid
supply
KΩ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics
Tables.
Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >
TA
Note 3: The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated
ambient temperature can exceed the maximum allowable junction temperature of 150°C. Positive number (+) is sourcing, negative number (-) is sinking.
Note 4: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 5: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-
Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 6: Slew Rate is the average of the rising and falling edges.
Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 8: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality
Control (SQC) method.
Note 9: Drift Determined by dividing the change in parameter at temperature extremes by the total temperature change. Value is the worst case of TaMIN to 25°
C and 25°C to TaMAX
.
Note 10: At amplifier inputs.
Note 11: Enable voltage is referred to V- (negative supply voltage).
Note 12: For annotation brevity, “HP”=High Power, “MP”=Medium Power, “LP” =Low Power, “DIS”=Disabled or shut down, “SE”=Single Ended Mode,
“DM”=Differential Mode. See table 1 in Applications section for power setting details. It is also assumed RG = RG1 = RG2
www.national.com
10
Typical Performance Characteristics Unless otherwise specified, TA = 25°C, Avcl = +1, RF=RG = 1kΩ,
fully differential input, VS = +10V, RL = 2 kΩ//20pF differentially, Input CMR and VOCM = mid supply and HP mode unless otherwise
noted.
Frequency Response at 10V
VOCM Frequency Response at 10V
3
0
3
0
-3
-6
-9
HP
-3
-6
HP
MP
-9
Avcl = +1
MP
-12
-12
Vout = 200mVp-p
Differential
LP
ΔVocm = 200mVp-p
LP
-15
-15
1M
10M
100M
1G
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
30140524
30140525
Frequency Response at 6.6V
VOCM Frequency Response at 6.6V
3
0
3
0
-3
-6
HP
-3
-6
HP
MP
-9
-9
MP
Avcl = +1
-12
-12
Vout = 200mVp-p
Differential
LP
ΔVocm = 200mVp-p
LP
-15
-15
1M
10M
100M
1G
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
30140526
30140527
Frequency Response at 5V
VOCM Frequency Response at 5V
3
0
3
0
-3
-6
HP
-3
-6
HP
MP
MP
-9
-9
-12
Avcl = +1
-12
Vout = 200mVp-p
Differential
LP
ΔVocm = 200mVpp
LP
-15
-15
10k
1M
10M
100M
1G
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
30140504
30140505
11
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Distortion at 10V, High Power
-40
Distortion at 6.6V, High Power
-40
f = 1KHz
f = 1KHz
-60
-80
-60
-80
-100
-120
-140
-160
-100
-120
-140
-160
HD2
HD3
HD2
HD3
4
0
2
4
6
8
10 12 14 16 18
0
2
6
8
10
12
DIFFERENTIAL OUTPUT (Vpp)
DIFFERENTIAL OUTPUT (Vpp)
30140506
30140508
30140510
30140507
Distortion at 10V, Mid Power
Distortion at 6.6V, Mid Power
-40
-60
-40
-60
f = 1KHz
f = 1KHz
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
HD2
HD3
HD2
HD3
0
2
4
6
8
10 12 14 16 18
0
2
4
6
8
10
12
DIFFERENTIAL OUTPUT (Vpp)
DIFFERENTIAL OUTPUT (Vpp)
30140509
Distortion at 10V, Low Power
Distortion at 6.6V, Low Power
-40
-40
-60
f = 1KHz
f = 1KHz
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
HD2
HD2
HD3
4
HD3
0
2
4
6
8
10 12 14 16 18
0
2
6
8
10
12
DIFFERENTIAL OUTPUT (Vpp)
DIFFERENTIAL OUTPUT (Vpp)
30140511
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12
Distortion at 5V, High Power
THD+N at 10V
THD+N at 6.6V
THD+N at 5V
-40
-60
f = 1KHz
-80
HD3
-100
-120
-140
-160
HD2
0
1
2
3
4
5
6
7
8
8
8
DIFFERENTIAL OUTPUT (Vpp)
30140512
30140514
30140516
30140563
Distortion at 5V, Mid Power
-40
-60
f = 1KHz
-80
-100
-120
-140
-160
HD2
HD3
0
1
2
3
4
5
6
7
DIFFERENTIAL OUTPUT (Vpp)
30140564
Distortion at 5V, Low Power
-40
-60
f = 1KHz
-80
-100
-120
-140
-160
HD2
HD3
0
1
2
3
4
5
6
7
DIFFERENTIAL OUTPUT (Vpp)
30140565
13
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Voltage Noise at 10V
Current Noise at 10V
100
10
1
100
10
1
HP
HP
MP
MP
LP
LP
Differential Out
Differential Out
Referred to Input
Referred to Input
0.1
1
1
1
10
100
1k
10k
100k
1
1
1
10
100
1k
10k
10k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
30140518
30140519
Voltage Noise at 6.6V
Current Noise at 6.6V
100
10
1
100
10
1
HP
HP
MP
LP
LP
MP
Differential Out
Differential Out
Referred to Input
Referred to Input
0.1
10
100
1k
10k
100k
10
100
1k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
30140520
30140521
Voltage Noise at 5V
Current Noise at 5V
100
10
1
100
10
1
HP
HP
MP
MP
LP
LP
Differential Out
Differential Out
Referred to Input
Referred to Input
0.1
10
100
1k
10k
100k
10
100
1k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
30140522
30140523
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14
Pulse Response at 10V
Pulse Response at 6.6V
1.5
1.0
1.5
1.0
MP
MP
HP
HP
0.5
0.5
0.0
0.0
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
LP
LP
MP
MP
0
40
80
120
160
200
0
40
80
120
160
200
TIME (ns)
TIME (ns)
30140513
30140515
Pulse Response at 5V
1.5
1.0
MP
HP
0.5
0.0
-0.5
-1.0
-1.5
LP
MP
0
20 40 60 80 100120140160180200
TIME (ns)
30140517
15
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Application Section
The LMP8350 is a fully differential voltage feedback amplifier
designed to drive precision differential ADC converters. The
LMP8350, though fully integrated for ultimate balance and
distortion performance, functionally provides three channels.
Two of these channels are the V+ and V− signal path chan-
nels, which function similarly to inverting mode operational
amplifiers and are the primary signal paths.
The enable pin should not be allowed to float. If the enable
pin is not used it can be tied to V+ to select the high power
mode or set with two resistors.
Each power setting has a +/-400mV tolerance at each level,
though it is recommended to keep the set voltage within the
center of the range as performance may vary near the tran-
sition zones.
The third “channel” is the common mode (VOCM) feedback
circuit. This is the circuit that sets the output common mode
as well as driving the V+ and V− outputs to be equal magnitude
and opposite phase, even when only one of the two input
channels is driven. The common mode feedback circuit al-
lows for single ended to differential operation. The output
common mode voltage is set by applying the appropriate volt-
age to the VOCM pin.
During shutdown, both outputs are in a high impedance state,
so the feedback and gain set resistors will then set the input
and output impedance of the circuit. For this reason input to
output isolation will be poor in the disabled state.
The voltage at the EN pin can be generated with a resistive
voltage divider or a buffer connected to a voltage source or a
DAC. The schematic diagram below shows how to generate
EN voltage with a resistive voltage divider.
Values of RA and RB can be calculated to achieve the voltages
in Table 2, however their sum should be below 50kΩ to keep
the voltage at the enable pin stable. Recommended values
for Ra and Rb are given in Table 3.
ENABLE PIN AND POWER MODE SELECTION
The LMP8350 is equipped with a four level enable (EN) pin
to select one of three power modes or shutdown. These
modes are selected by applying the appropriate voltage to the
EN pin.
TABLE 3. Recommended Ra and Rb for Mode Selection
Each power level has a corresponding performance level.
The high power mode will have the best overall BW and dis-
tortion performance, but at the cost of higher supply current
and some DC accuracy. The Low power mode has the lowest
supply current, but with a noticeable loss of AC performance
and output drive capabilities. The mid-power mode provides
the best balance of AC and precision DC specifications. In
disable mode, the amplifier is shutdown and the output stage
goes into a high impedance state. Table 1 summarizes these
performance trade-offs.
Mode
10V
RA=0
RB=inf
6.6V
RA=0
RB=inf
5V
RA=0
RB=inf
VEN
High Power
>7/8 VS
Med Power
Low Power
Shutdown
RA=18K RA=18K RA=18K 5/8 VS
RB=30K RB=30K RB=30K
RA=33K RA=33K RA=33K 3/8 VS
RB=18K RB=18K RB=18K
RA=Inf
RB=0
RA=Inf
RB=0
RA=Inf
RB=0
<1/8 VS
TABLE 1. Performance vs. Power Mode Summary
Mode VS –3dB
HD2
(dBc)
Noise
(nV/ (V/µS)
Hz)
SR
Typ
Vos
(mV)
VOCM PIN AND OUTPUT COMMON MODE SETTING
BW
(MHz)
Output common mode voltage is set by the VOCM pin. Both
outputs will be offset in the same direction (phase) by an
amount equal to the applied VOCM voltage.
10
6.6
5
118
116
114
87
–124.7
–124.7
–125.5
–122.8
–122.8
–122.6
–117.2
–117.2
–117.0
4.6
4.5
4.5
4.8
4.8
4.8
8.0
8.0
8.0
507
488
476
393
376
366
178
166
160
0.6
0.3
0.2
0.08
0.1
0.1
0.1
0.1
0.1
High
Med
Low
The VOCM pin, if left unconnected, will self-bias to mid-supply .
Two internal 60KΩ resistors set this midpoint. These resistors
are shown in Figure 1.
10
6.6
5
85
84
10
6.6
5
31
29
28
To set the mode, internally the voltage at the EN pin is com-
pared against the total supply voltage (VS) and sets the cur-
rent consumption as shown in the table below. The EN pin
voltage is referenced to the V- pin.
TABLE 2. Enable Pin Mode Selection
30140558
VEN
(VS = V+
- V-)
Power VEN
@
VEN
6.6V
@
VEN
5V
@
IS
mA
Mode
10V
FIGURE 1. VOCM Internal Bias Circuit
7/8 * VS
High
Med
Low
Dis
8.75
6.25
3.75
1.25
5.775
4.125
2.475
0.825
4.375 13 to 15
The equivalent resistance looking into the VOCM pin will look
like 30KΩ to mid supply, plus about ±700nA for internal base
currents (which scales with power mode and supply current).
If left floating, the VOCM input should be bypassed to ground
with a 0.1 µF ceramic capacitor.
5/8 * VS
3/8 * VS
1/8 * VS
3.125
1.875
0.625
7 to 9
2 to 3
<1
www.national.com
16
If a different output common mode voltage is desired, the
VOCM pin should be driven by a clean, low impedance source
to override the internal divider resistors. The VOCM pin should
be bypassed to ground with a 0.1 µF ceramic capacitor. It
should be noted that any signal or noise coupling into the
VOCM will be passed as common mode noise and may result
in the loss of dynamic range, degraded CMRR, degraded bal-
ance and higher distortion. The VOCM pin is primarily intended
as a DC bias path and is not intended for use as a signal path.
When fed with a differential signal, the LMP8350 provides
excellent distortion, balance and common mode rejection,
provided the resistors RF, RG and any input termination re-
sistors (RT) are well matched and strict symmetry is observed
in board layout. With a DC CMRR of over 80 dB, the DC and
low frequency CMRR of most circuits will be dominated by the
external resistor matching and board trace resistance. At low
distortion levels, board layout symmetry and supply bypass-
ing become a factor as well. It is assumed throughout this
document that RF1 = RF2 and RG1 = RG2 for maximum channel
symmetry
For applications that can tolerate slight shifts in the VOCMvolt-
age over temperature, it is also possible to use a single
resistor to program the VOCM voltage by paralleling one of the
internal resistors to change the ratio.
Precision resistors of at least 0.1% accuracy or better are
recommended and careful board layout will also be required
for optimum performance.
FULL BANDWIDTH LIMITATIONS
Operation with RF feedback resistors as low as 300 ohms is
possible in the High and Medium power modes. This will
slightly improve the noise and bandwidth results. However,
feedback resistors with RF values of less than 1KΩ should be
avoided in the low power mode due to the reduced output
drive current capabilities. If low value resistors (<300Ω) must
be used in the low power mode, the maximum output swing
will need to be limited.
Although the LMP8350 has a unity gain bandwidth of over
200MHz, it is primarily intended for lower sample rate, high-
precision ADC’s with baseband analog input signal band-
widths in the DC to <1MHz range (not to be confused with
sampling rate). The LMP8350's high open loop bandwidth is
used to provide ultra low-distortion and fast settling times.
Maximum power bandwidth is limited by the internal output
common mode feedback path, which is limited to 1MHz to
5MHz. Operation with input signals above 1MHz with near full
output swings can cause random shifts in the output common
mode and possible AC instabilities. For this reason, the
LMP8350 is not intended to be used wide bandwidth (>1MHz)
signal paths. Single ended inputs rely on the common mode
signal path and will have a bandwidth limited to that of the
internal common mode buffer.
The resistors RO help keep the amplifier stable when pre-
sented with a load CL, as is common when driving an analog
to digital converter (ADC).
FULLY DIFFERENTIAL OPERATION
The LMP8350 will perform best when used with split supplies
and in a fully differential configuration. See Figure 2 for rec-
ommend circuits.
30140551
FIGURE 3. Fully Differential Cable Driver
With up to 15 VPP differential output voltage swing and 80 mA
of linear drive current, the LMP8350 makes an excellent pre-
cision cable driver as shown in Figure 3. The LMP8350 is also
suitable for driving differential cables from a single ended
source.
30140550
FIGURE 2. Typical Fully Differential Application
The circuit shown in Figure 2 is a typical fully differential ap-
plication as might be used to drive a Sigma Delta ADC. In this
circuit, closed loop gain, is (AV) = VOUT/ VIN = RF/RG, where
RF=RF1=RF2 and RG=RG1=RG2. For all the applications in this
data sheet , VIN is presumed to be the voltage presented to
the circuit by the signal source. For differential signals this will
be the difference of the signals on each input (which will be
double the magnitude of each individual signal), while in sin-
gle ended inputs it will just be the driven input signal.
17
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30140555
FIGURE 5. Relating AV to Input/Output Common Mode
Voltages
In Figure 5 the differential closed loop gain is = AV= RF/RG.
Please note that in single ended to differential operation VIN
is measured single ended while VOUT is measured differen-
tially. This means that gain is really one-half, or 6 dB, less
when measured on either of the output pins separately.
30140552
FIGURE 4. Single Ended in Differential Out
SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT
Figure 4 shows a typical application where an LMP8350 is
used to produce a differential signal from a single ended
source. It should be noted that compared to differential input,
using a single ended input will reduce gain by 1/2, so that the
closed loop gain will be; Gain = AV = 0.5 * RF/RG.
In single ended input operation the output common mode
voltage is set by the VOCM pin. Also, In this mode the common
mode feedback circuit must recreate the signal that is not
present on the unused differential input pin. The common
mode feedback circuit is responsible for ensuring balanced
output with a single ended input.
Balance error is defined as the amount of input signal that
couples into the output common mode. It is measured as the
undesired output common mode swing divided by the signal
on the input. Balance error can be caused by either a channel
to channel gain error, or phase error. Either condition will pro-
duce a common mode shift. As mentioned in the previous
FULL BANDWIDTH LIMITATIONS section, the overall band-
width is limited due to the VOCM buffer bandwidth limitations
in this configuration.
30140556
FIGURE 6. AC Coupled for Single Supply Operation
Supply and VOCM pin bypassing are also critical in this mode
of operation.
POWER SUPPLY AND VOCM BYPASSING
The LMP8350 requires supply bypassing capacitors as
shown in Figure 7 and Figure 8 for fastest settling time and
overall stability.
SINGLE SUPPLY OPERATION
As shown in Figure 5, the input common mode voltage is less
than the output common voltage. It is set by current flowing
through the feedback network from the device output. The in-
put common mode voltage range places constraints on gain
settings. Possible solutions to this limitation include AC cou-
pling the input signal, using split power supplies and limiting
stage gain. AC coupling with single supply is shown in Figure
6.
VICM= Input common mode voltage = (V+IN+V−IN)/2.
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18
sure stability. In addition, the resistors form part of a low pass
filter which helps to provide anti alias and noise reduction
functions. The CS capacitor helps to smooth the current
spikes associated with the internal switching circuits of the
ADC and also are a key component in the low pass filtering
of the ADC input. The capacitor should be a low distortion
capacitor, such as an NPO, to avoid causing significant dis-
tortion terms. In the circuit of Figure 9, the cutoff frequency of
the filter is 1/ (2*π*(RISO1+RISO2) *(CS + CCONVERTER)), which
should be slightly less than the sampling frequency. Note that
the ADC input capacitance must be factored into the frequen-
cy response of the input filter. Also as shown in Figure 9, the
input capacitance to many ADCs is variable based on the
clock cycle. For lower speed, precision ADC's, the external
cap is generally sized to ten times the internal sampling ca-
pacitor value. See the data sheet for your particular ADC for
details.
30140553
FIGURE 7. Split Supply Bypassing Capacitors
The 0.01 µF and 0.1 µF capacitors should be leadless surface
mount (SMT) ceramic capacitors and should be no more than
3 mm from the supply pins. The SMT capacitors should be
connected directly to a ground plane. Thin traces or small vias
will reduce the effectiveness of bypass capacitors.
30140557
FIGURE 9. Driving an ADC
The amplifier and ADC should be located as close together
as possible. Both devices require that the filter components
be in close proximity to them. The amplifier needs to have
minimal parasitic loading on the output traces, and the ADC
is sensitive to high frequency noise that may couple in on its
input lines. Some high performance ADCs have an input
stage that has a bandwidth of several times its sample rate.
The sampling process results in all input signals presented to
the input stage mixing down into the Nyquist range (DC to Fs/
2). See AN-236 for more details on the subsampling process
and the requirements this imposes on the filtering necessary
in your system.
30140554
FIGURE 8. Single Supply Bypassing Capacitors
Also shown in both figures is a capacitor from the VOCM pin to
ground. The VOCM pin sets the output common mode voltage.
Any noise on this input is transferred directly to the output.
The VOCM pin should be bypassed even if the pin in not used.
There is an internal resistive divider on chip to set the output
common mode voltage to the mid point of the supply pins. The
impedance looking into this pin is approximately 30 kΩ. If a
different output common mode voltage is desired drive this
pin with a clean, accurate voltage reference.
CAPACITIVE DRIVE
As noted in the Driving ADC section, capacitive loads should
be isolated from the amplifier output with small valued resis-
tors. This is particularly the case when the load has a resistive
component that is 500Ω or higher. A typical ADC has capac-
itive components of around 8 to 18pF, and the resistive com-
ponent could be 1000Ω or higher. If driving a transmission
line, such as a twisted pair, using matching resistors will be
sufficient to isolate any subsequent capacitance.
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog to digital converters (ADC) present challenging load
conditions. They typically have high impedance inputs with
large and often variable capacitive components. As well,
there are usually current spikes associated with switched ca-
pacitor or sample and hold circuits. Figure 9 shows a typical
circuit for driving an ADC. The two resistors serve to isolate
the capacitive loading of the ADC from the amplifier and en-
19
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POWER DISSIPATION
applied to the input pins. Using the shutdown mode is one
way to conserve power and still prevent unexpected opera-
tion.
The LMP8350 is optimized for maximum performance in the
small form factor of the standard SOIC package, and is es-
sentially a dual channel amplifier. To ensure maximum output
drive and highest performance, thermal shutdown is not pro-
vided. Therefore, it is of utmost importance to make sure that
the TJMAX of 150°C is never exceeded due to the overall power
dissipation.
BOARD LAYOUT
While the main signal path frequencies may be fairly low, the
ultra-low distortion and settling time specifications rely on
wide internal bandwidths. Precautions usually taken for high
speed amplifiers should be followed to maintain the best set-
tling times and lowest distortion specifications. In order to get
maximum benefit from the differential circuit architecture,
board layout and component selection is very critical. The cir-
cuit board should have low a inductance ground plane and
well bypassed broad supply lines. External components
should be leadless surface mount types. The feedback net-
work and output matching resistors should be composed of
short traces and precision resistors (0.1%). The output match-
ing resistors should be placed within 3-4 mm of the amplifier
as should the supply bypass capacitors.
Follow these steps to determine the Maximum power dissi-
pation for the LMP8350:
1. Calculate the quiescent (no-load) power: PAMP = ICC
*
(VS), where VS = V+ - V−. (Be sure to include any current
through the feedback network if VOCM is not mid rail.)
2. Calculate the RMS power dissipated in each of the output
stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms ((VS
− V−OUT) * I−OUT) , where VOUT and IOUT are the voltage
and the current measured at the output pins of the
differential amplifier as if they were single ended
amplifiers and VS is the total supply voltage.
The LMP8350 is sensitive to parasitic capacitances on the
outputs. Ground and power plane metal should be removed
from beneath the amplifier and from beneath RF and RG.
3. Calculate the total RMS power: PT = PAMP + PD.
The maximum power that the LMP8350 package can dissi-
pate at a given temperature can be derived with the following
equation:
With any differential signal path symmetry is very important.
Even small amounts of asymmetry will contribute to distortion
and balance errors. Special attention should be paid to where
the bypass capacitors are grounded, as this also affects set-
tling and distortion performance.
PMAX = (150° – TAMB)/ θJA, where TAMB = Ambient temperature
(°C) and θJA = Thermal resistance, from junction to ambient,
for a given package (°C/W). For the SOIC package θJA is 150°
C/W.
The LMH730154 evaluation board is an example of good lay-
out techniques. Evaluation boards are available for purchase
through the product folder on National’s web site.
NOTE: If VOCM is not 0V then there will be quiescent current
flowing in the feedback network. This current should be in-
cluded in the thermal calculations and added into the quies-
cent power dissipation of the amplifier.
EVALUATION BOARD
Generally, a good high frequency layout will keep power sup-
ply and ground traces away from the inverting input and
output pins. Parasitic capacitances on these nodes to ground
will cause frequency response peaking and possible circuit
oscillations (see Application Note OA-15 for more informa-
tion). National Semiconductor suggests the following evalua-
tion boards as a guide for high frequency layout and as an aid
in device testing and characterization:
ESD PROTECTION
The LMP8350 is protected against electrostatic discharge
(ESD) on all pins. The LMP8350 will survive 2000V Human
Body model and 200V Machine model events. Under normal
operation the ESD diodes have no effect on circuit perfor-
mance. There are occasions, however, when the ESD diodes
will be evident. If the LMP8350 is driven by a large signal while
the device is powered down the ESD diodes will conduct . The
current that flows through the ESD diodes will either exit the
chip through the supply pins or will flow through the device,
hence it is possible to power up a chip with a large signal
Device
Package
Evaluation Board
Part Number
LMH730154
LMP8350MA
SOIC
www.national.com
20
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
21
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Notes
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