LMP92018CISQX [TI]
Analog System Monitor and Controller; 模拟系统监视器和控制器
| 型号： | LMP92018CISQX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Analog System Monitor and Controller |
| 文件： | 总34页 (文件大小：1100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMP92018
LMP92018 Analog System Monitor and Controller
Literature Number: SNAS514A
November 17, 2011
LMP92018
Analog System Monitor and Controller
1.0 General Description
2.0 Features
LMP92018 is a complete analog monitoring and control circuit
which integrates an eight channel 10-bit Analog-to-Digital
Converter (ADC), four 10-bit Digital-to-Analog Converters
(DACs), an internal reference, an internal temperature sen-
sor, a12-bit GPIO port, and a 10MHz SPI interface.
8 Analog Voltage Monitoring Channels
10-bit ADC with programmable input MUX
■
■
■
Internal/External Reference
Tolerates high-source impedance at lower sampling rates
4 Programmable Analog Voltage Outputs
The eight channels of the ADC can be used to monitor rail
voltages, current sense amplifier outputs, health monitors or
sensors while the four DACs can be used to control PA (Pow-
er Amplifier) bias points, control actuators, potentiometers,
etc.
Four 10-bit DACs
■
■
■
Internal/External Reference
Drives loads up to 1nF
Voltage Reference
Both the ADC and DACs can use either the internal 2.5V ref-
erence or an external reference independently allowing for
flexibility in system design.
User-selectable source: external or internal
■
■
Internal Reference 2.5V
The built-in digital temperature sensor enables accurate
(±2.5°C) local temperature measurement whose value is cap-
tured in the user accessible register.
Temperature Sensor
±2.5°C Accuracy
■
12-bit GPIO Port
The LMP92018 also includes a 12-bit GPIO port which allows
for the resources of the microcontroller to be further extended,
thus providing even more flexibility and reducing the number
of signal interfacing to the microcontroller.
Each bit individually programmable
■
■
User-selectable rail
SPI-Compatible Bus
Both the GPIO port and the SPI compatible interface have
independent supply pins enabling the LMP92018 to interface
with low voltage microcontrollers.
User-selectable rail
■
LLP-36 package (6mm x 6mm, 0.5 mm pitch)
The LMP92018 is available in a space saving 6mm x 6mm
LLP 36-pin package and is specified over the full -30°C to
+85°C temperature range.
3.0 Applications
Communication Infrastructure
■
■
System Monitoring and Control
Industrial Monitoring and Control
■
4.0 Block Diagram
30152336
National Semiconductor® is a registered trademark of National Semiconductor Corporation.
© 2011 Texas Instruments Incorporated
301523
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5.0 Typical Application
30152306
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2
30152336
to control bias conditions of external circuits, position of ser-
vos, etc.
6.0 Overview
The LMP92018 has a flexible, feature-rich functionality which
makes it ideally suited for many analog monitoring and control
applications, for example, base-station PA subsystems. This
device provides the analog interface between a pro-
grammable supervisor, such as a microcontroller, and an
analog system whose behavior is to be monitored and con-
trolled by the supervisor.
6.3 INTERNAL DIGITAL TEMPERATURE SENSOR
An on-board digital temperature sensor is available to report
the device's own temperature. The temperature sensor output
is stored in the internal register for user readback via the SPI
interface.
6.4 INTERNAL VOLTAGE REFERENCE SOURCE
To facilitate the analog monitoring functionality, the device
contains a single 10-bit ADC preceded by a 8-input multiplex-
or.
The user can choose to enable the internal reference of 2.5V
to use with the ADC and/or DACs. The internal reference
source can also drive an external load.
The analog control functionality is served by four 10-bit volt-
age output DACs.
6.5 12-BIT GENERAL PURPOSE I/O
Additional digital monitoring and control can be realized via
the General Purpose I/O port GPIO[11:0].
The GPIO port can be used to expand the microcontroller ca-
pabilities. This port is memory mapped to the internal register,
which in turn is accessible via the SPI interface. Each bit is
individually programmable as an input or an output
Two more blocks are present for added functionality: a local
temperature sensor and an internal reference voltage gener-
ator.
6.6 SPI INTERFACE
6.1 8-CHANNEL ANALOG SENSE WITH 10-BIT ADC
The microcontroller communicates with LMP92018 via a pop-
ular SPI interface. This interface provides the user full access
to all Data, Status and Control registers of the device.
The user can monitor up to 8 external voltages with the 10-bit
ADC and its 8-channel input MUX. Typically these voltages
will be generated by the analog sensors, instrumentation am-
plifiers, current sense amplifiers, or simply resistive dividers
if high potentials need to be measured.
6.2 PROGRAMMABLE ANALOG CONTROL VOLTAGE
OUTPUTS
Four identical individually programmable 10-bit DAC blocks
are available to generate analog voltages, which can be used
3
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7.0 Connection Diagram
30152308
36–Pin LLP36 (SQA36A)
Top View
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4
8.0 Pin Descriptions
Name
VDD
Pin
1
Function
Supply rail
GPIO rail
ESD Structures
VGPIO
4
VIO
5
SPI rail
GND
DAP
2, 3 14
*
Device Ground
Die Attach Pad. For best thermal
conductivity and best noise immunity
DAP should be soldered to the PCB pad
which is connected directly to circuit
common node (GND).
IN[7:0]
35:28
Analog input
OUT[3:0]
DOUT
10:13
9
Analog output
SPI Data Output
General Purpose Digital I/O. Logic level
is referenced to VGPIO pin.
GPIO[11:0]
15:18; 20:27
CSB
SCLK
DIN
6
7
SPI Chip Select, Active LO
SPI Data Clock
8
SPI Data Input
DRBYB
19
Data Ready, open-drain active LO
ADC/DAC Voltage Reference Input or
Output
REF
36
9.0 Ordering Information
Order Number
LMP92018CISQ
LMP92018CISQX
NS Package Number
Transport Media
Tape-and reel: 1000 pieces
Tape-and reel: 2500 pieces
SQA36A
5
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Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Applications .................................................................................................................................... 1
4.0 Block Diagram ................................................................................................................................ 1
5.0 Typical Application ........................................................................................................................... 2
6.0 Overview ........................................................................................................................................ 3
6.1 8-CHANNEL ANALOG SENSE WITH 10-BIT ADC ....................................................................... 3
6.2 PROGRAMMABLE ANALOG CONTROL VOLTAGE OUTPUTS .................................................... 3
6.3 INTERNAL DIGITAL TEMPERATURE SENSOR .......................................................................... 3
6.4 INTERNAL VOLTAGE REFERENCE SOURCE ........................................................................... 3
6.5 12-BIT GENERAL PURPOSE I/O ............................................................................................... 3
6.6 SPI INTERFACE ...................................................................................................................... 3
7.0 Connection Diagram ........................................................................................................................ 4
8.0 Pin Descriptions .............................................................................................................................. 5
9.0 Ordering Information ........................................................................................................................ 5
10.0 Absolute Maximum Ratings ............................................................................................................. 7
11.0 Operating Conditions (Note 1, Note 2) ............................................................................................... 7
12.0 Electrical Characteristics ................................................................................................................ 7
13.0 SPI Interface Timing Diagram ........................................................................................................ 11
14.0 Typical Performance Characteristics .............................................................................................. 12
15.0 Instruction Set ............................................................................................................................. 14
15.1 TEMPERATURE SENSOR CONFIGURE ................................................................................ 14
15.2 REFERENCE CONFIGURE ................................................................................................... 14
15.3 DAC CONFIGURE ............................................................................................................... 15
15.4 UPDATE ALL DACs ............................................................................................................. 15
15.5 GENERAL CONFIGURATION ............................................................................................... 15
15.6 GPIO CONFIGURE .............................................................................................................. 16
15.7 STATUS ............................................................................................................................. 16
15.8 GPI STATE ......................................................................................................................... 16
15.9 GPO DATA .......................................................................................................................... 17
15.10 VENDOR ID ....................................................................................................................... 17
15.11 VERSION/STEPPING ......................................................................................................... 17
15.12 DAC DATA REGISTER ACCESS ......................................................................................... 18
15.13 ADC INPUT MUX SELECT DATA READ COMMAND .............................................................. 18
15.14 TEMPERATURE SENSOR OUTPUT REGISTER ................................................................... 19
15.15 NOOP — No Operation ....................................................................................................... 19
16.0 Functional Description ................................................................................................................. 20
16.1 ANALOG SENSE SUBSYSTEM ............................................................................................. 20
16.1.1 Sampling and Conversion ............................................................................................ 20
16.1.2 Sampling Transient ..................................................................................................... 20
16.1.3 Conversion Sequence ................................................................................................. 20
16.1.4 ADC Reference Selection ............................................................................................ 21
16.2 PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM ............................................................... 22
16.2.1 DAC Core .................................................................................................................. 22
16.2.2 DAC Reference Selection ............................................................................................ 22
16.3 DIGITAL TEMPERATURE SENSOR ....................................................................................... 24
16.4 INTERNAL VOLTAGE REFERENCE SOURCE ........................................................................ 25
16.5 GENERAL PURPOSE DIGITAL I/O ........................................................................................ 26
16.6 SERIAL INTERFACE ............................................................................................................ 27
16.6.1 SPI Write ................................................................................................................... 27
16.6.2 SPI Read ................................................................................................................... 27
16.6.3 SPI Daisy Chain ......................................................................................................... 28
17.0 Application Circuit Example ........................................................................................................... 29
18.0 Physical Dimensions .................................................................................................................... 30
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6
10.0 Absolute Maximum Ratings (Note
11.0 Operating Conditions (Note 1, Note
1, Note 2)
2)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Operating Ambient Temperature
VDD Voltage Range
VIO Voltage Range
VGPIO Voltage Range
DAC Output Load C
θJA
−40°C to 125°C
4.75V to 5.25V
1.8V to VDD
1.8V to VDD
0nF to 1nF
VDD Relative to GND
VIO Relative to GND
VGPIO Relative to GND
Voltage between any 2 pins (Note 3)
Current in or out of any pin (Note 3)
Current through VDD
−0.3V to 6.0V
−0.3V to VDD
−0.3V to VDD
6.0V
25.2°C/W
2.4°C/W
θJC
5mA
For Soldering specifications:
32mA, TA = 125°C
44mA, TA = 85°C
See
product
folder
at
www.national.com
and
www.national.com/ms/MS-SOLDERING.pdf.
Current through VGPIO
Current through GND
20mA, TA = 125°C
54mA, TA = 125°C
66mA, TA = 85°C
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
ESD Susceptibility(Note 4)
Human Body Model
Machine Model
2500V
200V
Charged Device Model
1500V
12.0 Electrical Characteristics
Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over the
temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output CL = 200 pF
unless otherwise noted.
Symbol
ADC CHARACTERISTICS
Resolution with No Missing
Parameter
Conditions
Min
Typ
Max
Units
10
10
Bits
Codes
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
Offset Error
−0.9
−1
+1
1
LSB
OE
−2
+2
OEDRIFT
OEMTCH
GE
Offset Error Temperature Drift
Offset Error Match (Note 9)
Gain Error
0.001
0.001
LSB/°C
LSB
−1
−2
1
2
GEDRIFT
GEMTCH
SINAD
THD
Gain Error Temperature Drift
Gain Error Match (Note 9)
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
LSB/°C
LSB
−1
58
1
10 kHz Sine Wave
10 kHz Sine Wave, up to 5th harmonic
10 kHz Sine Wave
dB
dBc
dB
−69
70
SFDR
Offset Error change with VDD
Gain Error change with VDD
−150
−150
PSRR
Power Supply Rejection Ratio
DAC CHARACTERISTICS
Resolution
10
10
10
Bits
Bits
Monotonicity
RL = 100k
RL = 100k
RL = 100k
RL = 100k
DNL
INL
Differential Non-Linearity
−0.5
−2
+0.5
+2
LSB
Integral Non-Linearity
OE
Offset Error(Note 6)
10
mV
OEDRIFT
Offset Error Temperature Drift
1
µV/°C
VDD = 5.25V, REF=5, RL = 100k,
CODE=3FFh
FSE
GE
Full-Scale Error
-0.4
+0.3
+0.2
%FS
RL = 100k
Gain Error(Note 7)
−0.2
7
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Symbol
Parameter
Conditions
RL = 100k
Min
Typ
1.4
7
Max
Units
GEDRIFT
Gain Error Temperature Drift
ppm/° C
IOUT = 200 µA
IOUT = 1mA
IOUT = 200 µA
IOUT = 1mA
RL = 100k
ZCO
FSO
Zero Code Output
mV
V
31
4.975
4.975
4.975
Full Scale Output at code 3FFh
Output Short Circuit Current
(Source) (Note 5)
VDD = 5V, OUT = 0V,
Input Code =3 FFh
IOS
IOS
−67
76
Output Short Circuit Current
(Sink) (Note 5)
VDD = 5V, OUT = DREF,
Input Code = 000h
mA
pF
TA = 85° C
10
Continuous Output Current per
Channel (to prevent damage)
IO
CL
TA = 125° C
6.5
Maximum Load Capacitance
DC Output Impedance
1000
1.7
RL = 2k or ∞
Enabled
Ω
ROUT
Disabled
>20
MΩ
ANALOG INPUT CHARACTERISTICS
VIN
FS Input Range
REF
+1
V
ILEAK
ADC in HOLD or Power Down
µA
−1
In Acquisition mode
In Conversion mode
33
3
CINA
Input Capacitance
pF
V
REFERENCE CHARACTERISTICS
ADC Reference Input Range
2.5
2.5
VDD
VDD
DAC Reference Input Range
DAC Reference Input Resistance
DAC Reference Input Current
50
kΩ
µA
125
1
ADC Reference Current, during
conversion, average value
IVREF(ADC)
IVREF(PD)
External Reference, REF = VDD
µA
REF pin Current in Powerdown
REF Output Voltage
10
µA
V
2.5
Internal Reference Tolerance
REF Output Temperature Drift
REF Output Maximum Current
REF Output Load Regulation
REF Output Rail Regulation
–0.15
0.15
–0.6
%
17
1
ppm/°C
mA
%
±0.04
%
4.75V≤VDD≤5.25V
TEMPERATURE SENSOR
Resolution
0.0625
°C
°C
Temperature Error (Note 9)
DIGITAL INPUT CHARACTERISTICS (GPIO[11:0])
−40°C to +125°C
−2.5
+2.5
VIH
Input HIGH Voltage
0.7x VGPIO
V
0.3x
VGPIO
VIL
Input LO Voltage
Hysteresis
250
±0.005
4
mV
µA
pF
IIND
Digital Input Current
Input Capacitance
±1
CIND
DIGITAL INPUT CHARACTERISTICS (CSB, DIN, SCLK)
VIH
VIL
Input HIGH Voltage
Input LO Voltage
Hysteresis
0.7 x VIO
V
V
0.3 x VIO
±1
250
mV
µA
IIND
Digital Input Current
±0.005
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Symbol
Parameter
Input Capacitance
Conditions
Min
Typ
Max
Units
CIND
4
pF
DIGITAL OUTPUT CHARACTERISTICS (GPIO[11:0])
IOUT = 200 µA
0.01
0.07
0.4
0.4
VOL
Output LO Voltage
V
V
IOUT = 1.6 mA
VGPIO = VDD = 5V
IOUT = 200µA
VGPIO-0.2
VGPIO-0.5
VOH
Output HI Voltage
IOUT = 1.6 mA
VGPIO = VDD = 5V
TRI-STATE Output Leakage
Current
IOZH, IOZL
COUT
VGPIO=VDD
±5
µA
pF
Output Capacitance
4
DIGITAL OUTPUT CHARACTERISTICS (DOUT)
IOUT = 200 µA
0.01
0.07
0.4
0.6
V
V
VOL
Output LO Voltage
IOUT = 1.6 mA
VIO = 3.3V
IOUT = 200 µA
VIO-0.2
VIO-0.5
VOH
Output HI Voltage
V
IOUT = 1.6 mA
VIO = 3.3V
TRI-STATE Output Leakage
Current
IOZH, IOZL
COUT
VGPIO = 1.8V =VDD
±5
µA
pF
Output Capacitance
4
DIGITAL OUTPUT CHARACTERISTICS (DRDYB)
IOUT = 1.6 mA
VOH_MAX
Maximum Output HI Voltage
VIO-0.5
µA
V
VIO = 3.3V to VDD
VOL
Output LO Voltage
Force 0V or VDD
0.01
5
POWER SUPPLY CHARACTERISTICS
VDD
VGPIO
VIO
Supply Voltage Range
GPIO Rail Range
SPI Rail Range
4.75
1.8
5.5
VDD
VDD
V
1.8
Supply Current, Conversion
Mode
IDD
4
mA
OUT[3:0] pins RL = ∞
OUT[3:0] pins RL = ∞
Power Consumption, Conversion
Mode
PWRCONV
21
mW
Supply Current, Power-Down
Mode
IPD
50
µA
V
VPOR
Power-On Reset (Note 8)
1.9
2.7
AC ELECTRICAL CHARACTERISTICS
tTRACK
tHOLD
t8+9×t1
15×t1
ADC Track Time
ADC Hold Time
Dictated by SPI bus activity
Dictated by SPI bus activity
µs
µs
25%FS to 75%FS code change,
RL = 2K, CL = 200 pF
ts
DAC Settling Time (Note 9)
20
µs
tCONV
Temperature Conversion Time
25.85
ms
SPI TIMING CHARACTERISTICS
SPI Clock Period during ADC
data access
t1
t1
178
178
12500
5000
ns
ns
SPI Clock Period during
Temperature Sensor access
SPI Clock Period for all
transactions not involving ADC or
Temperature Sensor
t1
tr
100
ns
SCLK Rise Time
2
ns
9
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Symbol
Parameter
SCLK Fall Time
Conditions
Min
Typ
Max
2
Units
ns
tf
t2
t3
SCLK HIGH Time
SCLK LOW Time
8
8
ns
ns
CSB set-up time to SCLK falling
edge
t4
5
ns
t5
t6
DIN Set-up time
5
4
ns
ns
DIN Hold time
CSB hold time after 24th falling
edge of SCLK
t7
t8
10
ns
ns
CSB High Pulse Width
30
10
5
CL=30pF, VIO=1.8
DOUT hold time after SCLK
Rising Edge
tDH
ns
CL=30pF, 3V≤VIO≤5.25V
DOUT Delay after SCLK Rising
Edge
tDD
t11
tDOZ
tZDO
CL=30pF
40
ns
ns
ns
ns
SCLK Delay after CSB Rising
Edge
3
5
CSB Rising Edge to DOUT TRI-
STATE
4
10
14
CSB Falling Edge to DOUT
active
sink/source 200uA, CL=150pF
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds power supplies (VIN < GND or VIN > VDD), the current at that pin must not exceed 5mA, and the
voltage (VIN) at that pin relative to any other pin must not exceed 6.0V. See Pin Descriptions for additional details of input circuit structures.
Note 4: The Human Body Model (HBM) is a 100 pF capacitor charged to the specified voltage then discharged through a 1.5k resistor into each pin. The Machine
Model (MM) is a 200 pF capacitor charged to specified voltage then discharged directly into each pin. The Charged Device Model (CDM) is a specified circuit
characterizing an ESD event that occurs when a device acquires charge through some triboelectric (frictional) or electrostatic induction process and then abruptly
touches a grounded object or surface.
Note 5: Indicates the typical internal short circuit current limit. Sustained operation at this level will lead to device damage.
Note 6: DAC Offset is the y-intercept of the straight line defined by DAC output at code 0d12 and 0d1011points of the measured transfer characteristic.
Note 7: DAC Gain Error is the difference in slope of the straight line defined by DAC output at code 0d12 and 0d1011 points of transfer characteristic, and that
of the ideal characteristic.
Note 8: During the power up the supply rail must ramp up beyond VPOR MIN for the device to acquire default state. After the supply rail has reached the nominal
level, the rail can drop as low as VPOR MAX for the current state to be maintained.
Note 9: Device Specification is guaranteed by characterization and is not tested in production.
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13.0 SPI Interface Timing Diagram
30152309
30152310
30152311
30152312
11
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14.0 Typical Performance Characteristics
ADC: DNL
ADC: INL
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
256
512
768
1024
0
256
512
768
1024
OUTPUT CODE
OUTPUT CODE
30152361
30152360
DAC: DNL
DAC: INL
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
256
512
INPUT CODE
768
1024
0 1002003004005006007008009001000
INPUT CODE
30152365
30152364
ADC: DNL vs. Temperature
ADC: INL vs. Temperature
0.5
0.5
Min INL
Max INL
Min DNL
Max DNL
0.4
0.3
0.4
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-30
-10
10
30
50
70
90
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
30152363
30152362
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12
DAC: DNL vs Temperature
DAC: INL vs Temperature
0.5
0.4
0.5
0.4
Min DNL
Max DNL
Min INL
Max INL
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-30
-10
10
30
50
70
90
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
30152366
30152367
OUTx Output Load Regulation
20
Temperature Sensor Error
1.5
1.0
0.5
0.0
-0.5
15
10
5
0
-5
-10
-15
-20
-10 -8 -6 -4 -2
0
2
4
6
8
10
-40 -20
0
20 40 60 80 100 120
DAC OUTPUT CURRENT (mA)
TEMPERATURE (°C)
30152368
30152371
Internal Reference Output
Temperature Drift
15
10
5
0
-5
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
30152370
13
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15.0 Instruction Set
The following is a complete listing of the instruction set supported by the LMP92018. Where applicable the default state or register
content is indicated in bold type.
The digital interface (SPI) protocol is described in Section 16.6 SERIAL INTERFACE. The interface timing diagram is in Section 13.0
SPI Interface Timing Diagram
NOTE: the tables in following sections detail the data transfers of 2 subsequent SPI frames . The FRAME 1 column shows
the user input into pin DIN of the device. The FRAME 2 column in the device output at DOUT.
15.1 TEMPERATURE SENSOR CONFIGURE
A single bit, TSS, controls the mode of operation of the internal temperature sensor. The bit can be set and tested via the SPI
transactions shown in the following table. The internal temperature sensor is described in Section 16.3 DIGITAL TEMPERATURE
SENSOR.
FRAME 1: DIN
Payload
15:1
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
0
23
15:1
0
Bit→
READ
WRITE
1
0
0010000
0010000
x
x
1
0
0010000
0010000
000000000000000
000000000000000
TSS
0
000000000000000
TSS
x
Don't Care
1: Temperature Sensor in Continuous Conversion Mode
TSS
0: Temperature Sensor In One Shot Mode
15.2 REFERENCE CONFIGURE
The internal reference mode of operation is controlled by a 3 bit sequence, CREF. The sequence can be set and tested via the
SPI transactions shown in the following table. The reference block is described in Section 16.4 INTERNAL VOLTAGE REFERENCE
SOURCE.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
15:3
2:0
23
15:3
2:0
Bit→
READ
WRITE
1
0
0010001
0010001
x
x
1
0
0010001
0010001
0000000000000
0000000000000
CREF
000
0000000000000
CREF
x
Don't care
Reference Mode Selector
000: AREF external, DREF internal
001: AREF and DREF internal; REF pin is internally
disconnected
010: AREF and DREF external
CREF 011: AREF internal, DREF external
100: Deep Sleep
101: AREF and DREF internal; REF driven by internal
reference
110: Deep Sleep
111: Deep Sleep
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14
15.3 DAC CONFIGURE
The individual DACs can be enabled by setting a corresponding bit in the 4–bit CDAC word. The CDAC word can be set and tested
via the SPI transactions shown in the following table. The DAC block is described in Section 16.2 PROGRAMMABLE ANALOG
OUTPUT SUBSYSTEM.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
15:4
3:0
23
15:4
3:0
Bit→
READ
WRITE
1
0
0011000
0011000
x
x
1
0
0011000
0011000
000000000000
000000000000
CDAC
0000
000000000000
CDAC
x
Don't care
1: enables DAC corresponding to bit position
CDAC 0: disables corresponding DAC
e.g. CDAC=[0101] enables DAC2 and DAC0
15.4 UPDATE ALL DACs
All 4 DAC channels' outputs can be simultaneously set to the same level corresponding to a 10–bit DDATA code. The sequence
in the following table provides a WRITE only functionality. The DAC block is described in Section 16.2 PROGRAMMABLE ANALOG
OUTPUT SUBSYSTEM.
FRAME 1: DIN
FRAME 2: DOUT
Payload
11:2
0000000000 00
Command
22:16
Payload
11:2
Command
22:16
23
15:12
1:0
23
15:12
1:0
Bit→
WRITE
0
0011001
0000
DDATA
00
0
0011001
0000
x
Don't care
DDATA will be loaded into all all DACs' input registers
simultaneously. DDATA is a 10–bit unsigned integer.
DDATA
15.5 GENERAL CONFIGURATION
The device can indicate to the new ADC conversion data availability via the DRDYB pin. This functionality is enabled by setting
the internal DRDY bit. The bit can be set and tested via the SPI transactions shown in the following table. Details of the DRDYB
pin functionality are described in Section 16.1.3 Conversion Sequence and Section 16.3 DIGITAL TEMPERATURE SENSOR
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
15:1
0
23
15:1
0
Bit→
READ
WRITE
1
0
0011110
0011110
x
x
1
0
0011110
0011110
000000000000000
000000000000000
DRDY
0
000000000000000
DRDY
x
Don't Care
1: Disables the DRDYB pin function
DRDY
0: Enables the DRDYB pin function
15
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15.6 GPIO CONFIGURE
Individual bits of the general purpose digital I/O port can be configured to drive (output), or sense (input) only. Setting a corre-
sponding bit in the 12–bit CGPIO word will enable that pin to drive. The sequences in the following table provide a READ and
WRITE capability for the internal CGPIO register. The GPIO block is described in Section 16.5 GENERAL PURPOSE DIGITAL I/
O.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
15:12
11:0
23
15:12
11:0
Bit→
READ
WRITE
1
0
0011111
0011111
x
x
1
0
0011111
0011111
0000
0000
CGPIO
0000
CGPIO
000000000000
x
Don't Care
1: sets corresponding GPIO pin as output
0: sets corresponding GPIO pin as input
e.g. CGPIO=[000011110000] enables GPIO[7:4] pins as
outputs, all other GPIO pins are inputs
CGPIO
15.7 STATUS
Internal bit, RDY, indicates when the device has completed its power-up sequence. The RDY bit can be tested via the SPI trans-
action shown in the following table.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
0100000
23
15:1
0
23
15:1
0
Bit→
READ
1
0100000
x
x
1
000000000000000
RDY
x
Don't Care
Internal Power On Reset circuit sets this bit
RDY 1: device ready
0: device not ready
15.8 GPI STATE
The logic state present at the GPIO pins of the device is always reported in the SGPI register. The SGPI register contents can be
tested via the SPI transaction shown in the following table. The GPIO block is described in Section 16.5 GENERAL PURPOSE
DIGITAL I/O.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
15:12
11:0
23
15:12
11:0
Bit→
READ
1
0110000
x
x
1
0110000
0000
SGPI
x
Don't Care
Each bit Indicates the state at the corresponding GPIO
pins of the device
SGPI
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16
15.9 GPO DATA
The GPIO pins configured to drive, will drive the state indicated in the CGPO register. The CGPO register can be set or tested via
the SPI transactions shown in the following table. The GPIO block is described in Section 16.5 GENERAL PURPOSE DIGITAL I/
O.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
15:12
11:0
23
15:12
11:0
Bit→
READ
WRITE
1
0
0110001
0110001
x
x
1
0
0110001
0110001
0000
0000
CGPO
12'b0
0000
CGPO
x
Don't Care
Each bit will be forced at the corresponding GPIO pin of
CGPO the device. Bits corresponding to GPIO pins configured as
inputs will be ignored. CGPO[11:0]=0x000
15.10 VENDOR ID
The 16–bit ID sequence is factory set, and can only be tested via the SPI transaction shown in the table below.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
15:0
23
15:0
Bit→
READ
1
1000000
x
1
1000000
ID
x
Don't Care
ID
Vendor ID number. National Semiconductor ID = 0x0028.
15.11 VERSION/STEPPING
Version and Stepping words are factory set and can only be tested via the SPI transaction shown in the table below.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
23
15:4
3:0
23
15:4
3:0
Bit→
READ
1
1000001
x
x
1
1000001
VER
STEP
x
Don't Care
VER Indicates the device version number. VER=0x000
STEP Indicates stepping number. STEP = 0x0
17
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15.12 DAC DATA REGISTER ACCESS
Each DAC's input data register, DDATA, is individually addressable, and its contents can be updated without affecting remaining
3 DACs. The content of each DDATA can be tested and set via the SPI transactions shown in the following table. The DAC block
is described in Section 16.2 PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM.
FRAME 1: DIN
FRAME 2: DOUT
Command Payload
Command
23 22:18 17:16
Payload
11:2
15:12
1:0
23
22:18
17:16
15:12
11:2
1:0
Bit→
READ
WRITE
1
0
10100
10100
ADR
ADR
x
x
x
1
0
10100
10100
ADR
ADR
0000
0000
DDATA
10'b0
00
00
0000
DDATA
00
x
Don't Care
DAC address:
00: DAC0
ADR 01: DAC1
10: DAC2
11: DAC3
DAC input data. DDATA is a 10–bit unsigned integer.
DDATA=0x000
DDATA
15.13 ADC INPUT MUX SELECT DATA READ COMMAND
The selection of the analog input, and the read-back of the ADC conversion result are completed by the SPI transaction shown in
the following table. The ADC block is described in Section 16.1 ANALOG SENSE SUBSYSTEM.
FRAME 1: DIN
FRAME 2: DOUT
Payload
Command
23 22:19 18:16
1100 ADR
Payload
11:2
Command
15:12
1:0
23 22:19 18:16
15:12
11:2
1:0
Bit→
READ
1
x
x
x
1
1100
ADR
0000
ADATA
00
x
Don't Care
ADC Input Address:
000: IN0
001: IN1
010: IN2
ADR 011: IN3
100: IN4
101: IN5
110: IN6
111: IN7
ADATA ADC output Data. ADATA is a 10–bit unsigned integer.
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15.14 TEMPERATURE SENSOR OUTPUT REGISTER
The contents of the internal temperature sensor output register can be tested by the SPI transaction shown in the following table.
The internal temperature sensor is described in Section 16.3 DIGITAL TEMPERATURE SENSOR.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
22:16
1110000
Command
23
15:12
11:0
23
22:16
15:12
11:0
Bit→
READ
1
x
x
1
1110000
0000
TDATA
x
Don't Care
Temperature Sensor Output Data. TDATA is a 12–bit
signed integer.
TDATA
15.15 NOOP — No Operation
NOOP offers no functionality of its own. It is provided as the means of completing the pending READ operation i.e. “pushing out”
the data requested in the previous transaction.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Payload
Command
23:16
Command
23:16
15:0
15:0
Bit→
NOOP
00000000
x
00000000
16'b0
x
Don't Care
19
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16.1.2 Sampling Transient
16.0 Functional Description
As noted in Section 16.1.1 Sampling and Conversion the
charge acquired during TRACK period is maintained through-
out the conversion process. Since the successive sample
operations will involve different input potentials an instanta-
neous current will flow at the beginning of TRACK period. This
always leads to temporary disturbance of the input potential.
This current, and resulting disturbance, will vary with the mag-
nitude of the sampled signal and source impedance ROUT,
see Figure 1. If ROUT is excessive, and resulting RC time
constant of the input circuit too long, the preceding sample
may affect the new sample's accuracy.
16.1 ANALOG SENSE SUBSYSTEM
The device is capable of monitoring up to 8 externally applied
voltages. The system is centered around a 10-bit SAR ADC
fronted by an 8-input mux.
16.1.1 Sampling and Conversion
The external voltage is sampled onto the internal CHOLD ca-
pacitor during the TRACK period, see Figure 1. Once ac-
quired, the stored charge is measured using the Successive
Approximation Register (SAR) method. The timing of the in-
ternal state machine is governed by the user defined signals
CSB and SCLK. The sequence of the events is described in
Section 16.1.3 Conversion Sequence.
If high ROUT cannot be avoided, another method of improv-
ing the acquisitin accuracy is to lengthen the TRACK time.
The ADC TRACK time is fully controlled by the user inputs
CSB and SCLK, see Figure 2. The time allotted for the
CHOLD to settle can be arbitrarily adjusted via the length of the
CSB=High period and the frequency of SCLK, subject to lim-
itations on CSB and SCLK timing as shown in Section 12.0
Electrical Characteristics .
Attention should be paid to the output impedance of the
sensed voltage source and the capacitance present at the INx
input of the device (which is dominated by CHOLD during
TRACK time). The combined circuit's RC limits the bandwidth
and settling time of the input signal. At maximum SPI bus data
rate, it is recommended to limit the output resistance ROUT
of the signal source to assure the accuracy of the conversion.
16.1.3 Conversion Sequence
The ADC conversion sequence and output activity are shown
in Figure 2. The ADC readback occupies 2 SPI frames. The
first frame is used to issue a read command and connect the
ADC input to the specified device input pin INx. At the end of
the first frame, at the rising edge of the CSB, the ADC sam-
pling capacitor is connected to the signal source, INx, and the
TRACK period begins. The second frame executes the SAR
algorithm (the HOLD period) on the acquired sample and
shifts the resulting data out through the DOUT output. The
TRACK period extends for 9 SCLK cycles, then the mux dis-
connects the sampling capacitor from the signal source, and
the SAR operation begins. The data is shifted out MSB first.
Once the SAR operation is completed, the ADC powers down
for the remainder of the second frame.
During the HOLD period (duration of t HOLD specified in Sec-
tion 12.0 Electrical Characteristics ) , all mux switches are
OFF, and the charge captured on CHOLD is measured to pro-
duce an ADC output code. This charge is never lost during
the conversion, unless the SCLK is so slow that the charge is
lost due to the internal capacitor's leakage. Under normal
conditions the charge stored is modified only during TRACK
period.
Below is a typical ADC output code as a function of input volt-
age at device pin INx, x=0...7:
If DRDYB output pin functionality is enabled, see Section 15.5
GENERAL CONFIGURATION, then DRDYB output will be
low while ADC output data is present at DOUT.
In the expression above AREF is the reference voltage input
to the internal ADC. See Section 16.4 INTERNAL VOLTAGE
REFERENCE SOURCE.
If the ADC is not in TRACK or HOLD, the internal PD (Power
Down) signal of the ADC is asserted thus powering down all
the active circuits of the ADC, and opening all analog input
mux switches. See the PD period in the Figure 2.
30152337
FIGURE 1. ADC During TRACK Period
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20
30152338
FIGURE 2. ADC Sequence Diagram
16.1.4 ADC Reference Selection
In contrast, the Figure 4 shows the sampling capacitor during
TRACK period when the internally generated reference is se-
lected as the reference source of the ADC. In this configura-
tion ½CHOLD is used to sample the input signal effectively
attenuating it by a factor of 2. The resulting overall ADC trans-
fer function becomes:
By default, the ADC operates from the external reference
voltage applied at the REF pin of the device. It should be not-
ed that due to the architecture of the ADC the DC current
flowing into the REF input is zero during conversion. Howev-
er, the transient currents ( see IVREF in Section 12.0 Electrical
Characteristics ) during the HOLD time can be significant. For
further details of reference source selection see Section 16.4
INTERNAL VOLTAGE REFERENCE SOURCE
Selection of the ADC reference source automatically dictates
the attenuation level of the input signal. Figure 3 shows the
ADC input configuration during the TRACK period when the
REF pin is chosen as the source of the reference voltage. The
entire CHOLD available is used to acquire the signal. The trans-
fer function of the ADC in this configuration remains as shown
in Section 16.1.1 Sampling and Conversion
30152340
FIGURE 4. ADC Sampling when AREF is Internally
Supplied
30152339
FIGURE 3. ADC Sampling when AREF is Externally
Supplied
21
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16.2 PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM
User can select the source of the reference input to all DACs.
This functionality is described in Section 16.2.2 DAC Refer-
ence Selection
This subsystem consists of 4 identical DACs whose output is
a function of the user programmable registers DACx. This
functionality is described in Section 16.2.1 DAC Core. The
DAC input registers are individually addressable, as de-
scribed Section 15.12 DAC DATA REGISTER ACCESS. The
user can also update all of the DAC input registers to the same
value with a single SPI command. See Section 15.4 UPDATE
ALL DACs
16.2.1 DAC Core
The DAC core is based on a Resistive String architecture
which guarantees monotonicity of its transfer function. The
input data is single-registered, meaning that the OUTx of the
DAC is updated as soon as the data is updated in the DAC
input data register at the end of the SPI transaction.
Each DAC channel can be individually enabled/disabled via
the SPI interface command. See Section 15.3 DAC CON-
FIGURE. When a channel is disabled, its output OUTx is in
HiZ state, but the DAC input register still maintains its data.
The functional diagram of the DAC Core is shown in Figure 5
30152341
FIGURE 5. DAC Block Diagram
The ideal DAC core transfer function from DATAx to OUTx ,
x=0...3, can be expressed as:
from the internal reference generator block. The reference
block functionality is described in Section 16.4 INTERNAL
VOLTAGE REFERENCE SOURCE.
Reference selection automatically forces configuration of the
DACs' output buffers. If the external reference source, which
is DREF driven by the REF device pin, is selected then all of
the DAC output buffers are in 1x configuration, as seen
inFigure 6. In the external reference mode, each active DAC
presents a resistive load to the source attached to the device's
REF pin, see Figure 5 and Figure 9.
The above expression is subject to non-idealities of the re-
sistor string and limitations of the output buffer. These limita-
tions are tabulated in Section 12.0 Electrical Characteristics
In Figure 5, the PD (Power Down) signal is asserted when the
given channel is disabled via the SPI command. The PD
causes the DAC buffer bias currents to shut down, and it
breaks the current path through the resistive string.
The overall DAC transfers function remains as shown in Sec-
tion 16.2.1 DAC Core
16.2.2 DAC Reference Selection
All DAC channels operate from the same, user selectable,
reference source. In Figure 5, DREF input can be supplied by
the external source, applied to the REF pin of the device, or
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22
30152343
FIGURE 6. DAC Buffer when DREF Externally Supplied
30152342
If the internal reference generator is selected to drive the
DAC's DREF input, then all of the DACs' buffers are auto-
matically forced into 2x gain configuration as shown in Figure
7. This results in an overall transfer function of the DACs to
change to:
FIGURE 7. DAC Buffer when DREF Internally Supplied
23
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16.3 DIGITAL TEMPERATURE SENSOR
In One-Shot mode temperature sensor is inactive until the
user issues an instruction, via SPI interface, to read the tem-
perature sensor data. The temperature conversion com-
mences at the rising edge of CSB following the read
instruction. After the delay of tCONV, the new temperature data
is available in the temperature sensor output register. If con-
figured, the DRDYB output indicates when the temperature
conversion has been completed, see .
The local temperature sensor (TS) operates in one of the 2
possible modes: Continuous or One-Shot. The user selects
the mode of operation via the SPI instruction, see Sec-
tion 15.1 TEMPERATURE SENSOR CONFIGURE. The out-
put of the temperature sensor is a 12 bit signed integer, where
each LSB represents 0.0625°C. Temperature sensor's output
code (TDATA) examples are shown in Table 1.
The SPI instruction for accessing the temperature data is de-
scribed in Section 15.14 TEMPERATURE SENSOR OUT-
PUT REGISTER
TABLE 1. Temperature Readout Examples
Temperature
125°C
TDATA
In Figure 8 below a One-Shot temperature read transaction
is shown. The temperature readback occupies 2 SPI frames:
the first frame is used to issue temperature sensor read in-
struction, the second frame is used for the data readback. The
falling edge of the DRDYB signal indicates the instance the
new temperature data is present in the output register. The
DRDYB is deasserted by the rising edge of the CSB.
0111.1101.0000
0001.1001.0000
0000.0000.0001
0000.0000.0000
1111.1111.1111
1101.1000.0000
25°C
0.0625°C
0°C
−0.0625°C
−40°C
NOTE: The DRDYB output in One-Shot temperature con-
version mode is asynchronous to the SCLK of the SPI
interface. DRDYB functionality is not provided in the
Continuous mode of the temperature sensor operation.
In Continuous mode, the temperature sensor operates in the
background and independently of the SPI bus activity. Sub-
sequent temperature conversion results are stored in the
output register which can be accessed by the user via the SPI
interface.
30152347
FIGURE 8. One-Shot Temperature Read Sequence
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24
16.4 INTERNAL VOLTAGE REFERENCE SOURCE
CREF register is shown in Section 15.2 REFERENCE CON-
FIGURE. The switch activity due to the CREF content is
tabulated in Table 2.
The device has a built in precision 2.5V reference block which
can be used to provide reference potential to either the ADC
(AREF) or the DACs (DREF), both at once, or to external load
via REF pin. The precision reference is always isolated from
its loads by individual buffers, see Figure 9.
The modes corresponding to CREF=(100) or (110) or (111)
are the Deep Sleep modes. In these modes the internal tem-
perature sensor, the ADC, the DACs, and the reference block
buffers (but not the 2.5V reference) are powered down.
The CREF register sets the reference block mode of opera-
tion. The SPI instruction to update or read contents of the
30152344
FIGURE 9. Reference Selector Diagram
TABLE 2. Reference Selector Functionality
(1 to CLOSE Switch)
Switch
CREF
000
001
010
011
100
101
110
111
A
1
0
1
0
0
0
0
0
B
0
0
1
1
0
0
0
0
C
0
0
0
0
0
1
0
0
D
0
1
0
1
0
1
0
0
E
1
1
0
0
0
1
0
0
25
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16.5 GENERAL PURPOSE DIGITAL I/O
The GPIOx pins can be configured as outputs by setting the
individual bits in the CGPIO registers. Each bit in CGPIO reg-
ister enables corresponding output buffer in the GPIOx port.
See Section 15.6 GPIO CONFIGURE. Once the drive is en-
abled, the logic state at the outputs is dictated by the contents
of the CGPO register. See Section 15.9 GPO DATA.
The GPIO[11:0] port is memory mapped to registers SGPI
and CGPO. Both registers are accessible through the SPI in-
terface.
The SGPI register content reflects at all times the digital state
at the GPIOx device pins. The format of the read command
of the General Purpose Digital I/O is shown in Section 15.8
GPI STATE.
The functional diagram of the General Purpose Digital I/O is
shown in Figure 10.
30152345
FIGURE 10. General Purpose Digital I/O Diagram
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26
16.6 SERIAL INTERFACE
general format of the 24 bit data stream is shown in Figure
11. The full Instruction Set is tabulated in Section 15.0 In-
struction Set.
The 4-wire interface is compatible with SPI, QSPI and MI-
CROWIRE, as well as most DSPs. See the Section 13.0 SPI
Interface Timing Diagram for timing information of the read
and write sequences. The serial interface uses four signals
CSB, SCLK, DIN and DOUT.
A bus transaction is initiated by the falling edge of the CSB.
Once CSB is low, the input data is sampled at the DIN pin by
the falling edge of the SCLK, and shifted into the internal shift
register (FIFO). The output data is put out on the DOUT pin
on the rising edge of SCLK. At least 24 SCLK cycles are re-
quired for a valid transfer to occur. If CSB is raised before 24th
rising edge of the SCLK, the transfer is aborted and preceding
data ignored. If the CSB is held low after the 24th falling edge
of the SCLK, the data will continue to flow through the internal
shift register (FIFO) and out the DOUT pin. When CSB tran-
sitions high, the internal controller decodes the FIFO contents
— most recent 24 bits that were received before the rising
edge of CSB.
30152349
FIGURE 11. General SPI Frame Format
16.6.1 SPI Write
SPI write operation occupies a single 24–bit frame, as shown
in Figure 12. Write operation always starts with a leading 0
(zero) in the 8–bit COMMAND sequence. The format of the
data transfer and user instruction set is shown in Section 15.0
Instruction Set.
While CSB is high, DOUT is in a high-Z state. At the falling
edge of CSB, DOUT presents the MSB of the data present in
the shift register. DOUT is updated on every subsequent
falling edge of SCLK (note — the first DOUT transition will
happen on the first rising edge AFTER the first falling edge of
SCLK when CSB is low).
Note that write operation also produces DOUT activity. The
DOUT output echoes back the previous frame's COMMAND
byte, followed by 16 zeros.
The 24 bits of data contained in the FIFO are interpreted as
an 8 bit COMMAND word followed by 16 bits of DATA. The
30152354
FIGURE 12. SPI Write Transaction
16.6.2 SPI Read
Reading of the specific content requires 2 SPI frames, as
shown in Figure 13. The first frame is used to issue a read
command, which always begins with RW bit set in the COM-
MAND byte. The second frame echoes back the first frame's
COMMAND byte, followed by the 16–bit PAYLOAD contain-
ing the requested data. Consult Section 15.0 Instruction Set
for the COMMAND format and returned data alignment within
PAYLOAD.
The read operation requires all 4 wires of the SPI interface:
SCLK, CSB, DIN, DOUT. The simplest read operation occurs
automatically during any valid transaction on the SPI bus
since DOUT pin always shifts out the leading 8 bits (COM-
MAND) of the previous transaction — this is regardless of the
RW bit setting in the COMMAND byte. This functionality gives
the user an easy method of verifying the SPI link.
27
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30152350
FIGURE 13. SPI Read Transaction
16.6.3 SPI Daisy Chain
trary length can be constructed since individual devices do
not count the data bits shifted in. Instead, they wait to decode
the contents of their respective shift registers until CSB is
raised high.
It is possible to control multiple LMP92018s with a single
master equipped with one SPI interface. This is accomplished
by connecting the multiple LMP92018 devices in a Daisy
Chain. The scheme is depicted in Figure 14. A chain of arbi-
30152351
FIGURE 14. SPI Daisy Chain
A typical bus cycle for this scheme is initiated by the falling
CSB. After the 24 SCLK cycles new data starts to appear at
the DOUT pin of the first device in the chain, and starts shifting
into the second device. After the 72 SCLK cycles following the
falling CSB edge, all three devices in this example will contain
new data in their input shift registers. Raising CSB will begin
the process of decoding data in each device. When in the
Daisy Chain the full READ and WRITE capability of every de-
vice is maintained.
30152352
FIGURE 15. SPI Daisy Chain Transaction
A sample of SPI data transfer appropriate for a 3 device Daisy
Chain is shown in Figure 15.
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17.0 Application Circuit Example
30152346
29
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18.0 Physical Dimensions inches (millimeters) unless otherwise noted
LLP-36 Package
NS Package Number SQA36A
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30
Notes
31
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Notes
TI/NATIONAL INTERIM IMPORTANT NOTICE
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Transportation and Automotive www.ti.com/automotive
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
相关型号：
LMP92064
Precision Low-Side, 125 kSps Simultaneous Sampling,Current Sensor and Voltage Monitor with SPI
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