LMR16030PDDAR [TI]
具备 40uA Iq 的 SIMPLE SWITCHER 60V、3A 降压转换器 | DDA | 8 | -40 to 125;型号: | LMR16030PDDAR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具备 40uA Iq 的 SIMPLE SWITCHER 60V、3A 降压转换器 | DDA | 8 | -40 to 125 PC 开关 光电二极管 转换器 |
文件: | 总38页 (文件大小:2407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMR16030
ZHCSF41B –DECEMBER 2015 –REVISED MARCH 2021
具有40µA IQ 的LMR16030 SIMPLE SWITCHER® 60V、3A 降压转换器
4.3V 至 60V 的宽输入范围,适用于从工业到汽车各类
应用中非稳压电源的电源调节。该稳压器在睡眠模式下
1 特性
的静态电流为 40μA,非常适合电池供电型系统。它
在关断模式下具有 1μA 的超低电流,可进一步延长电
池使用寿命。该稳压器的可调开关频率范围较宽,这使
得效率或外部元件尺寸能够得到优化。内部环路补偿意
味着用户不用承担设计环路补偿组件的枯燥工作。并且
还能够以最大限度减少器件的外部元件数。精密使能输
入简化了稳压器控制和系统电源排序。此外,该器件还
内置多种保护特性:逐周期电流限制保护、应对功耗过
大的热感测和热关断保护、以及输出过压保护。
• 推出的新产品:LM76003 60V、3.5A、2.2MHz 同
步转换器
• 4.3V 至60V 输入范围
• 3A 持续输出电流
• 40µA 超低静态工作电流
• 155mΩ 高侧MOSFET
• 电流模式控制
• 可调节开关频率范围:200kHz 至2.5MHz
• 与外部时钟频率同步
• 内置补偿功能,便于使用
• 支持高占空比运行
• 精密使能输入
LMR16030 采用焊盘外露的8 引脚HSOIC 封装,可实
现低热阻。
新产品 LM76003 需要很少的外部元件,引脚分配设计
可简化PCB 布局,提供更好的EMI 和热性能。请参阅
器件比较表以比较规格。
• 1µA 关断电流
• 热保护、过压保护和短路保护
• 带PowerPAD™ 的8 引脚HSOIC 封装
• 可使用LM76003 并借助WEBENCH® Power
Designer 创建定制设计方案
• 可使用LM16030 并借助WEBENCH® Power
Designer 创建定制设计方案
器件信息
封装(1)
封装尺寸(标称值)
器件型号
LMR16030PDDAR
HSOIC (8)
4.89mm x 3.90mm
(电源正常)
LMR16030SDDAR
2 应用
HSOIC (8)
4.89mm x 3.90mm
(软启动)
• 汽车电池稳压
• 工业电源
• 电信和数据通信系统
• 通用宽VIN 稳压
(1) 如需了解所有可用封装,请参见数据表末尾的可订购产品附
录。
3 说明
LMR16030 是一款带有集成型高侧 MOSFET 的60V、
3A SIMPLE SWITCHER 降压稳压器。该器件具有
VIN up to 60 V
100
90
80
70
60
50
40
30
CIN
VIN
BOOT
SW
EN
CBOOT
L
VOUT
RT/SYNC
D
RFBT
RT
COUT
RFBB
FB
SS
20
CSS
VIN = 12 V
VIN = 24 V
VIN = 48 V
GND
10
0
0.0001
0.001
0.01
IOUT (A)
0.05
0.2 0.5
1
2 3
简化版原理图(LMR16030S)
D012
效率与输出电流间的关系VOUT = 5V,fsw = 500kHz
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSAH9
LMR16030
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ZHCSF41B –DECEMBER 2015 –REVISED MARCH 2021
Table of Contents
7.4 Device Functional Modes..........................................18
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 19
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 接收文档更新通知................................................... 27
11.3 支持资源..................................................................27
11.4 Trademarks............................................................. 27
11.5 静电放电警告...........................................................27
11.6 术语表..................................................................... 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
Information.................................................................... 28
4 Revision History
Changes from Revision A (May 2016) to Revision B (March 2021)
Page
• 添加了WEBENCH 链接..................................................................................................................................... 1
• 添加了LM76003 链接.........................................................................................................................................1
• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
• 添加了LM76003 的信息..................................................................................................................................... 1
Changes from Revision * (December 2015) to Revision A (May 2016)
Page
• 在完整版数据表中将“产品预发布”更改为“量产数据”..................................................................................1
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5 Pin Configuration and Functions
BOOT
1
8
SW
VIN
EN
2
3
4
7
6
5
GND
Thermal Pad
(9)
SS or PGOOD
FB
RT/SYNC
图5-1. 8-Pin (HSOIC) DDA Package (Top View)
表5-1. Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
Bootstrap capacitor connection for high-side MOSFET driver. Connect a high quality 0.1-μF
capacitor from BOOT to SW.
BOOT
1
P
P
A
Connect to power supply and bypass capacitors CIN. Path from VIN pin to high frequency
bypass CIN and GND must be as short as possible.
VIN
EN
2
3
Enable pin with internal pullup current source. Pull below 1.2 V to disable. Float or connect to
VIN to enable. Adjust the input undervoltage lockout with two resistors. See 节7.3.6.
Resistor Timing or External Clock input. An internal amplifier holds this pin at a fixed voltage
when using an external resistor to ground to set the switching frequency. If the pin is pulled
above the PLL upper threshold, a mode change occurs and the pin becomes a
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock
input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the
operating mode returns to frequency programming by resistor.
RT/SYNC
FB
4
A
Feedback input pin. Connect to the feedback divider to set VOUT. Do not short this pin to
ground during operation.
5
6
A
A
SS pin for soft-start version. Connect to a capacitor to set soft-start time.
PGOOD pin for Power Good version, open drain output for power-good flag. Use a 10-kΩto
100-kΩpullup resistor to logic rail or other DC voltage no higher than 7 V.
SS
or
PGOOD
GND
7
8
9
G
P
System ground pin
Switching output of the regulator. Internally connected to high-side power MOSFET. Connect
to power inductor.
SW
Thermal Pad
G
Major heat dissipation path of the die. Must be connected to ground plane on PCB.
(1) A = Analog, P = Power, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of -40°C to 125°C (unless otherwise noted) (1)
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
UNIT
VIN, EN to GND
BOOT to GND
SS to GND
65
71
5
Input Voltages
V
FB to GND
7
RT/SYNC to GND
PGOOD to GND
BOOT to SW
3.6
7
6.5
65
150
150
Output Voltages
V
SW to GND
-3
TJ
Junction temperature
Storage temperature
-40
-65
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM)(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM) (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40°C to 125°C (unless otherwise noted) (1)
MIN
MAX UNIT
VIN
4.3
60
50
VOUT
0.8
Buck Regulator
BOOT
66
V
V
SW
-1
0
60
FB
5
EN
0
60
RT/SYNC
0
3.3
3
Control
SS
0
PGOOD to GND
0
5
Switching frequency range at RT mode
Switching frequency range at SYNC mode
Operating junction temperature, TJ
200
250
-40
2500
2300
125
Frequency
kHz
°C
Temperature
(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance
limits. For ensured specifications, see 节6.5.
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6.4 Thermal Information
LMR16030
THERMAL METRIC (1) (2)
DDA (HSOIC)
8 PINS
42.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
9.9
ψJT
25.4
ψJB
RθJC(top)
RθJC(bot)
RθJB
56.1
3.8
25.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a maximum junction temperature (TJ) of 125°C, which is
illustrated in the Recommended Operating Conditions.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following
conditions apply: VIN = 4.3 V to 60 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY (VIN PIN)
VIN
Operation input voltage
4.3
3.8
60
V
V
UVLO
Under voltage lockout thresholds
Rising threshold
4.0
285
1.0
4.2
Hysteresis
mV
μA
ISHDN
IQ
Shutdown supply current
3.0
VEN = 0 V, TA = 25 °C, 4.3 V ≤VIN ≤60
V
Operating quiescent current (non-
switching)
VFB = 1.0 V, TA = 25 °C
40
μA
ENABLE (EN PIN)
VEN_TH
EN Threshold Voltage
EN PIN current
1.05
1.20
-4.6
-1.0
-3.6
1.38
V
IEN_PIN
Enable threshold +50 mV
Enable threshold -50 mV
μA
μA
IEN_HYS
SOFT-START
ISS
EN hysteresis current
SS pin current
For External Soft-Start version only, TA
25 °C
=
-3.0
4.0
μA
tSS
Internal soft-start time
For Power-Good version only, 10% to
90% of FB voltage
ms
POWER GOOD (PGOOD PIN)
VPG_UV Power-good flag under voltage tripping
POWER GOOD (% of FB voltage)
POWER BAD (% of FB voltage)
POWER BAD (% of FB voltage)
POWER GOOD (% of FB voltage)
% of FB voltage
94
92
%
%
%
%
%
nA
threshold
VPG_OV
Power-good flag over voltage tripping
threshold
109
107
2
VPG_HYS
IPG
Power-good flag recovery hysteresis
PGOOD leakage current at high level
output
VPull-Up = 5 V
10
200
VPG_LOW
PGOOD low level output voltage
IPull-Up = 1 mA
0.1
1.6
V
V
VIN_PG_MIN
Minimum VIN for valid PGOOD output
1.95
VPull-Up < 5 V at IPull-Up = 100 μA
VOLTAGE REFERENCE (FB PIN)
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Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following
conditions apply: VIN = 4.3 V to 60 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VFB
Feedback voltage
TJ = 25 °C
0.746 0.750 0.754
0.735 0.750 0.765
V
V
TJ = -40 °C to 125 °C
HIGH-SIDE MOSFET
RDS_ON
On-resistance
VIN = 12 V, BOOT to SW = 5.8 V
VIN = 12 V, TA = 25 °C, Open Loop
155
320
mΩ
HIGH-SIDE MOSFET CURRENT LIMIT
ILIMT
THERMAL PERFORMANCE
TSHDN Thermal shutdown threshold
THYS Hysteresis
Current limit
3.80
4.75
5.70
A
170
12
°C
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6.6 Switching Characteristics
Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Switching frequency
1758 1912 2066
RT = 11.5 kΩ
fSW
kHz
V
Switching frequency range at SYNC mode
SYNC clock high level threshold
SYNC clock low level threshold
250
1.7
2300
0.5
VSYNC_HI
VSYNC_LO
Measured at 500 kHz, VSYNC_HI > 3 V,
VSYNC_LO < 0.3 V
TSYNC_MIN
TLOCK_IN
TON_MIN
DMAX
Minimum SYNC input pulse width
PLL lock in time
30
100
90
ns
µs
ns
Measured at 500 kHz
VIN = 12 V, BOOT to SW = 5.8 V, ILoad = 1
A
Minimum controllable on time
Maximum duty cycle
fSW = 200 kHz
97%
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6.7 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 24 V, fSW = 500 KHz, L = 8.2 µH, COUT = 2 × 47 µF, TA =
25°C.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
VIN = 36 V
VIN = 48 V
VIN = 60 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
0.001
0.01
0.1
IOUT (A)
1
3
0.001
0.01
0.1
IOUT (A)
1
3
D002
D001
VOUT = 3.3 V
fSW = 500 KHz
VOUT = 3.3 V
fSW = 500 KHz
图6-2. Efficiency vs. Load Current
图6-1. Efficiency vs. Load Current
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
VIN = 12 V
VIN = 18 V
VIN = 24 V
VIN = 36 V
VIN = 48 V
VIN = 60 V
0.001
0.01
0.1
IOUT (A)
1
3
0.001
0.01
0.1
IOUT (A)
1
3
D003
D004
VOUT = 5 V
fSW = 500 KHz
VOUT = 5 V
fSW = 500 KHz
图6-3. Efficiency vs. Load Current
图6-4. Efficiency vs. Load Current
0.2
0.15
0.1
125
100
75
50
25
0
VFB Falling
VFB Rising
0.05
0
-0.05
-0.1
-0.15
-0.2
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 48 V
0.001
0.01
0.1
IOUT (A)
1
3
0
0.1
0.2
0.3
0.4
VFB (V)
0.5
0.6
0.7
D005
D005
VOUT = 5 V
fSW = 500 KHz
图6-5. Load Regulation
图6-6. Frequency vs VFB
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6.7 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 24 V, fSW = 500 KHz, L = 8.2 µH, COUT = 2 × 47 µF, TA =
25°C.
3.4
3.3
3.2
3.1
3
5.5
5
4.5
4
3 A
2 A
1 A
0.5 A
0.1 A
3 A
2 A
1 A
0.5 A
0.1 A
3.5
3
4
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
VIN (V)
5
4.5
5
5.5
VIN (V)
6
6.5
D006
D007
VOUT = 3.3 V
fSW = 500 KHz
VOUT = 5 V
fSW = 500 KHz
图6-7. Dropout Curve
图6-8. Dropout Curve
0.754
0.752
0.75
6
5.8
5.6
5.4
5.2
5
VIN = 12 V
VIN = 60 V
0.748
0.746
0.744
4.8
4.6
4.4
4.2
4
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
Junction Temperature (°C)
50
75
100
125
150
Junction Temperature (èC)
D010
D011
VIN = 12 V
图6-9. Voltage Reference vs Junction Temperature
图6-10. High-Side Current Limit vs Junction Temperature
50
45
40
35
30
4
3.95
3.9
3.85
UVLO_H
UVLO_L
25
3.8
IQ
ISHDN
20
3.75
3.7
15
10
5
3.65
3.6
0
0
5
10 15 20 25 30 35 40 45 50 55 60
VIN (V)
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
D008
D009
图6-11. Shut-down Current and Quiescent Current
IOUT = 0 A
图6-12. UVLO Threshold
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7 Detailed Description
7.1 Overview
The LMR16030 SIMPLE SWITCHER® regulator is an easy-to-use step-down DC-DC converter that operates
from a 4.3-V to 60-V supply voltage. It integrates a 155-mΩ (typical) high-side MOSFET and is capable of
delivering up to 3-A DC load current with exceptional efficiency and thermal performance in a very small solution
size. The operating current is typically 40 μA under no load condition (not switching). When the device is
disabled, the supply current is typically 1 μA. An extended family is available in 1-A and 2-A load options in pin-
to-pin compatible packages.
The LMR16030 implements constant frequency peak current mode control with sleep mode at light load to
achieve high efficiency. The device is internally compensated, which reduces design time, and requires fewer
external components. The switching frequency is programmable from 200 kHz to 2.5 MHz by an external resistor
RT. The LMR16030 is also capable of synchronization to an external clock within the 250-kHz to 2.3-MHz
frequency range, which allows the device to be optimized to fit small board space at higher frequency, or high
efficient power conversion at lower frequency.
Other features included for more comprehensive system requirements are precision enable, adjustable soft-start
time, and approximately 97% duty cycle by aBOOT capacitor recharge circuit. These features provide a flexible
and easy-to-use platform for a wide range of applications. Protection features include overtemperature
shutdown, VOUT overvoltage protection (OVP), VIN undervoltage lockout (UVLO), cycle-by-cycle current limit,
and short-circuit protection with frequency foldback.
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7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Fixed Frequency Peak Current Mode Control
The following operating description of the LMR16030 will refer to the Functional Block Diagram and to the
waveforms in 图 7-1. The LMR16030 output voltage is regulated by turning on the high-side N-MOSFET with
controlled ON time. During high-side switch ON time, the SW pin voltage swings up to approximately VIN, and
the inductor current iL increases with alinear slope (VIN – VOUT) / L. When the high-side switch is off, inductor
current discharges through a freewheel diode with a slope of –VOUT / L. The control parameter of the buck
converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch ON time and TSW is the
switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In
an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
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VSW
D = tON/ TSW
VIN
tON
tOFF
t
0
-VD
TSW
iL
ILPK
IOUT
ûiL
t
0
图7-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LMR16030 employs fixed-frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current to control the ON time of
the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency at normal load condition. At very light load, the
LMR16030 operates in sleep mode to maintain high efficiency and the switching frequency decreases with
reduced load current.
7.3.2 Slope Compensation
The LMR16030 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
7.3.3 Sleep Mode
The LMR16030 operates in sleep mode at light load currents to improve efficiency by reducing switching and
gate drive losses. If the output voltage is within regulation and the peak switch current at the end of any
switching cycle is below the current threshold of 300 mA, the device enters sleep mode. The sleep mode current
threshold is the peak switch current level corresponding to a nominal internal COMP voltage of 400 mV.
When in sleep mode, the internal COMP voltage is clamped at 400 mV, the high-side MOSFET is inhibited, and
the device draws only 40-μA (typical) input quiescent current. Since the device is not switching, the output
voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the internal
COMP voltage. The high-side MOSFET is enabled and switching resumes when the error amplifier lifts internal
COMP voltage above 400 mV. The output voltage recovers to the regulated value, and internal COMP voltage
eventually falls below the sleep mode threshold, at which time the device again enters sleep mode.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The LMR16030 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or
greater is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the LMR16030
operates at approximate 97% duty cycle. When the high-side MOSFET is continuously on for five or six
switching cycles (five or six switching cycles for frequency lower than 1 MHz, and 10 or 11 switching cycles for
frequency higher than 1 MHz) and the voltage from BOOT to SW drops below 3.2 V, the high-side MOSFET is
turned off and an integrated low-side MOSFET pulls SW low to recharge the BOOT capacitor.
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Since the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 97%. The effective duty cycle of the converter during dropout is
mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode,
voltage and the printed circuit board resistance.
7.3.5 Adjustable Output Voltage
The internal voltage reference produces a precise 0.75-V (typical) voltage reference over the operating
temperature range. The output voltage is set by a resistor divider from the output voltage to the FB pin. It is
recommended to use 1% tolerance or better and a temperature coefficient of 100 ppm or less divider resistors.
Select the low-side resistor RFBB for the desired divider current and use 方程式 1 to calculate high-side RFBT
.
Larger value divider resistors are good for efficiency at light load. However, if the values are too high, the
regulator is more susceptible to noise and voltage errors from the FB input current may become noticeable. RFBB
in the range from 10 kΩ to 100 kΩ is recommended for most applications.
V
OUT
R
FBT
FBB
FB
R
图7-2. Output Voltage Setting
VOUT - 0.75
0.75
RFBT
=
ìRFBB
(1)
7.3.6 Enable and Adjustable Undervoltage Lockout
The LMR16030 is enabled when the VIN pin voltage rises above 4.0 V (typical) and the EN pin voltage exceeds
the enable threshold of 1.2 V (typical). The LMR16030 is disabled when the VIN pin voltage falls below 3.715 V
(typical) or when the EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source (typically
IEN = 1 μA) that enables operation of the LMR16030 when the EN pin is floating.
Many applications will benefit from the employment of an enable divider RENT and RENB in 图 7-3 to establish a
precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.
When EN terminal voltage exceeds 1.2 V, an additional hysteresis current (typically IHYS = 3.6 μA) is sourced
out of EN terminal. When the EN terminal is pulled below 1.2 V, IHYS current is removed. This additional current
facilitates adjustable input voltage UVLO hysteresis. Use 方程式 2 and 方程式 3 to calculate RENT and RENB for
desired UVLO hysteresis voltage.
I
I
EN
EN_HYS
VIN
V
IN
R
R
ENT
EN
V
EN
ENB
图7-3. System UVLO By Enable Dividers
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VSTART - VSTOP
IHYS
RENT
=
(2)
VEN
RENB
=
VSTART - VEN
RENT
+ IEN
(3)
where VSTART is the desired voltage threshold to enable LMR16030, VSTOP is the desired voltage threshold to
disable device, IEN = 1 μA and IHYS = 3.6 μA typically.
7.3.7 External Soft Start
The LMR16030S has an external soft-start pin for programmable output ramp-up time. The soft-start feature is
used to prevent inrush current impacting the LMR16030 and its load when power is first applied. The soft-start
time can be programed by connecting an external capacitor CSS from SS pin to GND. An internal current source
(typically ISS = 3 μA) charges CSS and generates a ramp from 0 V to VREF. The soft-start time can be calculated
by 方程式4:
CSS(nF)ì VREF(V)
tSS(ms) =
ISS(mA)
(4)
The internal soft start resets while the device is disabled or in thermal shutdown.
7.3.8 Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the LMR16030 can be programmed by the resistor RT from the RT/SYNC pin and
GND pin. The RT/SYNC pin cannot be left floating or shorted to ground. To determine the timing resistance for a
given switching frequency, use 方程式5 or the curve in 图7-4. 表7-1 gives typical RT values for a given fSW
.
RT(kW) = 42904 ì ƒSW (kHz)-1.088
(5)
140
120
100
80
60
40
20
0
0
500
1000 1500
Frequency (kHz)
2000
2500
D008
图7-4. RT Versus Frequency Curve
表7-1. Typical Frequency Setting RT Resistance
fSW (kHz)
RT (kΩ)
133
200
350
500
750
1000
73.2
49.9
32.4
23.2
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表7-1. Typical Frequency Setting RT Resistance (continued)
fSW (kHz)
RT (kΩ)
15.0
1500
1912
11.5
2200
9.76
The LMR16030 switching action can also be synchronized to an external clock from 250 kHz to 2.3 MHz.
Connect a square wave to the RT/SYNC pin through either circuit network shown in 图 7-5. Internal oscillator is
synchronized by the falling edge of external clock. The recommendations for the external clock include: high
level no lower than 1.7 V, low level no higher than 0.5 V, and have a pulse width greater than 30 ns. When using
a low impedance signal source, the frequency setting resistor RT is connected in parallel with an AC coupling
capacitor CCOUP to a termination resistor RTERM (for example, 50 Ω). The two resistors in series provide the
default frequency setting resistance when the signal source is turned off. A 10 pF ceramic capacitor can be used
for CCOUP. 图7-6, 图7-7, and 图7-8 show the device synchronized to an external system clock.
C
COUP
PLL
RT/SYNC
PLL
RT/SYNC
R
T
Lo-Z
Clock
Hi-Z
Clock
Source
Source
R
T
R
TERM
图7-5. Synchronizing to an External Clock
图7-6. Synchronizing in CCM
图7-7. Synchronizing in DCM
图7-8. Synchronizing in Sleep Mode
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方程式 6 calculates the maximum switching frequency limitation set by the minimum controllable on time and the
input-to-output step-down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required at maximum input voltage.
≈
’
IOUT ìRIND + VOUT + VD
V -IOUT ìRDS_ON + VD
IN_MAX
1
ƒSW(max)
=
ì
∆
∆
«
÷
÷
◊
tON
(6)
where
• IOUT = Output current
• RIND = Inductor series resistance
• VIN_MAX = Maximum input voltage
• VOUT = Output voltage
• VD = Diode voltage drop
• RDS_ON = High-side MOSFET switch on resistance
• tON = Minimum on time
7.3.9 Power Good (PGOOD)
The LMR16030P has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is
within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault
protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage.
Voltage seen by the PGOOD pin should never exceed 7 V. A resistor divider pair can be used to divide the
voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.
Refer to 图 7-9. When the FB voltage is within the power-good band, +7% above and -6% below the internal
reference VREF typically, the PGOOD switch is turned off and the PGOOD voltage is pulled up to the voltage
level defined by the pullup resistor or divider. When the FB voltage is outside of the tolerance band, +9% above
or -8% below VREF typically, the PGOOD switch is turned on and the PGOOD pin voltage is pulled low to indicate
power bad.
VREF
109%
107%
94%
92%
PGOOD
High
Low
图7-9. Power-Good Flag
7.3.10 Overcurrent and Short Circuit Protection
The LMR16030 is protected from overcurrent condition by cycle-by-cycle current limiting on the peak current of
the high-side MOSFET. High-side MOSFET overcurrent protection is implemented by the nature of the Peak
Current Mode control. The high-side switch current is compared to the output of the Error Amplifier (EA) minus
slope compensation every switching cycle. Please refer to 节 7.2 for more details. The peak current of high-side
switch is limited by a clamped maximum peak current threshold which is constant,so the peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
The LMR16030 also implements a frequency foldback to protect the converter in severe overcurrent or short
conditions. The oscillator frequency is divided by 2, 4, and 8 as the FB pin voltage decrease to 75%, 50%, 25%
of VREF. The frequency foldback increases the off time by increasing the period of the switching cycle, so that it
provides more time for the inductor current to ramp down and leads to a lower average inductor current. Lower
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frequency also means lower switching loss. Frequency foldback reduces power dissipation and prevents
overheating and potential damage to the device.
7.3.11 Overvoltage Protection
The LMR16030 employs an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. The
OVP feature minimizes output overshoot by turning off the high-side switch immediately when FB voltage
reaches to the rising OVP threshold which is nominally 109% of the internal voltage reference VREF. When the
FB voltage drops below the falling OVP threshold, which is nominally 107% of VREF, the high-side MOSFET
resumes normal operation.
7.3.12 Thermal Shutdown
The LMR16030 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C (typical). The high-side MOSFET stops switching when thermal shundown activates. Once the
die temperature falls below 158°C (typical), the device reinitiates the power-up sequence controlled by the
internal soft-start circuitry.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LMR16030. When VEN is below 1.0 V, the device is in
shutdown mode. The switching regulator is turned off and the quiescent current drops to 1.0 µA typically. The
LMR16030 also employs undervoltage lockout protection. If VIN voltage is below the UVLO level, the regulator is
turned off.
7.4.2 Active Mode
The LMR16030 is in active mode when VEN is above the precision enable threshold and VIN is above its UVLO
level. The simplest way to enable the LMR16030 is to connect the EN pin to VIN pin. This allows self start-up
when the input voltage is in the operation range: 4.3 V to 60 V. Please refer to 节 7.3.6 for details on setting
these operating levels.
In active mode, depending on the load current, the LMR16030 is in one of three modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple.
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation.
3. Sleep mode when internal COMP voltage drop to 400 mV at very light load.
7.4.3 CCM Mode
CCM operation is employed in the LMR16030 when the load current is higher than half of the peak-to-peak
inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in
this mode and the maximum output current of 3 A can be supplied by the LMR16030.
7.4.4 Light Load Operation
When the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR16030 operates in
DCM. At even lighter current loads, sleep mode is activated to maintain high efficiency operation by reducing
switching and gate drive losses.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The LMR16030 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 3 A. The following design procedure can be used to select
components for the LMR16030. This section presents a simplified discussion of the design process.
8.2 Typical Application
The LMR16030 only requires a few external components to convert from wide voltage range supply to a fixed
output voltage. A schematic of 5-V / 3-A application circuit is shown in 图 8-1. The external components have to
fulfill the needs of the application, but also the stability criteria of the control loop of the device.
7 V to 60 V
CBOOT
BOOT
SW
VIN
EN
CIN
5 V / 3 A
L
COUT
D
RFBT
RT/SYNC
SS
FB
RFBB
RT
GND
CSS
图8-1. Application Circuit, 5-V Output
8.2.1 Design Requirements
This example details the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These parameters are typically determined at
the system level:
表8-1. Design Parameters
Input voltage, VIN
Output voltage, VOUT
7 V to 60 V, typical 24 V
5.0 V
3 A
Maximum output current, IO_MAX
Transient response, 0.3 A to 3 A
Output voltage ripple
5%
50 mV
400 mV
500 KHz
Input voltage ripple
Switching frequency, fSW
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM76003 device with the WEBENCH® Power Designer.
Click here to create a custom design using the LM16030 device with the WEBENCH® Power Designer.
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1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Set-Point
The output voltage of LMR16030 is externally adjustable using a resistor divider network. The divider network is
comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. 方程式 7 is used to determine the
output voltage:
VOUT - 0.75
0.75
RFBT
=
ìRFBB
(7)
Choose the value of RFBT to be 100 kΩ. With the desired output voltage set to 5 V and the VFB = 0.75 V, the
RFBB value can then be calculated using 方程式 7. The formula yields to a value 17.65 kΩ. Choose the closest
available value of 17.8 kΩ for RFBB
.
8.2.2.3 Switching Frequency
For desired frequency, use 方程式8 to calculate the required value for RT.
RT(kW) = 42904 ì ƒSW (kHz)-1.088
(8)
For 500 KHz, the calculated RT is 49.66 kΩ and standard value 49.9 kΩ can be used to set the switching
frequency at 500 KHz.
8.2.2.4 Output Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The
inductance is based on the desired peak-to-peak ripple current, ΔiL. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use 方程式
9 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. A reasonable value of KIND must be 20%-40%.
During an instantaneous short or overcurrent operation event, the RMS and peak inductor current can be high.
The inductor current rating must be higher than current limit.
VOUT ì(V
- VOUT )
IN_MAX
DiL =
VIN_MAX ìL ì ƒSW
(9)
V
- VOUT
VOUT
IN_MAX ì ƒSW
IN_MAX
LMIN
=
ì
IOUT ìKIND
V
(10)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. Too low of
an inductance can generate too large of an inductor current ripple such that over current protection at the full
load can be falsely triggered. It also generates more conduction loss since the RMS current is slightly higher.
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Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak
current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current
ripple improves the comparator signal to noise ratio.
For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 7.64 µH, and a
nearest standard value is chosen: 8.2 µH. A standard 8.2-μH ferrite inductor with a capability of 3-A RMS
current and 6-A saturation current can be used.
8.2.2.5 Output Capacitor Selection
The output capacitor or capacitors, COUT, must be chosen with care since it directly affects the steady state
output voltage ripple, loop stability and the voltage overshoot and undershoot during load current transients.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the Equivalent Series Resistance (ESR) of the output capacitors:
DVOUT_ESR = DiL ìESR = KIND ìIOUT ìESR
(11)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
DiL
KIND ìIOUT
8ì ƒSW ìCOUT 8ì ƒSW ìCOUT
DVOUT_C
=
=
(12)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The control loop of the regulator usually needs three or more clock cycles to respond to the output voltage
droop. The output capacitance must be large enough to supply the current difference for three clock cycles to
maintain the output voltage within the specified range. 方程式 13 shows the minimum output capacitance
needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors
absorb energy stored in the inductor. The catch diode cannot sink current so the energy stored in the inductor
results in an output voltage overshoot. 方程式 14 calculates the minimum capacitance required to keep the
voltage overshoot within a specified range.
3ì(IOH -IOL
ƒSW ì VUS
)
COUT
>
(13)
(14)
IO2 H -IO2 L
(VOUT + VOS )2 - VO2UT
COUT
>
ìL
where
• KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT
• IOL = Low level output current during load transient
• IOH = High level output current during load transient
• VUS = Target output voltage undershoot
)
• VOS = Target output voltage overshoot
For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and
chose KIND = 0.4. 方程式 11 yields ESR no larger than 41.7 mΩ and 方程式 12 yields COUT no smaller than 6
μF. For the target overshoot and undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT
can be calculated to be no smaller than 64.8 μF and 6.4 μF by 方程式 13 and 方程式 14 respectively. In
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summary, the most stringent criteria for the output capacitor is 100 μF. For this design example, two 47-μF, 16-
V, X7R ceramic capacitors with 5-mΩ ESR are used in parallel.
8.2.2.6 Schottky Diode Selection
The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. The
current rating for the diode must be equal to the maximum output current for best reliability in most applications.
In cases where the input voltage is much greater than the output voltage, the average diode current is lower. In
this case it is possible to use a diode with a lower average current rating, approximately (1-D) × IOUT however
the peak current rating must be higher than the maximum load current. A 3-A rated diode is a good starting
point.
8.2.2.7 Input Capacitor Selection
The LMR16030 device requires high frequency input decoupling capacitor or capacitors and a bulk input
capacitor, depending on the application. The typical recommended value for the high frequency decoupling
capacitor is 4.7 μF to 10 μF. A high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating is
recommended. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input
voltage is recommended. Additionally, some bulk capacitance can be required, especially if the LMR16030
circuit is not located within approximately 5 cm from the input voltage source. This capacitor is used to provide
damping to the voltage spike due to the lead inductance of the cable or the trace. For this design, two 2.2-μF,
X7R ceramic capacitors rated for 100 V are used. 0.1 μF for high-frequency filtering and place it as close as
possible to the device pins.
8.2.2.8 Bootstrap Capacitor Selection
Every LMR16030 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and
rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
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8.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 24 V, fSW = 500 KHz, L = 8.2 µH, COUT = 2 × 47 µF, TA =
25°C.
VIN = 24 V
VOUT = 5 V
IOUT = 2 A
VIN = 24 V
VOUT = 5 V
IOUT = 2 A
IOUT = 0 A
IOUT = 2 A
图8-3. Start-up By VIN
图8-2. Start-up By EN
VIN = 24 V
VOUT = 5 V
VIN = 24 V
VOUT = 5 V
IOUT = 200 mA
图8-4. Sleep Mode
图8-5. DCM Mode
VIN = 24 V
VOUT = 5 V
IOUT: 20% →80% of 3 A
Slew rate = 100 mA/μs
图8-6. CCM Mode
图8-7. Load Transient
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VIN = 24 V
VOUT = 5 V
VIN = 24 V
VOUT = 5 V
图8-8. Output Short
图8-9. Output Short Recovery
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9 Power Supply Recommendations
The LMR16030 is designed to operate from an input voltage supply range between 4.3 V and 60 V. This input
supply must be able to withstand the maximum input current and maintain a stable voltage. The resistance of the
input supply rail should be low enough that an input current transient does not cause a high enough drop at the
LMR16030 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is
located more than a few inches from the LMR16030, additional bulk capacitance can be required in addition to
the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic
capacitor is a typical choice.
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ZHCSF41B –DECEMBER 2015 –REVISED MARCH 2021
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The feedback network, resistor RFBT and RFBB, should be kept close to the FB pin. VOUT sense path away
from noisy nodes and preferably through a layer on the other side of a shielding layer.
2. The input bypass capacitor CIN must be placed as close as possible to the VIN pin and ground. Grounding
for both the input and output capacitors should consist of localized top side planes that connect to the GND
pin and PAD.
3. The inductor L should be placed close to the SW pin to reduce magnetic and electrostatic noise.
4. The output capacitor, COUT should be placed close to the junction of L and the diode D. The L, D, and COUT
trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency.
5. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the system
ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane.
6. For more detail on switching power supply layout considerations see SNVA021 Application Note AN-1149.
10.2 Layout Example
Output Bypass
Capacitor
Output
Inductor
Rectifier Diode
BOOT
Capacitor
Input Bypass
Capacitor
BOOT
VIN
SW
GND
SS
Soft-Start
Capacitor
EN
RT/SYNC
FB
UVLO Adjust
Resistor
Output Voltage
Set Resistor
Thermal VIA
Signal VIA
Frequency
Set Resistor
图10-1. Layout
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ZHCSF41B –DECEMBER 2015 –REVISED MARCH 2021
11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM76003 device with the WEBENCH® Power Designer.
Click here to create a custom design using the LM16030 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
PowerPAD™ is a trademark of TI.
TI E2E™ is a trademark of Texas Instruments.
SIMPLE SWITCHER® is a registered trademark of TI.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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ZHCSF41B –DECEMBER 2015 –REVISED MARCH 2021
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR16030PDDA
LMR16030PDDAR
LMR16030SDDA
LMR16030SDDAR
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DDA
DDA
8
8
8
8
75
RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SB3P
SB3P
SB3S
SB3S
Samples
Samples
Samples
Samples
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
75 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMR16030PDDA
LMR16030PDDA
LMR16030SDDA
LMR16030SDDA
DDA
DDA
DDA
DDA
HSOIC
HSOIC
HSOIC
HSOIC
8
8
8
8
75
75
75
75
507
517
517
507
8
3940
635
4.32
4.25
4.25
4.32
7.87
7.87
8
635
3940
Pack Materials-Page 1
PACKAGE OUTLINE
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
A
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.4
2.8
9
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.71
2.11
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.4)
SOLDER MASK
OPENING
TYP
9
SYMM
(1.3)
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
8
1
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
SYMM
9
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
0.125
0.150
0.175
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
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