LMX2331UTM/NOPB [TI]
PLL FREQUENCY SYNTHESIZER, 2000MHz, PDSO20, 0.173 INCH, PLASTIC, TSSOP-20;
| 型号： | LMX2331UTM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PLL FREQUENCY SYNTHESIZER, 2000MHz, PDSO20, 0.173 INCH, PLASTIC, TSSOP-20 光电二极管 |
| 文件： | 总49页 (文件大小：4568K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2002
LMX2330U/LMX2331U/LMX2332U
™
PLLatinum Ultra Low Power Dual Frequency
Synthesizer for RF Personal Communications
LMX2330U 2.5 GHz/600 MHz
LMX2331U 2.0 GHz/600 MHz
LMX2332U 1.2 GHz/600 MHz
General Description
Features
n Ultra Low Current Consumption
The LMX233xU devices are high performance frequency
synthesizers with integrated dual modulus prescalers. The
LMX233xU devices are designed for use as RF and IF local
oscillators for dual conversion radio transceivers.
n Upgrade and Compatible to LMX233xL Family
n 2.7V to 5.5V Operation
n Selectable Synchronous or Asynchronous Powerdown
Mode:
ICC-PWDN = 1 µA typical
n Selectable Dual Modulus Prescaler:
A 32/33 or a 64/65 prescale ratio can be selected for the 2.5
GHz LMX2330U RF synthesizer. A 64/65 or a 128/129 pres-
cale ratio can be selected for both the LMX2331U and
LMX2332U RF synthesizers. The IF circuitry contains an 8/9
or a 16/17 prescaler. Using a proprietary digital phase locked
loop technique, the LMX233xU devices generate very
stable, low noise control signals for RF and IF voltage con-
trolled oscillators. Both the RF and IF synthesizers include a
two-level programmable charge pump. The RF synthesizer
has dedicated Fastlock circuitry.
LMX2330U
LMX2331U
LMX2332U
RF: 32/33 or 64/65
RF: 64/65 or 128/129
RF: 64/65 or 128/129
LMX2330U/31U/32U IF: 8/9 or 16/17
n Selectable Charge Pump TRI-STATE® Mode
n Programmable Charge Pump Current Levels
RF and IF: 0.95 or 3.8 mA
Serial data is transferred to the devices via a three-wire
interface (Data, LE, Clock). Supply voltages from 2.7V to
5.5V are supported. The LMX233xU family features ultra low
current consumption:
™
n Selectable Fastlock Mode for the RF Synthesizer
n Push-Pull Analog Lock Detect Output
n Available in 20-Pin TSSOP, 24-Pin CSP, and 20-Pin
UTCSP
LMX2330U (2.5 GHz)—3.3 mA, LMX2331U (2.0 GHz)
—2.9 mA, LMX2332U (1.2 GHz)—2.5 mA at 3.0V.
Applications
The LMX233xU devices are available in 20-Pin TSSOP,
24-Pin CSP, and 20-Pin UTCSP surface mount plastic pack-
ages.
n Mobile Handsets
(GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC,
DCS)
n Cordless Handsets
(DECT, DCT)
n Wireless Data
n Cable TV Tuners
Thin Shrink Small Outline Package
Ultra Thin Chip Scale Package
(SLE20A)
(MTC20)
Chip Scale Package (SLB24A)
10136695
10136680
10136681
™
PLLatinum is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS101366
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Functional Block Diagram
10136601
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2
Connection Diagrams
Chip Scale Package (SLB)
(Top View)
Thin Shrink Small Outline Package (TM)
(Top View)
10136602
10136639
Ultra Thin Chip Scale Package (SLE)
(Top View)
10136696
Pin Descriptions
Pin
Pin No.
Pin No.
Pin No.
I/O
Description
Name 20-Pin UTCSP 24-Pin CSP 20-Pin TSSOP
VCC
20
24
1
—
Power supply bias for the RF PLL analog and digital circuits.
VCC may range from 2.7V to 5.5V. Bypass capacitors should be
placed as close as possible to this pin and be connected directly
to the ground plane.
VP RF
Do RF
1
2
2
3
2
3
—
O
RF PLL charge pump power supply. Must be ≥ VCC.
RF PLL charge pump output. The output is connected to the
external loop filter, which drives the input of the VCO.
Ground for the RF PLL digital circuitry.
GND
3
4
4
5
4
5
—
I
fIN RF
RF PLL prescaler input. Small signal input from the VCO.
3
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Pin Descriptions (Continued)
Pin
Pin No.
Pin No.
Pin No.
I/O
Description
Name 20-Pin UTCSP 24-Pin CSP 20-Pin TSSOP
fIN RF
5
6
6
I
RF PLL prescaler complementary input. For single ended
operation, this pin should be AC grounded. The LMX233xU RF
PLL can be driven differentially when the bypass capacitor is
omitted.
GND
6
7
7
8
7
8
—
I
Ground for the RF PLL analog circuitry.
OSCin
Reference oscillator input. The input has an approximate VCC/2
threshold and can be driven from an external CMOS or TTL logic
gate.
™
GND
FoLD
8
9
10
11
9
—
O
Ground for the IF PLL digital circuits, MICROWIRE , FoLD, and
oscillator circuits.
10
Programmable multiplexed output pin. Functions as a general
purpose CMOS TRI-STATE output, RF/IF PLL push-pull analog
lock detect output, N and R divider output or Fastlock output,
which connects a parallel resistor to the external loop filter.
MICROWIRE Clock input. High impedance CMOS input. Data is
clocked into the 22-bit shift register on the rising edge of Clock.
MICROWIRE Data input. High impedance CMOS input. Binary
serial data. The MSB of Data is shifted in first. The last two bits
are the control bits.
Clock
Data
10
11
12
14
11
12
I
I
LE
12
15
13
I
MICROWIRE Latch Enable input. High impedance CMOS input.
When LE transitions HIGH, Data stored in the shift register is
loaded into one of 4 internal control registers.
GND
fIN IF
13
14
16
17
14
15
—
I
Ground for the IF PLL analog circuitry.
IF PLL prescaler complementary input. For single ended
operation, this pin should be AC grounded. The LMX233xU IF
PLL can be driven differentially when the bypass capacitor is
omitted.
fIN IF
GND
15
16
18
19
16
17
I
IF PLL prescaler input. Small signal input from the VCO.
Ground for the IF PLL digital circuitry, MICROWIRE, FoLD, and
oscillator circuits.
—
Do IF
17
20
18
O
IF PLL charge pump output. The output is connected to the
external loop filter, which drives the input of the VCO.
VP IF
VCC
18
19
22
23
19
20
—
—
IF PLL charge pump power supply. Must be ≥ VCC.
Power supply bias for the IF PLL analog and digital circuits,
MICROWIRE, FoLD, and oscillator circuits. VCC may range from
2.7V to 5.5V. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground
plane.
NC
X
1, 9, 13, 21
X
—
No connect.
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Ordering Information
Model
Temperature Range
Package Description
Ultra Thin Chip Scale
Package (UTCSP)
Tape and Reel
Packing
NS Package Number
LMX2330USLEX
−40˚C to +85˚C
2500 Units Per Reel
SLE20A
LMX2330USLBX
LMX2330UTM
−40˚C to +85˚C
−40˚C to +85˚C
Chip Scale Package
(CSP) Tape and Reel
Thin Shrink Small
Outline Package
(TSSOP)
2500 Units Per Reel
73 Units Per Rail
SLB24A
MTC20
LMX2330UTMX
LMX2331USLEX
−40˚C to +85˚C
−40˚C to +85˚C
Thin Shrink Small
Outline Package
(TSSOP) Tape and
Reel
2500 Units Per Reel
2500 Units Per Reel
MTC20
Ultra Thin Chip Scale
Package (UTCSP)
Tape and Reel
SLE20A
LMX2331USLBX
LMX2331UTM
−40˚C to +85˚C
−40˚C to +85˚C
Chip Scale Package
(CSP) Tape and Reel
Thin Shrink Small
Outline Package
(TSSOP)
2500 Units Per Reel
73 Units Per Rail
SLB24A
MTC20
LMX2331UTMX
LMX2332USLEX
−40˚C to +85˚C
−40˚C to +85˚C
Thin Shrink Small
Outline Package
(TSSOP) Tape and
Reel
2500 Units Per Reel
2500 Units Per Reel
MTC20
Ultra Thin Chip Scale
Package (UTCSP)
Tape and Reel
SLE20A
LMX2332USLBX
LMX2332UTM
−40˚C to +85˚C
−40˚C to +85˚C
Chip Scale Package
(CSP) Tape and Reel
Thin Shrink Small
Outline Package
(TSSOP)
2500 Units Per Reel
73 Units Per Rail
SLB24A
MTC20
LMX2332UTMX
−40˚C to +85˚C
Thin Shrink Small
Outline Package
(TSSOP) Tape and
Reel
2500 Units Per Reel
MTC20
5
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Detailed Block Diagram
10136603
Notes:
1. A 64/65 or 128/129 prescaler ratio can be selected for the LMX2331U and LMX2332U RF synthesizers. A 32/33 or 64/65 prescaler ratio can be selected for the
LMX2330U RF synthesizer.
2. V
supplies power to the RF and IF prescalers, RF and IF feedback dividers, RF and IF reference dividers, RF and IF phase detectors, the OSC buffer,
CC
in
MICROWIRE, and F LD circuitry.
o
3. V RF and V IF supply power to the charge pumps. They can be run separately as long as V RF ≥ V
and V IF ≥ V
.
CC
P
P
P
CC
P
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6
Absolute Maximum Ratings (Notes 1,
Recommended Operating
Conditions (Note 1)
2, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
VCC to GND
+2.7V to +5.5V
VCC to +5.5V
VCC to +5.5V
−40˚C to +85˚C
VP RF to GND
Power Supply Voltage
VP IF to GND
VCC to GND
−0.3V to +6.5V
−0.3V to +6.5V
−0.3V to +6.5V
Operating Temperature (TA)
VP RF to GND
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate condi-
tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi-
tions, refer to the Electrical Characteristics section. The guaranteed specifi-
cations apply only for the conditions listed.
VP IF to GND
Voltage on any pin to GND (VI)
<
VI must be +6.5V
−0.3V to VCC+0.3V
−65˚C to +150˚C
+260˚C
Storage Temperature Range (TS)
Lead Temperature (solder 4 s) (TL)
TSSOP θJA Thermal Impedance
CSP θJA Thermal Impedance
Note 2: This device is a high performance RF integrated circuit with an ESD
rating 2 kV and is ESD sensitive. Handling and assembly of this device
<
114.5˚C/W
should only be done at ESD protected work stations.
Note 3: GND = 0V
112˚C/W
Electrical Characteristics
VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified
Value
Typ
Symbol
Parameter
Conditions
Units
Min
Max
ICC PARAMETERS
ICC
ICC
ICC
Power Supply
LMX2330U
Clock, Data and LE = GND
OSCin = GND
3.3
2.9
4.3
3.8
mA
mA
RF + IF
Current, RF + IF
Synthesizers
LMX2331U
PWDN RF Bit = 0
PWDN IF Bit = 0
LMX2332U
LMX2330U
2.5
2.3
3.3
3.0
mA
mA
Power Supply
Current, RF
Clock, Data and LE = GND
OSCin = GND
RF
LMX2331U
1.9
2.5
mA
Synthesizer Only
PWDN RF Bit = 0
PWDN IF Bit = 1
LMX2332U
LMX233xU
1.5
1.0
2.0
1.3
mA
mA
Power Supply
Current, IF
Clock, Data and LE = GND
OSCin = GND
IF
Synthesizer Only
PWDN RF Bit = 1
PWDN IF Bit = 0
ICC-PWDN
Powerdown Current
LMX233xU
Clock, Data and LE = GND
OSCin = GND
1.0
10.0
µA
PWDN RF Bit = 1
PWDN IF Bit = 1
RF SYNTHESIZER PARAMETERS
fIN RF
LMX2330U
LMX2331U
LMX2332U
500
200
100
96
2500
2000
1200
65631
MHz
MHz
MHz
RF Operating
Frequency
NRF
RF N Divider Range
Prescaler = 32/33
(Note 4)
Prescaler = 64/65
(Note 4)
192
384
3
131135
262143
Prescaler = 128/129
(Note 4)
RRF
RF R Divider Range
32767
10
FφRF
RF Phase Detector Frequency
MHz
7
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Electrical Characteristics (Continued)
VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified
Value
Typ
Symbol
Parameter
Conditions
Units
Min
−15
−10
Max
0
RF SYNTHESIZER PARAMETERS
PfIN RF
RF Input Sensitivity
2.7V ≤ VCC ≤ 3.0V
(Note 5)
dBm
dBm
mA
<
3.0 VCC ≤ 5.5V
0
(Note 5)
IDo RF
RF Charge Pump Output Source
Current
VDo RF = VP RF/2
IDo RF Bit = 0
(Note 6)
-0.95
-3.80
0.95
3.80
SOURCE
VDo RF = VP RF/2
IDo RF Bit = 1
(Note 6)
mA
mA
mA
IDo RF
SINK
RF Charge Pump Output Sink Current VDo RF = VP RF/2
IDo RF Bit = 0
(Note 6)
VDo RF = VP RF/2
IDo RF Bit = 1
(Note 6)
IDo RF
RF Charge Pump Output TRI-STATE 0.5V ≤ VDo RF ≤ VP RF - 0.5V
-2.5
2.5
10
nA
%
TRI-STATE Current
(Note 6)
IDo RF
SINK
Vs
RF Charge Pump Output Sink Current VDo RF = VP RF/2
3
Vs Charge Pump Output Source
Current Mismatch
TA = +25˚C
(Note 7)
IDo RF
SOURCE
IDo RF
Vs
RF Charge Pump Output Current
0.5V ≤ VDo RF ≤ VP RF - 0.5V
10
10
15
%
%
Magnitude Variation Vs Charge Pump TA = +25˚C
VDo RF
IDo RF
Vs
Output Voltage
(Note 7)
RF Charge Pump Output Current
Magnitude Variation Vs Temperature
VDo RF = VP RF/2
(Note 7)
TA
IF SYNTHESIZER PARAMETERS
fIN IF
IF Operating
Frequency
LMX2330U
LMX2331U
LMX2332U
45
45
45
24
600
600
MHz
MHz
MHz
600
NIF
IF N Divider Range
Prescaler = 8/9
(Note 4)
16391
Prescaler = 16/17
(Note 4)
48
3
32767
RIF
IF R Divider Range
32767
10
FφIF
IF Phase Detector Frequency
IF Input Sensitivity
MHz
dBm
PfIN IF
2.7V ≤ VCC ≤ 5.5V
-10
0
(Note 5)
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Electrical Characteristics (Continued)
VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified
Value
Typ
Symbol
Parameter
Conditions
Units
Min
Max
IF SYNTHESIZER PARAMETERS
IDo IF
IF Charge Pump Output Source
Current
VDo IF = VP IF/2
-0.95
-3.80
0.95
3.80
mA
SOURCE
IDo IF Bit = 0
(Note 6)
VDo IF = VP IF/2
IDo IF Bit = 1
(Note 6)
mA
mA
mA
IDo IF
SINK
IF Charge Pump Output Sink Current VDo IF = VP IF/2
IDo IF Bit = 0
(Note 6)
VDo IF = VP IF/2
IDo IF Bit = 1
(Note 6)
IDo IF
IF Charge Pump Output TRI-STATE
0.5V ≤ VDo IF ≤ VP IF - 0.5V
(Note 6)
IF Charge Pump Output Sink Current VDo IF = VP IF/2
-2.5
2.5
10
nA
%
TRI-STATE Current
IDo IF
SINK
Vs
3
Vs Charge Pump Output Source
Current Mismatch
TA = +25˚C
(Note 7)
IDo IF
SOURCE
IDo IF
Vs
IF Charge Pump Output Current
0.5V ≤ VDo IF ≤ VP IF - 0.5V
10
10
15
%
%
Magnitude Variation Vs Charge Pump TA = +25˚C
VDo IF
IDo IF
Vs
Output Voltage
(Note 7)
IF Charge Pump Output Current
Magnitude Variation Vs Temperature
VDo IF = VP IF/2
(Note 7)
TA
OSCILLATOR PARAMETERS
FOSC
VOSC
IOSC
Oscillator Operating Frequency
2
40
MHz
VPP
µA
Oscillator Sensitivity
(Note 8)
0.5
VCC
100
Oscillator Input Current
VOSC = VCC = 5.5V
VOSC = 0V, VCC = 5.5V
-100
µA
DIGITAL INTERFACE (Data, LE, Clock, FoLD)
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
High-Level Output Voltage
0.8 VCC
V
V
0.2 VCC
1.0
VIH = VCC = 5.5V
VIL = 0V, VCC = 5.5V
IOH = −500 µA
−1.0
−1.0
µA
µA
V
IIL
1.0
VOH
VCC
0.4
−
VOL
Low-Level Output Voltage
IOL = 500 µA
0.4
V
MICROWIRE INTERFACE
tCS
Data to Clock Set Up Time
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
50
10
50
50
50
50
ns
ns
ns
ns
ns
ns
tCH
Data to Clock Hold Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
tCWH
tCWL
tES
Clock to Load Enable Set Up Time
Latch Enable Pulse Width
tEW
9
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Electrical Characteristics (Continued)
VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified
Value
Typ
Symbol
Parameter
Conditions
Units
Min
Max
PHASE NOISE CHARACTERISTICS
LN(f) RF
L(f) RF
RF Synthesizer Normalized Phase
TCXO Reference Source
IDo RF Bit = 1
-212.0
-77.24
dBc/
Hz
Noise Contribution
(Note 10)
RF Synthesizer Single LMX2330U
Side Band Phase
fIN RF = 2450 MHz
f = 1 kHz Offset
FφRF = 200 kHz
Loop Bandwidth = 7.5 kHz
N = 12250
dBc/
Hz
Noise Measured
FOSC = 10 MHz
VOSC = 0.632 VPP
IDo RF Bit = 1
PWDN IF Bit = 1
TA = +25˚C
(Note 11)
LMX2331U
fIN RF = 1960 MHz
f = 1 kHz Offset
FφRF = 200 kHz
Loop Bandwidth = 15 kHz
N = 9800
-79.18
dBc/
Hz
FOSC = 10 MHz
VOSC = 0.632 VPP
IDo RF Bit = 1
PWDN IF Bit = 1
TA = +25˚C
(Note 11)
LMX2332U
fIN RF = 900 MHz
f = 1 kHz Offset
FφRF = 200 kHz
Loop Bandwidth = 12 kHz
N = 4500
-85.94
dBc/
Hz
FOSC = 10 MHz
VOSC = 0.632 VPP
IDo RF Bit = 1
PWDN IF Bit = 1
TA = +25˚C
(Note 11)
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Electrical Characteristics (Continued)
VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified
Value
Typ
Symbol
Parameter
Conditions
Units
Min
Max
PHASE NOISE CHARACTERISTICS
LN(f) IF
L(f) IF
IF Synthesizer Normalized Phase
TCXO Reference Source
IDo IF Bit = 1
-212.0
-99.00
dBc/
Hz
Noise Contribution
(Note 10)
IF Synthesizer Single LMX233xU
Side Band Phase
fIN IF = 200 MHz
f = 1 kHz Offset
FφIF = 200 kHz
Loop Bandwidth = 18 kHz
N = 1000
dBc/
Hz
Noise Measured
FOSC = 10 MHz
VOSC = 0.632 VPP
IDo IF Bit = 1
PWDN RF Bit = 1
TA = +25˚C
(Note 11)
<
Note 4: Some of the values in this range are illegal divide ratios (B A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N
*
≥ P (P−1), where P is the value of the prescaler selected.
Note 5: Refer to the LMX233xU f Sensitivity Test Setup section
IN
Note 6: Refer to the LMX233xU Charge Pump Test Setup section
Note 7: Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made.
Note 8: Refer to the LMX233xU OSC Sensitivity Test Setup section
in
Note 9: Refer to the LMX233xU Serial Data Input Timing section
Note 10: Normalized Phase Noise Contribution is defined as : L (f) = L(f) − 20 log (N) − 10 log (F ), where L(f) is defined as the single side band phase noise
N
φ
measured at an offset frequency, f, in a 1 Hz bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL’s loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and F is the RF/IF phase detector
φ
comparison frequency.
Note 11: The synthesizer phase noise is measured with the LMX2330TMEB/LMX2330SLBEB/LMX2330SLEEB Evaluation boards and the HP8566B Spectrum
Analyzer.
11
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Typical Performance Characteristics
Sensitivity
LMX2330U fIN RF Input Power Vs Frequency
VCC = VP RF = 3.0V
10136642
LMX2330U fIN RF Input Power Vs Frequency
VCC = VP RF = 5.5V
10136643
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Typical Performance Characteristics
Sensitivity (Continued)
LMX2331U fIN RF Input Power Vs Frequency
VCC = VP RF = 3.0V
10136644
LMX2331U fIN RF Input Power Vs Frequency
VCC = VP RF = 5.5V
10136645
13
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Typical Performance Characteristics
Sensitivity (Continued)
LMX2332U fIN RF Input Power Vs Frequency
VCC = VP RF = 3.0V
10136646
LMX2332U fIN RF Input Power Vs Frequency
VCC = VP RF = 5.5V
10136647
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Typical Performance Characteristics
Sensitivity (Continued)
LMX233xU fIN IF Input Power Vs Frequency
VCC = VP IF = 3.0V
10136648
LMX233xU fIN IF Input Power Vs Frequency
VCC = VP IF = 5.5V
10136649
15
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Typical Performance Characteristics
Sensitivity (Continued)
LMX233xU OSCin Input Voltage Vs Frequency
VCC = 3.0V
10136652
LMX233xU OSCin Input Voltage Vs Frequency
VCC = 5.5V
10136653
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Typical Performance Characteristics
Charge Pump
LMX233xU RF Charge Pump Sweeps
−40˚C ≤ TA ≤ +85˚C
10136660
17
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Typical Performance Characteristics
Charge Pump (Continued)
LMX233xU IF Charge Pump Sweeps
−40˚C ≤ TA ≤ +85˚C
10136661
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Typical Performance Characteristics
Input Impedance
LMX233xU TSSOP fIN RF Input Impedance
VCC= 3.0V, TA = +25˚C
LMX233xU TSSOP fIN RF Input Impedance
VCC= 5.5V, TA = +25˚C
10136666
10136667
LMX233xU CSP fIN RF Input Impedance
VCC= 3.0V, TA = +25˚C
LMX233xU CSP fIN RF Input Impedance
VCC= 5.5V, TA = +25˚C
10136668
10136669
19
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Typical Performance Characteristics
Input Impedance (Continued)
LMX233xU UTCSP fIN RF Input Impedance
VCC= 3.0V, TA = +25˚C
LMX233xU UTCSP fIN RF Input Impedance
VCC= 5.5V, TA = +25˚C
10136697
10136697
21
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Typical Performance Characteristics
Input Impedance (Continued)
LMX233xU TSSOP fIN IF Input Impedance
VCC= 3.0V, TA = +25˚C
LMX233xU TSSOP fIN IF Input Impedance
VCC= 5.5V, TA = +25˚C
10136671
10136672
LMX233xU CSP fIN IF Input Impedance
VCC= 3.0V, TA = +25˚C
LMX233xU CSP fIN IF Input Impedance
VCC= 5.5V, TA = +25˚C
10136673
10136674
23
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24
Typical Performance Characteristics
Input Impedance (Continued)
LMX233xU UTCSP fIN IF Input Impedance
VCC= 3.0V, TA = +25˚C
LMX233xU UTCSP fIN IF Input Impedance
VCC= 5.5V, TA = +25˚C
10136699
10136699
25
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26
Typical Performance Characteristics
Input Impedance (Continued)
LMX233xU TSSOP OSCin Input Impedance Vs Frequency
TA = +25˚C
10136676
LMX233xU CSP OSCin Input Impedance Vs Frequency
TA = +25˚C
10136677
27
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28
Typical Performance Characteristics
Input Impedance (Continued)
LMX233xU UTCSP OSCin Input Impedance Vs Frequency
TA = +25˚C
101366A1
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30
Charge Pump Current Specification Definitions
10136637
I1 = Charge Pump Sink Current at VD = V − ∆V
o
P
I2 = Charge Pump Sink Current at VD = V /2
o
P
I3 = Charge Pump Sink Current at VD = ∆V
o
I4 = Charge Pump Source Current at VD = V − ∆V
o
P
I5 = Charge Pump Source Current at VD = V /2
o
P
I6 = Charge Pump Source Current at VD = ∆V
o
∆V = Voltage offset from the positive and negative rails. Dependent on the VCO tuning range relative to V
and GND. Typical values are between 0.5V and
CC
1.0V.
V
refers to either V RF or V IF
P P
P
VD refers to either VD RF or VD IF
o
o
o
ID refers to either ID RF or ID IF
o
o
o
Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage
10136663
Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch
10136664
Charge Pump Output Current Magnitude Variation Vs Temperature
10136665
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Test Setups
LMX233xU Charge Pump Test Setup
10136650
The block diagram above illustrates the setup required to
measure the LMX233xU device’s RF charge pump sink cur-
rent. The same setup is used for the LMX2330TMEB/
LMX2330SLEEB Evaluation Boards. The IF charge pump
measurement setup is similar to the RF charge pump mea-
surement setup. The purpose of this test is to assess the
functionality of the RF charge pump.
sured by switching the Charge Pump Gain’s state between
1X and 4X in Code Loader.
Let Fr represent the frequency of the signal applied to the
OSCin pin, which is simply zero in this case (DC), and let Fp
represent the frequency of the signal applied to the fIN RF
pin. The phase detector is sensitive to the rising edges of Fr
and Fp. Assuming positive VCO characteristics; the charge
pump turns ON and sinks current when the first rising edge
of Fp is detected. Since Fr has no rising edge, the charge
pump continues to sink current indefinitely.
This setup uses an open loop configuration. A power supply
is connected to Vcc and swept from 2.7V to 5.5V. By means
of a signal generator, a 10 MHz signal is typically applied to
the fIN RF pin. The signal is one of two inputs to the phase
detector. The 3 dB pad provides a 50 Ω match between the
Toggling the Phase Detector Polarity state to negative
VCO characteristics allows the measurement of the RF
charge pump source current. Likewise, selecting TRI-STATE
(TRI-STATE IDo RF Bit = 1) for Charge Pump State in Code
Loader facilitates the measurement of the TRI-STATE cur-
rent.
PLL and the signal generator. The OSCin pin is tied to Vcc
.
This establishes the other input to the phase detector. Alter-
natively, this input can be tied directly to the ground plane.
With the Do RF pin connected to a Semiconductor Param-
eter Analyzer in this way, the sink, source, and TRI-STATE
currents can be measured by simply toggling the Phase
Detector Polarity and Charge Pump State states in Code
Loader. Similarly, the LOW and HIGH currents can be mea-
The measurements are repeated at different temperatures,
namely TA = -40˚C, +25˚C, and +85˚C.
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Test Setups (Continued)
LMX233xU fIN Sensitivity Test Setup
10136640
The block diagram above illustrates the setup required to
measure the LMX233xU device’s RF input sensitivity level.
The same setup is used for the LMX2330TMEB/
LMX2330SLEEB Evaluation Boards. The IF input sensitivity
test setup is similar to the RF sensitivity test setup. The
purpose of this test is to measure the acceptable signal level
to the fIN RF input of the PLL chip. Outside the acceptable
signal range, the feedback divider begins to divide incor-
rectly and miscount the frequency.
selecting the RF PLL N Divider Output word (FoLD Word =
6 or 14) in Code Loader. A Universal Counter is connected to
the FoLD pin and tied to the 10 MHz reference output of the
signal generator. The output of the feedback divider is thus
monitored and should be equal to fIN RF / N.
The fIN RF input frequency and power level are then swept
with the signal generator. The measurements are repeated
at different temperatures, namely TA = -40˚C, +25˚C, and
+85˚C. Sensitivity is reached when the frequency error of the
divided RF input is greater than or equal to 1 Hz. The power
attenuation from the cable and the 3 dB pad must be ac-
counted for. The feedback divider will actually miscount if too
much or too little power is applied to the fIN RF input.
Therefore, the allowed input power level will be bounded by
the upper and lower sensitivity limits. In a typical application,
if the power level to the fIN RF input approaches the sensi-
tivity limits, this can introduce spurs and degradation in
phase noise. When the power level gets even closer to these
limits, or exceeds it, then the RF PLL loses lock.
The setup uses an open loop configuration. A power supply
is connected to Vcc and swept from 2.7V to 5.5V. The IF PLL
is powered down (PWDN IF Bit = 1). By means of a signal
generator, an RF signal is applied to the fIN RF pin. The 3 dB
pad provides a 50 Ω match between the PLL and the signal
generator. The OSCin pin is tied to Vcc. The N value is
typically set to 10000 in Code Loader, i.e. RF N_CNTRB
Word = 156 and RF N_CNTRA Word = 16 for PRE RF Bit =
1 (LMX2330U) or PRE RF = 0 (LMX2331U and LMX2332U).
The feedback divider output is routed to the FoLD pin by
33
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Test Setups (Continued)
LMX233xU OSCin Sensitivity Test Setup
10136641
The block diagram above illustrates the setup required to
measure the LMX233xU device’s OSCin buffer sensitivity
level. The same setup is used for the LMX2330TMEB/
LMX2330SLEEB Evaluation Boards. This setup is similar to
the fIN sensitivity setup except that the signal generator is
now connected to the OSCin pin and both fIN pins are tied to
VCC. The 51 Ω shunt resistor matches the OSCin input to the
signal generator. The R counter is typically set to 1000, i.e.
RF R_CNTR Word = 1000 or IF R_CNTR Word = 1000. The
reference divider output is routed to the FoLD pin by select-
ing the RF PLL R Divider Output word (FoLD Word = 2 or
10) or the IF PLL R Divider Output word (FoLD Word = 1 or
9) in Code Loader. Similarly, a Universal Counter is con-
nected to the FoLD pin and is tied to the 10 MHz reference
output from the signal generator. The output of the reference
divider is monitored and should be equal to OSCin/ RF
R_CNTR or OSCin/ IF R_CNTR.
Again, VCC is swept from 2.7V to 5.5V. The OSCin input
frequency and voltage level are then swept with the signal
generator. The measurements are repeated at different tem-
peratures, namely TA = -40˚C, +25˚C, and +85˚C. Sensitivity
is reached when the frequency error of the divided input
signal is greater than or equal to 1 Hz.
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Test Setups (Continued)
LMX233xU fIN Impedance Test Setup
10136679
The block diagram above illustrates the setup required to
measure the LMX233xU device’s RF input impedance. The
IF input impedance and reference oscillator impedance set-
ups are very much similar. The same setup is used for the
LMX2330TMEB/ LMX2330SLEEB Evaluation Boards. Mea-
suring the device’s input impedance facilitates the design of
appropriate matching networks to match the PLL to the VCO,
or in more critical situations, to the characteristic impedance
of the printed circuit board (PCB) trace, to prevent undesired
transmission line effects.
must be included in the calibration. Although not shown, 0 Ω
resistors are used to complete the RF OUT transmission line
(trace).
To implement an open standard, the end of the RF OUT
trace is simply left open. To implement a short standard, a 0
Ω resistor is placed at the end of the RF OUT transmission
line. Last of all, to implement a matched load standard, two
100 Ω resistors in parallel are placed at the end of the RF
OUT transmission line. The Network Analyzer calculates the
calibration coefficients based on the measured S11 param-
eters. With this all done, calibration is now complete.
Before the actual measurements are taken, the Network
Analyzer needs to be calibrated, i.e. the error coefficients
need to be calculated. Therefore, three standards will be
used to calculate these coefficients: an open, short and a
matched load. A 1-port calibration is implemented here.
The PLL chip is then placed on the PCB. A power supply is
connected to VCC and swept from 2.7V to 5.5V. The OSCin
pin is tied to the ground plane. Alternatively, the OSCin pin
can be tied to VCC. In this setup, the complementary input
(fIN RF) is AC coupled to ground. With the Network Analyzer
still connected to RF OUT, the measured fIN RF impedance
is displayed.
To calculate the coefficients, the PLL chip is first removed
from the PCB. The Network Analyzer port is then connected
to the RF OUT connector of the evaluation board and the
desired operating frequency is set. The typical frequency
range selected for the LMX233xU device’s RF synthesizer is
from 100 MHz to 2500 MHz. The standards will be located
down the length of the RF OUT transmission line. The trans-
mission line adds electrical length and acts as an offset from
the reference plane of the Network Analyzer; therefore, it
Note: The impedance of the reference oscillator is measured
when the oscillator buffer is powered up (PWDN RF Bit = 0
or PWDN IF Bit = 0), and when the oscillator buffer is
powered down (PWDN RF Bit = 1 and PWDN IF Bit = 1).
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LMX233xU Serial Data Input Timing
10136610
Notes:
1. Data is clocked into the 22-bit shift register on the rising edge of Clock
2. The MSB of Data is shifted in first.
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1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX233xU, a
voltage controlled oscillator (VCO), and a passive loop filter.
The frequency synthesizer includes a phase detector, cur-
rent mode charge pump, programmable reference R and
feedback N frequency dividers. The VCO frequency is es-
tablished by dividing the crystal reference signal down via
the reference divider to obtain a comparison reference fre-
quency. This reference signal, Fr, is then presented to the
input of a phase/frequency detector and compared with the
feedback signal, Fp, which was obtained by dividing the VCO
frequency down by way of the feedback divider. The phase/
frequency detector measures the phase error between the Fr
and Fp signals and outputs control signals that are directly
proportional to the phase error. The charge pump then
pumps charge into or out of the loop filter based on the
magnitude and direction of the phase error. The loop filter
converts the charge into a stable control voltage for the
VCO. The phase/frequency detector’s function is to adjust
the voltage presented to the VCO until the feedback signal’s
frequency and phase match that of the reference signal.
When this “Phase-Locked” condition exists, the VCO fre-
quency will be N times that of the comparison frequency,
where N is the feedback divider ratio.
LMX2331U and LMX2332U RF synthesizers. The IF circuitry
contains an 8/9 or a 16/17 prescaler.
1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N
COUNTERS)
The programmable feedback dividers operate in concert with
the prescalers to divide the input signal, fIN, by a factor of N.
The output of the programmable reference divider is pro-
vided to the feedback input of the phase detector circuit. The
divide ratio should be chosen such that the maximum phase
comparison frequency (FφRF or FφIF) of 10 MHz is not ex-
ceeded.
The programmable feedback divider circuit is comprised of
an A counter (swallow counter) and a B counter (program-
mble binary counter). The RF N_CNTRA counter is a 7-bit
CMOS swallow counter, programmable from 0 to 127. The IF
N_CNTRA counter is also a 7-bit CMOS swallow counter,
but programmable from 0 to 15. The three most significant
bits are ’don’t cares’ in this case. The RF N_CNTRB and IF
N_CNTRB counters are both 11-bit CMOS binary counters,
programmable from 3 to 2047. A continuous integer divide
*
ratio is achieved if N ≥ P (P−1), where P is the value of the
prescaler selected. Divide ratios less than the minimum con-
tinuous divide ratio are achievable as long as the binary
programmable counter value is greater than the swallow
counter value (N_CNTRB ≥ N_CNTRA). Refer to Sections
2.5.1, 2.5.2, 2.7.1 and 2.7.2 for details on how to program
the N_CNTRA and N_CNTRB counters. The following equa-
tions are useful in determining and programming a particular
value of N:
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for both the RF and IF
PLLs is provided from an external reference via the OSCin
pin. The reference buffer circuit supports input frequencies
from 5 to 40 MHz with a minimum input sensitivity of 0.5 VPP
.
N = (P x N_CNTRB) + N_CNTRA
fIN = N x Fφ
The reference buffer circuit has an approximate VCC/2 input
threshold and can be driven from an external CMOS or TTL
logic gate. Typically, the OSCin pin is connected to the output
of a crystal oscillator.
Definitions:
Fφ:
RF or IF phase detector comparison
frequency
1.2 REFERENCE DIVIDERS (R COUNTERS)
fIN
:
RF or IF input frequency
The reference dividers divide the reference input signal,
OSCin, by a factor of R. The output of the reference divider
circuits feeds the reference input of the phase detector. This
reference input to the phase detector is often referred to as
the comparison frequency. The divide ratio should be chosen
such that the maximum phase comparison frequency (FφRF
or FφIF) of 10 MHz is not exceeded.
N_CNTRA: RF or IF A counter value
N_CNTRB: RF or IF B counter value
P:
Preset modulus of the dual moduIus
prescaler
LMX2330U RF synthesizer: P = 32 or 64
LMX2331U RF synthesizer: P = 64 or 128
LMX2332U RF synthesizer: P = 64 or 128
LMX233xU IF synthesizer: P = 8 or 16
The RF and IF reference dividers are each comprised of
15-bit CMOS binary counters that support a continuous in-
teger divide ratio from 3 to 32767. The RF and IF reference
divider circuits are clocked by the output of the reference
buffer circuit which is common to both.
1.5 PHASE/FREQUENCY DETECTORS
The RF and IF phase/frequency detectors are driven from
their respective N and R counter outputs. The maximum
frequency for both the RF and IF phase detector inputs is 10
MHz. The phase/frequency detector outputs control the re-
spective charge pumps. The polarity of the pump-up or
pump-down control signals are programmed using the PD-
_POL RF or PD_POL IF control bits, depending on whether
the RF or IF VCO characteristics are positive or negative.
Refer to Sections 2.4.2 and 2.6.2 for more details. The
phase/frequency detectors have a detection range of −2π to
+2π. The phase/frequency detectors also receive a feedback
signal from the charge pump in order to eliminate dead zone.
1.3 PRESCALERS
The fIN RF (fIN IF) and fIN RF (fIN IF) input pins drive the input
of a bipolar, differential-pair amplifier. The output of the bi-
polar, differential-pair amplifier drives a chain of ECL D-type
flip-flops in a dual modulus configuration. The output of the
prescaler is used to clock the subsequent feedback dividers.
The RF and IF PLL complementary inputs can be driven
differentially, or the negative input can be AC coupled to
ground through an external capacitor for single ended con-
figuration. A 32/33 or a 64/65 prescale ratio can be selected
for the 2.5 GHz LMX2330U RF synthesizer. A 64/65 or a
128/129 prescale ratio can be selected for both the
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1.0 Functional Description (Continued)
PHASE COMPARATOR AND INTERNAL CHARGE
PUMP CHARACTERISTICS
10136611
Notes:
1. The minimum width of the pump-up and pump-down current pulses occur at the D RF or D IF pins when the loop is phase locked.
o
o
2. The diagram assumes positive VCO characteristics, i.e. PD_POL RF or PD_POL IF = 1.
3.
4.
5.
F
F
is the phase detector input from the reference divider (R counter).
is the phase detector input from the programmable feedback divder (N counter).
refers to either the RF or IF charge pump output.
r
p
D
o
1.6 CHARGE PUMPS
1.8 MULTI-FUNCTION OUTPUTS
The charge pump directs charge into or out of an external
loop filter. The loop filter converts the charge into a stable
control voltage which is applied to the tuning input of the
VCO. The charge pump steers the VCO control voltage
towards VP RF or VP IF during pump-up events and towards
GND during pump-down events. When locked, Do RF or Do
IF are primarily in a TRI-STATE mode with small corrections
occuring at the phase comparator rate. The charge pump
output current magnitude can be selected by toggling the IDo
RF or IDo IF control bits.
The LMX233xU device’s FoLD output pin is a multi-function
output that can be configured as the RF FastLock output, a
push-pull analog lock detect output, counter reset, or used to
monitor the output of the various reference divider (R
counter) or feedback divider (N counter) circuits. The FoLD
control word is used to select the desired output function.
When the PLL is in powerdown mode, the FoLD output is
pulled to a LOW state. A complete programming description
of the multi-function output is provided in Section 2.8 FoLD.
1.8.1 Push-Pull Analog Lock Detect Output
1.7 MICROWIRE SERIAL INTERFACE
An analog lock detect status generated from the phase
detector is available on the FoLD output pin if selected. The
lock detect output goes HIGH when the charge pump is
inactive. It goes LOW when the charge pump is active during
a comparison cycle. When viewed with an oscilloscope,
narrow negative pulses are observed when the charge pump
turns on. The lock detect output signal is a push-pull con-
figuration.
The programmable register set is accessed via the MI-
CROWIRE serial interface. The interface is comprised of
three signal pins: Clock, Data and LE (Latch Enable). Serial
data is clocked into the 22-bit shift register on the rising edge
of Clock. The last two bits decode the internal control regis-
ter address. When LE transitions HIGH, data stored in the
shift register is loaded into one of four control registers
depending on the state of the address bits. The MSB of Data
is loaded in first. The synthesizers can be programmed even
in power down mode. A complete programming description
is provided in Section 2.0 Programming Description.
Three separate lock detect signals are routed to the multi-
plexer. Two of these monitor the ‘lock’ status of the individual
synthesizers. The third detects the condition when both the
RF and IF synthesizers are in a ‘locked state’. External
circuitry however, is required to provide a steady DC signal
to indicate when the PLL is in a locked state. Refer to
Section 2.8 FoLD for details on how to program the different
lock detect options.
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1.0 Functional Description (Continued)
1.8.2 Open Drain FastLock Output
The LMX233xU Fastlock feature allows faster loop response
time during lock aquisition. The loop response time (lock
time) can be approximately halved if the loop bandwidth is
doubled. In order to achieve this, the same gain/ phase
relationship at twice the loop bandwidth must be maintained.
This can be achieved by increasing the charge pump current
from 0.95 mA (IDo RF Bit = 0) in the steady state mode, to
3.8 mA (IDo RF Bit = 1) in Fastlock. When the FoLD output is
configured as a FastLock output, an open drain device is
enabled. The open drain device switches in a parallel resis-
tor R2’ to ground, of equal value to resistor R2 of the external
loop filter. The loop bandwidth is effectively doubled and
stability is maintained. Once locked to the correct frequency,
the PLL will return to a steady state condition. Refer to
Section 2.8 FoLD for details on how to configure the FoLD
output to an open drain Fastlock output.
1.9 POWER CONTROL
Each synthesizer in the LMX233xU device is individually
power controlled by device powerdown bits. The powerdown
word is comprised of the PWDN RF (PWDN IF) bit, in
conjuction with the TRI-STATE IDo RF (TRI-STATE IDo IF)
bit. The powerdown control word is used to set the operating
mode of the device. Refer to Sections 2.4.4, 2.5.4, 2.6.4,
and 2.7.4 for details on how to program the RF or IF power-
down bits.
When either the RF synthesizer or the IF synthesizer enters
the powerdown mode, the respective prescaler, phase de-
tector, and charge pump circuit are disabled. The Do RF (Do
IF), fIN RF (fIN IF), and fIN RF (fIN IF) pins are all forced to a
high impedance state. The reference divider and feedback
divider circuits are held at the load point during powerdown.
The oscillator buffer is disabled when both the RF and IF
synthesizers are powered down. The OSCin pin is forced to
a HIGH state through an approximate 100 kΩ resistance
when this condition exists. When either synthesizer is acti-
vated, the respective prescaler, phase detector, charge
pump circuit, and the oscillator buffer are all powered up.
The feedback divider, and the reference divider are held at
load point. This allows the reference oscillator, feedback
divider, reference divider and prescaler circuitry to reach
proper bias levels. After a finite delay, the feedback and
reference dividers are enabled and they resume counting in
‘close’ alignment (the maximum error is one prescaler cycle).
The MICROWIRE control register remains active and ca-
pable of loading and latching data while in the powerdown
mode.
1.8.3 Counter Reset
Three separate counter reset functions are provided. When
the FoLD is programmed to Reset IF Counters, both the IF
feedback divider and the IF reference divider are held at their
load point. When the Reset RF Counters is programmed,
both the RF feedback divider and the RF reference divider
are held at their load point. When the Reset All Counters
mode is enabled, all feedback dividers and reference divid-
ers are held at their load point. When the device is pro-
grammed to normal operation, both the feedback divider and
reference divider are enabled and resume counting in ‘close’
alignment to each other. Refer to Section 2.8 FoLD for more
details.
1.8.4 Reference Divider and Feedback Divider Output
Synchronous Powerdown Mode
The outputs of the various N and R dividers can be moni-
tored by selecting the appropriate FoLD word. This is essen-
tial when performing OSCin or fIN sensitivity measurements.
Refer to the Test Setups section for more details. Refer to
Section 2.8 FoLD for more details on how to route the
appropriate divider output to the FoLD pin.
In this mode, the powerdown function is gated by the charge
pump. When the device is configured for synchronous pow-
erdown, the device will enter the powerdown mode upon
completion of the next charge pump pulse event.
Asynchronous Powerdown Mode
In this mode, the powerdown function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous powerdown, the part will go
into powerdown mode immediately.
TRI-STATE IDo
PWDN
Operating Mode
0
1
0
1
0
0
1
1
PLL Active, Normal Operation
PLL Active, Charge Pump Output in High Impedance State
Synchronous Powerdown
Asynchronous Powerdown
Notes:
1. TRI-STATE IDo refers to either the TRI-STATE IDo RF or TRI-STATE IDo IF bit .
2. PWDN refers to either the PWDN RF or PWDN IF bit.
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2.0 Programming Description
2.1 MICROWIRE INTERFACE
The 22-bit shift register is loaded via the MICROWIRE interface. The shift register consists of a 20-bit Data[19:0] Field and a 2-bit
Address[1:0] Field as shown below. The Address Field is used to decode the internal control register address. When LE
transitions HIGH, data stored in the shift register is loaded into one of 4 control registers depending on the state of the address
bits. The MSB of Data is loaded in first. The Data Field assignments are shown in Section 2.3 CONTROL REGISTER CONTENT
MAP.
MSB
LSB
Data[19:0]
Address[1:0]
21
2 1
0
2.2 CONTROL REGISTER LOCATION
The address bits Address[1:0] decode the internal register address. The table below shows how the address bits are mapped into
the target control register.
Address[1:0]
Field
Target
Register
IF R
0
0
1
1
0
1
0
1
IF N
RF R
RF N
2.3 CONTROL REGISTER CONTENT MAP
The control register content map describes how the bits within each control register are allocated to specific control functions.
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2.0 Programming Description (Continued)
2.4 IF R REGISTER
The IF R register contains the IF R_CNTR, PD_POL IF, IDo IF, and TRI-STATE IDo IF control words, in addition to two bits that
compose the FoLD control word. The detailed descriptions and programming information for each control word is discussed in the
following sections. IF R_CNTR[14:0]
Reg. Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
Field
Data Field
TRI-
PD_
POL
IF
R
STATE ID
o
IF R_CNTR[14:0]
0
0
F LD0 F LD2
o
o
ID
IF
o
IF
IF
2.4.1 IF R_CNTR[14:0] IF Synthesizer Programmable Reference Divider (R Counter)
IF R[2:16]
The IF reference divider (IF R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are
prohibited.
Divide Ratio
IF R_CNTR[14:0]
14
0
13
0
12
0
11
0
10
0
9
0
0
•
8
0
0
•
7
0
0
•
6
0
0
•
5
0
0
•
4
0
0
•
3
0
0
•
2
0
1
•
1
1
0
•
0
1
0
•
3
4
•
0
0
0
0
0
•
•
•
•
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.4.2 PD_POL IF
IF Synthesizer Phase Detector Polarity
IF R[17]
The PD_POL IF bit is used to control the IF synthesizer’s phase detector polarity based on the VCO tuning characteristics.
Control Bit
Register Location
Description
Function
0
IF VCO Negative
Tuning
1
PD_POL IF
IF R[17]
IF Phase Detector
Polarity
IF VCO Positive
Tuning
Characteristics
Characteristics
IF VCO Characteristics
10136609
2.4.3 IDo IF
IF Synthesizer Charge Pump Current Gain
IF R[18]
The IDo IF bit controls the IF synthesizer’s charge pump gain. Two current levels are available.
Control Bit
Register Location
Description
Function
0
1
IDo IF
IF R[18]
IF Charge Pump
Current Gain
LOW
HIGH
0.95 mA
3.80 mA
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42
2.0 Programming Description (Continued)
2.4.4 TRI-STATE IDo IF
IF Synthesizer Charge Pump Tri-state Current
IF R[19]
The TRI-STATE IDo IF bit allows the charge pump to be switched between a normal operating mode and a high impedance output
state. This happens asynchronously with the change in the TRI-STATE IDo IF bit.
Furthermore, the TRI-STATE IDo IF bit operates in conjuction with the PWDN IF bit to set a synchronous or an asynchronous
powerdown mode.
Control Bit
Register Location
Description
Function
0
1
TRI-STATE IDo IF
IF R[19]
IF Charge Pump
IF Charge Pump
Normal Operation
IF Charge Pump
Output in High
TRI-STATE Current
Impedance State
2.5 IF N REGISTER
The IF N register contains the IF N_CNTRA, IF N_CNTRB, PRE IF, and PWDN IF control words. The IF N_CNTRA and IF
N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming
information for each control word is discussed in the following sections.
Reg. Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
Field
Data Field
IF
N
PWDN PRE
IF IF
IF N_CNTRB[10:0]
IF N_CNTRA[6:0]
IF N[2:8]
0
1
2.5.1 IF N_CNTRA[6:0]
IF Synthesizer Swallow Counter (A Counter)
The IF N_CNTRA control word is used to setup the IF synthesizer’s A counter. The A counter is a 7-bit swallow counter used in
the programmable feedback divider. The IF N_CNTRA control word can be programmed to values ranging from 0 to 15. The three
most significant bits are ‘don’t care bits’ in this case.
Divide Ratio
IF N_CNTRA[6:0]
6
X
X
•
5
X
X
•
4
X
X
•
3
0
0
•
2
0
0
•
1
0
0
•
0
0
1
•
0
1
•
15
X
X
X
1
1
1
1
2.5.2 IF N_CNTRB[10:0]
IF Synthesizer Programmable Binary Counter (B Counter)
IF N[9:19]
The IF N_CNTRB control word is used to setup the IF synthesizer’s B counter. The B counter is an 11-bit programmable binary
counter used in the programmable feedback divider. The IF N_CNTRB control word can be programmed to values ranging from
3 to 2047.
Divide
Ratio
IF N_CNTRB[10:0]
10
0
9
0
0
•
8
0
0
•
7
0
0
•
6
0
0
•
5
0
0
•
4
0
0
•
3
0
0
•
2
0
1
•
1
1
0
•
0
1
0
•
3
4
•
0
•
2047
1
1
1
1
1
1
1
1
1
1
1
2.5.3 PRE IF
IF Synthesizer Prescaler Select
IF N[20]
The IF synthesizer utilizes a selectable dual modulus prescaler.
Control Bit
Register Location
Description
Function
0
1
PRE IF
IF N[20]
IF Prescaler Select
8/9 Prescaler
Selected
16/17 Prescaler
Selected
43
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2.0 Programming Description (Continued)
2.5.4 PWDN IF
IF SYNTHESIZER POWERDOWN
IF N[21]
The PWDN IF bit is used to switch the IF PLL between a powered up and powered down mode.
Furthermore, the PWDN IF bit operates in conjuction with the TRI-STATE IDo IF bit to set a synchronous or an asynchronous
powerdown mode.
Control Bit
Register Location
Description
Function
IF PLL Powerdown
0
1
PWDN IF
IF N[21]
IF Powerdown
IF PLL Active
2.6 RF R REGISTER
The RF R register contains the RF R_CNTR, PD_POL RF, IDo RF, and TRI-STATE IDo RF control words, in addition to two bits
that compose the FoLD control word. The detailed descriptions and programming information for each control word is discussed
in the following sections.
Reg. Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
Field
Data Field
RF
R
TRI-
PD_
POL
RF
STATE ID
o
RF R_CNTR[14:0]
1
0
F LD1 F LD3
o
o
ID
RF
o
RF
2.6.1 RF R_CNTR[14:0]
RF Synthesizer Programmable Reference Divider (R Counter)
RF R[2:16]
The RF reference divider (RF R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3
are prohibited.
Divide Ratio
RF R_CNTR[14:0]
14
0
13
0
12
0
11
0
10
0
9
0
0
•
8
0
0
•
7
0
0
•
6
0
0
•
5
0
0
•
4
0
0
•
3
0
0
•
2
0
1
•
1
1
0
•
0
1
0
•
3
4
•
0
0
0
0
0
•
•
•
•
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.6.2 PD_POL RF
RF Synthesizer Phase Detector Polarity
RF R[17]
The PD_POL RF bit is used to control the RF synthesizer’s phase detector polarity based on the VCO tuning characteristics.
Control Bit
Register Location
Description
Function
0
1
PD_POL RF
RF R[17]
RF Phase Detector
Polarity
RF VCO Negative
Tuning
RF VCO Positive
Tuning
Characteristics
Characteristics
RF VCO Characteristics
10136682
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44
2.0 Programming Description (Continued)
2.6.3 IDo RF
RF Synthesizer Charge Pump Current Gain
RF R[18]
The IDo RF bit controls the RF synthesizer’s charge pump gain. Two current levels are available.
Control Bit
Register Location
Description
Function
0
1
IDo RF
RF R[18]
RF Charge Pump
Current Gain
LOW
HIGH
0.95 mA
3.80 mA
2.6.4 TRI-STATE IDo RF
RF Synthesizer Charge Pump TRI-STATE Current
RF R[19]
The TRI-STATE IDo RF bit allows the charge pump to be switched between a normal operating mode and a high impedance
output state. This happens asynchronously with the change in the TRI-STATE IDo RF bit.
Furthermore, the TRI-STATE IDo RF bit operates in conjuction with the PWDN RF bit to set a synchronous or an asynchronous
powerdown mode.
Control Bit
Register Location
Description
Function
0
1
TRI-STATE IDo RF
RF R[19]
RF Charge Pump
RF Charge Pump
Normal Operation
RF Charge Pump
Output in High
TRI-STATE Current
Impedance State
2.7 RF N REGISTER
The RF N register contains the RF N_CNTRA, RF N_CNTRB, PRE RF, and PWDN RF control words. The RF N_CNTRA and RF
N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming
information for each control word is discussed in the following sections.
Reg. Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Address
Field
Data Field
RF
N
PWDN PRE
RF RF
RF N_CNTRB[10:0]
RF N_CNTRA[6:0]
RF N[2:8]
1
1
2.7.1 RF N_CNTRA[6:0]
RF Synthesizer Swallow Counter (A Counter)
The RF N_CNTRA control word is used to setup the RF synthesizer’s A counter. The A counter is a 7-bit swallow counter used
in the programmable feedback divider. The RF N_CNTRA control word can be programmed to values ranging from 0 to 127.
Divide Ratio
RF N_CNTRA[6:0]
6
0
0
•
5
0
0
•
4
0
0
•
3
0
0
•
2
0
0
•
1
0
0
•
0
0
1
•
0
1
•
127
1
1
1
1
1
1
1
2.7.2 RF N_CNTRB[10:0]
RF Synthesizer Programmable Binary Counter (B Counter)
RF N[9:19]
The RF N_CNTRB control word is used to setup the RF synthesizer’s B counter. The B counter is an 11-bit programmable binary
counter used in the programmable feedback divider. The RF N_CNTRB control word can be programmed to values ranging from
3 to 2047.
Divide
Ratio
RF N_CNTRB[10:0]
10
0
9
0
0
•
8
0
0
•
7
0
0
•
6
0
0
•
5
0
0
•
4
0
0
•
3
0
0
•
2
0
1
•
1
1
0
•
0
1
0
•
3
4
•
0
•
2047
1
1
1
1
1
1
1
1
1
1
1
45
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2.0 Programming Description (Continued)
2.7.3 PRE RF
The RF synthesizer utilizes a selectable dual modulus prescaler.
LMX2330U RF Synthesizer Prescaler Select
RF Synthesizer Prescaler Select
RF N[20]
Control Bit
Register Location
Description
Function
0
32/33 Prescaler
Selected
1
PRE RF
RF N[20]
RF Prescaler Select
64/65 Prescaler
Selected
LMX2331U and LMX2332U RF Synthesizer Prescaler Select
Control Bit
Register Location
Description
Function
0
64/65 Prescaler
Selected
1
PRE RF
RF N[20]
RF Prescaler Select
128/129 Prescaler
Selected
2.7.4 PWDN RF
RF SYNTHESIZER POWERDOWN
RF N[21]
The PWDN RF bit is used to switch the RF PLL between a powered up and powered down mode.
Furthermore, the PWDN RF bit operates in conjuction with the TRI-STATE IDo RF bit to set a synchronous or an asynchronous
powerdown mode.
Control Bit
Register Location
Description
Function
RF PLL Powerdown
0
1
PWDN RF
RF N[21]
RF Powerdown
RF PLL Active
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46
2.0 Programming Description (Continued)
2.8 FoLD[3:0]
MULTI-FUNCTION OUTPUT SELECT
[RF R[20], IF R[20], RF R [21], IF R[21]]
The FoLD control word is used to select which signal is routed to the FoLD pin.
FoLD3
FoLD2
FoLD1
FoLD0
FoLD Output State
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LOW Logic State Output
IF PLL R Divider Output, Push-Pull Output
RF PLL R Divider Output, Push-Pull Output
Open Drain Fastlock Output
IF PLL Analog Lock Detect, Push-Pull Output
IF PLL N Divider Output, Push-Pull Output
RF PLL N Divider Output, Push-Pull Output
Reset IF Counters, LOW Logic State Output
RF Analog Lock Detect, Push-Pull Output
IF PLL R Divider Output, Push-Pull Output
RF PLL R Divider Output, Push-Pull Output
Reset RF Counters, LOW Logic State Output
RF and IF Analog Lock Detect, Push-Pull Output
IF PLL N Divider Output, Push-Pull Output
RF PLL N Divider Output, Push-Pull Output
Reset All Counters, LOW Logic State Output
47
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Pin Thin Shrink Small Outline Package (TM)
NS Package Number MTC20
24-Pin Chip Scale Package (SLB)
NS Package Number SLB24A
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48
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Pin Ultra Thin Chip Scale Package (SLE)
NS Package Number SLE20A
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相关型号：
LMX2332ATMX
IC PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20, 0.173 INCH, PLASTIC, TSSOP-20, PLL or Frequency Synthesis Circuit
NSC
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