MCT8316Z_V02_技术文档

MCT8316Z

SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

MCT8316Z Sensored Trapezoidal Integrated FET BLDC Motor Driver

1 Features

3 Description

•

Three-phase BLDC motor driver with integrated

Sensored Trapezoidal control

– Hall Sensor based Trapezodial (120°)

commutation

– Supports Analog or Digital Hall inputs

– Configurable PWM modulation: Synchronous/

Asynchronous

– Cycle-by-cycle current limit to limit phase

current

– Supports up to 200-kHz PWM frequency

– Active Demagnetization to reduce power losses

4.5-V to 35-V operating voltage (40-V abs max)

High output current capability: 8-A Peak

Low MOSFET on-state resistance

– 95-mΩ R_DS(ON)(HS + LS) at T_A= 25°C

Low power sleep mode

– 1.5-µA at V_VM= 24-V, T_A= 25°C

Integrated built-in current sense

– Doesn't require external current sense resistors

Flexible device configuration options

– MCT8316ZR: 5-MHz 16-bit SPI interface for

device configuration and fault status

– MCT8316ZT: Hardware pin based configuration

Supports 1.8-V, 3.3-V, and 5-V logic inputs

Built-in 3.3-V (5%), 30-mA LDO regulator

Built-in 3.3-V/5-V, 200-mA buck regulator

Delay compensation reduces duty cycle distortion

Suite of integrated protection features

The MCT8316Z provides a single-chip code-free

sensored trapezoidal solution for customers driving

12- to 24-V brushless-DC motors. The MCT8316Z

integrates three 1/2-H bridges with 40-V absolute

maximum capability and a very low RDS(ON) of

95 mOhms (high-side and low-side combined) to

enable high power drive capability. Current is sensed

using an integrated current sensing feature which

eliminates the need for external sense resistors.

Power management features of an adjustable buck

regulator and LDO generate the necessary voltage

rails for the device and can be used to power external

circuits.

•

MCT8316Z implements sensored trapezoidal control

in a fixed-function state machine, so an external

microcontroller is not required to spin the brushless-

DC motor. The device integrates three analog hall

comparators for position sensing to achieve sensored

trapezoidal BLDC motor control. The control scheme

is highly configurable through hardware pins or

register settings ranging from motor current limiting

behavior to fault response. The speed can be

controlled through a PWM input.

•

There are a large number of protection features

integrated into the MCT8316Z, intended to protect the

device, motor, and system against fault events.

Refer Application Information for design consideration

and recommendation on device usage.

– Supply undervoltage lockout (UVLO)

– Charge pump undervoltage (CPUV)

– Overcurrent protection (OCP)

Device Information⁽¹⁾

PART NUMBER

MCT8316ZR

PACKAGE

VQFN (40)

BODY SIZE (NOM)

7.00 mm × 5.00 mm

– Motor lock protection

– Thermal warning and shutdown (OTW/OTSD)

– Fault condition indication pin (nFAULT)

– Optional fault diagnostics over SPI interface

MCT8316ZT

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

2 Applications

4.5V to 35V (40V abs max)

Buck/LDO out

3.3 or 5.0 V, up to

200mA

8-A peak output current,

typically 12- to 24-V,

•

Brushless-DC (BLDC) Motor Modules

Small home appliances

HVAC motors

Office automation machines

Factory automation and robotics

MCT8316Z

A

B

C

Buck/LDO out

SPEED

PWM input

Sensored

Trap

Control

H

DIRECTION

BRAKE

H

FGOUT

Speed feecback

nFAULT

Buck/LDO Regulator

SPI

Only on SPI

variant

Hall inputs support:

Diﬀerenꢀal Hall elements

Integrated Current Sensing

Diﬀerenꢀal analog output Hall-eﬀect sensors

Digital output Hall-eﬀect sensors

Single-ended analog output Hall-eﬀect sensors

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

MCT8316Z

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SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table ..............................................3

6 Pin Configuration and Functions...................................4

Pin Functions.................................................................... 5

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 7

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................8

7.5 Electrical Characteristics.............................................8

7.6 SPI Timing Requirements......................................... 16

7.7 SPI Secondary Mode Timings...................................17

7.8 Typical Characteristics..............................................17

8 Detailed Description......................................................18

8.1 Overview...................................................................18

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................21

8.4 Device Functional Modes..........................................59

8.5 SPI Communication.................................................. 60

8.6 Register Map.............................................................63

9 Application and Implementation..................................78

9.1 Application Information............................................. 78

9.2 Hall Sensor Configuration and Connection...............79

9.3 Typical Applications.................................................. 83

10 Power Supply Recommendations..............................88

10.1 Bulk Capacitance....................................................88

11 Layout...........................................................................89

11.1 Layout Guidelines................................................... 89

11.2 Layout Example...................................................... 90

11.3 Thermal Considerations..........................................91

12 Device and Documentation Support..........................92

12.1 Support Resources................................................. 92

12.2 Trademarks.............................................................92

12.3 Electrostatic Discharge Caution..............................92

12.4 Glossary..................................................................92

4 Revision History

Changes from Revision A (October 2021) to Revision B (November 2021)

Page

•

Updated MCT8316ZR from pre production to production status .......................................................................1

Changes from Revision * (March 2021) to Revision A (October 2021)

Page

•

Updated Device Status to Production Data........................................................................................................ 1

2

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5 Device Comparison Table

DEVICE

PACKAGES

40-pin VQFN (7x5 mm)

INTERFACE

BUCK REGULATOR

MCT8316ZR

MCT8316ZT

SPI

Yes

Hardware

Table 5-1. MCT8316ZR (SPI variant) vs. MCT8316ZT (Hardware variant) configuration comparison

Parameters

MCT8316ZR (SPI variant)

PWM_MODE (4 settings)

SLEW (4 settings)

MCT8316ZT (Hardware variant)

MODE pin (7 settings)

SLEW pin (4 settings)

DIR pin (2 settings)

PWM control mode settings

Slew rate settings

Direction settings

DIR (2 settings)

DRVOFF pin configuration

Current limit threshold

Current limit configuration

DRV_OFF (2 settings)

Enabled

ILIMIT pin: AVDD/2 to AVDD/2-0.4V

ILIM_RECIR (2 settings),

PWM_100_DUTY_SEL

Recirculation fixed to Brake mode and PWM

frequency for 100% duty fixed to 20 kHz

CSA GAIN

Lead angle settings

Buck enable

CSA_GAIN (4 settings)

ADVANCE_LVL (8 settings)

BUCK_DIS (2 settings)

BUCK_SEL(4 settings)

Fixed to 0.15 V/A

ADVANCE pin (7 settings)

Enabled

Buck threshold

VSEL_BK pin (4 settings)

Buck configuration: power sequencing,

current limit and slew rate

BUCK_PS_DIS (2 settings) and BUCK_CL(2 Power sequencing enabled, current limit: 600

settings)

mA and slew rate: 1000 V/us

FGOUT configuration

FGOUT_SEL (4 settings)

Fixed to 3x commutation frequency

Motor lock configuration: mode, detection and

retry timing

MTR_LOCK_MODE (4 settings),

MTR_LOCK_TDET (4 settings),

MTR_LOCK_RETRY (2 settings)

Enabled with latched shutdown mode and

detection time of 1000 ms

Active demagnetization

EN_AAR (2 settings) and EN_ASR (2

settings)

MODE pin (7 settings)

OCP configuration: Mode,

OCP_MODE (4 settings) , OCP_LVL (4

settings) ,OCP_DEG (4 settings) and

OCP_RETRY (2 settings)

Enabled with latched shutdown mode, level is

fixed to 16A with 0.6 us deglitch time

Overvoltage protection configuration

OVP_EN (2 settings) , OVP_SEL (2 settings)

Enabled and level is fixed to 34V (typ)

Disabled

Driver delay compensation configuration

DLYCMP_EN (2 settings), DLY_TARGET (16

settings)

SDO pin configuration

SPI fault configuration

SDO_MODE (2 settings)

NA

SPI_PARITY(2 settings), SPI_SCLK_FLT(2

settings), SPI_ADDR_FLT(2 settings)

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6 Pin Configuration and Functions

32

31

30

29

28

27

26

25

24

23

22

21

HNC

NC

AGND

FB_BK

GND_BK

SW_BK

CPL

1

2

NC

AGND

FB_BK

GND_BK

SW_BK

CPL

1

2

32

31

30

29

28

27

26

25

24

23

22

21

HNC

HPC

3

HNB

3

HNB

4

HPB

4

HPB

5

HNA

5

HNA

6

HPA

MCT8316ZR

(Thermal PAD)

6

HPA

MCT8316ZT

(Thermal Pad)

CPH

7

AGND

AVDD

NC

CPH

7

AGND

AVDD

VSEL_BK

nSLEEP

nFAULT

DRVOFF

CP

8

CP

8

VM

9

VM

9

VM

10

11

12

nSLEEP

nFAULT

DRVOFF

VM

10

11

12

VM

PGND

Figure 6-1. MCT8316ZR 40-Pin VQFN With Exposed

Thermal Pad Top View

Figure 6-2. MCT8316ZT 40-Pin VQFN With Exposed

Thermal Pad Top View

4

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Pin Functions

40-pin Package

MCT8316ZR MCT8316ZT

TYPE⁽¹⁾

DESCRIPTION

NAME

Advance angle level setting. This pin is a 7-level input pin set by an external

resistor.

ADVANCE

—

35

I

Device analog ground. Refer Layout Guidelines for connections

recommendation.

AGND

AVDD

2, 26

GND

3.3-V internal regulator output. Connect an X5R or X7R, 1-µF, 6.3-V ceramic

PWR O capacitor between the AVDD and AGND pins. This regulator can source up to

30 mA externally.

25

High → Brake the motor when High by turning all low side MOSFETs ON

Low → normal operation

BRAKE

CP

38

8

38

8

I

Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor

between the CP and VM pins.

PWR O

CPH

CPL

7

6

7

6

PWR

Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic

capacitor between the CPH and CPL pins. TI recommends a capacitor voltage

rating at least twice the normal operating voltage of the device.

Direction pin for setting the direction of the motor rotation to clockwise or

counterclockwise.

DIR

—

21

3

36

21

3

I

When this pin is pulled high the six MOSFETs in the power stage are turned

OFF making all outputs Hi-Z.

DRVOFF

FB_BK

I

Feedback for buck regulator. Connect to buck regulator output after the

inductor/resistor.

PWR I

Motor Speed indicator output. Open-drain output requires an external pull-up

resistor to 1.8V to 5.0V. It can be set to different division factor of Hall signals

(see FGOUT Signal)

FGOUT

40

O

Buck regulator ground. Refer Layout Guidelines for connections

recommendation.

GND_BK

HPA

4

GND

Phase A hall element positive input. Noise filter capacitors may be desirable,

connected between the positive and negative hall inputs.

27

29

31

28

30

27

29

31

28

30

I

Phase B hall element positive input. Noise filter capacitors may be desirable,

connected between the positive and negative hall inputs.

HPB

Phase C hall element positive input. Noise filter capacitors may be desirable,

connected between the positive and negative hall inputs.

HPC

Phase A hall element negative input. Noise filter capacitors may be desirable,

connected between the positive and negative hall inputs.

HNA

Phase B hall element negative input. Noise filter capacitors may be desirable,

connected between the positive and negative hall inputs.

HNB

Phase C hall element negative input. Noise filter capacitors may be desirable,

connected between the positive and negative hall inputs.

HNC

ILIM

MODE

NC

32

37

32

37

33

1

I

Set the threshold for phase current used in cycle by cycle current limit.

PWM input mode setting. This pin is a 7-level input pin set by an external

resistor.

—

I

1, 24

—

No connection, open

Fault indicator. Pulled logic-low with fault condition; Open-drain output requires

an external pull-up resistor to 1.8V to 5.0V. If external supply is used to pull up

nFAULT, ensure that it is pulled to >2.2V on power up or the device will enter

test mode

nFAULT

22

O

Serial chip select. A logic low on this pin enables serial interface

communication.

nSCS

36

23

—

I

Driver nSLEEP. When this pin is logic low, the device goes into a low-power

sleep mode. An 20 to 40-µs low pulse can be used to reset fault conditions

without entering sleep mode.

nSLEEP

23

OUTA

OUTB

13, 14

16, 17

13, 14

16, 17

PWR O Half bridge output A

PWR O Half bridge output B

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40-pin Package

TYPE⁽¹⁾

DESCRIPTION

NAME

MCT8316ZR

MCT8316ZT

OUTC

19, 20

PWR O Half bridge output C

Device power ground. Refer Layout Guidelines for connections

recommendation.

PGND

PWM

SCLK

SDI

12, 15, 18

GND

PWM input for motor control. Set the duty cycle and switching frequency of the

phase voltage of the motor.

39

35

34

33

39

—

I

Serial clock input. Serial data is shifted out and captured on the corresponding

rising and falling edge on this pin (SPI devices).

Serial data input. Data is captured on the falling edge of the SCLK pin (SPI

devices).

I

Serial data output. Data is shifted out on the rising edge of the SCLK pin. This

pin requires an external pullup resistor (SPI devices).

SDO

O

I

Slew rate control setting. This pin is a 4-level input pin set by an external

resistor (Hardware devices).

SLEW

—

5

34

5

SW_BK

PWR O Buck switch node. Connect this pin to an inductor or resistor.

Power supply. Connect to motor supply voltage; bypass to PGND with two

0.1-µF capacitors (for each pin) plus one bulk capacitor rated for VM. TI

PWR I

VM

9, 10, 11

—

9, 10, 11

24

recommends a capacitor voltage rating at least twice the normal operating

voltage of the device.

Buck output voltage setting. This pin is a 4-level input pin set by an external

resistor.

VSEL_BK

I

Thermal

pad

GND

Must be connected to analog ground.

(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect

6

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7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX UNIT

Power supply pin voltage (VM)

–0.3

40

4

V

V/µs

V

Power supply voltage ramp (VM)

Voltage difference between ground pins (GND_BK, PGND, AGND)

Charge pump voltage (CPH, CP)

–0.3

–1

0.3

V_M+ 6

V_M+ 0.3

5.75

V

Charge pump negative switching pin voltage (CPL)

Switching regulator pin voltage (FB_BK)

Switching node pin voltage (SW_BK)

Analog regulators pin voltage (AVDD)

Logic pin input voltage (DRVOFF, PWM, nSCS, nSLEEP, SCLK, SDI)

Logic pin output voltage (nFAULT, SDO)

Output pin voltage (OUTA, OUTB, OUTC)

Ambient temperature, T_A

V

V_M+ 0.3

4

V

5.75

V

5.75

V

V_M+ 1

125

V

–40

–65

°C

Junction temperature, T_J

150

Storage tempertaure, T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

V_VM

f_PWM

I_OUT

Power supply voltage

V_VM

4.5

24

35

200

8

V

kHz

A

Output PWM frequency

Peak output winding current

OUTA, OUTB, OUTC

(1)

DRVOFF, INHx, INLx, nSCS, nSLEEP,

SCLK, SDI

V_IN

Logic input voltage

–0.1

5.5

V

V_OD

Open drain pullup voltage

Push-pull voltage

nFAULT, SDO

SDO

–0.1

2.2

5.5

V

V_SDO

I_OD

V_VREF

T_A

Open drain output current

Voltage reference pin voltage

Operating ambient temperature

Operating Junction temperature

nFAULT, SDO

VREF

5

mA

V

2.8

–40

AVDD

125

150

°C

T_J

(1) Power dissipation and thermal limits must be observed

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7.4 Thermal Information

MCT8316ZT,

MCT8316ZR

THERMAL METRIC⁽¹⁾

UNIT

VQFN (RGF)

40 Pins

25.7

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

15.2

7.3

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JB

7.2

R_θJC(bot)

2.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLIES

V_VM> 6 V, nSLEEP = 0, T_A= 25 °C

nSLEEP = 0

1.5

2.5

5

µA

I_VMQ

VM sleep mode current

nSLEEP = 1, PWM = 0, SPI =

'OFF', BUCK_DIS = 1;

4

10 mA

VM standby mode current

(Buck regulator disabled)

I_VMS

V_VM> 6 V, nSLEEP = 1, PWM = 0, SPI =

'OFF', T_A= 25 °C, BUCK_DIS = 1;

5

6

mA

V_VM> 6 V, nSLEEP = 1, PWM = 0, SPI =

'OFF', I_BK= 0, T_A= 25 °C, BUCK_DIS =

0;

5

VM standby mode current

(Buck regulator enabled)

I_VMS

nSLEEP = 1, PWM = 0, SPI = 'OFF', I_BK

= 0, BUCK_DIS = 0;

6

10

18

11

17

10 mA

13 mA

21 mA

15 mA

24 mA

V_VM> 6 V, nSLEEP = 1, f_PWM= 25 kHz,

T_A= 25 °C, BUCK_DIS = 1

V_VM> 6 V, nSLEEP = 1, f_PWM= 200 kHz,

T_A= 25 °C, BUCK_DIS = 1

VM operating mode current

(Buck regulator disabled)

I_VM

nSLEEP =1, f_PWM= 25 kHz, BUCK_DIS

= 1

nSLEEP =1, f_PWM= 200 kHz,

BUCK_DIS = 1

V_VM> 6 V, nSLEEP = 1, f_PWM

=

25 kHz, T_A= 25 °C, BUCK_DIS =

0; BUCK_PS_DIS = 0

11

19

13 mA

22 mA

V_VM> 6 V, nSLEEP = 1, f_PWM

=

200 kHz, T_A= 25 °C, BUCK_DIS =

0; BUCK_PS_DIS = 0

VM operating mode current

(Buck regulator enabled)

I_VM

nSLEEP =1, f_PWM= 25 kHz, BUCK_DIS

= 0; BUCK_PS_DIS = 0

12

18

16 mA

27 mA

nSLEEP =1, f_PWM= 200 kHz,

BUCK_DIS = 0; BUCK_PS_DIS = 0

0 mA ≤ I_AVDD≤ 30 mA; BUCK_PS_DIS =

0

V_AVDD

Analog regulator voltage

3.1

3.6

3.3

3.465

V

I_AVDD

V_VCP

f_CP

External analog regulator load

Charge pump regulator voltage

Charge pump switching frequency

30 mA

VCP with respect to VM

4.7

5.2

V

400

kHz

8

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T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PWM low time required for motor lock

detection

t_{PWM_LOW}

t_WAKE

200

ms

V_VM> V_UVLO, nSLEEP = 1 to outputs

ready and nFAULT released

Wakeup time

1

ms

t_SLEEP

t_RST

Sleep Pulse time

Reset Pulse time

nSLEEP = 0 period to enter sleep mode

nSLEEP = 0 period to reset faults

120

20

µs

40

BUCK REGULATOR

V_VM> 6 V, 0 mA ≤ I_BK≤ 200 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

5.0

4.0

5.7

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 200 mA,

BUCK_SEL = 01b

Buck regulator average voltage

V_VM> 6 V, 0 mA ≤ I_BK≤ 200 mA,

BUCK_SEL = 10b

V_BK

(L_BK= 47 µH, C_BK= 22 µF)

(SPI Device)

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 200 mA,

BUCK_SEL = 11b

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤ I_BK≤ 200 mA

V_VM

–

I_BK*(R_LBK

+

V

2)⁽¹⁾

V_VM> 6 V, 0 mA ≤ I_BK≤ 50 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 50 mA,

BUCK_SEL = 01b

5.0

4.0

5.7

Buck regulator average voltage

(L_BK= 22 µH, C_BK= 22 µF)

(SPI Device)

V_VM> 6 V, 0 mA ≤ I_BK≤ 50 mA,

BUCK_SEL = 10b

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 50 mA,

BUCK_SEL = 11b

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤ I_BK≤ 50 mA

V_VM

–

+

I_BK*(R_LBK

V

2) ⁽¹⁾

V_VM> 6 V, 0 mA ≤ I_BK≤ 40 mA,

BUCK_SEL = 00b

3.1

4.6

3.7

5.2

3.3

3.5

5.4

4.3

6.2

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 40 mA,

BUCK_SEL = 01b

5.0

4.0

5.7

Buck regulator average voltage

(R_BK= 22 Ω, C_BK= 22 µF)

(SPI Device)

V_VM> 6 V, 0 mA ≤ I_BK≤ 40 mA,

BUCK_SEL = 10b

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 40 mA,

BUCK_SEL = 11b

V_VM< 6.0 V (BUCK_SEL = 00b, 01b,

10b) or V_VM< 6.0 V (BUCK_SEL = 11b),

0 mA ≤ I_BK≤ 40 mA

V_VM–

I_BK*(R_BK+2

V

(1)

)

V_VM> 6 V, 0 mA ≤ I_BK≤ 200 mA,

VSEL_BK pin tied to AGND

3.1

4.6

3.3

5.0

3.5

5.4

V_VM> 6 V, 0 mA ≤ I_BK≤ 200

mA, VSEL_BK pin to Hi-Z

V_VM> 6 V, 0 mA ≤ I_BK≤ 200

mA, VSEL_BK pin to 47 kΩ +/- 5% tied

to AVDD

Buck regulator average voltage

(L_BK= 47 µH, C_BK= 22 µF)

(HW Device)

3.7

5.2

4.0

5.7

4.3

6.2

V_BK

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 200 mA,

VSEL_BK pin tied to AVDD

V_VM–

V_VM< 6.0 V, 0 mA ≤ I_BK≤ 200 mA

I_BK*(R_LBK

+

V

2)⁽¹⁾

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MAX UNIT

SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

V_VM> 6 V, 0 mA ≤ I_BK≤ 50 mA,

VSEL_BK pin tied to AGND

3.1

3.3

3.5

5.4

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 50

mA, VSEL_BK pin to Hi-Z

4.6

3.7

5.2

5.0

4.0

5.7

V_VM> 6 V, 0 mA ≤ I_BK≤ 50

mA, VSEL_BK pin to 47 kΩ +/- 5% tied

to AVDD

Buck regulator average voltage

(L_BK= 22 µH, C_BK= 22 µF)

(HW Device)

4.3

6.2

V

V_BK

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 50 mA,

VSEL_BK pin tied to AVDD

V_VM–

V_VM< 6.0 V, 0 mA ≤ I_BK≤ 50 mA

I_BK*(R_LBK

+

2)⁽¹⁾

V_VM> 6 V, 0 mA ≤ I_BK≤ 40 mA,

VSEL_BK pin tied to AGND

3.1

4.6

3.3

3.5

5.4

V

V_VM> 6 V, 0 mA ≤ I_BK≤ 40

mA, VSEL_BK pin to Hi-Z

5.0

4.0

5.7

V_VM> 6 V, 0 mA ≤ I_BK≤ 40

mA, VSEL_BK pin to 47 kΩ +/- 5% tied

to AVDD

Buck regulator average voltage

(R_BK= 22 Ω, C_BK= 22 µF)

(HW Device)

3.7

5.2

4.3

6.2

V

V_BK

V_VM> 6.7 V, 0 mA ≤ I_BK≤ 40 mA,

VSEL_BK pin tied to AVDD

V_VM–

V_VM< 6.0 V, 0 mA ≤ I_BK≤ 40 mA

I_BK*(R_BK+2

(1)

)

V_VM> 6 V, 0 mA ≤ I_BK≤ 200 mA, Buck

regulator with inductor, L_BK= 47 uH, C_BK

= 22 µF

–100

100 mV

V_VM> 6 V, 0 mA ≤ I_BK≤ 50 mA, Buck

regulator with inductor, L_BK= 22 uH, C_BK

= 22 µF

V_{BK_RIP}

Buck regulator ripple voltage

V_VM> 6 V, 0 mA ≤ I_BK≤ 50 mA, Buck

regulator with resistor; R_BK= 22 Ω, C_BK

= 22 µF

100 mV

200 mA

L_BK= 47 uH, C_BK= 22 µF,

BUCK_PS_DIS = 1b

L_BK= 47 uH, C_BK= 22 µF,

BUCK_PS_DIS = 0b

200 –

I_AVDD

mA

L_BK= 22 uH, C_BK

22 µF, BUCK_PS_DIS = 1b

=

50 mA

I_BK

External buck regulator load

L_BK= 22 uH, C_BK= 22 µF,

BUCK_PS_DIS = 0b

50 –

I_AVDD

mA

R_BK= 22 Ω, C_BK

22 µF, BUCK_PS_DIS = 1b

=

40 mA

R_BK= 22 Ω, C_BK= 22 µF,

BUCK_PS_DIS = 0b

40 –

I_AVDD

mA

Regulation Mode

Linear Mode

20

535 kHz

f_{SW_BK}

Buck regulator switching frequency

10

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SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

V_BKrising, BUCK_SEL = 00b

V_BKfalling, BUCK_SEL = 00b

V_BKrising, BUCK_SEL = 01b

V_BKfalling, BUCK_SEL = 01b

V_BKrising, BUCK_SEL = 10b

V_BKfalling, BUCK_SEL = 10b

V_BKrising, BUCK_SEL = 11b

V_BKfalling, BUCK_SEL = 11b

V_BKrising, VSEL_BK pin tied to AGND

V_BKfalling, VSEL_BK pin tied to AGND

MIN

2.7

2.5

4.2

4.0

2.7

2.5

4.2

4

TYP

2.8

2.6

4.4

4.2

2.8

2.6

4.4

4.2

2.8

2.6

MAX UNIT

2.9

2.7

V

4.55

4.35

2.9

Buck regulator undervoltage lockout

(SPI Device)

V_{BK_UV}

2.7

4.55

4.35

2.9

2.7

2.5

2.7

V_BKrising, VSEL_BK pin to 47 kΩ +/- 5%

tied to AVDD

4.3

4.1

4.4

4.2

4.5

4.3

V

V_BKfalling, VSEL_BK pin to 47 kΩ +/-

5% tied to AVDD

Buck regulator undervoltage lockout

(HW Device)

V_{BK_UV}

V_BKrising, VSEL_BK pin to Hi-Z

2.7

2.5

4.2

4.0

2.8

2.6

4.4

4.2

2.9

2.7

V

V_BKfalling, VSEL_BK pin to Hi-Z

V_BKrising, VSEL_BK pin tied to AVDD

V_BKfalling, VSEL_BK pin tied to AVDD

4.55

4.35

Buck regulator undervoltage lockout

hysteresis

V_{BK_UV_HYS}

Rising to falling threshold

90

200

320 mV

BUCK_CL = 0b

BUCK_CL = 1b

360

80

600

150

900 mA

250 mA

Buck regulator Current limit threshold

(SPI Device)

I_{BK_CL}

Buck regulator Current limit threshold

(HW Device)

I_{BK_CL}

360

600

900 mA

Buck regulator Overcurrent protection

trip point

I_{BK_OCP}

2

3

1

4

A

t_{BK_RETRY}

Overcurrent protection retry time

0.7

1.3 ms

LOGIC-LEVEL INPUTS (BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK, SDI)

V_IL

Input logic low voltage

0

1.5

1.6

180

95

0.6

5.5

V

Other Pins

V_IH

Input logic high voltage

nSLEEP

Other PIns

300

250

420 mV

V_HYS

I_IL

Input logic hysteresis

Input logic low current

Input logic high current

nSLEEP

V_PIN(Pin Voltage) = 0 V

nSLEEP, V_PIN(Pin Voltage) = 5 V

Other pins, V_PIN(Pin Voltage) = 5 V

nSLEEP

–1

1

30

µA

kΩ

pF

10

I_IH

30

75

150

70

200

100

30

300

130

R_PD

C_ID

Input pulldown resistance

Input capacitance

Other pins

LOGIC-LEVEL INPUTS (nSCS)

V_IL

Input logic low voltage

Input logic high voltage

Input logic hysteresis

Input logic low current

Input logic high current

Input pullup resistance

Input capacitance

0

1.5

0.6

5.5

V

V_IH

V_HYS

I_IL

180

300

420 mV

V_PIN(Pin Voltage) = 0 V

V_PIN(Pin Voltage) = 5 V

75

25

µA

kΩ

pF

I_IH

–1

80

R_PU

C_ID

100

30

130

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MAX UNIT

SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

FOUR-LEVEL INPUTS (SLEW, VSEL_BK)

0.2*AVD

V_L1

V_L2

V_L3

V_L4

Input mode 1 voltage

Input mode 2 voltage

Input mode 3 voltage

Input mode 4 voltage

Tied to AGND

0

V

D

0.27*AV

DD

0.545*AV

DD

Hi-Z

0.5*AVDD

0.606*AV 0.757*AVD 0.909*AV

47 kΩ +/- 5% tied to AVDD

Tied to AVDD

DD

D

DD

0.945*AV

DD

AVDD

R_PU

R_PD

Input pullup resistance

To AVDD

To AGND

70

100

130

kΩ

Input pulldown resistance

FOUR-LEVEL INPUTS (OCP/SR)

0.09*AV

DD

V_L1

V_L2

V_L3

V_L4

V_L5

V_L6

V_L7

Input mode 1 voltage

Input mode 2 voltage

Input mode 3 voltage

Input mode 4 voltage

Input mode 5 voltage

Input mode 6 voltage

Input mode 7 voltage

Tied to AGND

0

V

0.12*AV

DD

0.2*AVD

D

22 kΩ ± 5% to AGND

100 kΩ ± 5% to AGND

Hi-Z

0.15*AVDD

0.33*AVDD

0.5*AVDD

0.66*AVDD

0.85*AVDD

0.27*AV

DD

0.4*AVD

D

0.45*AV

DD

0.55*AV

DD

0.6*AVD

D

0.73*AV

DD

100 kΩ ± 5% to AVDD

22 kΩ ± 5% to AVDD

Tied to AVDD

0.77*AV

DD

0.9*AVD

D

0.94*AV

DD

AVDD

R_PU

R_PD

Input pullup resistance

To AVDD

To AGND

80

100

120

kΩ

Input pulldown resistance

OPEN-DRAIN OUTPUTS (FGOUT, nFAULT)

V_OL

I_OH

Output logic low voltage

Output logic high current

Output capacitance

I_OD= 5 mA

V_OD= 5 V

0.4

1

V

–1

µA

pF

C_OD

30

PUSH-PULL OUTPUTS (SDO)

V_OL

V_OH

I_OL

Output logic low voltage

I_OP= 5 mA

V_OP= 0 V

V_OP= 5 V

0

2.2

–1

0.4

5.5

1

V

Output logic high voltage

V

Output logic low leakage current

Output logic high leakage current

Output capacitance

µA

pF

I_OH

–1

1

C_OD

30

DRIVER OUTPUTS

V_VM> 6 V, I_OUT= 1 A, T_A= 25°C

V_VM< 6 V, I_OUT= 1 A, T_A= 25°C

V_VM> 6 V, I_OUT= 1 A, T_J= 150 °C

V_VM< 6 V, I_OUT= 1 A, T_J= 150 °C

95

105

140

145

120 mΩ

130 mΩ

185 mΩ

190 mΩ

Total MOSFET on resistance (High-side

+ Low-side)

R_DS(ON)

12

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SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_VM= 24 V, SLEW = 00b or SLEW pin

tied to AGND

14

25

45 V/us

V_VM= 24 V, SLEW = 01b or SLEW pin to

Hi-Z

30

80

50

125

200

25

80 V/us

185 V/us

280 V/us

45 V/us

80 V/us

185 V/us

280 V/us

Phase pin slew rate switching low to high

(Rising from 20 % to 80 %)

SR

V_VM= 24 V, SLEW = 10b or SLEW pin to

47 kΩ +/- 5% to AVDD

V_VM= 24 V, SLEW = 11b or SLEW pin

tied to AVDD

130

14

V_VM= 24 V, SLEW = 00b or SLEW pin

tied to AGND

V_VM= 24 V, SLEW = 01b or SLEW pin to

Hi-Z

30

50

Phase pin slew rate switching high to low

(Falling from 80 % to 20 %

SR

V_VM= 24 V, SLEW = 10b or SLEW pin to

47 kΩ +/- 5% to AVDD

80

125

200

V_VM= 24 V, SLEW = 11b or SLEW pin

tied to AVDD

110

Leakage current on OUTx

V_OUTx= V_VM, nSLEEP = 1

V_OUTx= 0 V, nSLEEP = 1

5

1

mA

µA

I_LEAK

V_VM= 24 V, SR = 25 V/µs, HS driver ON

to LS driver OFF

1800

1100

650

3400

1550

1000

750

ns

V_VM= 24 V, SR = 50 V/µs, HS driver ON

to LS driver OFF

Output dead time (high to low / low to

high)

t_DEAD

V_VM= 24 V, SR = 125 V/µs, HS driver

ON to LS driver OFF

V_VM= 24 V, SR = 200 V/µs, HS driver

ON to LS driver OFF

500

V_VM= 24 V, PWM = 1 to OUTx

transisition, SR = 25 V/µs

2000

1200

800

4550

2150

1350

1050

V_VM= 24 V, PWM = 1 to OUTx

transisition, SR = 50V/µs

Propagation delay (high-side / low-side

ON/OFF)

t_PD

V_VM= 24 V, PWM = 1 to OUTx

transisition, SR = 125 V/µs

V_VM= 24 V, PWM = 1 to OUTx

transisition, SR = 200 V/µs

650

ns

t_{MIN_PULSE}

Minimum output pulse width

SR = 200 V/µs

600

CURRENT SENSE AMPLIFIER

CSA_GAIN = 00

0.15

0.3

0.6

1.2

0.15

0.3

0.6

1.2

V/A

%

CSA_GAIN = 01

G_CSA

Current sense gain (SPI Device)

CSA_GAIN = 10

CSA_GAIN = 11

GAIN pin tied to AGND

GAIN pin to Hi-Z

G_CSA

Current sense gain (HW Device)

Current sense gain error

GAIN pin to 47 kΩ ± 5% to AVDD

GAIN pin tied to AVDD

T_A= 25°C, I_PHASE< 4A

T_A= 25°C, I_PHASE> 4A

I_PHASE< 4 A

–2

–3

–5

–3

–5

2

3

5

3

5

%

G_{CSA_ERR}

%

I_PHASE> 4 A

%

T_A= 25°C

%

Current sense gain error matching

between phases A, B and C

I_MATCH

%

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SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

FS_POS

FS_NEG

Full scale positive current measurement

Full scale negative current measurement

8

A

–8

A

V

V_VREF

–

V_LINEAR

SOX output voltage linear range

0.25

Phase current = 0 A, G_CSA= 0.15 V/A

Phase current = 0 A, G_CSA= 0.3 V/A

Phase current = 0 A, G_CSA= 0.6 V/A

Phase current = 0 A, G_CSA= 1.2 V/A

Step on SOX = 1.2 V, G_CSA= 0.15 V/A

Step on SOX = 1.2 V, G_CSA= 0.3 V/A

Step on SOX = 1.2 V, G_CSA= 0.6 V/A

Step on SOX = 1.2 V, G_CSA= 1.2 V/A

Phase current = 0 A

–50

50 mA

I_OFFSET

Current sense offset low side current in

1

μs

t_SET

Settling time to ±1%, 30 pF

V_DRIFT

I_VREF

Drift offset

–160

160 µA/℃

VREF input current

VREF = 3.0 V

50

80

56

22

µA

dB

AVDD to SOx, DC

55

39

5

PSRR

Power Supply Rejection Ratio

AVDD to SOx, 10 kHz

AVDD to SOx, 500 kHz

HALL COMPARATORS

AVDD –

1.2

V_ICM

Input Common Mode Voltage (Hall)

0.5

V

HALL_HYS = 0

HALL_HYS = 1

1.5

35

5

50

5

8

mV

Voltage hysteresis (SPI Device)

V_HYS

75 mV

Voltage hysteresis (HW Device)

1.5

8

mV

Between Hall A, Hall B and Hall C

comparator

ΔV_HYS

Hall comparator hysteresis difference

–8

V_H(MIN)

I_I

t_HDG

t_HEDG

Minimum Hall Differential Voltage

Input leakage current

40

–1

mV

μA

μs

HPX = HNX = 0 V

During Power up

1

Hall deglitch time

0.7

1.15

1.4

1.7

Hall Enable deglitch time

μs

PULSE-BY-PULSE CURRENT LIMIT

Voltage on VLIM pin for cycle by cycle

current limit

AVDD/2–

0.4

V_LIM

AVDD/2

V

A

Current limit corresponding to VLIM pin

voltage range

I_LIMIT

0

8

I_{LIM_AC}

t_BLANK

Current limit accuracy

–10

10

%

Cycle by cycle current limit blank time

5

µs

ADVANCE ANGLE

ADVANCE_LVL = 000 b

ADVANCE_LVL = 001 b

ADVANCE_LVL = 010 b

ADVANCE_LVL = 011 b

ADVANCE_LVL = 100 b

ADVANCE_LVL = 101 b

ADVANCE_LVL = 110 b

ADVANCE_LVL = 111 b

0

4

°

7

11

15

20

25

30

Advance Angle Setting

(SPI Device)

θ_ADV

14

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SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Advance pin tied to AGND

0

°

Advance pin tied to 22 kΩ ± 5% to

AGND

4

°

Advance pin tied to 100 kΩ ± 5% to

AGND

11

15

20

°

Advance Angle Setting

(HW Device)

θ_ADV

Advance pin tied to Hi-Z

Advance pin tied to 100 kΩ ± 5% to

AVDD

Advance pin tied to 22 kΩ ± 5% to AVDD

Advance pin tied to Tied to AVDD

25

30

°

PROTECTION CIRCUITS

V_UVLOSupply undervoltage lockout (UVLO)

VM rising

VM falling

4.3

4.1

140

3

4.4

4.2

200

5

4.5

4.3

V

V_{UVLO_HYS}Supply undervoltage lockout hysteresis Rising to falling threshold

350 mV

t_UVLO

Supply undervoltage deglitch time

7

µs

V

Supply rising, OVP_EN = 1, OVP_SEL =

0

32.5

31.8

20

34

33

22

21

35

Supply falling, OVP_EN = 1, OVP_SEL

= 0

34.3

23

V

Supply overvoltage protection (OVP)

(SPI Device)

V_OVP

Supply rising, OVP_EN = 1, OVP_SEL =

1

Supply falling, OVP_EN = 1, OVP_SEL

= 1

19

22

Rising to falling threshold, OVP_SEL = 1

Rising to falling threshold, OVP_SEL = 0

0.9

0.7

2.5

2.3

2.2

75

1

0.8

5

1.1

0.9

7

V

Supply overvoltage protection (OVP)

(SPI Device)

V_{OVP_HYS}

t_OVP

Supply overvoltage deglitch time

µs

V

Supply rising

2.5

2.4

100

2.85

2.65

2.7

2.6

Charge pump undervoltage lockout

(above VM)

V_CPUV

Supply falling

V

V_{CPUV_HYS}Charge pump UVLO hysteresis

Rising to falling threshold

Supply rising

140 mV

2.7

2.5

3

V

V_{AVDD_UV}

Analog regulator undervoltage lockout

Supply falling

2.8

V_{AVDD_}

Analog regulator undervoltage lockout

hysteresis

Rising to falling threshold

180

200

240 mV

UV_HYS

OCP_LVL = 0b

10

15

16

24

20

28

A

Overcurrent protection trip point (SPI

Device)

OCP_LVL = 1b

I_OCP

OCP pin tied to AGND

OCP pin tied to AVDD

OCP_DEG = 00b

OCP_DEG = 01b

OCP_DEG = 10b

OCP_DEG = 11b

10

16

21.5

31

A

Overcurrent protection trip point (HW

Device)

15

24

A

0.06

0.3

0.7

1.1

0.3

0.6

1.25

1.6

0.6

1.1

1.8

2.5

µs

Overcurrent protection deglitch time

(SPI Device)

t_OCP

Overcurrent protection deglitch time

(HW Device)

0.06

0.3

0.6

6

µs

OCP_RETRY = 0

OCP_RETRY = 1

4

5

ms

Overcurrent protection retry time

(SPI Device)

t_RETRY

450

500

560 ms

ms

Overcurrent protection retry time

(HW Device)

t_RETRY

4

5

6

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SLVSF18B – MARCH 2021 – REVISED NOVEMBER 2021

T_J= –40°C to +150°C, V_VM= 4.5 to 35 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 24 V

PARAMETER

TEST CONDITIONS

MOTOR_LOCK_TDET = 00b

MOTOR_LOCK_TDET = 01b

MOTOR_LOCK_TDET = 10b

MOTOR_LOCK_TDET = 11b

MIN

TYP

MAX UNIT

330 ms

550 ms

1100 ms

5500 ms

270

300

450

500

Motor lock detection time

(SPI Device)

t_{MTR_ LOCK}

900

1000

5000

4500

Motor lock detection time

(HW Device)

t_{MTR_ LOCK}

900

1000

1100 ms

MOTOR_LOCK_RETRY = 0b

MOTOR_LOCK_RETRY = 1b

450

500

550 ms

t_{MTR_LOCK_R}Motor lock retry time

(SPI Device)

ETRY

4500

5000

5500 ms

t_{MTR_LOCK_R}Motor lock retry time

450

500

550 ms

(HW Device)

ETRY

T_OTW

Thermal warning temperature (FET)

Die temperature (T_J)

160

25

170

30

180

35

°C

T_{OTW_HYS}

T_TSD

T_{TSD_HYS}

T_TSD

Thermal warning hysteresis (FET)

Thermal shutdown temperature

Thermal shutdown hysteresis

175

25

185

30

195

35

Thermal shutdown temperature (FET)

Thermal shutdown hysteresis (FET)

170

25

180

30

190

35

T_{TSD_HYS}

(1) R_LBKis resistance of inductor L_BK

7.6 SPI Timing Requirements

MIN

NOM

MAX UNIT

t_READY

SPI ready after power up

nSCS minimum high time

nSCS input setup time

nSCS input hold time

1

ms

ns

t_{HI_nSCS}

t_{SU_nSCS}

t_{HD_nSCS}

t_SCLK

300

25

SCLK minimum period

SCLK minimum high time

SCLK minimum low time

SDI input data setup time

SDI input data hold time

SDO output data delay time

SDO enable delay time

SDO disable delay time

100

50

t_SCLKH

t_SCLKL

50

t_{SU_SDI}

t_{HD_SDI}

t_{DLY_SDO}

t_{EN_SDO}

t_{DIS_SDO}

25

50

16

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7.7 SPI Secondary Mode Timings

t_{HD_nSCS}

t_{HI_nSCS}

t_{SU_nSCS}

t_SCLK

t_SCLKH

t_SCLKL

X

MSB

LSB

X

t_{DIS_SDO}

t_{DLY_SDO}

t_{SU_SDI}

t_{HD_SDI}

Z

MSB

LSB

Z

t_{EN_SDO}

Figure 7-1. SPI Secondary Mode Timing Diagram

7.8 Typical Characteristics

17

16

15

160

150

140

F_PWM= 200 kHz

14

13

12

11

10

9

130

120

110

100

90

T_J= -40 C

T_J= 25 C

T_J= 150 C

80

F_PWM= 25 kHz

70

8

60

7

-40 -20

0

20

40

60

80 100 120 140

6

9

12

15

18

21

24

27

30

33

36

Junction Temperature (V)

Supply Voltage (V)

Figure 7-3. R_DS(ON)(high and low side combined)

for MOSFETs over temperature

Figure 7-2. Supply current over supply voltage

100

5.75

5.5

T_J= -40 C

97.5

T_J= 25 C

T_J= -150 C

5.25

5

95

92.5

90

4.75

BUCK_SEL = 00b

BUCK_SEL = 01b

BUCK_SEL = 10b

BUCK_SEL = 11b

4.5

87.5

85

4.25

4

82.5

80

3.75

3.5

3.25

3

77.5

75

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Buck Output Load Current (A)

4

8

12

16

20

24

28

32

36

Supply Voltage (V)

Figure 7-5. Buck regulator output voltage over load

current

Figure 7-4. Buck regulator efficiency over supply

voltage

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8 Detailed Description

8.1 Overview

The MCT8316Z device is an integrated 100-mΩ (combined high-side and low-side MOSFET's on-state

resistance) driver for 3-phase motor-drive applications. The device reduces system component count, cost, and

complexity by integrating three half-bridge MOSFETs, gate drivers, charge pump, linear regulator for the external

load and buck regulator. A standard serial peripheral interface (SPI) provides a simple method for configuring

the various device settings and reading fault diagnostic information through an external controller. Alternatively,

a hardware interface (H/W) option allows for configuring the most commonly used settings through fixed external

resistors.

The architecture uses an internal state machine to protect against short-circuit events, and protect against dv/dt

parasitic turnon of the internal power MOSFET.

The MCT8316Z device integrates three-phase sensored trapezoidal commutation using analog or digital hall

sensors for position detection.

In addition to the high level of device integration, the MCT8316Z device provides a wide range of

integrated protection features. These features include power-supply undervoltage lockout (UVLO), charge-pump

undervoltage lockout (CPUV), overcurrent protection (OCP), AVDD undervoltage lockout (AVDD_UV), buck

regulator ULVO for MCT8316ZR/T and overtemperature shutdown (OTW and OTSD). Fault events are indicated

by the nFAULT pin with detailed information available in the SPI registers on the SPI device version.

The MCT8316ZT and MCT8316ZR device are available in 0.5-mm pin pitch, VQFN surface-mount packages.

The VQFN package size is 7 mm × 5 mm.

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8.2 Functional Block Diagram

V_VM

+

C_VM1

C_CP

VM

C_VM2

C_FLY

CPL

Replace Inductor (L_BK

)

CP

CPH

with Resistor (R_BK) for

larger external load

or to reduce power

dissipa on

To AVDD and

Buck Regulator

Regulators

Ext.

Load

AVDD

AGND

V_VM

C_AVDD1

Charge Pump

AVDD Linear Regulator

L_BK

Ext.

SW_BK

Load

C_BK

R_BK

I/O Control

GND_BK

V_VM

Buck Regulator

FB_BK

nSLEEP

PWM

Protection

Differential Comparators

HPC

HNC

HPB

Overcurrent

Protection

+

-

(Optional)

Input

Control

Thermal Warning

Thermal Shutdown

To

Digital

Control

+

-

HNB

HPA

BRAKE

AVDD

+

-

HNA

Predriver Stage

VCP

Power Stage

VM

Output

R_nFAULT

nFAULT

AVDD

HS Pre-

driver

R_FGOUT

OUTA

VLS

FGOUT

LS Pre-

driver

Current

Sense for

Phase - A

PGND

Digital Control

Interface

ISEN_A

Predriver Stage

VCP

Power Stage

VM

SCLK

SDI

SPI

AVDD or

Buck Output

HS Pre-

driver

AVDD

Hall A

OUTB

SDO**

nSCS

ILIM

Hall B

Hall C

VLS

AVDD

LS Pre-

driver

Current

Sense for

Phase - B

PGND

ISEN_B

Predriver Stage

VCP

Power Stage

VM

+

-

ISEN_A

A_V

SOA

HS Pre-

driver

ISEN_B

ISEN_C

Output

Offset

Bias

SOB

SOC

OUTC

A_V

VLS

LS Pre-

driver

Current

Sense for

Phase - C

AVDD

Current Sense and Current Limit

PGND

ISEN_C

** SDO can be conﬁgured to open drain or push

pull conﬁguraꢀon

PGND

TPAD

Figure 8-1. MCT8316ZR Block Diagram

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V_VM

+

C_VM1

C_CP

VM

C_VM2

C_FLY

CPL

Replace Inductor (L_BK

)

CP

CPH

with Resistor (R_BK) for

larger external load

or to reduce power

dissipaꢀon

To AVDD and

Buck Regulator

Regulators

Ext.

Load

AVDD

AGND

V_VM

C_AVDD1

Charge Pump

AVDD Linear Regulator

L_BK

Ext.

SW_BK

Load

C_BK

R_BK

I/O Control

GND_BK

V_VM

Buck Regulator

FB_BK

nSLEEP

Protection

Differential Comparators

PWM

DIR

HPC

HNC

HPB

Overcurrent

Protection

+

-

(Optional)

Thermal Warning

Thermal Shutdown

To

Digital

Control

+

-

HNB

HPA

BRAKE

+

-

HNA

Input

Control

Predriver Stage

VCP

Power Stage

VM

ADVANCE

HS Pre-

driver

MODE

SLEW

OUTA

VLS

LS Pre-

driver

Current

Sense for

Phase - A

VSEL_BK

PGND

Digital Control

AVDD

ISEN_A

Predriver Stage

VCP

Power Stage

VM

Output

R_nFAULT

AVDD or

Buck Output

HS Pre-

driver

nFAULT

AVDD

Hall A

OUTB

R_FGOUT

Hall B

Hall C

VLS

FGOUT

LS Pre-

driver

Current

Sense for

Phase - B

PGND

ILIM

ISEN_B

Predriver Stage

VCP

Power Stage

VM

+

-

ISEN_A

A_V

SOA

HS Pre-

driver

ISEN_B

ISEN_C

Output

Offset

Bias

SOB

SOC

OUTC

A_V

VLS

LS Pre-

driver

Current

Sense for

Phase - C

AVDD

PGND

Current Sense and Current Limit

ISEN_C

PGND

TPAD

Figure 8-2. MCT8316ZT Block Diagram

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8.3 Feature Description

Table 8-1 lists the recommended values of the external components for the driver.

Note

TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into

internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on

power up or the device will enter internal test mode.

Table 8-1. MCT8316Z External Components

COMPONENTS

PIN 1

PIN 2

RECOMMENDED

X5R or X7R, 0.1-µF, TI recommends a capacitor

voltage rating at least twice the normal operating

voltage of the device

C_VM1

VM

PGND

≥ 10-µF, TI recommends a capacitor voltage rating at

least twice the normal operating voltage of the device

C_VM2

C_CP

VM

CP

PGND

VM

X5R or X7R, 16-V, 1-µF capacitor

X5R or X7R, 47-nF, TI recommends a capacitor

voltage rating at least twice the normal operating

voltage of the pin

C_FLY

C_AVDD

C_BK

CPH

AVDD

CPL

X5R or X7R, 1-µF, ≥ 6.3-V. In order for AVDD to

accurately regulate output voltage, capacitor should

have effective capacitance between 0.7-µF to 1.3-µF

at 3.3-V across operating temperature.

AGND

X5R or X7R, 22-µF, buck-output rated capacitor. TI

recommends a capacitor voltage rating at least twice

the normal operating voltage of the pin

SW_BK

GND_BK

L_BK

SW_BK

VCC

FB_BK

Output inductor

5.1-kΩ, Pullup resistor

R_nFAULT

R_MODE

R_SLEW

nFAULT

MODE

AGND or AVDD

AGND

MCT8316Z hardware interface

X5R or X7R, 0.1-µF, AVDD-rated capacitor (Optional)

SLEW

R_ADVANCE

R_{VSEL_BK}

C_ILIM

ADVANCE

VSEL_BK

ILIM

8.3.1 Output Stage

The MCT8316Z device consists of an integrated 100-mΩ (combined high-side and low-side FET's on-state

resistance) NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the

proper gate-bias voltage to the high-side NMOS FET's across a wide operating-voltage range in addition to

providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side

MOSFETs. The device has three VM motor power-supply pins which are to be connected together to the

motor-supply voltage.

8.3.2 PWM Control Mode (1x PWM Mode)

The MCT8316Z family of devices provides seven different control modes to support various commutation and

control methods. The MCT8316Z device provides a 1x PWM control mode for driving the BLDC motor in

trapezoidal current-control mode. The MCT8316Z device uses 6-step block commutation tables that are stored

internally. This feature lets a three-phase BLDC motor be controlled using a single PWM sourced from a simple

controller. The PWM is applied on the PWM pin and determines the output frequency and duty cycle of the

half-bridges.

The MCT8316Z family of devices supports both analog and digital hall inputs by changing mode input setting.

Differential hall inputs should be connected to HPx and HNx pins (see Figure 8-3). Digital hall inputs should be

connected to the HPx pins while keeping the HNx pins floating (see Figure 8-4).

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The half-bridge output states are managed by the HPA, HNA, HPB, HNB, HPC and HNC pins in analog mode

and HPA, HPB, HPC in digital mode which are used as state logic inputs. The state inputs are the position

feedback of the BLDC motor. The 1x PWM mode usually operates with synchronous rectification (low-side

MOSFET recirculation); however, the mode can be configured to use asynchronous rectification (MOSFET body

diode freewheeling) as shown below

Table 8-2. PWM_MODE Configuration

MODE Pin (Hardware

MODE Type

Mode 1

Hall Configuration

Analog Hall Input

Digital Hall Input

Modulation

Asynchronous

ASR and AAR Mode

ASR and AAR Disabled

Variant)

Connected to AGND

Connected to AGND with

R_MODE1

Mode 2

Connected to AGND with

R_MODE2

Mode 3

Mode 4

Mode 5

Analog Hall Input

Digital Hall Input

Analog Hall Input

Synchronous

ASR and AAR Disabled

ASR and AAR Enabled

Hi-Z

Connected to AVDD with

R_MODE2

Connected to AVDD with

R_MODE1

Mode 6

Mode 7

Digital Hall Input

Synchronous

ASR and AAR Enabled

Connected to AVDD

Note

Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during

operation of the power MOSFETs. Set PWM to a low level before changing the MODE pin or

PWM_MODE register.

8.3.2.1 Analog Hall Input Configuration

Figure 8-3 shows the connection of Analog Hall inputs to the driver. Analog hall elements are fed to the hall

comparators, which zero crossing is used to generate the commutation logic.

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MCT8316Z

HPC

HNC

HPB

(Optional)

Analog Hall

Comparator Input

HNB

HPA

HNA

PWM

DIR

MCU_PWM

MCU_GPIO

OUTA

MCU_GPIO

BRAKE

Hall A

Hall B

Hall C

OUTB

OUTC

Figure 8-3. 1x PWM Mode with Analog Hall Input

Note

Texas Instruments recommends motor direction (DIR) change when the motor is stationary.

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8.3.2.2 Digital Hall Input Configuration

Figure 8-4 shows the connection of Digital Hall inputs to the driver.

MCT8316Z

HPC

HNC

HPB

X

Digital Inputs

HNB

HPA

HNA

PWM

DIR

MCU_PWM

MCU_GPIO

OUTA

MCU_GPIO

BRAKE

Hall A

Hall B

Hall C

OUTB

OUTC

Figure 8-4. 1x PWM Mode with Digital Hall Input

8.3.2.3 Asynchronous Modulation

The DIR pin controls the direction of BLDC motor in either clockwise or counter-clockwise direction. Tie the DIR

pin low if this feature is not required.

The BRAKE input halts the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs

when it is pulled high. This brake is independent of the states of the other input pins. Tie the BRAKE pin low if

this feature is not required.

Table 8-3 shows the configuration in 1x PWM mode with asynchronous modulation.

Table 8-3. Asynchronous Modulation

HALL INPUTS

DIR = 0

HALL_A HALL_B HALL_C HALL_A HALL_B HALL_C

DRIVER OUTPUTS

DIR = 1

PHASE A

PHASE B PHASE C

STATE

DESCRIPTION

High

Low

Side

High

Side

Low

Side

High

Side

Low

Side

/HPA

/HPB

/HPC

/HPA

/HPB

/HPC

Side

Stop

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L

PWM

L

H

L

H

L

H

L

Stop

Align

L

Align

1

2

3

4

5

6

PWM

L

B → C

A → C

A → B

C → B

C → A

B → A

PWM

L

H

L

PWM

L

PWM

L

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8.3.2.4 Synchronous Modulation

Table 8-4 shows the configuration in 1x PWM mode with synchronous modulation.

Table 8-4. Synchronous Modulation

HALL INPUTS

DIR = 0

HALL_A HALL_B HALL_C HALL_A HALL_B HALL_C

DRIVER OUTPUTS

DIR = 1

PHASE A

PHASE B PHASE C

STATE

DESCRIPTION

High

Low

Side

High

Side

Low

Side

High

Side

Low

Side

/HPA

/HPB

/HPC

/HPA

/HPB

/HPC

Side

Stop

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L

PWM

L

!PWM

L

Stop

Align

L

H

L

H

Align

1

2

3

4

5

6

PWM

!PWM

L

H

B → C

A → C

A → B

C → B

C → A

B → A

PWM

L

!PWM

L

H

L

H

PWM

L

!PWM

L

H

L

H

PWM

!PWM

8.3.2.5 Motor Operation

Figure 8-5 and Figure 8-6 shows the BLDC motor commutation with direction setting (DIR) as 0 and 1

respectively.

Hall A

Hall B

Hall C

Hall A

Hall B

Hall C

&t

I_dc

V_an

i_a

V_an

i_a

0

&t

2Œ/3

V_bn

i_b

V_bn

i_b

0

2Œ/3

V_cn

i_c

V_cn

i_c

0

&t

2Œ/3

HA, LB

HA, LC

HB, LC

HB, LA

HC, LA

HC, LB

HB, LA

HC, LA

HC, LB

HA, LB

HA, LC

HB, LC

&t

2Œ

Figure 8-5. BLDC Motor Commutation with DIR = 0 Figure 8-6. BLDC Motor Commutation with DIR = 1

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8.3.3 Device Interface Modes

The MCT8316Z family of devices supports two different interface modes (SPI and hardware) to let the end

application design for either flexibility or simplicity. The two interface modes share the same four pins, allowing

the different versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one

interface version and potentially switch to another with minimal modifications to their design.

8.3.3.1 Serial Peripheral Interface (SPI)

The SPI devices support a serial communication bus that lets an external controller send and receive data

with the MCT8316Z. This support lets the external controller configure device settings and read detailed fault

information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are

described as follows:

•

The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on

the SDI and SDO pins.

•

The SDI pin is the data input.

The SDO pin is the data output. The SDO pin can be configured to either open-drain or push-pull through

SDO_MODE.

•

The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the

MCT8316Z.

For more information on the SPI, see the Section 8.5 section.

8.3.3.2 Hardware Interface

Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are ADVANCE,

MODE, SLEW and VSEL_BK.

This conversion lets the application designer configure the most common device settings by tying the pin logic

high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for an SPI bus from

the external controller. General fault information can still be obtained through the nFAULT pin.

•

The MODE pin configures the PWM control mode.

The SLEW pin configures the slew rate of the output voltage.

The ADVANCE pin configures the lead angle of the output with respect to hall signals.

The VSEL_BK pin is used to configure the buck regulator voltage.

For more information on the hardware interface, see the Section 8.3.10 section.

AVDD

R_SLEW

AVDD

SCLK

SDI

SLEW

AVDD

MODE

SPI

Interface

VCC

R_PU

AVDD

Hardware

Interface

SDO

nSCS

ADVANCE

AVDD

GAIN

R_GAIN

Figure 8-7. MCT8316ZR SPI Interface

Figure 8-8. MCT8316ZT Hardware Interface

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8.3.4 Step-Down Mixed-Mode Buck Regulator

The MCT8316ZR and MCT8316ZT has an integrated mixed-mode buck regulator in conjunction with AVDD

to supply regulated 3.3 V or 5.0 V power for an external controller or system voltage rail. Additionally, the

buck output can also be configured to 4.0 V or 5.7 V for supporting the extra headroom for external LDO

for generating a 3.3 V or 5.0 V supplies. The output voltage of the buck is set by the VSEL_BK pin in the

MCT8316ZT device (hardware variant) and BUCK_SEL bits in the MCT8316ZR device (SPI variant).

TThe buck regulator has a low quiescent current of ~1-2 mA during light loads to prolong battery life. The device

improves performance during line and load transients by implementing a pulse-frequency current-mode control

scheme which requires less output capacitance and simplifies frequency compensation design.

To disable the buck regulator, set the BUCK_DIS bit in the MCT8316ZR (SPI variant). The buck regulator cannot

be disabled in the MCT8316ZT (hardware variant).

Note

If the buck regulator is unused, the buck pins SW_BK, GND_BK, and FB_BK cannot be left floating

or connected to ground. The buck regulator components L_BK/R_BKand C_BKmust be connected in

hardware.

Table 8-5. Recommended settings for Buck Regulator

Buck Mode

Buck output voltage Max output current Max output current Buck current limit

AVDD power

sequencing

from AVDD (I_AVDD

)

from Buck (I_BK)

Inductor - 47 μH

Inductor - 22 μH

Resistor - 22 μH

3.3 V or 4.0 V

5.0 V or 5.7 V

3.3 V or 4.0 V

5.0 V or 5.7 V

3.3 V or 4.0 V

30 mA

200 mA - I_AVDD

600 mA (BUCK_CL = Not supported

0b)

(BUCK_PS_DIS = 1)

30 mA

200 mA - I_AVDD

50 mA - I_AVDD

40 mA - I_AVDD

600 mA (BUCK_CL = Supported

0b)

(BUCK_PS_DIS = 0)

150 mA (BUCK_CL = Not supported

1b)

(BUCK_PS_DIS = 1)

150 mA (BUCK_CL = Supported

1b)

(BUCK_PS_DIS = 0)

150 mA (BUCK_CL = Not supported

1b)

(BUCK_PS_DIS = 1)

150 mA (BUCK_CL = Supported

1b)

(BUCK_PS_DIS = 0)

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8.3.4.1 Buck in Inductor Mode

The buck regulator in MCT8316Z device is primarily designed to support low inductance of 47µH and 22µH

inductors. The 47µH inductor allows the buck regulator to operate up to 200 mA load current support, whereas

the 22µH inductor limits the load current to 50 mA.

Figure 8-9 shows the connection of buck regulator in inductor mode.

VM

SW_BK

Ext. Load

V_BK

Control

L_BK

C_BK

GND_BK

FB_BK

Figure 8-9. Buck (Inductor Mode)

8.3.4.2 Buck in Resistor mode

If the external load requirements is less than 40mA, the inductor can be replaced with a resistor. In resistor mode

the power is dissipated across the external resistor and the efficiency is lower than buck in inductor mode.

Figure 8-10 shows the connection of buck regulator in resistor mode.

VM

SW_BK

Ext. Load

V_BK

Control

R_BK

C_BK

GND_BK

FB_BK

Figure 8-10. Buck (Resistor Mode)

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8.3.4.3 Buck Regulator with External LDO

The buck regulator also supports the voltage requirement to fed to external LDO to generate standard 3.3 V or

5.0 V output rail with higher accuracies. The buck output voltage should be configured to 4 V or 5.5 V to provide

for a extra headroom to support the external LDO for generating 3.3 V or 5 V rail as shown in Figure 8-11.

This allows for a lower-voltage LDO design to save cost and better thermal management due to low drop-out

voltage.

VM

V_LDO

(3.3V / 5V)

V_BK

SW_BK

(4V / 5.7V)

V_IN

V_LDO

Ext. Load

C_LDO

Control

L_BK

3.3V / 5V

LDO

C_BK

GND_BK

FB_BK

GND

External LDO

GND

Figure 8-11. Buck Regulator with External LDO

8.3.4.4 AVDD Power Sequencing on Buck Regulator

The AVDD LDO has an option of using the power supply from mixed mode buck regulator to reduce power

dissipation internally. The power sequencing mode allows on-the-fly changeover of LDO power supply from DC

mains (VM) to buck output (VBK) as shown in Figure 8-12. This sequencing can be configured through the

BUCK_PS_DIS bit . Power sequencing is supported only when buck output voltage is set to 5.0 V or 5.7 V.

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VM

SW_BK

L_BK

Ext. Load

V_BK

Control

C_BK

GND_BK

FB_BK

BUCK_PS_DIS

V_BK

VM

REF

+

–

AVDD

AGND

External Load

C_AVDD

Figure 8-12. AVDD Power Sequencing on mixed mode Buck Regulator

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8.3.4.5 Mixed mode Buck Operation and Control

The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control.

The output voltage of the buck regulator is compared with the internal reference voltage (V_{BK_REF}) which is

internally generated depending on the buck-output voltage setting (BUCK_SEL) which constitutes an outer

voltage control loop. Depending on the comparator output going high (V_BK< V_{BK_REF}) or low (V_BK> V_{BK_REF}),

the high-side power FET of the buck turns on and turna off respectively. An independent current control loop

monitors the current in high-side power FET (I_BK) and turns off the high-side FET when the current becomes

higher than the buck current limit (I_{BK_CL}). This implements a current limit control for the buck regulator. Figure

8-13 shows the architecture of the buck and various control/protection loops.

SW_BK

I_BK

Ext. Load

V_BK

VM

L_BK

PWM Control

and Driver

C_BK

GND_BK

I_BK

+

Current Limit

OC Protection

UV Protection

_

I_{BK_CL}

I_BK

+

_

I_{BK_OCP}

FB_BK

V_BK

+

_

V_{BK_UVLO}

VM

V_BK

+

_

Voltage Control

V_{BK_REF}

Buck

Reference

Voltage

BUCK_SEL

Buck Control

Generator

Figure 8-13. Buck Operation and Control Loops

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8.3.5 AVDD Linear Voltage Regulator

A 3.3-V, linear regulator is integrated into the MCT8316Z family of devices and is available for use by external

circuitry. The AVDD regulator is used for powering up the internal digital circuitry of the device and additionally,

this regulator can also provide the supply voltage for a low-power MCU or other circuitry supporting low current

(up to 30 mA). The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R,

1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.

The AVDD nominal, no-load output voltage is 3.3V.

FB_BK

BUCK_PS_DIS

V_BK

VM

REF

+

–

AVDD

AGND

External Load

C_AVDD

Figure 8-14. AVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator with VM as supply

(BUCK_PD_DIS = 1)

2 = (8_8/F 8_#8&&) × +_#8&&

(1)

For example, at a V_VMof 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in Equation

2.

P = 24 V - 3.3 V ì 20 mA = 414 mW

(

)

(2)

Use Equation 3 to calculate the power dissipated in the device by the AVDD linear regulator with buck output as

supply (BUCK_PD_DIS = 0)

P =

V

− V

× I

(3)

FB_BK

AVDD AVDD

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8.3.6 Charge Pump

Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the

VM power supply to enhance the high-side FETs fully. The MCT8316Z integrates a charge-pump circuit that

generates a voltage above the VM supply for this purpose.

The charge pump requires two external capacitors for operation. See the block diagram, pin descriptions and

see section (Section 8.3 ) for details on these capacitors (value, connection, and so forth).

The charge pump shuts down when nSLEEP is low.

VM

C_CP

CP

CPH

VM

Charge

Pump

Control

C_FLY

CPL

Figure 8-15. MCT8316Z Charge Pump

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8.3.7 Slew Rate Control

An adjustable gate-drive current control to the MOSFETs of half-bridges is implemented to achieve the slew

rate control. The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and

duration of diode recovery spikes, and switching voltage transients related to parasitics. These slew rates are

predominantly determined by the rate of gate charge to internal MOSFETs as shown in Figure 8-16.

VM

VCP (Internal)

Slew Rate

Control

OUTx

VCP (Internal)

Slew Rate

Control

GND

Figure 8-16. Slew Rate Circuit Implementation

The slew rate of each half-bridge can be adjusted by the SLEW pin in hardware device variant or by using the

SLEW bits in SPI device variant. Each half-bridge can be selected to either of a slew rate setting of 25-V/µs,

50-V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the rise time and fall time of the voltage on OUTx

pin as shown in Figure 8-17.

V_OUTx

VM

80%

20%

0

Time

t_fall

t_rise

Figure 8-17. Slew Rate Timings

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8.3.8 Cross Conduction (Dead Time)

The device is fully protected for any cross conduction of MOSFETs. In half-bridge configuration, the operation

of high-side and low-side MOSFETs are ensured to avoid any shoot-through currents by inserting a dead time

(t_dead). This is implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs

and ensuring that VGS of high-side MOSFET has reached below turn-off levels before switching on the low-side

MOSFET of same half-bridge as shown in Figure 8-18 and Figure 8-19.

VM

Gate

Control

+

VGS

HS

LS

œ

OUTx

Gate

Control

+

GND

VGS

œ

Figure 8-18. Cross Conduction Protection

OUTx HS

OUTx

Gate

(VGS_HS)

10%

t_DEAD

OUTx

Gate

(VHS_LS)

10%

OUTx LS

Time

Figure 8-19. Dead Time

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8.3.9 Propagation Delay

The propagation delay time (t_pd) is measured as the time between an input logic edge to change in gate driver

voltage. This time has three parts consisting of the digital input deglitcher delay, analog driver, and comparator

delay.

The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate

drivers. To support multiple control modes, a small digital delay is added as the input command propagates

through the device.

PWM

OUTx High

t_PD

1V

OUTx Low

OUTx

Time

Figure 8-20. Propagation Delay Timing

8.3.9.1 Driver Delay Compensation

MCT8316Z monitors the prorogation delay internally and adds a variable delay on top of it to provide fixed delay

as shown in Figure 8-21 and Figure 8-22. Delay compensation feature reduces uncertainty caused in timing of

current measurement and also reduces duty cycle distortion caused due to propagation delay.

The fixed delay is summation of propagation delay (t_PD) caused to internal driver delay and variable delay (t_VAR

)

added to compensate for uncertainty. The fixed delay can be configured through DLY_TARGET register. Refer

Table 8-6 for recommendation on configuration for DLY_TARGET for different slew rate settings.

Delay compensation is only available in SPI variant MCT8316ZR and can be enabled by configuring

DLYCMP_EN and DLY_TARGET. It is disabled in hardware variant MCT8316ZT

PWM

1V

OUTx

Time

t_VAR

t_PD

t_VAR

t_PD

DLY_TARGET

Figure 8-22. Delay Compensation with current

flowing into the phase

Figure 8-21. Delay Compensation with current

flowing out of phase

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Table 8-6. Delay Target Recommendation

SLEW RATE

200 V/μs

125 V/μs

50 V/μs

DLY_TARGET

DLY_TARGET = 0x5 (1.2 μs)

DLY_TARGET = 0x8 (1.8 μs)

DLY_TARGET = 0xB (2.4 μs)

DLY_TARGET = 0xF (3.2 μs)

25 V/μs

8.3.10 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.

8.3.10.1 Logic Level Input Pin (Internal Pulldown)

Figure 8-23 shows the input structure for the logic level pins, BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK and

SDI. The input can be with a voltage or external resistor. It is recommended to put these pins low in device sleep

mode to reduce leakage current through internal pull-down resistors.

AVDD

STATE

V_IH

CONNECTION

Tied to AVDD

Tied to GND

INPUT

Logic High

Logic Low

V_IL

R_PD

ESD

Figure 8-23. Logic-Level Input Pin Structure

8.3.10.2 Logic Level Input Pin (Internal Pullup)

Figure 8-24 shows the input structure for the logic level pin, nSCS. The input can be driven with a voltage or

external resistor.

AVDD

STATE

V_IH

CONNECTION

Tied to AVDD

Tied to GND

INPUT

R_PU

Logic High

Logic Low

V_IL

ESD

Figure 8-24. Logic nSCC

8.3.10.3 Open Drain Pin

Figure 8-25 shows the structure of the open-drain output pins, nFAULT, FGOUT and SDO in open drain mode.

The open-drain output requires an external pullup resistor to function properly.

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AVDD

STATE

No Fault

Fault

STATUS

R_PU

Pulled-Up

OUTPUT

Inactive

Active

Pulled-Down

ESD

Figure 8-25. Open Drain

8.3.10.4 Push Pull Pin

Figure 8-26 shows the structure of SDO in push-pull mode.

AVDD

STATE

V_OH

STATUS

Pulled-Up

OUTPUT

V_OL

Pulled-Down

ESD

Logic High

Logic Low

Figure 8-26. Push Pull

8.3.10.5 Four Level Input Pin

Figure 8-27 shows the structure of the four level input pins, SLEW and VSEL_BK on hardware interface devices.

The input can be set with an external resistor.

CONTROL

AVDD

STATE

V_L1

RESISTANCE

Tied to AGND

Setting-1

Setting-2

Setting-3

Setting-4

+

R_PU

œ

Hi-Z (>2000 kΩ to

AGND)

V_L2

V_L3

V_L4

+

R_PD

47 kΩ ±5%

to AVDD

œ

Tied to AVDD

+

œ

Figure 8-27. Four Level Input Pin Structure

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8.3.10.6 Seven Level Input Pin

Figure 8-28 shows the structure of the seven level input pins, ADVANCE and MODE, on hardware interface

devices. The input can be set with an external resistor.

CONTROL

Setting-1

+

œ

STATE

V_L1

RESISTANCE

Tied to AGND

Setting-2

Setting-3

Setting-4

Setting-5

Setting-6

Setting-7

+

AVDD

œ

22 kꢀ 5%

to AGND

V_L2

V_L3

V_L4

V_L5

V_L6

V_L7

+

100 kꢀ 5%

to AGND

R_PU

œ

Hi-Z (>2000 kΩ

to AGND)

R_PD

+

100 kꢀ 5%

to AVDD

œ

Latch

22 kΩ ±5%

to AVDD

+

Tied to AVDD

œ

+

œ

Figure 8-28. Seven Level Input Pin Structure

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8.3.11 Active Demagnetization

MCT8316Z family of devices has smart rectification features (active demagnetization) which decreases power

losses in the device by reducing diode conduction losses. When this feature is enabled, the device automatically

turns ON the corresponding MOSFET whenever it detects diode conduction. This feature can be configured

with the MODE pins in hardware variants. In SPI device variants this can be configured through EN_ASR and

EN_AAR bits. The smart rectification is classified into two categories of automatic synchronous rectification

(ASR) mode and automatic asynchronous rectification (AAR) mode which are described in sections below.

Note

In SPI device variants both bits, EN_ASR and EN_AAR needs to set to 1 to enable active

demagnetization.

The MCT8316Z device includes a high-side (AD_HS) and low-side (AD_LS) comparator which detects the

negative flow of current in the device on each half-bridge. The AD_HS comparator compares the sense-FET

output with the supply voltage (VM) threshold, whereas the AD_LS comparator compares with the ground (0-V)

threshold. Depending upon the flow of current from OUTx to VM or PGND to OUTx, the AD_HS or the AD_LS

comparator trips. This comparator provides a reference point for the operation of active demagnetization feature.

VM

AD_HS

Comparator

+

-

Sense

FET

(To Digital)

OUTX

VM

+

-

Sense

FET

AD_LS

Comparator

0V (GND)

PGND

VREF

I/V Converter

SOX

GAIN

Figure 8-29. Active Demagnetization Operation

Table 8-7 shows the configuration of ASR and AAR mode in the MCT8316Z device.

Table 8-7. PWM_MODE Configuration

MODE Pin

(Hardware Variant)

ASR and AAR

configuration

MODE Type

Mode 1

Hall Configuration

Analog Hall Input

Digital Hall Input

Analog Hall Input

Digital Hall Input

Analog Hall Input

Modulation

Asynchronous

Synchronous

ASR and AAR Mode

EN_ASR = 0,

EN_AAR = 0

ASR and AAR

Disabled

Connected to AGND

with R_MODE1

EN_ASR = 0,

EN_AAR = 0

ASR and AAR

Disabled

Mode 2

Connected to AGND

with R_MODE2

EN_ASR = 0,

EN_AAR = 0

ASR and AAR

Disabled

Mode 3

EN_ASR = 0,

EN_AAR = 0

ASR and AAR

Disabled

Mode 4

Hi-Z

Connected to AVDD

with R_MODE2

EN_ASR = 1,

EN_AAR = 1

ASR and AAR

Enabled

Mode 5

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Table 8-7. PWM_MODE Configuration (continued)

MODE Pin

(Hardware Variant)

ASR and AAR

configuration

MODE Type

Hall Configuration

Modulation

ASR and AAR Mode

Connected to AVDD

with R_MODE1

Mode 6

Mode 7

EN_ASR = 1,

EN_AAR = 1

ASR and AAR

Enabled

Digital Hall Input

Synchronous

Connected to AVDD

8.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)

The automatic synchronous rectification (ASR) mode is divided into two categories of ASR during commutation

and ASR during PWM mode.

8.3.11.1.1 Automatic Synchronous Rectification in Commutation

Figure 8-30 shows the operation of active demagnetization during the BLDC motor commutation. As shown

in Figure 8-30 (a), the current is flowing from HA to LC in one commutation state. During the commutation

changeover as shown in Figure 8-30 (b), the HC switch is turned on, whereas the commutation current (due to

motor inductance) in OUTA flows through the body diode of LA. This incorporates a higher diode loss depending

on the commutation current. This commutation loss is reduced by turning on the LA for the commutation time as

shown in Figure 8-30 (c).

Similarly the operation of high-side FET is realized in Figure 8-30 (d), (e) and (f).

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VM

HB

HC

HA

HB

HC

HA

OUTA

OUTB

OUTC

LA

LB

LC

LA

LB

LC

(a) Current flowing from HA to LC

VM

(d) Current flowing from HC to LA

VM

Decay Current

HB

HC

HB

OUTA

LB

HC

HA

OUTA

OUTB

LA

LB

LC

LA

LC

(e) Decay current with AD disabled

VM

(b) Decay current with AD disabled

VM

Decay Current

HB

HC

HB

OUTA

LB

HC

HA

OUTA

OUTB

LA

LB

LC

LA

LC

(c) Decay current with AD enabled

(f) Decay current with AD enabled

Figure 8-30. ASR in BLDC Motor Commutation

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Figure 8-31 (a) shows the BLDC motor phase current waveforms for automatic synchronous rectification mode

in BLDC motor operating with trapezoidal commutation. This figure shows the operation of various switches in a

single commutation cycle.

Figure 8-31 (b) shows the zoomed waveform of commutation cycle with details on the ASR mode start with

margin time (t_margin) and ASR mode early stop due to active demag. comparator threshold and delays.

Current Limit

Phase ”A‘

Current

LA

HA

HA, LB

HB, LC

HB, LA

HC, LA

HC, LB

HA, LC

(a) Commutation current of Phase —A“

t_margin

t_dead

HA Conducts

LA Body Diode

Conducts

HA Body Diode

Conducts

Phase ”A‘

Current

LA Conducts

t_dead

HC, LA

HC, LB

HA, LC

HB, LC

(b) Zoomed waveform of Active Demagnetization

Figure 8-31. Current Waveforms for ASR in BLDC Motor Commutation

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8.3.11.1.2 Automatic Synchronous Rectification in PWM Mode

Figure 8-32 shows the operation of ASR in PWM mode. As shown in this figure, a PWM is applied only on

the high-side FET, whereas the low-side FET is always off. During the PWM off time, current decays from the

low-side FET which results in higher power losses. Therefore, this mode supports turning on the low-side FET

during the low-side diode conduction.

PWM_HS

(Applied)

&t

PWM_LS

(Applied)

&t

PWM_HS

(Actual)

&t

PWM_LS

(Actual)

&t

I_a

&t

ASR Mode Disabled

ASR Mode Enabled

Figure 8-32. ASR in PWM Mode

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8.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)

Figure 8-33 shows the operation of AAR in PWM mode. As shown in this figure, a PWM is applied in a

synchronous rectification to the high-side and low-side FETs. During the low-side FET conduction, for lower

inductance motors, the current can decay to zero and becomes negative since low side FET is in on-state. This

creates a negative torque on the BLDC motor operation. When AAR mode is enabled, the current during the

decay is monitored and the low-side FET is turned off as soon as the current reaches near to zero. This saves

the negative current building in the BLDC motor which results in better noise performance and better thermal

management.

PWM_HS

(Applied)

&t

PWM_LS

(Applied)

&t

PWM_HS

(Actual)

&t

PWM_LS

(Actual)

&t

I_a

&t

AAR Mode Disabled

AAR Mode Enabled

Figure 8-33. AAR in PWM Mode

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8.3.12 Cycle-by-Cycle Current Limit

The current-limit circuit activates if the current flowing through the low-side MOSFET exceeds the I_LIMITcurrent.

This feature restricts motor current to less than the I_LIMIT

.

The current-limit circuitry utilizes the current sense amplifier output of the three phases compared with the

voltage at ILIM pin. Figure 8-34 shows the implementation of current limit circuitry. As shown in this figure, the

output of current sense amplifiers is combined with star connected resistive network. This measured voltage

V_MEASis compared with the external reference voltage e V_ILIMpin to realize the current limit implementation. The

relation between current sensed on OUTX pin and V_MEASthreshold is given as:

8

^#8&&W

: ;

¤

A F k +_176#+ +_176$+ +_176%× )#+0 3o

8_/'#5= @

2

(4)

where

•

AVDD is 3.3-V LDO output

OUTX is current flowing into the low-side MOSFET

GAIN is the CSA_GAIN setting

The I_LIMITthreshold can be adjusted by configuring ILIM pin between AVDD/2 to (AVDD/2 - 0.4) V. AVDD/2 is

minimum value and when it is applied on ILIM pin cycle by cycle current limit is disabled, whereas maximum

threshold of 8A can be configured by applying (AVDD/2 - 0.4) V on ILIM pin.

VM

AVDD

I/V Converter

SOA

OUTA

Sense

FET

GAIN

PGND

SOB

To PWM

V_MEAS

V_ILIM

Controller

-

+

ILIM

SOC

Figure 8-34. Current Limit Implementation

When then the current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle

as shown in Figure 8-35. The low-side FETs can operate in brake mode or high-Z mode by configuring the

ILIM_RECIR bit in the SPI device variant.

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PWM

OUTx

I_LIMIT

Bridge Operating in

Brake Mode

I_BRIDGE

Time

Figure 8-35. Cycle-by-Cycle Current-Limit Operation

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In the MCT8316Z device, when the current limit activates in synchronous rectification mode, the current

recirculates through the low-side FETs while the high-side FETs are disabled as shown in Figure 8-36

Moreover, when the current limit activates in asynchronous rectification mode, the current recirculates through

the body diodes of the low-side FETs while the high-side FETs are disabled as shown in Figure 8-37

VM

HB

HC

HA

HB

HC

HA

X

OUTA

OUTB

OUTC

LA

LB

LC

LA

LB LC

X X X

Figure 8-36. Brake State

Figure 8-37. Coast State

Note

The current-limit circuit is ignored immediately after the PWM signal goes active for a short blanking

time to prevent false trips of the current-limit circuit.

Note

During the brake operation, a high-current can flow through the low-side FETs which can eventually

trigger the over current protection circuit. This allows the body-diode of the high-side FET to conduct

and pump brake energy to the VM supply rail.

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8.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input

In case of 100% duty cycle applied on PWM input, there is no edge available to turn high-side FET back on.

To overcome this problem, MCT8316Z has built in internal PWM clock which is used to turn high-side FET back

on once it is disabled after exceeding I_LIMITthreshold. In SPI variant MCT8316ZR, this internal PWM clock can

be configured to either 20 kHz or 40 kHz through PWM_100_DUTY_SEL. In H/W variant MCT8316ZT PWM

internal clock is set to 20 kHz. Figure 8-38 shows operation with 100 % duty cycle.

PWM

Internal

PWM

OUTx

ILIMIT

Bridge Operating in

Brake Mode

Time

Figure 8-38. Cycle-by-Cycle Current-Limit Operation with 100% PWM Duty Cycle

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8.3.13 Hall Comparators (Analog Hall Inputs)

Three comparators are provided to process the raw signals from the Hall-effect sensors to commutate the motor.

The Hall comparators sense the zero crossings of the differential inputs and pass the information to digital logic.

The Hall comparators have hysteresis, and their detect threshold is centered at 0. The hysteresis is defined as

shown in Figure 8-39.

In addition to the hysteresis, the Hall inputs are deglitched with a circuit that ignores any extra Hall transitions

for a period of t_HDEGafter sensing a valid transition. Ignoring these transitions for the t_HDEGtime prevents PWM

noise from being coupled into the Hall inputs, which can result in erroneous commutation.

If excessive noise is still coupled into the Hall comparator inputs, adding capacitors between the positive and

negative inputs of the Hall comparators may be required. The ESD protection circuitry on the Hall inputs

implements a diode to the AVDD pin. Because of this diode, the voltage on the Hall inputs should not exceed the

AVDD voltage.

Because the AVDD pin is disabled in sleep mode (nSLEEP inactive), the Hall inputs should not be driven by

external voltages in sleep mode. If the Hall sensors are powered externally, the supply to the Hall sensors should

be disabled if the MCT8316Z device is put into sleep mode. In addition, the Hall sensors' power supply should

be powered up after enabling the motor otherwise an invalid Hall state may cause a delay in motor operation.

Hall Differential

Voltage (V_ID/2)

V_HYS/2

Hall Comparator

Common Mode

Voltage (V_CM

)

Hall Comparator

Output

t_HDEG(Hall

Deglitch Time)

Time

Figure 8-39. Hall Comparators Operation

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8.3.14 Advance Angle

The MCT8316Z includes device an advance angle feature to advance the commutation by a specified electrical

angle based on the voltage on the ADVANCE pin (in H/W device variant) or the ADVANCE bits (in SPI device

variant). Figure 8-40 shows the operation of advance angle feature.

Hall A

&t

Hall B

&t

Hall C

&t

Before Advance

After Advance

V_an

i_a

0

&t

Advance

Angle

V_bn

i_b

0

&t

2Œ/3

V_cn

i_c

0

&t

2Œ/3

HA, LB

HA, LC

HB, LC

HB, LA

HC, LA

HC, LB

&t

2Œ

Figure 8-40. Advance Angle

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8.3.15 FGOUT Signal

The MCT8316Z device also has an open-drain FGOUT signal that can be used for closed-loop speed control of

a BLDC motor. This signal includes the information of all three Hall-elements inputs as shown in Section 8.3.15.

In the MCT8316ZR (SPI variant), FGOUT can be configured to be a different division factor of Hall signals as

shown in Section 8.3.15. In the MCT8316ZT (Hardware variant), the default mode is FGOUT_SEL = 00b.

Hall Input

(HPA, HNA)

Hall Input

(HPB, HNB)

Hall Input

(HPC, HNC)

Hall Comparator

Output (HA) /

Digital Hall Input

Hall Comparator

Output (HB) /

Digital Hall Input

Hall Comparator

Output (HC) /

Digital Hall Input

FGOUT

(FGOUT_SEL =

00b)

FGOUT

(FGOUT_SEL =

01b)

FGOUT

(FGOUT_SEL =

10b)

FGOUT

(FGOUT_SEL =

11b)

Time

Figure 8-41. FGOUT Signal

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8.3.16 Protections

The MCT8316Z family of devices is protected against VM undervoltage, charge pump undervoltage, and

overcurrent events. Table 8-8 summarizes various faults details.

Table 8-8. Fault Action and Response (SPI Devices)

FAULT

CONDITION

CONFIGURATION

REPORT

H-BRIDGE

LOGIC

RECOVERY

Automatic:

V_VM> V_{UVLO_R}

CLR_FLT, nSLEEP Reset Pulse (NPOR

bit)

VM undervoltage

(NPOR)

V_VM< V_UVLO

—

Hi-Z

Disabled

Automatic:

V_AVDD> V_{AVDD_UV_R}

CLR_FLT, nSLEEP Reset Pulse (NPOR

bit)

AVDD undervoltage

(NPOR)

V_AVDD< V_{AVDD_UV}

V_{FB_BK}< V_{BK_UV}

V_CP< V_CPUV

—

Hi-Z

Active

Hi-Z

Disabled

Active

Automatic:

V_{FB_BK}> V_{BUCK_UV_R}

CLR_FLT, nSLEEP Reset Pulse

(BUCK_UV bit)

Buck undervoltage

(BUCK_UV)

nFAULT

Automatic:

V_VCP> V_CPUV

CLR_FLT, nSLEEP Reset Pulse

(VCP_UV bit)

Charge pump

undervoltage

(VCP_UV)

Active

OVP_EN = 0b

OVP_EN = 1b

None

Active

Hi-Z

Active

No action (OVP Disabled)

OverVoltage

Protection

(OVP)

Automatic:

V_VM< V_OVP

CLR_FLT, nSLEEP Reset Pulse (OVP bit)

V_VM> V_OVP

FAULT

Latched:

CLR_FLT, nSLEEP Reset Pulse (OCP

bits)

OCP_MODE = 00b

OCP_MODE = 01b

nFAULT

Hi-Z

Active

Retry:

t_RETRY

Overcurrent

Protection

(OCP)

I_PHASE> I_OCP

Automatic:

CLR_FLT, nSLEEP Reset Pulse (OCP

bits)

OCP_MODE = 10b

OCP_MODE = 11b

—

nFAULT

None

Active

No action

Buck Overcurrent

Protection

(BUCK_OCP)

Retry:

t_RETRY

I_BK> I_{BK_OC}

nFAULT

Automatic:

CLR_FLT, nSLEEP Reset Pulse

(SPI_FLT bit)

SPI_FLT_REP = 0b

nFAULT

Active

SPI Error

(SPI_FLT)

SCLK fault and ADDR

fault

SPI_FLT_REP = 1b

—

None

Active

Hi-Z

Active

No action

OTP Error

(OTP_ERR)

Latched:

OTP reading is erroneous

nFAULT

Power Cycle, nSLEEP Reset Pulse

Latched:

MTR_LOCK_MODE = 00b

MTR_LOCK_MODE = 01b

MTR_LOCK_MODE = 10b

nFAULT

Hi-Z

Active

CLR_FLT, nSLEEP Pulse (MTR_LOCK

bit)

Retry:

t_{MTR_LOCK_RETRY}

Motor Lock

(MTR_LOCK)

No Hall Signals >

t_{MTR_LOCK_TDET}

Automatic:

CLR_FLT, nSLEEP Reset Pulse (OCP

bits)

Active

MTR_LOCK_MODE = 11b

OTW_REP = 0b

None

Active

No action

Thermal warning

(OTW)

Automatic:

T_J< T_OTW– T_HYS

CLR_FLT, nSLEEP Pulse (OTW bit)

T_J> T_OTW

OTW_REP = 1b

—

nFAULT

Active

Hi-Z

Active

Automatic:

T_J< T_OTSD– T_HYS

CLR_FLT, nSLEEP Pulse (OTS bit)

Thermal shutdown

(OTSD)

T_J> T_OTSD

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8.3.16.1 VM Supply Undervoltage Lockout (NPOR)

If at any time the input supply voltage on the VM pin falls lower than the V_UVLOthreshold (VM UVLO falling

threshold), all of the integrated FETs, driver charge-pump and digital logic controller are disabled as shown in

Figure 8-42. Normal operation resumes (driver operation) when the VM undervoltage condition is removed. The

NPOR bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VM. The NPOR

bit remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (t_RST).

V_UVLO(max) rising

V_UVLO(min) rising

V_UVLO(max) falling

V_UVLO(min) falling

V_VM

DEVICE ON

DEVICE OFF

DEVICE ON

Time

Figure 8-42. VM Supply Undervoltage Lockout

8.3.16.2 AVDD Undervoltage Lockout (AVDD_UV)

If at any time the voltage on AVDD pin falls lower than the V_{AVDD_UV}threshold, all of the integrated FETs, driver

charge-pump and digital logic controller are disabled. Normal operation resumes (driver operation) when the

AVDD undervoltage condition is removed. The NPOR bit is reset and latched low in the IC status (IC_STAT)

register once the device presumes VM. The NPOR bit remains in reset condition until cleared through the

CLR_FLT bit or an nSLEEP pin reset pulse (t_RST).

8.3.16.3 BUCK Undervoltage Lockout (BUCK_UV)

If at any time the voltage on VFB_BK pin falls lower than the V_{BK_UV}threshold, the integrated FETs of the buck

regulator are disabled while the driver FETs, charge pump, and digital logic control continue to operate normally.

The nFAULT pin is driven low in the event of a buck undervoltage fault, and the BK_FLT bit in IC_STAT register

is set in SPI devices. The FAULT and BUCK_UV bits are also latched high in the registers on SPI devices.

Normal operation starts again (buck regulator operation and the nFAULT pin is released) when the BUCK

undervoltage condition clears. The BK_FLT and BUCK_UV bits stay set until cleared through the CLR_FLT bit or

an nSLEEP pin reset pulse (t_RST).

8.3.16.4 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin (charge pump) falls lower than the V_CPUVthreshold voltage of the

charge pump, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and VCP_UV

bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and

the nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set until cleared

through the CLR_FLT bit or an nSLEEP pin reset pulse (t_RST). The CPUV protection is always enabled in both

hardware and SPI device varaints.

8.3.16.5 Overvoltage Protections (OV)

If at any time input supply voltage on the VM pins rises higher lower than the V_OVPthreshold voltage, all of the

integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and OVP bits are also latched high

in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released)

when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin

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reset pulse (t_RST). Setting the OVP_EN bit high on the SPI devices enables this protection feature. On hardware

interface devices, the OVP protection is always enabled and set to a 34-V threshold.

The OVP threshold is also programmable on the SPI device variant. The OVP threshold can be set to 20-V or

32-V based on the OVP_SEL bit.

V_VM

V_OVP(max) rising

V_OVP(min) rising

V_OVP(max) falling

V_OVP(min) falling

DEVICE ON

DEVICE OFF

DEVICE ON

nFAULT

Time

Figure 8-43. Over Voltage Protection

8.3.16.6 Overcurrent Protection (OCP)

A MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across

a FET exceeds the I_OCPthreshold for longer than the t_OCPdeglitch time, an OCP event is recognized and

action is done according to the OCP_MODE bit. On hardware interface devices, the I_OCPthreshold is fixed at

16-A threshold, the t_{OCP_DEG}is fixed at 0.6-µs, and the OCP_MODE bit is configured for latched shutdown.

On SPI devices, the I_OCPthreshold is set through the OCP_LVL SPI register, the t_{OCP_DEG}is set through the

OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: OCP latched shutdown,

OCP automatic retry, OCP report only, and OCP disabled.

8.3.16.6.1 OCP Latched Shutdown (OCP_MODE = 00b)

After a OCP event in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,

and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again (driver

operation and the nFAULT pin is released) when the OCP condition clears and a clear faults command is issued

either through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).

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Peak Current due

to deglitch time

I_OCP

I_OUTx

t_OCP

nFAULT Released

nFAULT Pulled High

nFAULT

Fault Condition

Clear Fault

Time

Figure 8-44. Overcurrent Protection - Latched Shutdown Mode

8.3.16.6.2 OCP Automatic Retry (OCP_MODE = 01b)

After a OCP event in this mode, all the FETs are disabled and the nFAULT pin is driven low. The FAULT,

OCP, and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again

automatically (driver operation and the nFAULT pin is released) after the t_RETRYtime elapses. After the t_RETRY

time elapses, the FAULT, OCP, and corresponding FET's OCP bits stay latched until a clear faults command is

issued either through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).

Peak Current due

to deglitch time

I_OCP

I_OUTx

t_RETRY

t_OCP

nFAULT Released

nFAULT Pulled High

Fault Condition

nFAULT

Time

Figure 8-45. Overcurrent Protection - Automatic Retry Mode

8.3.16.6.3 OCP Report Only (OCP_MODE = 10b)

No protective action occurs after a OCP event in this mode. The overcurrent event is reported by driving the

nFAULT pin low and latching the FAULT, OCP, and corresponding FET's OCP bits high in the SPI registers. The

MCT8316Z continues to operate as usual. The external controller manages the overcurrent condition by acting

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appropriately. The reporting clears (nFAULT pin is released) when the OCP condition clears and a clear faults

command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).

8.3.16.6.4 OCP Disabled (OCP_MODE = 11b)

No action occurs after a OCP event in this mode.

8.3.16.7 Buck Overcurrent Protection

A buck overcurrent event is sensed by monitoring the current flowing through buck regulator’s FETs. If the

current across the buck regulator FET exceeds the I_{BK_OCP}threshold for longer than the t_{BK_OCP}deglitch time,

an OCP event is recognized. The buck OCP mode is configured in automatic retry setting. In this setting, after

a buck OCP event is detected, all the buck regulator’s FETs are disabled and the nFAULT pin is driven low.

The FAULT, BK_FLT, and BUCK_OCP bits are latched high in the SPI registers. Normal operation starts again

automatically (driver operation and the nFAULT pin is released) after the t_{BK_RETRY}time elapses. The FAULT,

BK_FLT, and BUCK_OCP bits stay latched until the t_RETRYperiod expires.

8.3.16.8 Motor Lock (MTR_LOCK)

During motor is in lock condition the hall signals will be not available, so a Motor Lock event is sensed by

monitoring the hall signals. If the hall signals are not present for for longer than the t_{MTR_LOCK}, a MTR_LCK event

is recognized and action is done according to the MTR_LOCK_MODE bits. On hardware interface devices, the

t_{MTR_LOCK}threshold is set to 1000-ms, and the MTR_LOCK_MODE bit is configured for latched shutdown. On

SPI devices, the t_{MTR_LOCK}threshold is set through the MTR_LOCK_TDET register and the MTR_LOCK_MODE

bit can operate in four different modes: MTR_LOCK latched shutdown, MTR_LOCK automatic retry, MTR_LOCK

report only, and MTR_LOCK disabled.

8.3.16.8.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)

After a motor lock event in this mode, all FETs are disabled and the nFAULT pin is driven low. The FAULT and

MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again (driver operation and the

nFAULT pin is released) when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP

reset pulse (t_RST).

8.3.16.8.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b)

After a motor lock event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven

low. The FAULT and MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again

automatically (driver operation and the nFAULT pin is released) after the t_{MTR_LOCK_RETRY}time elapses. The

FAULT and MTR_LOCK bits stay latched until the t_{MTR_LOCK_RETRY}period expires.

8.3.16.8.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)

No protective action occurs after a MTR_LOCK event in this mode. The motor lock event is reported by driving

the nFAULT pin low and latching the FAULT and MTR_LOCK bits high in the SPI registers. The MCT8316Z

continues to operate as usual. The external controller manages the motor lock condition by acting appropriately.

The reporting clears (nFAULT pin is released) when a clear faults command is issued either through the

CLR_FLT bit or an nSLEEP reset pulse (t_RST).

8.3.16.8.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)

No action occurs after a MTR_LOCK event in this mode.

8.3.16.8.5

Note

The motor lock detection scheme requires the PWM off-time (t_{PWM_OFF}) to be lower than the motor

lock detection time (t_{MTR_LOCK}

)

8.3.16.9 Thermal Warning (OTW)

If the die temperature exceeds the trip point of the thermal warning (T_OTW), the OT bit in the IC status (IC_STAT)

register and OTW bit in the status register is set. The reporting of OTW on the nFAULT pin can be enabled by

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setting the over-temperature warning reporting (OTW_REP) bit in the configuration control register. The device

performs no additional action and continues to function. In this case, the nFAULT pin releases when the die

temperature decreases below the hysteresis point of the thermal warning (T_{OTW_HYS}). The OTW bit remains set

until cleared through the CLR_FLT bit or an nSLEEP reset pulse (t_RST) and the die temperature is lower than

thermal warning trip (T_OTW).

Note

Over temperature warning is not reported on nFAULT pin by default.

8.3.16.10 Thermal Shutdown (OTS)

If the die temperature exceeds the trip point of the thermal shutdown limit (T_OTS), all the FETs are disabled, the

charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OT bit in the IC status

(IC_STAT) register and OTS bit in the status register is set. Normal operation starts again (driver operation

and the nFAULT pin is released) when the overtemperature condition clears. The OTS bit stays latched high

indicating that a thermal event occurred until a clear fault command is issued either through the CLR_FLT bit or

an nSLEEP reset pulse (t_RST). This protection feature cannot be disabled.

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8.4 Device Functional Modes

8.4.1 Functional Modes

8.4.1.1 Sleep Mode

The nSLEEP pin manages the state of the MCT8316Z family of devices. When the nSLEEP pin is low, the

device goes to a low-power sleep mode. In sleep mode, all FETs are disabled, sense amplifiers are disabled,

buck regulator (if present) is disabled, the charge pump is disabled, the AVDD regulator is disabled, and the SPI

bus is disabled. The t_SLEEPtime must elapse after a falling edge on the nSLEEP pin before the device goes to

sleep mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high. The t_WAKEtime

must elapse before the device is ready for inputs.

In sleep mode and when V_VM< V_UVLO, all MOSFETs are disabled.

Note

During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low

as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the

nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the

t_SLEEPor t_WAKEtime.

Note

TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into

internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on

power up or the device will enter internal test mode.

8.4.1.2 Operating Mode

When the nSLEEP pin is high and the V_VMvoltage is greater than the V_UVLOvoltage, the device goes to

operating mode. The t_WAKEtime must elapse before the device is ready for inputs. In this mode the charge

pump, AVDD regulator, buck regulator, and SPI bus are active.

8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)

In the case of device latched faults, the MCT8316Z family of devices goes to a partial shutdown state to help

protect the power MOSFETs and system.

When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT

SPI bit on SPI devices or issuing a reset pulse to the nSLEEP pin on either interface variant. The nSLEEP

reset pulse (t_RST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence

should fall with the t_RSTtime window or else the device will start the complete shutdown sequence. The reset

pulse has no effect on any of the regulators, device settings, or other functional blocks.

8.4.2 DRVOFF functionality

When DRVOFF pin is pulled high, all six MOSFETs are disabled. If nSLEEP is high when the DRVOFF pin is

high, the charge pump, AVDD regulator, buck regulator, and SPI bus are active and any driver-related faults

such as OCP will be inactive. DRVOFF pin independently disables MOSFETs which will stop motor commutation

irrespective of status of PWM input pin.

Note

Since DRVOFF pin independently disables MOSFET, it can trigger fault condition resulting in nFAULT

getting pulled low.

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8.5 SPI Communication

8.5.1 Programming

On MCT8316Z SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out

diagnostic information. The SPI operates in secondary mode and connects to a controller. The SPI input data

(SDI) word consists of a 16-bit word, with a 6-bit address and 8 bits of data. The SPI output consists of 16 bit

word, with a 8 bits of status information (STAT register) and 8-bit register data.

A valid frame must meet the following conditions:

•

The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.

The nSCS pin should be pulled high for at least 400 ns between words.

When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is

placed in the Hi-Z state.

•

Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK

pin.

•

The most significant bit (MSB) is shifted in and out first.

A full 16 SCLK cycles must occur for transaction to be valid.

If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word

is ignored.

•

For a write command, the existing data in the register being written to is shifted out on the SDO pin following

the 8-bit status data.

The SPI registers are reset to the default settings on power up and when the device is enters sleep mode

8.5.1.1 SPI Format

The SDI input data word is 16 bits long and consists of the following format:

•

1 read or write bit, W (bit B15)

6 address bits, A (bits B14 through B9)

Parity bit, P (bit B8). Parity bit is set such that the SDI input data word has even number of 1s and 0s

8 data bits, D (bits B7 through B0)

The SDO output data word is 16 bits long and the first 8 bits are status bits. The data word is the content of the

register being accessed.

For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being

written to.

For a read command (W0 = 1), the response word is the data currently in the register being read.

nSCS

A1

S1

D1

R1

SDI

SDO

Figure 8-46.

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Master Controller

Device

MCLK

MO

MI

SCLK

SDI

SPI

Communication

SDO

SPI

Communication

nSCS

CS

Figure 8-47.

Table 8-9. SDI Input Data Word Format

R/W

ADDRESS

Parity

DATA

B15

W0

B14

B13

A4

B12

A3

B11

A2

B10

A1

B9

A0

B8

P

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

A5

Table 8-10. SDO Output Data Word Format

STATUS

B15

S7

B14

S6

B13

S5

B12

S4

B11

S3

B10

S2

B9

S1

B8

S0

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

nSCS

SCLK

SDI

X

Z

MSB

LSB

X

Z

SDO

Capture

Point

Propagate

Point

Figure 8-48. SPI Secondary Timing Diagram

SPI Error Handling

SPI Frame Error (SPI_SCLK_FLT: If the nSCS gets deasserted before the end of 16-bit frame, SPI frame error

is detected and SPI_SCLK_FLT bit is set in STAT2. The SPI_SCLK_FLT status bit is latched and can be cleared

when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse

SPI Address Error (SPI_ADDR_FLT): If an invalid address is provided in the ADDR field of the input SPI

data on SDI, SPI address error is detected and SPI_ADDR_FLT bit in STAT2 is set. Invalid address is any

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address that is not defined in Register Map i.e. address not falling in the range of address 0x0 to 0xC. The

SPI_ADDR_FLT status bit is latched and can be cleared when a clear faults command is issued either through

the CLR_FLT bit or an nSLEEP reset pulse

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8.6 Register Map

8.6.1 STATUS Registers

STATUS Registers lists the memory-mapped registers for the STATUS registers. All register offset addresses not

listed in STATUS Registers should be considered as reserved locations and the register contents should not be

modified.

Table 8-11. STATUS Registers

Offset Acronym

Register Name

IC Status Register

Status Register 1

Status Register 2

Section

0h

1h

2h

IC_Status_Register

Section 8.6.1.1

Section 8.6.1.2

Section 8.6.1.3

Status_Register_1

Status_Register_2

Complex bit access types are encoded to fit into small table cells. STATUS Access Type Codes shows the codes

that are used for access types in this section.

Table 8-12. STATUS Access Type Codes

Access Type

Code

Description

Read Type

R

Read

R-0

R

Read

-0

Returns 0s

Reset or Default Value

-n

Value after reset or the default

value

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8.6.1.1 IC_Status_Register Register (Offset = 0h) [Reset = 00h]

IC_Status_Register is shown in IC_Status_Register Register and described in IC_Status_Register Register Field

Descriptions.

Return to the STATUS Registers.

Figure 8-49. IC_Status_Register Register

7

6

5

4

3

2

1

0

MTR_LOCK

R-0h

BK_FLT

R-0h

SPI_FLT

R-0h

OCP

R-0h

NPOR

R-0h

OVP

R-0h

OT

FAULT

R-0h

Table 8-13. IC_Status_Register Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MTR_LOCK

BK_FLT

SPI_FLT

OCP

R

0h

Motor Lock Staus Bit

0h = No motor lock is detected

1h = Motor lock is detected

6

5

4

3

2

1

0

R

0h

Buck Fault Bit

0h = No buck regulator fault condition is detected

1h = Buck regulator fault condition is detected

SPI Fault Bit

0h = No SPI fault condition is detected

1h = SPI Fault condition is detected

Over Current Protection Status Bit

0h = No overcurrent condition is detected

1h = Overcurrent condition is detected

NPOR

OVP

Supply Power On Reset Bit

0h = Power on reset condition is detected on VM

1h = No power-on-reset condition is detected on VM

Supply Overvoltage Protection Status Bit

0h = No overvoltage condition is detected on VM

1h = Overvoltage condition is detected on VM

OT

Overtemperature Fault Status Bit

0h = No overtemperature warning / shutdown is detected

1h = Overtemperature warning / shutdown is detected

FAULT

Device Fault Bit

0h = No fault condition is detected

1h = Fault condition is detected

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8.6.1.2 Status_Register_1 Register (Offset = 1h) [Reset = 00h]

Status_Register_1 is shown in Status_Register_1 Register and described in Status_Register_1 Register Field

Descriptions.

Return to the STATUS Registers.

Figure 8-50. Status_Register_1 Register

7

6

5

4

3

2

1

0

OTW

R-0h

OTS

R-0h

OCP_HC

R-0h

OCL_LC

R-0h

OCP_HB

R-0h

OCP_LB

R-0h

OCP_HA

R-0h

OCP_LA

R-0h

Table 8-14. Status_Register_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

OTW

R

0h

Overtemperature Warning Status Bit

0h = No overtemperature warning is detected

1h = Overtemperature warning is detected

6

5

4

3

2

1

0

OTS

R

0h

Overtemperature Shutdown Status Bit

0h = No overtemperature shutdown is detected

1h = Overtemperature shutdown is detected

OCP_HC

OCL_LC

OCP_HB

OCP_LB

OCP_HA

OCP_LA

Overcurrent Status on High-side switch of OUTC

0h = No overcurrent detected on high-side switch of OUTC

1h = Overcurrent detected on high-side switch of OUTC

Overcurrent Status on Low-side switch of OUTC

0h = No overcurrent detected on low-side switch of OUTC

1h = Overcurrent detected on low-side switch of OUTC

Overcurrent Status on High-side switch of OUTB

0h = No overcurrent detected on high-side switch of OUTB

1h = Overcurrent detected on high-side switch of OUTB

Overcurrent Status on Low-side switch of OUTB

0h = No overcurrent detected on low-side switch of OUTB

1h = Overcurrent detected on low-side switch of OUTB

Overcurrent Status on High-side switch of OUTA

0h = No overcurrent detected on high-side switch of OUTA

1h = Overcurrent detected on high-side switch of OUTA

Overcurrent Status on Low-side switch of OUTA

0h = No overcurrent detected on low-side switch of OUTA

1h = Overcurrent detected on low-side switch of OUTA

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8.6.1.3 Status_Register_2 Register (Offset = 2h) [Reset = 00h]

Status_Register_2 is shown in Status_Register_2 Register and described in Status_Register_2 Register Field

Descriptions.

Return to the STATUS Registers.

Figure 8-51. Status_Register_2 Register

7

6

5

4

3

2

1

0

RESERVED

OTP_ERR

BUCK_OCP

BUCK_UV

VCP_UV

SPI_PARITY SPI_SCLK_FLT SPI_ADDR_FL

T

R-0-0h

R-0h

R-0-0h

R-0h

Table 8-15. Status_Register_2 Register Field Descriptions

Bit

7

Field

RESERVED

Type

R-0

R

Reset

Description

0h

Reserved

6

OTP_ERR

0h

One Time Programmabilty Error

0h = No OTP error is detected

1h = OTP Error is detected

5

4

3

2

1

0

BUCK_OCP

BUCK_UV

R

0h

Buck Regulator Overcurrent Staus Bit

0h = No buck regulator overcurrent is detected

1h = Buck regulator overcurrent is detected

R

Buck Regulator Undervoltage Staus Bit

0h = No buck regulator undervoltage is detected

1h = Buck regulator undervoltage is detected

VCP_UV

R

Charge Pump Undervoltage Status Bit

0h = No charge pump undervoltage is detected

1h = Charge pump undervoltage is detected

SPI_PARITY

SPI_SCLK_FLT

SPI_ADDR_FLT

R-0

R

SPI Parity Error Bit

0h = No SPI parity error is detected

1h = SPI parity error is detected

SPI Clock Framing Error Bit

0h = No SPI clock framing error is detected

1h = SPI clock framing error is detected

R

SPI Address Error Bit

0h = No SPI address fault is detected (due to accessing non-user

register)

1h = SPI address fault is detected

8.6.2 CONTROL Registers

CONTROL Registers lists the memory-mapped registers for the CONTROL registers. All register offset

addresses not listed in CONTROL Registers should be considered as reserved locations and the register

contents should not be modified.

Table 8-16. CONTROL Registers

Offset Acronym

Register Name

Section

3h

4h

5h

6h

7h

8h

9h

Control_Register_1

Control Register 1

Control Register 2A

Control Register 3

Control Register 4

Control Register 5

Control Register 6

Control Register 7

Section 8.6.2.1

Section 8.6.2.2

Section 8.6.2.3

Section 8.6.2.4

Section 8.6.2.5

Section 8.6.2.6

Section 8.6.2.7

Control_Register_2A

Control_Register_3

Control_Register_4

Control_Register_5

Control_Register_6

Control_Register_7

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Table 8-16. CONTROL Registers (continued)

Offset Acronym

Register Name

Section

Ah

Bh

Ch

Control_Register_8

Control_Register_9

Control_Register_10

Control Register 8

Control Register 9

Control Register 10

Section 8.6.2.8

Section 8.6.2.9

Section 8.6.2.10

Complex bit access types are encoded to fit into small table cells. CONTROL Access Type Codes shows the

codes that are used for access types in this section.

Table 8-17. CONTROL Access Type Codes

Access Type

Code

Description

Read Type

R

Read

R-0

R

Read

-0

Returns 0s

Write Type

W

Write

W1C

W

Write

1C

1 to clear

WAPU

W

Write

APU

Atomic write with password

unlock

Reset or Default Value

-n

Value after reset or the default

value

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8.6.2.1 Control_Register_1 Register (Offset = 3h) [Reset = 00h]

Control_Register_1 is shown in Control_Register_1 Register and described in Control_Register_1 Register Field

Descriptions.

Return to the CONTROL Registers.

Figure 8-52. Control_Register_1 Register

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

REG_LOCK

R/WAPU-0h

Table 8-18. Control_Register_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

2-0

RESERVED

REG_LOCK

R-0

0h

Reserved

R/WAPU

0h

Register Lock Bits

0h = No effect unless locked or unlocked

1h = No effect unless locked or unlocked

2h = No effect unless locked or unlocked

3h = Write 011b to this register to unlock all registers

4h = No effect unless locked or unlocked

5h = No effect unless locked or unlocked

6h = Write 110b to lock the settings by ignoring further register writes

except to these bits and address 0x03h bits 2-0.

7h = No effect unless locked or unlocked

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8.6.2.2 Control_Register_2A Register (Offset = 4h) [Reset = 80h]

Control_Register_2A is shown in Control_Register_2A Register and described in Control_Register_2A Register

Field Descriptions.

Return to the CONTROL Registers.

Figure 8-53. Control_Register_2A Register

7

6

5

4

3

2

1

0

RESERVED

R/W-2h

SDO_MODE

R/W-0h

SLEW

PWM_MODE

R/W-0h

CLR_FLT

W1C-0h

R/W-0h

Table 8-19. Control_Register_2A Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5

RESERVED

SDO_MODE

2h

Reserved

0h

SDO Mode Setting

0h = SDO IO in Open Drain Mode

1h = SDO IO in Push Pull Mode

4-3

2-1

0

SLEW

R/W

W1C

0h

Slew Rate Settings

0h = Slew rate is 25 V/µs

1h = Slew rate is 50 V/µs

2h = Slew rate is 125 V/µs

3h = Slew rate is 200 V/µs

PWM_MODE

CLR_FLT

Device Mode Selection

0h = Asynchronous rectification with analog Hall

1h = Asynchronous rectification with digital Hall

2h = Synchronous rectification with analog Hall

3h = Synchronous rectification with digital Hall

Clear Fault

0h = No clear fault command is issued

1h = To clear the latched fault bits. This bit automatically resets after

being written.

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8.6.2.3 Control_Register_3 Register (Offset = 5h) [Reset = 46h]

Control_Register_3 is shown in Control_Register_3 Register and described in Control_Register_3 Register Field

Descriptions.

Return to the CONTROL Registers.

Figure 8-54. Control_Register_3 Register

7

6

5

4

3

2

1

0

RESERVED

PWM_100_DU

TY_SEL

OVP_SEL

OVP_EN

RESERVED

OTW_REP

R-0-0h

R/W-1h

R/W-0h

R/W-1h

R/W-0h

Table 8-20. Control_Register_3 Register Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

RESERVED

R-0

0h

6

RESERVED

R/W

1h

5

RESERVED

0h

4

PWM_100_DUTY_SEL

0h

Freqency of PWM at 100% Duty Cycle

0h = 20KHz

1h = 40KHz

3

2

OVP_SEL

OVP_EN

R/W

0h

1h

Overvoltage Level Setting

0h = VM overvoltage level is 34-V

1h = VM overvoltage level is 22-V

Overvoltage Enable Bit

0h = Overvoltage protection is disabled

1h = Overvoltage protection is enabled

1

0

RESERVED

OTW_REP

R/W

1h

0h

Reserved

Overtemperature Warning Reporting Bit

0h = Over temperature reporting on nFAULT is disabled

1h = Over temperature reporting on nFAULT is enabled

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8.6.2.4 Control_Register_4 Register (Offset = 6h) [Reset = 10h]

Control_Register_4 is shown in Control_Register_4 Register and described in Control_Register_4 Register Field

Descriptions.

Return to the CONTROL Registers.

Figure 8-55. Control_Register_4 Register

7

6

5

4

3

2

1

0

DRV_OFF

R/W-0h

OCP_CBC

R/W-0h

OCP_DEG

R/W-1h

OCP_RETRY

R/W-0h

OCP_LVL

R/W-0h

OCP_MODE

R/W-0h

Table 8-21. Control_Register_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DRV_OFF

R/W

0h

Driver OFF Bit

0h = No Action

1h = Enter Low Power Standby Mode

6

OCP_CBC

OCP_DEG

R/W

0h

1h

OCP PWM Cycle Operation Bit

0h = OCP clearing in PWM input cycle change is disabled

1h = OCP clearing in PWM input cycle change is enabled

5-4

OCP Deglitch Time Settings

0h = OCP deglitch time is 0.2 µs

1h = OCP deglitch time is 0.6 µs

2h = OCP deglitch time is 1.25 µs

3h = OCP deglitch time is 1.6 µs

3

2

OCP_RETRY

OCP_LVL

R/W

0h

OCP Retry Time Settings

0h = OCP retry time is 5 ms

1h = OCP retry time is 500 ms

Overcurrent Level Setting

0h = OCP level is 16 A

1h = OCP level is 24 A

1-0

OCP_MODE

OCP Fault Options

0h = Overcurrent causes a latched fault

1h = Overcurrent causes an automatic retrying fault

2h = Overcurrent is report only but no action is taken

3h = Overcurrent is not reported and no action is taken

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8.6.2.5 Control_Register_5 Register (Offset = 7h) [Reset = 00h]

Control_Register_5 is shown in Control_Register_5 Register and described in Control_Register_5 Register Field

Descriptions.

Return to the CONTROL Registers.

Figure 8-56. Control_Register_5 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

ILIM_RECIR

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

EN_AAR

R/W-0h

EN_ASR

R/W-0h

CSA_GAIN

R/W-0h

Table 8-22. Control_Register_5 Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

ILIM_RECIR

0h

Reserved

6

0h

Current Limit Recirculation Settings

0h = Current recirculation through FETs (Brake Mode)

1h = Current recirculation through diodes (Coast Mode)

5

4

3

RESERVED

EN_AAR

R/W

0h

Reserved

Active Asynshronous Rectification Enable Bit

0h = AAR mode is disabled

1h = AAR mode is enabled

2

EN_ASR

R/W

0h

Active Synchronous Rectification Enable Bit

0h = ASR mode is disabled

1h = ASR mode is enabled

1-0

CSA_GAIN

Current Sense Amplifier's Gain Settings

0h = CSA gain is 0.15 V/A

1h = CSA gain is 0.3 V/A

2h = CSA gain is 0.6 V/A

3h = CSA gain is 1.2 V/A

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8.6.2.6 Control_Register_6 Register (Offset = 8h) [Reset = 00h]

Control_Register_6 is shown in Control_Register_6 Register and described in Control_Register_6 Register Field

Descriptions.

Return to the CONTROL Registers.

Figure 8-57. Control_Register_6 Register

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

RESERVED

R/W-0h

BUCK_PS_DIS

R/W-0h

BUCK_CL

R/W-0h

BUCK_SEL

R/W-0h

BUCK_DIS

R/W-0h

Table 8-23. Control_Register_6 Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7-6

5

RESERVED

BUCK_PS_DIS

R-0

0h

R/W

0h

4

0h

Buck Power Sequencing Disable Bit

0h = Buck power sequencing is enabled

1h = Buck power sequencing is disabled

3

BUCK_CL

R/W

0h

Buck Current Limit Setting

0h = Buck regulator current limit is set to 600 mA

1h = Buck regulator current limit is set to 150 mA

2-1

BUCK_SEL

Buck Voltage Selection

0h = Buck voltage is 3.3 V

1h = Buck voltage is 5.0 V

2h = Buck voltage is 4.0 V

3h = Buck voltage is 5.7 V

0

BUCK_DIS

R/W

0h

Buck Disable Bit

0h = Buck regulator is enabled

1h = Buck regulator is disabled

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8.6.2.7 Control_Register_7 Register (Offset = 9h) [Reset = 00h]

Control_Register_7 is shown in Control_Register_7 Register and described in Control_Register_7 Register Field

Descriptions.

Return to the CONTROL Registers.

Figure 8-58. Control_Register_7 Register

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

HALL_HYS

R/W-0h

BRAKE_MODE

R/W-0h

COAST

R/W-0h

BRAKE

R/W-0h

DIR

R/W-0h

Table 8-24. Control_Register_7 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

HALL_HYS

R-0

0h

Reserved

R/W

0h

Hall Comparator Hysteresis Settings

0h = 5 mV

1h = 50 mV

3

2

1

0

BRAKE_MODE

COAST

R/W

0h

Brake Mode Setting

0h = Device operation is braking in brake mode

1h = Device operation is coasting in brake mode

Coast Bit

0h = Device coast mode is disabled

1h = Device coast mode is enabled

BRAKE

Brake Bit

0h = Device brake mode is disabled

1h = Device brake mode is enabled

DIR

Direction Bit

0h = Motor direction is set to clockwise direction

1h = Motor direction is set to anti-clockwise direction

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8.6.2.8 Control_Register_8 Register (Offset = Ah) [Reset = 00h]

Control_Register_8 is shown in Control_Register_8 Register and described in Control_Register_8 Register Field

Descriptions.

Return to the CONTROL Registers.

Figure 8-59. Control_Register_8 Register

7

6

5

4

3

2

1

0

FGOUT_SEL

R/W-0h

RESERVED

MTR_LOCK_R

ETRY

MTR_LOCK_TDET

R/W-0h

MTR_LOCK_MODE

R-0-0h

R/W-0h

Table 8-25. Control_Register_8 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

FGOUT_SEL

R/W

0h

Electrical Frequency Generation Output Mode Bits

0h = FGOUT frequency is 3x commutation frequency

1h = FGOUT frequency is 1x of commutation frequency

2h = FGOUT frequency is 0.5x of commutation frequency

3h = FGOUT frequency is 0.25x of commutation frequency

5

4

RESERVED

R-0

0h

Reserved

MTR_LOCK_RETRY

R/W

Motor Lock Retry Time Settings

0h = 500 ms

1h = 5000 ms

3-2

1-0

MTR_LOCK_TDET

MTR_LOCK_MODE

R/W

0h

Motor Lock Detection Time Settings

0h = 300 ms

1h = 500 ms

2h = 1000 ms

3h = 5000 ms

Motor Lock Fault Options

0h = Motor lock causes a latched fault

1h = Motor lock causes an automatic retrying fault

2h = Motor lock is report only but no action is taken

3h = Motor lock is not reported and no action is taken

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8.6.2.9 Control_Register_9 Register (Offset = Bh) [Reset = 00h]

Control_Register_9 is shown in Control_Register_9 Register and described in Control_Register_9 Register Field

Descriptions.

Return to the CONTROL Registers.

Figure 8-60. Control_Register_9 Register

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

ADVANCE_LVL

R/W-0h

Table 8-26. Control_Register_9 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

2-0

RESERVED

R-0

0h

Reserved

ADVANCE_LVL

R/W

0h

Phase Advance Setting

0h = 0°

1h = 4°

2h = 7°

3h = 11°

4h = 15°

5h = 20°

6h = 25°

7h = 30°

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8.6.2.10 Control_Register_10 Register (Offset = Ch) [Reset = 00h]

Control_Register_10 is shown in Control_Register_10 Register and described in Control_Register_10 Register

Field Descriptions.

Return to the CONTROL Registers.

Figure 8-61. Control_Register_10 Register

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

DLYCMP_EN

R/W-0h

DLY_TARGET

R/W-0h

Table 8-27. Control_Register_10 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

DLYCMP_EN

R-0

0h

Reserved

R/W

0h

Driver Delay Compensation enable

0h = Disable

1h = Enable

3-0

DLY_TARGET

R/W

0h

Delay Target for Driver Delay Compensation

0h = 0 us

1h = 0.4 us

2h = 0.6 us

3h = 0.8 us

4h = 1 us

5h = 1.2 us

6h = 1.4 us

7h = 1.6 us

8h = 1.8 us

9h = 2 us

Ah = 2.2 us

Bh = 2.4 us

Ch = 2.6 us

Dh = 2.8 us

Eh = 3 us

Fh = 3.2 us

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The MCT8316Z can be used to drive Brushless-DC motors. The following design procedure can be used to

configure the MCT8316Z.

V_VM

+

10 nF

CPL

1 µF

VM

0.1 µF

10 µF

0.1 µF

CPH

CP

V_CC

R_CL1

ILIM

AVDD

Microcontroller

R_CL2

C_AVDD

AGND

Replace Inductor (L_BK) with Resistor

(R_BK) for larger external load or to

R_PU1

reduce power dissipaꢀon

L_BK

External

Load

GP-I

FGOUT

nFAULT

SW_BK

R_PU2

R_BK

C_BK

GP-I

MCT8316ZT

GND_BK

nSLEEP

DRVOFF

GP-O

Driver

Control

FB_BK

GP-O

PWM

DIR

GP-O

PWM

Control

Module

PWM

Control

Input

OUTA

OUTB

Hall

Sensors

BRAKE

GP-O

AVDD

Hall A

Hall B

Hall C

ADVANCE

SLEW

Hardware

interface

MODE

OUTC

PGND

VSEL_BK

HPA

HPC HNC

HNA HPB HNB

(Optional)

Figure 9-1. Primary Application Schematics for MCT8316ZT (hardware variant)

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V_VM

+

47 nF

CPL

1 µF

VM

0.1 µF

10 µF

0.1 µF

CPH

CP

V_CC

R_CL1

ILIM

AVDD

Microcontroller

R_CL2

C_AVDD

AGND

Replace Inductor (L_BK) with Resistor

(R_BK) for larger external load or to

R_PU1

reduce power dissipaꢀon

L_BK

External

GP-I

FGOUT

nFAULT

Load

SW_BK

R_PU2

R_BK

C_BK

GP-I

MCT8316ZR

GND_BK

FB_BK

nSLEEP

DRVOFF

GP-O

Driver

Control

GP-O

PWM

DIR

GP-O

PWM

Control

Module

PWM

Control

Input

OUTA

Hall

BRAKE

GP-O

Sensors

Hall A

Hall B

Hall C

OUTB

SDO

GP-I

GP-O

nSCS

SCLK

SPI

OUTC

PGND

SDI

HPA

HPC HNC

HNA HPB HNB

(Optional)

Figure 9-2. Primary Application Schematics for MCT8316ZR (SPIvariant)

9.2 Hall Sensor Configuration and Connection

The combinations of Hall sensor connections in this section are common connections.

9.2.1 Typical Configuration

The Hall sensor inputs on the MCT8316Z device can interface with a variety of Hall sensors. Typically, a Hall

element is used, which outputs a differential signal. To use this type of sensor, the AVDD regulator can be used

to power the Hall sensor. Figure 9-3 shows the connections.

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AVDD

HPx

INP

OUTN

OUTP

Hall

Comparator

Hall Sensor

+

-

INN

(Optional)

HNx

Figure 9-3. Typical Hall Sensor Configuration

Because the amplitude of the Hall-sensor output signal is very low, capacitors are often placed across the Hall

inputs to help reject noise coupled from the motor. Capacitors with a value of 1 nF to 100 nF are typically used.

9.2.2 Open Drain Configuration

Some motors use digital Hall sensors with open-drain outputs. These sensors can also be used with the

MCT8316Z device, with the addition of a few resistors as shown in Figure 9-4.

AVDD

1 to

4.7 kΩ

1 to

4.7 kΩ

VCC

HPx

HNx

Hall

Comparator

Hall Sensor

GND

OUT

+

-

To Other

HNx Inputs

Figure 9-4. Open-Drain Hall Sensor Configuration

The negative (HNx) inputs are biased to AVDD / 2 by a pair of resistors between the AVDD pin and ground. For

open-collector Hall sensors, an additional pullup resistor to the VREG pin is required on the positive (HPx) input.

Again, the AVDD output can usually be used to supply power to the Hall sensors.

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9.2.3 Series Configuration

Hall elements are also connected in series or parallel depending upon the Hall sensor current/voltage

requirement. Figure 9-5 shows the series connection of Hall sensors powered via the MCT8316Z internal LDO

(AVDD). This configuration is used if the current requirement per Hall sensor is high (>10 mA)

R_SE

AVDD

INP

HPA

HNA

HPB

HNB

HPC

HNC

Hall

Comparator

Hall Sensor

INN

OUTP

OUTN

+

-

INP

Hall

Comparator

Hall Sensor

INN

+

-

INP

Hall

Comparator

Hall Sensor

+

-

INN

GND

Figure 9-5. Hall Sensor Connected in Series Configuration

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9.2.4 Parallel Configuration

Figure 9-6 shows the parallel connection of Hall sensors which is powered by the AVDD. This configuration can

be used if the current requirement per Hall sensor is low (<10 mA).

AVDD

R_PL

INP

HPA

HNA

HPB

HNB

HPC

HNC

Hall

Comparator

Hall Sensor

OUTP

OUTN

+

-

INN

GND

INP

Hall

Comparator

Hall Sensor

+

-

INN

GND

INP

Hall

Comparator

Hall Sensor

+

-

INN

GND

Figure 9-6. Hall Sensors Connected in Parallel Configuration

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9.3 Typical Applications

9.3.1 Three-Phase Brushless-DC Motor Control With Current Limit

In this application, the MCT8316Z is used to drive a brushless-DC motor with current limit up to 100% duty cycle.

The following design procedure can be used to configure the MCT8316Zin current limit mode.

9.3.1.1 Detailed Design Procedure

Table 9-1 lists the example input parameters for the system design.

Table 9-1. Design Parameters

DESIGN PARAMETERS

Supply voltage

REFERENCE

V_VM

EXAMPLE VALUE

24 V

Motor peak current

PWM Frequency

I_PEAK

2 A

f_PWM

50 kHz

Slew Rate Setting

SR

200 V/µs

3.3 V

Buck regulator output voltage

V_BK

9.3.1.1.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example 12 V or 24 V). Operating a motor at a

higher voltage corresponds to a lower drive current to obtain the same motor power. Operating at lower voltages

generally allows for more accurate control of phase currents. The MCT8316Z functions down to a supply of 4.5V.

A higher operating voltage also corresponds to a higher obtainable rpm. The MCT8316Z allows for a range of

possible operating voltages because of a maximum VM rating of 40 V.

9.3.1.1.2 Using Active Demagnetization

Active demagnetization reduces power losses in the device by turning on the MOSFETs automatically when the

body diode starts conducting to reduce diode conduction losses. It is used in trapezoidal commutation when

switching commutation states (turning a high-side MOSFET off and another high-side MOSFET on while keeping

a low-side MOSFET on). Active demagnetization is enabled when EN_ASR and EN_AAR bits are set in the SPI

variant or MODE pin is set to Mode 5, Mode 6, or Mode 7 in the H/W variant.

When switching commutation states with active demagnetization disabled, dead time is inserted and the low-side

MOSFET’s body diode conducts while turning another high-side MOSFET on to continue sourcing current

through the motor. This conduction period causes higher power losses due to the forward-bias voltage of

the diode and slower dissipation of current. Figure 9-7 shows the body diode conducting when switching

commutation states.

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Figure 9-7. Active demagnetization disabled in MCT8316Z

When active demagnetization is enabled, the AD_HS and AD_LS comparators detect when the sense FET

voltage is higher or lower than the programmed threshold. After the dead time period, if the threshold is

exceeded for a fixed amount of time, the body diode is conducting and the logic core turns the low-side FET

on to provide a conduction path with smaller power losses. Once the V_DSvoltage is below the comparator

threshold, the MOSFET turns off and current briefly conducts through the body diode until the current completely

decays to zero. This is shown in Figure 9-8.

Figure 9-8. Active demagnetization enabled in MCT8316Z

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9.3.1.1.3 Using Delay Compensation

Differences in delays of dead time and propagation delay can cause mismatch in the output timings of PWMs,

which can lead to duty cycle distortion. In order to accommodate differences in propagation delay between

various input conditions, the MCT8316ZRintegrates a Delay Compensation feature.

Delay Compensation is used to match delay times for currents going into and out of phase by adding a variable

delay time (t_var) to match a preset target delay time. This delay time is configurable in SPI devices, and it is

recommended in the datasheets to choose a target delay time that is equal to the propagation delay time plus

the driver dead time (t_pd+ t_dead).

For an example of Delay Compensation implementation, please visit the Delay and Dead Time in Integrated

MOSFET Drivers application note.

9.3.1.1.4 Using the Buck Regulator

In the MCT8316Z, the buck regulator components must be populated whether the buck is used or unused.

If unused, Resistor Mode should be configured by placing a small value resistor of 22-ohm for R_BKand a 6.3-V

rated, 22-uF capacitor for C_BKto minimize board space and reduce component cost. To disable the buck

regulator, set the BUCK_DIS in the SPI variant. The buck cannot be disabled in the Hardware variant.

If the buck regulator is used, either the Inductor or Resistor Mode can be selected. Inductor Mode allows a

22-uH or 47-uH inductor be used for L_BK. C_BKis recommended to be 22-uF. Ensure an appropriate inductor is

chosen to allow for maximum peak saturation current at a 20% inductance drop since the buck can supply up to

600-mA external current.

Resistor Mode allows for power to be dissipated in an external resistor if the load requirement is less than

40-mA. Ensure the resistor is rated for the power dissipation required at worst case VM voltage dropout. See

Equation 5, Equation 6, and Equation 7 to calculate the resistor power rating required for a 24-V rated system,

3.3V buck output voltage, and 20-mA load current.

P

> V − V

× I

BK BK

(5)

(6)

(7)

R

M

BK

>

24V − 3.3V × 20mA

R

> 0.434W

R_BK

9.3.1.1.5 Power Dissipation and Junction Temperature Losses

To calculate the junction temperature of the MCT8316Z from power losses, use Equation 8. Note that the

thermal resistance θ_JAdepends on PCB configurations such as the ambient temperature, numbers of PCB

layers, copper thickness on top and bottom layers, and the PCB area.

℃

W

T ℃ = P

W × θ

+ T ℃

A

(8)

J

loss

JA

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9.3.1.2 Application Curves

Figure 9-9. Device Powerup with VM

Figure 9-11. Driver PWM Operation

Figure 9-13. Power Management

Figure 9-10. Device Powerup with nSLEEP

Figure 9-12. Driver PWM Operation with FGOUT

Figure 9-14. Driver PWM with Active

Demagnetization (ASR and AAR)

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Figure 9-15. Driver PWM Operation with Current

Figure 9-16. Driver 100% Operation with Current

Chopping

Limit

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10 Power Supply Recommendations

10.1 Bulk Capacitance

Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors, including:

•

The highest current required by the motor system

The capacitance and current capability of the power supply

The amount of parasitic inductance between the power supply and motor system

The acceptable voltage ripple

The type of motor used (brushed dc, brushless DC, stepper)

The motor braking method

The inductance between the power supply and the motor drive system limits the rate current can change from

the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands

or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

remains stable and high current can be quickly supplied.

The data sheet generally provides a recommended value, but system-level testing is required to determine the

appropriate sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 10-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases

when the motor transfers energy to the supply.

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11 Layout

11.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver

device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used

when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high

current.

Small-value capacitors such as the charge pump, AVDD, and VREF capacitors should be ceramic and placed

closely to device pins.

The high-current device outputs should use wide metal traces.

To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,

grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage

circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the

device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to

reduce voltage offsets and maintain gate driver performance.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to

connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate

the I2 × RDS(on) heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across

all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and

improve thermal dissipation from the die surface.

Separate the SW_BUCK and FB_BUCK traces with ground separation to reduce buck switching from coupling

as noise into the buck outer feedback loop. Widen the FB_BUCK trace as much as possible to allow for faster

load switching.

Recommended Layout Example for VQFN Package shows a layout example for the MCT8316Z.

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11.2 Layout Example

Recommended Layout Example for VQFN Package

90

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11.3 Thermal Considerations

The MCT8316Z has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C

(minimally) disables the device until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient

heatsinking, or too high an ambient temperature.

11.3.1 Power Dissipation

The power dissipated in the output FET resistance, or R_DS(on)dominates power dissipation in the MCT8316Z.

At start-up and fault conditions, this current is much higher than normal running current; remember to take these

peak currents and their duration into consideration.

The total device dissipation is the power dissipated in each of the three half-H-bridges added together.

The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.

Note that R_DS(on)increases with temperature, so as the device heats, the power dissipation increases. Take this

into consideration when sizing the heatsink.

A summary of equations for calculating each loss is shown below for trapezoidal control.

Table 11-1. MCT8316Z Power Losses for Trapezoidal Control

Loss type

Trapezoidal

Standby power

LDO (from VM)

FET conduction

FET switching

Diode

P_standby= VM x I_{VM_TA}

P_LDO= (VM-V_AVDD) x I_AVDD

P_CON= 2 x I_RMS(trap)x R_ds,on(TA)

P_SW= I_PK(trap)x V_PK(trap)x t_rise/fallx f_PWM

P_diode= I_RMS(trap)x V_diode

X t_diodex f_PWM

Buck

P_BK= 0.97 x V_BKx I_BK

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12 Device and Documentation Support

12.1 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.2 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.4 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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PACKAGE OUTLINE

VQFN - 1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

A

RGF0040E

5.1

4.9

B

PIN 1 INDEX AREA

7.1

6.9

1 MAX

C

SEATING PLANE

3.7 0.1

0.08

C

0.05

0.00

3.5

SYMM

(0.1) TYP

20

13

36X 0.5

21

12

SYMM

41

5.5

5.7 0.1

1

32

0.3

40X

0.2

0.1

0.05

PIN 1 ID

(OPTIONAL)

33

40

C

A B

0.5

0.3

40X

C

4224999/A 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGF0040E

PLASTIC QUAD FLAT PACK- NO LEAD

(3.7)

(3.5)

36X (0.5)

40X (0.6)

SYMM

33

40

40X (0.25)

1

32

(Ø0.2) VIA

TYP

SYMM

41

(5.7) (5.5)

(1.35)

(1.25)

21

12

20

13

(R0.05) TYP

(0.625)

(0.975)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 12X

0.07 MIN

ALL AROUND

METAL

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

NON- SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4224999/A 06/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGF0040E

PLASTIC QUAD FLAT PACK- NO LEAD

(3.5)

36X (0.5)

SYMM

33

40

40X (0.6)

40X (0.25)

41

32

1

(Ø0.2) VIA

TYP

SYMM

(5.5)

(0.675)

(1.35)

21

12X (1.15)

12

20

13

12X (1.05)

(R0.05) TYP

(1.25)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

69% PRINTED COVERAGE BY AREA

SCALE: 12X

4224999/A 06/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MCT8316Z0RRGFR

MCT8316Z0TRGFR

VQFN

RGF

40

3000

330.0

16.4

5.25

7.25

1.45

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

MCT8316Z0RRGFR

MCT8316Z0TRGFR

VQFN

RGF

40

3000

367.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

VQFN - 1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

A

RGF0040E

5.1

4.9

B

PIN 1 INDEX AREA

7.1

6.9

1 MAX

C

SEATING PLANE

0.08 C

3.8

3.6

3.5

0.05

0.00

(0.1) TYP

20

13

36X 0.5

21

12

SYMM

41

5.8

5.6

5.5

1

32

0.3

40X

PIN 1 ID

(OPTIONAL)

0.2

33

40

SYMM

0.1

C A B

C

0.5

0.3

40X

0.05

4224999/B 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGF0040E

PLASTIC QUAD FLAT PACK- NO LEAD

(4.8)

(3.7)

(3.5)

40

33

40X (0.6)

40X (0.25)

1

32

(Ø0.2) TYP

VIA

SYMM

41

(5.7) (5.5)

(6.8)

(1.35)

(1.25)

21

12

13

20

(R0.05) TYP

36x (0.5)

(0.625)

(0.975)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224999/B 06/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGF0040E

PLASTIC QUAD FLAT PACK- NO LEAD

(4.8)

(3.5)

36X (0.5)

40

33

40X (0.6)

40X (0.25)

41

1

32

12X

(1.15)

SYMM

(5.5)

(6.8)

(0.675)

(1.35)

12

21

(R0.05) TYP

13

20

(1.25)

12X (1.05)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

69% PRINTED COVERAGE BY AREA

SCALE: 12X

4224999/B 06/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MCT8316Z_V02
厂家：	TEXAS INSTRUMENTS
描述：	nullMCT8316Z Sensored Trapezoidal Integrated FET BLDC Motor Driver
文件：	总104页 (文件大小：4179K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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