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ONET2804TLP

ZHCSGK6 –JULY 2017

ONET2804TLP

低功耗 28 Gbps、4 通道限幅 TIA

1 特性

3 说明

1

•

4 通道多速率操作：高达 28Gbps

ONET2804TLP 器件是一款用于并行光互联的高增

益、限幅互阻抗放大器 (TIA)，数据速率高达

28Gbps。此器件与 750μm 间距光电二极管阵列结合

使用，可将光信号转换为差分输出电压。由内部电路提

供光电二极管反向偏置电压并感测提供给各光电二极管

的平均光电流。

电源为 3V 时的功耗：每通道 90mW

差动互阻抗：7.5kΩ

带宽：17.5GHz

输入噪声：2μA_rms

输入过载电流：3.2mA_PP

可编程输出电压

该器件可配合引脚控制或两线制串口使用，从而实现对

输出幅值、增益、带宽和输入阈值的控制。

可调增益和带宽

每通道的接收信号强度指示器 (RSSI)

通道之间的隔离（仅限于裸片）：40 dB

单电源：2.8V 至 3.3V

ONET2804TLP 具有 17.5GHz 带宽、7.5kΩ 增益、

2µA_rms输入参考噪声和每通道的接收信号强度指示器

(RSSI)。通道间的 40dB 隔离可降低接收器中的串扰。

增耗垫控制或 2 线控制

片上滤波电容器

该器件需要单个 2.8V 至 3.3V 电源，每通道典型功耗

为 90mW，差分输出幅度为 300 mV_PP。该器件工作温

度范围为 –40°C 至 +100°C，采用裸片形式，通道间

距为 750μm。

运行温度范围：–40°C 至 +100°C

裸片尺寸：3250μm × 1450μm，通道间距为

750μm

器件信息⁽¹⁾

2 应用

器件型号

封装

封装尺寸（标称值）

•

100G 以太网光发射器

ONET2804TLP

采用叠片封装的裸片 3250µm × 1450µm

ITU OTL4.4

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

具有内部重定时功能的 CFP2、CFP4 和 QSFP28

模块

LP38690 的

眼图

VCC

330 pF

RSSI

R_RSSI

GND

Photodiode

FILTER1

0.1 ꢀF

OUT1+

OUT1-

OUT+

OUT-

IN1

1 CHANNEL of 4

0.1 ꢀF

FILTER1

GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS796

ONET2804TLP

ZHCSGK6 –JULY 2017

www.ti.com.cn

7.4 Device Functional Modes........................................ 13

7.5 Programming........................................................... 13

7.6 Register Maps......................................................... 15

Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Applications ................................................ 21

Power Supply Recommendations...................... 23

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 DC Electrical Characteristics .................................... 6

6.5 AC Electrical Characteristics..................................... 6

6.6 Timing Requirements................................................ 7

6.7 Typical Characteristics: General ............................... 8

6.8 Typical Characteristics: Eye Diagrams ................... 10

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

8

9

10 Layout................................................................... 24

10.1 Layout Guidelines ................................................. 24

10.2 Layout Example .................................................... 24

11 器件和文档支持 ..................................................... 27

11.1 接收文档更新通知 ................................................. 27

11.2 社区资源................................................................ 27

11.3 商标....................................................................... 27

11.4 静电放电警告......................................................... 27

11.5 Glossary................................................................ 27

12 机械、封装和可订购信息....................................... 27

7

4 修订历史记录

日期

修订版本

注意

2017 年 7 月

*

初始发行版。

2

ONET2804TLP

www.ti.com.cn

ZHCSGK6 –JULY 2017

5 Pin Configuration and Functions

ONET2804TLP Bond Pad Assignment: Y Package

76-Pad Die

Top View

76 75 74 73 72 71 70 69 68 67 66 65 64

59

56

55 54

53 52

51 50 49 48

63 62 61

60

58 57

47

VCCO1

VCCO2

VCCI2

1

2

3

4

5

6

46

45

44

43

42

41

VCCO4

VCCO3

VCCI3

VCC14

NC

VCCI1

I2CENA

AMPL

TRSH

CHANNEL 1

CHANNEL 2

CHANNEL 4

CHANNEL 3

7

8

40

39

SCL

SDA

RATE

GAIN

RSSI1

RSSI2

RSSI4

RSSI3

9

38

37

10

19 20 21

23 24

28 29 30 31 32

36

11 12 13 14 15 16 17 18

22

25 26 27

33 34 35

Bond Pad Functions

PAD

I/O

DESCRIPTION

NAME

NO.

2-wire interface address programming pin. Leave this pad open for a default address of 0001100.

Grounding this pad changes the first address bit to a 1 (0001101).

ADR0

ADR1

54

53

Digital input

2-wire interface address programming pin. Leave this pad open for a default address of 0001100.

Grounding this pad changes the second address bit to a 1 (0001110).

3-state input for amplitude control of all four channels.

V_CC: 500-mV_PPdifferential output swing

Open: 300-mV_PPdifferential output swing (default)

GND: 250-mV_PPdifferential output swing

AMPL

6

Digital input

FILTER1

FILTER2

FILTER3

FILTER4

12, 14

19, 21

26, 28

33, 35

FILTERx is the bias voltage for the photodiode cathode.

These pads are biased to V_CC– 100 mV.

Analog

output

3-state input for gain control of all four channels.

V_CC: Minimum transimpedance

Open: Default transimpedance

GAIN

8

Digital input

GND: Medium transimpedance

11, 15, 18,

22, 25, 29,

32, 36, 47,

48, 51, 52,

55, 56, 59,

60, 63, 64,

67, 68, 71,

72, 75, 76

Circuit ground. All GND pads are connected on the die.

Bonding all pads is recommended, except for pads 11, 15, 18, 22, 25, 29, 32, and 36.

GND

Supply

3

ONET2804TLP

ZHCSGK6 –JULY 2017

www.ti.com.cn

Bond Pad Functions (continued)

PAD

I/O

DESCRIPTION

NAME

NO.

2-wire control option. Leave the pad unconnected for pad control of the device.

Two-wire control can be enabled by applying a high signal to the pad.

I2CENA

5

Digital input

IN1

IN2

IN3

IN4

13

20

27

34

Analog

input

INx is the data input to corresponding TIA channel (connect to photodiode anode)

16, 17, 23,

24, 30, 31,

42, 61, 62, connection

69

No

NC

Do not connect

Used to reset the 2-wire state machine and registers.

Leave open for normal operation and set low to reset the 2-wire interface.

NRESET

70

Digital input

OUT1–

OUT2–

OUT3–

OUT4–

OUT1+

OUT2+

OUT3+

OUT4+

73

65

57

49

74

66

58

50

Analog

output

Inverted CML data output for channel x. On-chip, 50-Ω, back-terminated to V_CC

.

Analog

output

Noninverted CML data output for channel x. On-chip, 50-Ω, back-terminated to V_CC

.

3-state input for bandwidth control of all four channels.

V_CC: Increase the bandwidth

Open: 21-GHz bandwidth (default)

GND: Reduce the bandwidth

RATE

7

Digital input

RSSI1

RSSI2

RSSI3

RSSI4

SCL

9

Indicates the strength of the received signal (RSSI) for channel x if the photodiode is biased from

FILTERx. The analog output current is proportional to the input data amplitude. Connect to an

external resistor to ground (GND). For proper operation, ensure that the voltage at the RSSIx pad

does not exceed V_CC– 0.65 V. If the RSSI feature is not used, leave these pads open.

10

37

38

40

Analog

output

Digital input 2-wire interface serial clock input. Includes a 10-kΩ pullup resistor to V_CC

.

Digital

input/output

SDA

39

2-wire interface serial data input. Includes a 10-kΩ pullup resistor to V_CC.

3-state input for the threshold control.

V_CC: Crossing point shifted down

Open: No threshold adjustment (default)

GND: Crossing point shifted up

TRSH

41

Digital input

V_CCI1

V_CCI2

V_CCI3

V_CCI4

V_CCO1

V_CCO2

V_CCO3

V_CCO4

4

3

Supply

2.8 V to 3.47 V supply voltage for the input TIAx stage.

44

43

1

2

2.8 V to 3.47 V supply voltage for the AGCx and CMLx amplifiers.

45

46

4

ONET2804TLP

www.ti.com.cn

ZHCSGK6 –JULY 2017

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply voltage⁽¹⁾

Voltage⁽¹⁾

V_CCIx, V_CCOx

–0.3

4

V

FILTERx, OUTx+, OUTx–, RSSIx, SCL, SDA, I2CENA, ICC_ADJ,

AMPL, RATE, GAIN, TRSH, ADR1, ADR0, and NRESET

–0.3

4

V

INx

–0.7

–8

5

8

mA

°C

Average input current

FILTERx

Continuous current at outputs OUTx+, OUTx–

Maximum junction temperature, T_J

Storage temperature, T_stg

–8

8

125

150

–65

°C

(1) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE

±1000

±500

UNIT

All pins except INx

INx pins

Human-body model (HBM), per

V_(ESD)

Electrostatic discharge

V

ANSI/ESDA/JEDEC JS-001⁽¹⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

3.47

2.7

UNIT

V

V_CC

Supply voltage

2.8

3.3

I_(INx)

Average input current

mA

°C

nH

pF

V

T_A

Operating backside die temperature

Wire-bond inductance at the FILTERx and INx pins

Photodiode capacitance

–40

100

L_(FILTER), L_(IN)

0.3

0.1

C_(PD)

V_IH

Digital input high voltage

Digital input low voltage

3-state input high voltage

3-state input low voltage

SDA, SCL

2

V_IL

0.8

0.4

V

V_CC– 0.4

V

5

ONET2804TLP

ZHCSGK6 –JULY 2017

www.ti.com.cn

6.4 DC Electrical Characteristics

over recommended operating conditions with V_OD= 300 mV_PP(unless otherwise noted); typical values are at V_CC= 3.3 V and

T_A= 25°C

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL⁽¹⁾

V_CC

Supply voltage

2.8

22

3.3

3.47

42

V

A

C

A

C

A

Per channel, 30-μA_PPinput, 27°C

I_CC

Supply current

Per channel, 30-μA_PPinput, maximum 85°C

Per channel, 30-μA_PPinput, maximum 100°C

Per channel, 30-μA_PPinput, 27°C

30

36

mA

73

139

P_(RX)

Receiver power dissipation

Per channel, 30-μA_PPinput, maximum 85°C

Per channel, 30-μA_PPinput, maximum 100°C

99

118

0.85

50

mW

V_IN

Input bias voltage

Output resistance

Photodiode bias voltage⁽²⁾

RSSI gain

0.75

40

0.98

60

V

Ω

R_OUT

Single-ended to V_CC

V_(FILTER)

A_{(RSSI_IB)}

2.8

3.2

V

Resistive load to GND⁽³⁾

0.49

0.5

0.54

2.5

A/A

RSSIx feature output offset

current (no light)

0

µA

A

(1) Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization

and simulation. (C) Typical value only for information.

(2) Regulated voltage is typically 100 mV lower than V_CC

.

(3) The RSSIx output is a current output that requires a resistive load to ground (GND). The voltage gain can be adjusted for the intended

application by choosing the external resistor; however, for proper operation, ensure that the voltage at RSSIx does not exceed

V_CC– 0.65 V.

6.5 AC Electrical Characteristics

over recommended operating conditions with V_OD= 300 mV_PP(unless otherwise noted); typical values are at V_CC= 3.3 V and

T_A= 25°C

TEST

PARAMETER

TEST CONDITIONS

25-μA_PPinput signal

25-μA_PPinput signal⁽²⁾

MIN

TYP

MAX

UNIT

LEVEL⁽¹⁾

Z₂₁

Small-signal transimpedance

–3-dB bandwidth

7.5

17.5

30

kΩ

GHz

kHz

μA

C

f_(3dB-H)

f_(3dB-L)

i_N(IN)

Low-frequency, –3-dB bandwidth

Input-referred RMS noise

CPD = 0.1 pF, 28-GHz BT4 filter⁽³⁾

2

35 µA_PP< i_IN< 250 µA_PP

(27.95 Gbps, PRBS9 pattern)

2

4

C

250 µA_PP< i_IN< 500 µA_PP

(27.95 Gbps, PRBS9 pattern)

DJ

Deterministic jitter

ps_PP

500 µA_PP< i_IN< 2900 µA_PP

(27.95 Gbps, PRBS9 pattern)

V_OD

Differential output voltage

Crosstalk

500-mV_PPsetting

Between adjacent channels, up to 20 GHz⁽⁴⁾

250

500

–40

1

700

mV_PP

dB

C

RSSIx response time

Power-supply rejection ratio

μs

PSRR

f < 10 MHz⁽⁵⁾

–15

dB

(1) Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization

and simulation. (C) Typical value only for information.

(2) The small-signal bandwidth is specified over process corners, temperature, and supply voltage variation. The assumed photodiode

capacitance is 0.1 pF and the bond-wire inductance is 0.3 nH. The small-signal bandwidth strongly depends on environmental

parasitics. Careful attention to layout parasitics and external components is necessary to achieve optimal performance.

(3) Input-referred RMS noise is (RMS output noise) / (gain at 100 MHz).

(4) Die only, no wire bonds.

(5) PSRR is the differential output amplitude divided by the voltage ripple on the supply. No input current at INx.

6

ONET2804TLP

www.ti.com.cn

ZHCSGK6 –JULY 2017

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

kHz

µs

f_SCK

t_BUF

SCK clock frequency

400

Bus free time between START and STOP conditions

1.3

0.6

Hold time after repeated START condition. After this period, the first clock

pulse is generated.

t_HDSTA

µs

t_LOW

t_HIGH

t_SUSTA

t_HDDAT

t_SUDAT

t_R

Low period of the SCK clock

High period of the SCK clock

Setup time for a repeated START condition

Data hold time

1.3

0.6

0

µs

ns

µs

Data setup time

100

Rise time of both SDA and SCK signals

Fall time of both SDA and SCK signals

Setup time for STOP condition

300

t_F

t_SUSTO

0.6

7

ONET2804TLP

ZHCSGK6 –JULY 2017

www.ti.com.cn

6.7 Typical Characteristics: General

typical operating condition is at V_CC= 3.3 V, T_A= 25°C, and V_OD= 300 mV_PP(unless otherwise noted)

10000

9500

9000

8500

8000

7500

7000

6500

6000

8000

7500

7000

6500

6000

5500

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

0

200

400

600

800

1000

-40

-20

0

20

40

60

80

100

120

Input Current (uA)

Temperature (èC)

D001

D002

Figure 1. Transimpedance vs Input Current

Figure 2. Small-Signal Transimpedance vs Ambient

Temperature

10

5

20

16

12

8

0

-5

-10

-15

-20

-25

-30

4

0

10M

100M

1G

10G

100G

-40

-20

0

20

40

60

80

100

Frequency (Hz)

Temperature (èC)

D003

D004

Figure 3. Gain vs Frequency

(Test Fixture Loss De-Embedded)

Figure 4. Small-Signal Bandwidth vs Ambient Temperature

(Test Fixture Loss De-Embedded)

300

16

14

12

10

8

275

250

225

200

175

150

125

100

75

6

4

2

50

0

50 100 150 200 250 300 350 400 450 500

100 200 300 400 500 600 700 800 900 1000 1100

Input Current (mA)

Average Input Current (mA)

D005

D006

Figure 5. Differential Output Voltage vs Input Current

Figure 6. Deterministic Jitter vs Input Current

8

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www.ti.com.cn

ZHCSGK6 –JULY 2017

Typical Characteristics: General (continued)

typical operating condition is at V_CC= 3.3 V, T_A= 25°C, and V_OD= 300 mV_PP(unless otherwise noted)

1.77

1.74

1.71

1.68

1.65

1.62

1.59

1.56

1.53

1.5

1500

1250

1000

750

500

250

0

Vout = 300 mVpp

Vout = 500 mVpp

1.47

-40

-20

0

20

40

60

80

100

120

0

250 500 750 1000 1250 1500 1750 2000 2250 2500

Temperature (èC)

Average Input Current (mA)

D007

D009

Figure 7. Input-Referred Noise vs Ambient Temperature

Figure 8. RSSIx Output Current vs Average Input Current

9

ONET2804TLP

ZHCSGK6 –JULY 2017

www.ti.com.cn

6.8 Typical Characteristics: Eye Diagrams

typical operating condition is at V_CC= 3.3 V, T_A= 25°C, and V_OD= 500 mV_PP(unless otherwise noted)

27.95 Gbps

Figure 10. Output Eye-Diagram, 500-µA_PPInput Current

Figure 9. Output Eye-Diagram, 30-µA_PPInput Current

27.95 Gbps

Figure 11. Output Eye-Diagram, 1.5-mA_PPInput Current

Figure 12. Output Eye-Diagram, 2.5-mA_PPInput Current

10

ONET2804TLP

www.ti.com.cn

ZHCSGK6 –JULY 2017

7 Detailed Description

7.1 Overview

The Functional Block Diagram section shows a simplified block diagram for one channel of the ONET2804TLP.

The ONET2804TLP consists of the signal path, supply filters, a control block for dc input bias, automatic gain

control (AGC) and received signal strength indication (RSSI), an analog reference block and a two-wire serial

interface and control logic block.

The signal path consists of a transimpedance amplifier (TIA) stage, a voltage amplifier, and a current-mode logic

(CML) output buffer. The on-chip filter circuit provides a filtered V_CCfor the PIN photodiode and for the

transimpedance amplifier. The RSSI provides the bias for the TIA stage and control for the AGC.

The DC input bias circuit and automatic gain control use internal low-pass filters to cancel the DC current on the

input and to adjust the transimpedance amplifier gain. Furthermore, circuitry is provided to monitor the received

signal strength.

The output amplitude, gain, bandwidth, and input threshold can be globally controlled through pin settings or

each channel can be individually controlled through the two-wire interface.

7.2 Functional Block Diagram

VCCO1

To Output Stages

To TIA Stages

1 Channel of 4

VCCI1

GND

AGC and

RSSI

FILTER1

RSSI1

Detection

VCC

R_F

Voltage Amplifier

with Selectable

Bandwidth

50 ꢀ 50 ꢀ

OUT1+

OUT1-

IN1

Gain

Stage

CML Output

Buffer

TIA

DC Offset

Cancellation

VCC

10 kꢀ

8 Bit Register

Settings

BW/AMP

Gain/Thres

Settings

SDA

SCL

SDA

SCL

8 Bit Register

I2CENA

NRESET

ADR0

NRESET

ADR0

2-Wire Control

Individual Channel Control

ADR1

AMPL

RATE

GAIN

TRSH

AMPL

RATE

GAIN

TRSH

Pin Control

Global for all 4 Channels

Band-Gap, Analog References

Power-On

Reset

2-Wire Interface and Control Logic

11

ONET2804TLP

ZHCSGK6 –JULY 2017

www.ti.com.cn

7.3 Feature Description

7.3.1 Signal Path

The first stage of the signal path is a transimpedance amplifier that converts the photodiode current into a

voltage. If the input signal current exceeds a certain value, the transimpedance gain is reduced by means of a

nonlinear AGC circuit to limit the signal amplitude.

The second stage is a limiting voltage amplifier that provides additional limiting gain and converts the single-

ended input voltage into a differential data signal. The output stage provides CML outputs with an on-chip, 50-Ω

termination to V_CC

.

The TIA has adjustable gain, amplitude, bandwidth, and input threshold that can be globally controlled through

pad settings or each channel can be individually controlled through the two-wire interface. The default mode of

operation is pad control where the state (open, high, or low) of the AMPL, BW, GAIN, and TRSH pads sets the

respective parameter. To enable two-wire control, set the I2CENA pad high and the functionality of each channel

can be controlled individually through the two-wire interface.

7.3.2 Gain Adjustment

The gain of all TIAs can be adjusted using the GAIN pad (pad 8) in pad control mode. Gain is set to default if the

pad is left open. Gain is reduced by approximately 4 dB if the pad is tied to ground, and reduced by

approximately 8 dB if the pad is tied to V_CC. In two-wire control mode, the gain of each channel can be adjusted

from minimum to default. Gain is controlled with the GAIN[1:0] bits in registers 2, 8, 14, and 20 for channels 1, 2,

3, and 4, respectively.

7.3.3 Amplitude Adjustment

The output amplifier of all buffers can be adjusted using the AMPL pad (pad 6) in pad control mode. The

amplitude is set to 300 mV_PPdifferential if the pad is left open, 250 mV_PPif the pad is tied to ground, and 450

mV_PPif the pad is tied to V_CCvoltage (recommended mode of operation). In two-wire control mode, the amplitude

of each channel can be adjusted from 0 mV_PPto 600 mV_PP. The amplitude is controlled with the AMPL[3:0] bits

in registers 1, 7, 13, and 19 for channels 1, 2, 3, and 4, respectively.

7.3.4 Rate Select

The small-signal bandwidth can be adjusted using the RATE pad (pad 7) in pad control mode. Bandwidth is

typically 20 GHz if the pad is left open. Bandwidth is reduced by approximately 0.4 GHz if the pad is tied to

ground, and increased by approximately 0.4 GHz if the pad is tied to V_CC. In two-wire control mode, the

bandwidth of each channel can be adjusted up or down using the RATE[3:0] register settings in registers 1, 7,

13, and 19 for channels 1, 2, 3, and 4, respectively.

7.3.5 Threshold Adjustment

The TIAs have DC offset cancellation to maintain a 50% crossing point; however, the crossing point can be

adjusted using the TRSH pad (pad 41) in pad control mode. No threshold adjustment is applied if the pad is left

open. The crossing point is shifted up approximately 12% if the pad is tied to ground, and is shifted down by

approximately 12% if the pad is tied to V_CC. In two-wire control mode, the crossing point can be adjusted up or

down using the TH[3:0] register settings in registers 2, 8, 14, and 20 for channels 1, 2, 3, and 4, respectively.

7.3.6 Filter Circuitry

The FILTERx pins provide a regulated and filtered V_CCfor a PIN photodiode bias. The supply voltages for the

transimpedance amplifier have on-chip capacitors but external filter capacitors are recommended to be used as

well for best performance. The input stage has a separate V_CCsupply (V_CCIx) that is not connected on-chip to the

supply of the limiting and CML stages (V_CCOx).

7.3.7 AGC and RSSI

The voltage drop across the regulated photodiode FET is monitored by the bias and RSSI control circuit block in

the case where a PIN diode is biased using the FILTERx pins.

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Feature Description (continued)

If the DC input current exceeds a certain level then this current is partially cancelled by means of a controlled

current source. This cancellation keeps the transimpedance amplifier stage within sufficient operating limits for

optimum performance.

The automatic gain control circuitry adjusts the voltage gain of the AGC amplifier to ensure limiting behavior of

the complete amplifier.

Finally, this circuit block senses the current through the FILTERx FET and generates a mirrored current that is

proportional to the input signal strength. The mirrored currents are available at the RSSIx outputs and can be

sunk to ground (GND) using an external resistor. For proper operation, ensure that the voltage at the RSSIx pad

does not exceed V_CC– 0.65 V.

7.4 Device Functional Modes

The device has two functional modes of operation: pad control mode and two-wire interface control mode.

7.4.1 Pad Control

The default mode of operation is pad control and the amplitude is recommended to be increased to the

450 mV_PPsetting by bonding AMPL (pad 6) to V_CC. If further adjustment is desired as described previously, then

the RATE (pad 7), GAIN (pad 8), and TRSH (pad 41) control pads and can be bonded to either ground (GND) or

V_CC

.

7.4.2 Two-Wire Interface Control

To enable two-wire interface, the I2CENA (pad 5) control pad must be bonded to V_CC. In this mode of operation,

pad control is not functional and all control is initiated through the two-wire interface as described in the

Programming section.

7.5 Programming

The ONET2804TLP uses a two-wire serial interface for digital control. For example, the two circuit inputs (SDA

and SCK) are driven by the serial data and serial clock from a microcontroller. Both inputs include 10-kΩ pullup

resistors to V_CC. For driving these inputs, an open-drain output is recommended. The two-wire interface allows

write access to the internal memory map to modify control registers and read access to read out control and

status signals. The ONET2804TLP is a slave device only, which means that the device cannot initiate a

transmission, but always relies on the availability of the SCK signal for the duration of the transmission. The

master device provides the clock signal as well as the START and STOP commands. The device is

recommended to be used on a bus with only one master. The protocol for a data transmission is as follows:

1. START command

2. 7-bit slave address (0001100) followed by an eighth bit that is the data direction bit (R/W). A zero indicates a

write operation and a 1 indicates a read operation.

3. 8-bit register address

4. 8-bit register data word

5. STOP command

Regarding timing, the ONET2804TLP is I²C compatible. Figure 13 illustrates the typical timing and Figure 14

illustrates a complete data transfer. Parameters for Figure 13 are defined in the Timing Requirements table.

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Programming (continued)

SDA

t_R

t_F

t_HDSTA

t_BUF

t_LOW

t_HIGH

SCK

P

S

P

t_HDSTA

t_HDDAT

t_SUDAT

t_SUSTA

t_SUSTO

Figure 13. I²C Timing Diagram

Write Sequence

1

8

1

8

1

7

S

Slave Address

Wr

A

Register Address

A

Data Byte

A

P

Read Sequence

1

8

1

8

1

7

S

Slave Address

Wr

A

Register Address

A

S

Slave Address

Rd

A

Data Byte

N

P

Legend

S

Start Condition

Write Bit (bit value = 0)

Read Bit (bit value = 1)

Acknowledge

Wr

Rd

A

Not Acknowledge

Stop Condition

N

P

Figure 14. Data Transfer

7.5.1 Bus Idle

Both the SDA and SCK lines remain high.

7.5.2 Start Data Transfer

A change in the state of the SDA line from high to low when the SCK line is high defines a START condition (S).

Each data transfer is initiated with a START condition.

7.5.3 Stop Data Transfer

A change in the state of the SDA line from low to high when the SCK line is high defines a STOP condition (P).

Each data transfer is terminated with a STOP condition; however, to continue communication on the bus, the

master can generate a repeated START condition and address another slave without first generating a STOP

condition.

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Programming (continued)

7.5.4 Data Transfer

Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the

transfer of data.

7.5.5 Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the

SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in

such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Setup and hold

times must be taken into account. When a slave-receiver does not acknowledge the slave address, the data line

must be left high by the slave. The master can then generate a STOP condition to abort the transfer. If the slave-

receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data

bytes, the master must abort the transfer. This requirement is indicated by the slave generating a not

acknowledge on the first subsequent byte. The slave leaves the data line high and the master generates the

STOP condition.

7.6 Register Maps

Table 1 lists the registers for the ONET2804TLP.

Table 1. Register Map

REGISTER

NAME

REGISTER DATA

ADDRESS

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

7

6

PD

5

4

3

2

1

0

Register 0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

Register 7

Register 8

Register 9

Register 10

Register 11

Register 12

Register 13

Register 14

Register 15

Register 16

Register 17

Register 18

Register 19

Register 20

Register 21

Register 22

Register 23

Register 24

Register 25

RESET

RATE3

PD

RESERVED RESERVED RESERVED RESERVED RESERVED

PWRITE

AMP0

TH0

RATE2

DIS

RATE1

GAIN1

RATE0

GAIN0

AMP3

TH3

AMP2

TH2

AMP1

TH1

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

RATE3

PD

RATE2

DIS

RATE1

GAIN1

RATE0

GAIN0

AMP3

TH3

AMP2

TH2

AMP1

TH1

AMP0

TH0

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

RATE3

PD

RATE2

DIS

RATE1

GAIN1

RATE0

GAIN0

AMP3

TH3

AMP2

TH2

AMP1

TH1

AMP0

TH0

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

RATE3

PD

RATE2

DIS

RATE1

GAIN1

RATE0

GAIN0

AMP3

TH3

AMP2

TH2

AMP1

TH1

AMP0

TH0

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

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7.6.1 Register Descriptions

This section describes the circuit functionality based on the register settings. Table 2 defines the various register

bit field types used in this document.

Table 2. Register Bit Field Types

SYMBOL

DESCRIPTION

ACCESS, READ ACTION, WRITE VALUE

Read-only

R

R/W

W

Read

Read, write, or both

Write

Read-write

Write-only

7.6.2 Register 0: Control Settings (address = 00h) [reset = 0h]

Figure 15. Register 0

7

6

5

4

3

2

1

0

RESET

W-0h

PD

RESERVED

R-Xh

RESERVED

R-Xh

RESERVED

R-Xh

RESERVED

R-Xh

RESERVED

R-Xh

PWRITE

R/W-0h

Table 3. Register 0 Field Descriptions

Bit

Field

Type Reset

Description

7

RESET

W

0h

Reset registers bit.

1 = Resets all registers to default values

0 = Normal operation

6

PD

R/W

0h

Power-down bit.

1 = Power down all channels (I_CCis approximately 4 mA)

0 = Normal operation

5-1

0

Reserved

PWRITE

R

Undefined

0h

Reserved. Read-only.

R/W

Parallel write mode bit.

1 = Parallel write enabled (write register value to all channels)

0 = Serial write

7.6.3 Register 1: Amplitude and Rate for Channel 1 (address = 01h) [reset = 0h]

Figure 16. Register 1

7

6

5

4

3

2

1

0

RATE3

R/W-0h

RATE2

R/W-0h

RATE1

R/W-0h

RATE0

R/W-0h

AMP3

R/W-0h

AMP2

R/W-0h

AMP1

R/W-0h

AMP0

R/W-0h

Table 4. Register 1 Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RATE[3 :0]

R/W

0h

Rate adjustments bits for channel 1.

0000 = 21 GHz (default)

0111 = BW decrease of approximately 0.4 GHz

1111 = BW increase of approximately 0.4 GHz

All others: Do not use

R/W

0h

Amplitude adjustment bits for channel 1.

Table 5 lists the bit settings for AMP[3:0].

3-0

AMP[3:0]

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Table 5. AMP[3:0] Bit Settings

BITS

0000

0001

0010

0011

0100

0101

0110

0111

AMPLITUDE ADJUSTMENT (mV_PP

)

BITS

1000

1001

1010

1011

1100

1101

1110

1111

AMPLITUDE ADJUSTMENT (mV_PP)

0 (default)

50

250

300

350

400

450

500

550

600

100

150

200

250

300

350

7.6.4 Register 2: Threshold and Gain for Channel 1 (address = 02h) [reset = 0h]

Figure 17. Register 2

7

6

5

4

3

2

1

0

PD

DIS

GAIN1

R/W-0h

GAIN0

R/W-0h

TH3

TH2

TH1

TH0

R/W-0h

Table 6. Register 2 Field Descriptions

Bit

Field

Type

Reset

Description

7

PD

R/W

0h

Power-down bit for channel 1.

1 = Power down channel 1

0 = Normal operation

6

DIS

R/W

0h

Disable output buffer for channel 1.

1 = Disable channel 1 output buffer

0 = Normal operation

Gain adjustment bits for channel 1.

00 = Default

5-4

GAIN[1:0]

TH[3:0]

01 = Do not use

10 = Medium (–4 dB)

11 = Minimum (–8 dB)

R/W

0h

Threshold adjustment bits for channel 1.

0000 = Zero shift

0001 = Minimum positive shift

0111 = Maximum positive shift

1000 = Zero shift

3-0

1001 = Minimum negative shift

1111 = Maximum negative shift

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7.6.5 Register 7: Amplitude and Rate for Channel 2 (address = 07h) [reset = 0h]

Figure 18. Register 7

7

6

5

4

3

2

1

0

RATE3

R/W-0h

RATE2

R/W-0h

RATE1

R/W-0h

RATE0

R/W-0h

AMP3

R/W-0h

AMP2

R/W-0h

AMP1

R/W-0h

AMP0

R/W-0h

Table 7. Register 7 Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RATE[3:0]

R/W

0h

Rate adjustments bits for channel 2.

0000 = 21 GHz (default)

0111 = BW decreases by approximately 0.4 GHz

1111 = BW increases by approximately 0.4 GHz

R/W

0h

Amplitude adjustment bits for channel 2.

Table 5 lists the bit settings for AMP[3:0].

3-0

AMP[3:0]

7.6.6 Register 8: Threshold and Gain for Channel 1 (address = 08h) [reset = 0h]

Figure 19. Register 8

7

6

5

4

3

2

1

0

PD

DIS

GAIN1

R/W-0h

GAIN0

R/W-0h

TH3

TH2

TH1

TH0

R/W-0h

Table 8. Register 8 Field Descriptions

Bit

Field

Type

Reset

Description

7

PD

R/W

0h

Power-down bit for channel 2.

1 = Power down channel 2

0 = Normal operation

6

DIS

R/W

0h

Disable output buffer for channel 2.

1 = Disable channel 2 output buffer

0 = Normal operation

Gain adjustment bits for channel 2.

00 = Default

5-4

GAIN[1:0]

TH[3:0]

01 = Do not use

10 = Medium (–4 dB)

11 = Minimum (–8 dB)

R/W

0h

Threshold adjustment bits for channel 2.

0000 = Zero shift

0001 = Minimum positive shift

0111 = Maximum positive shift

1000 = Zero shift

3-0

1001 = Minimum negative shift

1111 = Maximum negative shift

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7.6.7 Register 13: Amplitude and Rate for Channel 3 (address = 0Dh) [reset = 0h]

Figure 20. Register 13

7

6

5

4

3

2

1

0

RATE3

R/W-0h

RATE2

R/W-0h

RATE1

R/W-0h

RATE0

R/W-0h

AMP3

R/W-0h

AMP2

R/W-0h

AMP1

R/W-0h

AMP0

R/W-0h

Table 9. Register 13 Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RATE[3:0]

R/W

0h

Rate adjustments bits for channel 3.

0000 = 21 GHz (default)

0111 = BW decreases by approximately 0.4 GHz

1111 = BW increases by approximately 0.4 GHz

R/W

0h

Amplitude adjustment bits for channel 3.

Table 5 lists the bit settings for AMP[3:0].

3-0

AMP[3:0]

7.6.8 Register 14: Threshold and Gain for Channel 3 (address = 0Eh) [reset = 0h]

Figure 21. Register 14

7

6

5

4

3

2

1

0

PD

DIS

GAIN1

R/W-0h

GAIN0

R/W-0h

TH3

TH2

TH1

TH0

R/W-0h

Table 10. Register 14 Field Descriptions

Bit

Field

Type

Reset

Description

7

PD

R/W

0h

Power-down bit for channel 3.

1 = Power down channel 3

0 = Normal operation

6

DIS

R/W

0h

Disable output buffer for channel 3.

1 = Disable channel 3 output buffer

0 = Normal operation

Gain adjustment bits for channel 3.

00 = Default

5-4

GAIN[1:0]

TH[3:0]

01 = Do not use

10 = Medium (–4 dB)

11 = Minimum (–8 dB)

R/W

0h

Threshold adjustment bits for channel 3.

0000 = Zero shift

0001 = Minimum positive shift

0111 = Maximum positive shift

1000 = Zero shift

3-0

1001 = Minimum negative shift

1111 = Maximum negative shift

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7.6.9 Register 19: Amplitude and Rate for Channel 4 (address = 13h) [reset = 0h]

Figure 22. Register 19

7

6

5

4

3

2

1

0

RATE3

R/W-0h

RATE2

R/W-0h

RATE1

R/W-0h

RATE0

R/W-0h

AMP3

R/W-0h

AMP2

R/W-0h

AMP1

R/W-0h

AMP0

R/W-0h

Table 11. Register 19 Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RATE[3:0]

R/W

0h

Rate adjustments bits for channel 4.

0000 = 21 GHz (default)

0111 = BW decreases by approximately 0.4 GHz

1111 = BW increases by approximately 0.4 GHz

R/W

0h

Amplitude adjustment bits for channel 4.

Table 5 lists the bit settings for AMP[3:0].

3-0

AMP[3:0]

7.6.10 Register 20: Threshold and Gain for Channel 4 (address = 14h) [reset = 0h]

Figure 23. Register 20

7

6

5

4

3

2

1

0

PD

DIS

GAIN1

R/W-0h

GAIN0

R/W-0h

TH3

TH2

TH1

TH0

R/W-0h

Table 12. Register 20 Field Descriptions

Bit

Field

Type

Reset

Description

7

PD

R/W

0h

Power-down bit for channel 4.

1 = Power down channel 4

0 = Normal operation

6

DIS

R/W

0h

Disable output buffer for channel 4.

1 = Disable channel 4 output buffer

0 = Normal operation

Gain adjustment bits for channel 4.

00 = Default

5-4

GAIN[1:0]

TH[3:0]

01 = Do not use

10 = Medium (–4 dB)

11 = Minimum (–8 dB)

R/W

0h

Threshold adjustment bits for channel 4.

0000 = Zero shift

0001 = Minimum positive shift

0111 = Maximum positive shift

1000 = Zero shift

3-0

1001 = Minimum negative shift

1111 = Maximum negative shift

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Figure 24 shows the ONET2804TLP being used in a fiber optic receiver application with four channels running at

25 Gbps each and with pin control. Figure 27 illustrates the device being used with two-wire control. The

ONET2804TLP converts the electrical current generated by the PIN photodiode into a differential output voltage.

The FILTERx inputs provide a DC bias voltage for the PIN that is low-pass filtered. The photodiode must be

connected to the FILTERx pads for the bias circuit to function correctly because the voltage drop across the

photodiode FET is sensed and used by the bias circuit.

The RSSIx outputs are used to mirror the photodiode output current and can be connected via resistors to GND.

The voltage gain can be adjusted for the intended application by choosing the external resistor; however, for

proper operation of the ONET2804TLP, ensure that the voltage at RSSIx never exceeds V_CC– 0.65 V. If the

RSSIx outputs are not used when using the internal PD bias, then leave these outputs open.

The OUTx+ and OUTx– pins are internally terminated by 50-Ω pullup resisters to V_CC. The outputs must be AC

coupled (for example, by using 0.1-µF capacitors) to the succeeding device.

8.2 Typical Applications

8.2.1 Pad Control Application

VCC

AMPL

RATE

TRSH

CHANNEL 1

CHANNEL 2

CHANNEL 4

CHANNEL 3

GAIN

RSSI1

RSSI2

RSSI4

RSSI3

Substrate

750 ꢀm Pitch

Photodiode Array

Figure 24. Basic Application Circuit with Pad Control

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Typical Applications (continued)

8.2.1.1 Design Requirements

Table 13. Design Parameters

PARAMETER

Input voltage

Output voltage

VALUE

3.3 V

300 mV_PP

8.2.1.2 Detailed Design Procedure

The ONET2804TLP is designed to be used in conjunction with a 750-μm pitch photodiode array or individual

photodiodes and assembled into a receiver optical subassembly (ROSA). The TIA is typically mounted on a

ceramic substrate with etched connections for V_CC, RSSIx, and 100-Ω differential transmission lines for the

output voltage. The photodiode converts the optical input signal into a current that is supplied to the TIA through

wire bonds. The TIA then converts the input current into a voltage and further amplifies the signal. TI

recommends setting the output amplitude to the 300-mV_PPlevel by leaving AMPL (pad 6) floating.

The ROSA is typically mounted on a printed circuit board (PCB) with 100-Ω differential transmission lines and RF

connectors [such as GPPO^®or 2.4-mm subminiature version A (SMA) connectors]. When measuring the output

from the ROSA mounted on the PCB, the frequency dependent loss of the transmission lines affects the

frequency response. The loss can be de-embedded from the measurement to determine the actual frequency

response at the output of the ROSA.

8.2.1.3 Application Curves

10

5

10

5

0

-5

-10

-15

-20

-25

-30

-10

-15

-20

-25

-30

100

1000

10000

40000

100

1000

10000

40000

Frequency (MHz)

D015

D014

Figure 25. Gain vs Frequency (Without De-Embedding)

Figure 26. Gain vs Frequency (With De-Embedding)

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8.2.2 Two-Wire Control Application

VCC

CHANNEL 1

CHANNEL 2

CHANNEL 4

CHANNEL 3

SCL

SDA

RSSI4

RSSI3

RSSI1

RSSI2

Substrate

750 ꢀm Pitch

Photodiode Array

Figure 27. Basic Application Circuit with Two-Wire Control

8.2.2.1 Design Requirements

Table 14 lists the design requirements for this application.

Table 14. Design Parameters

PARAMETER

I2CENA pin voltage

Output voltage

VALUE

3.3 V

300 mV_PP

8.2.2.2 Detailed Design Procedure

As described in the Detailed Design Procedure section on the pad control application, TI generally recommends

setting the output voltage of the device to the 300-mV_PPsetting. The output voltage setting can be controlled by

bonding specific device pads as detailed in the Pad Control Application section, but can alternatively be

controlled using the device I²C interface. To set the output amplitude via the I²C interface, the I2CENA pad must

be connected to V_CC, which enables the I²C control and disables pad control. The output amplitude can then be

set to the 300-mV_PPmode by writing the value 0110 to bits[3:0] of the amplitude control registers for each

channel as described in the Register Maps section. Requirements to operate the I²C interface are detailed in the

Programming section.

9 Power Supply Recommendations

The ONET2804TLP is designed to operate from an input supply voltage range between 2.8 V and 3.47 V. There

are a total of eight power-supply pads (V_CCI[4:1] and V_CCO[4:0]) that must be connected for proper operation.

V_CCI[4:1] are used to supply power to the input transimpedance amplifier stages and V_CCO[4:1] are used to

supply power to the voltage amplifiers and output buffers. Each amplifier is powered up separately but there are

some common internal connections for support circuitry (such as the two-wire interface). Therefore, if only one

channel is being evaluated, all eight supply pads must be connected. Use two single-layer ceramic (SLC)

capacitors in the range of 270 pF to 680 pF for power-supply decoupling. V_CCI1, V_CCI2, V_CCO1, and V_CCO2

should be bonded to one capacitor and V_CCI3, V_CCI4, V_CCO3, and V_CCO4 should be bonded to the other

capacitor; see Figure 24 and Figure 27 for reference.

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10 Layout

10.1 Layout Guidelines

Careful attention to assembly parasitics and external components is necessary to achieve optimal performance.

•

Minimize the total capacitance on the INx pad by using a low capacitance photodiode (100 fF) and pay

attention to stray capacitances. Place the photodiode close to the ONET2804TLP die and keep the wire bond

inductance in the range of 300 pH to 400 pH.

•

Use identical termination and symmetrical transmission lines at the AC-coupled differential output pins

(OUTx+ and OUTx–).

Use short bond wire connections for the supply pins V_CCIx, V_CCOx, and GND. Supply voltage filtering is

provided on-chip but filtering can be improved by using an additional external capacitor.

The die has backside metal and conductive epoxy must be used to attach the die to ground.

10.2 Layout Example

The device dimensions are shown in Figure 28 and Table 15 provides the pad locations. The device is designed

for wire bonding not flip chip layouts.

52

51 50 49

76 75

74 73 72 71

64

59

56

55 54

53

48

47

62 61

60

70 69 68 67 66 65

63

58 57

1

2

3

4

5

6

46

45

44

43

42

41

CHANNEL 1

CHANNEL 2

CHANNEL 4

CHANNEL 3

7

8

40

39

9

38

37

10

19 20 21

23 24

28 29 30 31 32

36

11 12 13 14 15 16 17 18

22

25 26 27

33 34 35

3250ꢀm

Figure 28. Device Dimensions and Pad Locations

Die thickness: 203 µm ± 13 μm

Pad dimensions: 105 μm × 65 μm

Die size: 3250 μm ± 40 µm × 1450 μm ± 40 µm

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Layout Example (continued)

Table 15. Bond Pad Coordinates

COORDINATES

(Referenced to Pad 1)

PAD

SYMBOL

V_CCO1

TYPE

DESCRIPTION

X (µm)

0

Y (µm)

0

1

Supply

3.3-V supply voltage

I²C enable

2

0

–94

V_CCO2

V_CCI2

V_CCI1

I2CENA

AMPL

RATE

GAIN

RSSI1

RSSI2

GND

Supply

3

0

–188

Supply

4

0

–282

Supply

5

0

–376

Digital input

Analog output

Supply

6

0

–470

Amplitude control

Rate selection

7

0

–580

8

0

–704

Gain control

9

0

–814

Receiver signal strength indicator for channel 1

Receiver signal strength indicator for channel 2

Circuit ground

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

0

–908

180

290

400

510

620

720

829

929

1039

1149

1259

1369

1469

1580

1680

1790

1900

2010

2120

2239

2329

2429

2539

2649

2759

2869

3051

–1110

–908

FILTER1

IN1

Analog output

Analog input

Analog output

Supply

Bias voltage for photodiode 1

TIA input for channel 1

Bias voltage for photodiode 1

Circuit ground

FILTER1

GND

NC

No connection

Supply

Do not connect

NC

Do not connect

GND

Circuit ground

FILTER2

IN2

Analog output

Analog input

Analog output

Supply

Bias voltage for photodiode 2

TIA input for channel 2

Bias voltage for photodiode 2

Circuit ground

FILTER2

GND

NC

No connect

Supply

Do not connect

NC

Do not connect

GND

Circuit ground

FILTER3

IN3

Analog output

Analog input

Analog output

Supply

Bias voltage for photodiode 3

TIA input for channel 3

Bias voltage for photodiode 3

Circuit ground

FILTER3

GND

NC

No connect

Supply

Do not connect

NC

Do not connect

GND

Circuit ground

FILTER4

IN4

Analog output

Analog input

Analog output

Supply

Bias voltage for photodiode 4

TIA input for channel 4

Bias voltage for photodiode 4

Circuit ground

FILTER4

GND

RSSI3

RSSI4

SDA

Analog output

Digital input/output

Digital input

No connect

Supply

Receiver signal strength indicator for channel 3

Receiver signal strength indicator for channel 4

2-wire data

–814

–704

–579

SCL

2-wire clock

–470

TRSH

NC

Input threshold control (cross-point)

Do not connect

–376

–282

V_CCI4

V_CCI3

3.3-V supply voltage

–188

Supply

3.3-V supply voltage

25

ONET2804TLP

ZHCSGK6 –JULY 2017

www.ti.com.cn

Layout Example (continued)

Table 15. Bond Pad Coordinates (continued)

COORDINATES

(Referenced to Pad 1)

PAD

SYMBOL

TYPE

DESCRIPTION

X (µm)

3051

2888

2799

2699

2599

2499

2410

2322

2228

2139

2050

1950

1850

1750

1661

1572

1477

1388

1299

1199

1099

999

Y (µm)

–94

0

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

V_CCO3

Supply

3.3-V supply voltage

Circuit ground

V_CCO4

GND

140

GND

Circuit ground

OUT4–

OUT4+

GND

Analog output

Supply

Inverted data output for channel 4

Noninverted data output for channel 4

Circuit ground

GND

Supply

Circuit ground

ADR1

ADR0

GND

Digital input

Supply

2-wire address bit 1 control

2-wire address bit 0 control

Circuit ground

GND

Supply

Circuit ground

OUT3–

OUT3+

GND

Analog output

Supply

Inverted data output for channel 3

Noninverted data output for channel 3

Circuit ground

GND

Supply

Circuit ground

NC

No connection

Supply

Do not connect

NC

Do not connect

GND

Circuit ground

GND

Supply

Circuit ground

OUT2–

OUT2+

GND

Analog output

Supply

Inverted data output for channel 2

Noninverted data output for channel 2

Circuit ground

910

GND

Supply

Circuit ground

821

NC

No connect

Digital input

Supply

Do not connect

728

NRESET

GND

2-wire negative reset

Circuit ground

639

550

GND

Supply

Circuit ground

450

OUT1–

OUT1+

GND

Analog output

Supply

Inverted data output for channel 1

Noninverted data output for channel 1

Circuit ground

350

250

161

GND

Supply

Circuit ground

26

ONET2804TLP

www.ti.com.cn

ZHCSGK6 –JULY 2017

11 器件和文档支持

11.1 接收文档更新通知

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TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

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设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.3 商标

E2E is a trademark of Texas Instruments.

GPPO is a registered trademark of Gilbert Incorporated.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

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会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。

27

重要声明和免责声明

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型号：	ONET2804TLPY
厂家：	TEXAS INSTRUMENTS
描述：	具有 RSSI 的 28Gbps 低功耗 4 通道限幅跨阻放大器 \| Y \| 0 \| -40 to 100 放大器
文件：	总29页 (文件大小：907K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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