OPA211IDRGT [TI]
1.1nV/âHz Noise, Low Power, Precision Operational Amplifier in Small DFN-8 Package; 1.1nV / A ???? Hz的噪声，低功耗，小型精密运算放大器DFN- 8封装
| 型号： | OPA211IDRGT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.1nV/âHz Noise, Low Power, Precision Operational Amplifier in Small DFN-8 Package |
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OPA211
OPA2211
www.ti.com ...................................................................................................................................................... SBOS377G–OCTOBER 2006–REVISED MAY 2009
1.1nV/√Hz Noise, Low Power, Precision
Operational Amplifier in Small DFN-8 Package
1
FEATURES
DESCRIPTION
23
•
LOW VOLTAGE NOISE: 1.1nV/√Hz at 1kHz
The OPA211 series of precision operational
amplifiers achieves very low 1.1nV/√Hz noise density
with a supply current of only 3.6mA. This series also
offers rail-to-rail output swing, which maximizes
dynamic range.
•
INPUT VOLTAGE NOISE:
80nVPP (0.1Hz to 10Hz)
•
•
•
•
•
•
THD+N: –136dB (G = 1, f = 1kHz)
OFFSET VOLTAGE: 125µV (max)
OFFSET VOLTAGE DRIFT: 0.35µV/°C (typ)
LOW SUPPLY CURRENT: 3.6mA/Ch (typ)
UNITY-GAIN STABLE
The extremely low voltage and low current noise,
high speed, and wide output swing of the OPA211
series make these devices an excellent choice as a
loop filter amplifier in PLL applications.
GAIN BANDWIDTH PRODUCT:
80MHz (G = 100)
45MHz (G = 1)
In precision data acquisition applications, the
OPA211 series of op amps provides 700ns settling
time to 16-bit accuracy throughout 10V output swings.
This ac performance, combined with only 125µV of
offset and 0.35µV/°C of drift over temperature, makes
the OPA211 ideal for driving high-precision 16-bit
analog-to-digital converters (ADCs) or buffering the
output of high-resolution digital-to-analog converters
(DACs).
•
•
•
SLEW RATE: 27V/µs
16-BIT SETTLING: 700ns
WIDE SUPPLY RANGE:
±2.25V to ±18V, +4.5V to +36V
•
•
•
RAIL-TO-RAIL OUTPUT
The OPA211 series is specified over
a wide
OUTPUT CURRENT: 30mA
dual-power supply range of ±2.25V to ±18V, or for
single-supply operation from +4.5V to +36V.
DFN-8 (3mm × 3mm), MSOP-8, AND SO-8
The OPA211 is available in the small DFN-8 (3mm ×
3mm), MSOP-8, and SO-8 packages. A dual version,
the OPA2211, is available in the DFN-8 (3mm ×
3mm) or an SO-8 PowerPAD™ package. This series
of op amps is specified from TA = –40°C to +125°C.
APPLICATIONS
•
PLL LOOP FILTER
•
LOW-NOISE, LOW-POWER SIGNAL
PROCESSING
•
•
•
•
•
•
•
•
•
•
•
16-BIT ADC DRIVERS
DAC OUTPUT AMPLIFIERS
ACTIVE FILTERS
LOW-NOISE INSTRUMENTATION AMPS
ULTRASOUND AMPLIFIERS
PROFESSIONAL AUDIO PREAMPLIFIERS
LOW-NOISE FREQUENCY SYNTHESIZERS
INFRARED DETECTOR AMPLIFIERS
HYDROPHONE AMPLIFIERS
GEOPHONE AMPLIFIERS
INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
100
10
MEDICAL
1
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
OPA211
OPA2211
SBOS377G–OCTOBER 2006–REVISED MAY 2009...................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
UNIT
V
Supply Voltage
VS = (V+) – (V–)
40
(V–) – 0.5 to (V+) + 0.5
±10
Input Voltage
V
Input Current (Any pin except power-supply pins)
Output Short-Circuit(2)
Operating Temperature
Storage Temperature
mA
Continuous
(TA)
(TA)
(TJ)
–55 to +150
–65 to +150
200
°C
°C
°C
V
Junction Temperature
Human Body Model (HBM)
ESD Ratings
3000
Charged Device Model (CDM)
1000
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Short-circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE
DESIGNATOR
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
SINGLE
SHUTDOWN
DUAL
Standard Grade
DFN-8 (3mm × 3mm)
MSOP-8
ü
ü
ü
ü
DRG
DGK
OBDQ
OBCQ
OPA211AI
A TI OPA
211
SO-8
ü
D
DFN-8 (3mm × 3mm)
SO-8 PowerPAD
ü
ü
DRG
DDA
OBHQ
OPA2211AI
A TI OPA
2211
High Grade
DFN-8 (3mm × 3mm)
MSOP-8
ü
ü
ü
ü
DRG
DGK
OBDQ
OBCQ
OPA211I
TI OPA
211
SO-8
ü
D
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
2
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Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): OPA211 OPA2211
OPA211
OPA2211
www.ti.com ...................................................................................................................................................... SBOS377G–OCTOBER 2006–REVISED MAY 2009
PIN CONFIGURATIONS
OPA211
SO-8
OPA211
MSOP-8
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC(1)
V+
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
Shutdown(3)
V+
OUT
NC(1)
OUT
NC(1)
OPA211
DFN-8 (3mm × 3mm)
OPA2211
DFN-8 (3mm × 3mm)
NC(1)
1
2
3
4
8
7
6
5
Shutdown(3)
V+
V+
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
-IN
+IN
V-
OUT B
-IN B
+IN B
A
OUT
B
NC(1)
Pad(2)
Pad(2)
OPA2211
SO-8 PowerPAD
OUT A
1
2
3
4
8
7
6
5
V+
A
-IN A
+IN A
V-
OUT B
-IN B
+IN B
B
Pad(2)
(1) NC denotes no internal connection.
(2) Exposed thermal die pad on underside; connect thermal die pad to V–. Soldering the thermal pad improves heat
dissipation and provides specified performance.
(3) Shutdown function:
•
•
Device enabled: (V–) ≤ VSHUTDOWN ≤ (V+) – 3V
Device disabled: VSHUTDOWN ≥ (V+) – 0.35V
Copyright © 2006–2009, Texas Instruments Incorporated
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OPA211
OPA2211
SBOS377G–OCTOBER 2006–REVISED MAY 2009...................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±2.25V to ±18V
BOLDFACE limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Standard Grade
OPA211AI, OPA2211AI
High Grade
OPA211I(1)
PARAMETER
OFFSET VOLTAGE
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Input Offset Voltage
OPA211
VOS
VS = ±15V
VS = ±15V
±30
±50
0.35
0.1
±125
±150
1.5
1
±20
±50
µV
µV
OPA2211
Drift
dVOS/dT
0.15
0.85
0.5
3
µV/°C
µV/V
µV/V
vs Power Supply
PSRR
VS = ±2.25V to ±18V
0.1
Over Temperature
3
INPUT BIAS CURRENT
Input Bias Current
Over Temperature
OPA211
IB
VCM = 0V
±60
±25
±175
±50
±20
±125
nA
±200
±250
±100
±150
±200
nA
nA
nA
nA
OPA2211
Offset Current
IOS
VCM = 0V
±75
Over Temperature
NOISE
±150
Input Voltage Noise
Input Voltage Noise Density
en
f = 0.1Hz to 10Hz
f = 10Hz
80
2
80
2
nVPP
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
f = 100Hz
f = 1kHz
1.4
1.1
3.2
1.7
1.4
1.1
3.2
1.7
Input Current Noise Density
In
f = 10Hz
f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
VCM
V
S ≥ ±5V
(V–) + 1.8
(V–) + 2
114
(V+) – 1.4
(V+) – 1.4
(V–) + 1.8
(V–) + 2
114
(V+) – 1.4
(V+) – 1.4
V
V
VS < ±5V
Common-Mode Rejection Ratio
CMRR
V
S ≥ ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V
120
120
120
120
dB
dB
VS < ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V
110
110
INPUT IMPEDANCE
Differential
20k || 8
109 || 2
20k || 8
109 || 2
Ω || pF
Ω || pF
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
AOL
(V–) + 0.2V ≤ VO ≤ (V+) – 0.2V,
RL = 10kΩ
114
130
114
130
dB
AOL
(V–) + 0.6V ≤ VO ≤ (V+) – 0.6V,
RL = 600Ω
110
114
110
114
dB
Over Temperature
OPA211
AOL
AOL
AOL
(V–) + 0.6V ≤ VO ≤ (V+) – 0.6V,
110
103
100
110
103
dB
dB
dB
IO ≤ 15mA
OPA211
(V–) + 0.6V ≤ VO ≤ (V+) – 0.6V,
15mA ≤ IO ≤ 30mA
OPA2211 (per channel)
(V–) + 0.6V ≤ VO ≤ (V+)–0.6V,
IO ≤ 15mA
FREQUENCY RESPONSE
Gain-Bandwidth Product
GBW
SR
G = 100
G = 1
80
45
80
45
MHz
MHz
V/µs
ns
Slew Rate
27
27
Settling Time, 0.01%
0.0015% (16-bit)
tS VS = ±15V, G = –1, 10V Step, CL = 100pF
VS = ±15V, G = –1, 10V Step, CL = 100pF
G = –10
400
700
500
400
700
500
ns
Overload Recovery Time
Total Harmonic Distortion + Noise
ns
THD+N
G = +1, f = 1kHz,
VO = 3VRMS, RL = 600Ω
0.000015
–136
0.000015
–136
%
dB
(1) Shaded cells indicate different specifications from standard-grade version of device.
4
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Product Folder Link(s): OPA211 OPA2211
OPA211
OPA2211
www.ti.com ...................................................................................................................................................... SBOS377G–OCTOBER 2006–REVISED MAY 2009
ELECTRICAL CHARACTERISTICS: VS = ±2.25V to ±18V (continued)
BOLDFACE limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Standard Grade
OPA211AI, OPA2211AI
High Grade
OPA211I(1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
OUTPUT
Voltage Output
VOUT
RL = 10kΩ, AOL ≥ 114dB
RL = 600Ω, AOL ≥ 110dB
IO < 15mA, AOL ≥ 110dB
(V–) + 0.2
(V–) + 0.6
(V–) + 0.6
(V+) – 0.2
(V+) – 0.6
(V+) – 0.6
(V–) + 0.2
(V–) + 0.6
(V–) + 0.6
(V+) – 0.2
(V+) – 0.6
(V+) – 0.6
V
V
V
Short-Circuit Current
ISC
CLOAD
ZO
+30/–45
+30/–45
mA
pF
Ω
Capacitive Load Drive
Open-Loop Output Impedance
SHUTDOWN
See Typical Characteristics
5
See Typical Characteristics
5
f = 1MHz
Shutdown Pin Input Voltage(2)
Device disabled (shutdown)
Device enabled
(V+) – 0.35
(V+) – 0.35
V
V
(V+) – 3
(V+) – 3
Shutdown Pin Leakage Current
Turn-On Time(3)
1
2
3
1
1
2
3
1
µA
µs
µs
µA
Turn-Off Time(3)
Shutdown Current
POWER SUPPLY
Specified Voltage
Shutdown (disabled)
20
20
VS
IQ
±2.25
±18
4.5
6
±2.25
±18
4.5
6
V
Quiescent Current
(per channel)
IOUT = 0A
3.6
3.6
mA
mA
Over Temperature (per channel)
TEMPERATURE RANGE
Specified Range
Operating Range
Thermal Resistance
OPA211
TA
TA
–40
–55
+125
+150
–40
–55
+125
+150
°C
°C
SO-8
θ
150
200
65
150
200
65
°C/W
°C/W
°C/W
°C/W
JA
MSOP-8
θ
JA
(4)
DFN-8 (3mm × 3mm)
θ
JA
θ
20
20
JP
(4)
OPA2211
SO-8 PowerPAD
θ
θ
52
2
52
2
°C/W
°C/W
°C/W
°C/W
JA
θ
JP
(4)
DFN-8 (3mm × 3mm)
65
10
65
10
JA
θ
JP
(2) When disabled, the output assumes a high-impedance state.
(3) See Typical Characteristic graphs, Figure 41 through Figure 43.
(4) Typical θJA specification is based on the use of a high-k board.
Copyright © 2006–2009, Texas Instruments Incorporated
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OPA211
OPA2211
SBOS377G–OCTOBER 2006–REVISED MAY 2009...................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
INPUT VOLTAGE NOISE DENSITY
vs FREQUENCY
INPUT CURRENT NOISE DENSITY
vs FREQUENCY
100
10
1
100
10
1
0.1
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 1.
Figure 2.
THD+N RATIO vs OUTPUT VOLTAGE AMPLITUDE
THD+N RATIO vs FREQUENCY
0.1
-60
0.001
-100
VS = ±15V
VOUT = 3VRMS
0.01
-80
Measurement BW = 80kHz
G = 11
0.001
0.0001
-100
-120
-140
-160
0.0001
0.00001
0.001
-120
-140
-100
-120
-140
G = 11
RL = 600W
G = -1
G = 1
G = 1
RL = 600W
VS = ±15V
RL = 600W
1kHz Signal
RL = 5kW
0.00001
0.000001
Measurement BW = 80kHz
G = -1
0.01 0.1
1
10
100
10
100
1k
10k 20k
Output Voltage Amplitude (VRMS
)
Frequency (Hz)
Figure 3.
THD+N RATIO vs FREQUENCY
Figure 4.
CHANNEL SEPARATION vs FREQUENCY
-80
-90
VS = ±15V
VS = ±15V
VOUT = 3VRMS
VIN = 3.5VRMS
G = 1
Measurement BW > 500kHz
-100
-110
-120
-130
-140
-150
-160
-170
-180
RL = 600W
G = 11
RL = 600W
0.0001
RL = 2kW
G = -1
G = 1
RL = 600W
RL = 5kW
RL = 5kW
0.00001
10
100
1k
Frequency (Hz)
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Figure 6.
Figure 5.
6
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Product Folder Link(s): OPA211 OPA2211
OPA211
OPA2211
www.ti.com ...................................................................................................................................................... SBOS377G–OCTOBER 2006–REVISED MAY 2009
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY (Referred to Input)
0.1Hz TO 10Hz NOISE
160
140
120
100
80
-PSRR
+PSRR
60
40
20
0
Time (1s/div)
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
Figure 7.
Figure 8.
COMMON-MODE REJECTION RATIO
vs FREQUENCY
OPEN-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
140
120
100
80
10k
1k
100
60
10
1
40
20
0
0.1
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 9.
Figure 10.
GAIN AND PHASE vs FREQUENCY
NORMALIZED OPEN-LOOP GAIN vs TEMPERATURE
140
120
100
80
180
5
RL = 10kW
4
3
135
90
45
0
Phase
2
300mV Swing From Rails
200mV Swing From Rails
1
60
0
-1
-2
-3
-4
-5
40
Gain
20
0
-20
100
1k
10k
100k
1M
10M
100M
-75 -50 -25
0
25 50 75 100 125 150 175 200
Frequency (Hz)
Temperature (°C)
Figure 11.
Figure 12.
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OPA2211
SBOS377G–OCTOBER 2006–REVISED MAY 2009...................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 13.
Figure 14.
IB AND IOS CURRENT vs TEMPERATURE
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
200
150
100
50
2000
1500
1000
500
+IB
IOS
0
0
-50
-100
-150
-200
-500
-1000
-1500
-2000
-IB
-50
-25
0
25
50
75
100
125
150
(V-)+1.0 (V-)+1.5 (V-)+2.0
(V+)-1.5 (V+)-1.0 (V+)-0.5
Ambient Temperature (°C)
VCM (V)
Figure 15.
Figure 16.
VOS WARMUP
INPUT OFFSET CURRENT vs SUPPLY VOLTAGE
12
10
8
100
80
20 Typical Units Shown
5 Typical Units Shown
60
6
40
4
20
2
0
0
-2
-4
-6
-8
-10
-12
-20
-40
-60
-80
-100
0
10
20
30
40
50
60
2.25
4
6
8
10
12
14
16
18
Time (s)
VS (±V)
Figure 17.
Figure 18.
8
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OPA2211
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
INPUT OFFSET CURRENT vs COMMON-MODE VOLTAGE
100
VS = 36V
INPUT BIAS CURRENT vs SUPPLY VOLTAGE
150
100
50
3 Typical Units Shown
75
50
3 Typical Units Shown
Unit 1
Unit 2
25
0
0
Unit 3
-25
-50
-75
-100
-50
-100
-150
Common-Mode Range
-IB
+IB
1
5
10
15
20
25
30
35
2.25
4
6
8
10
12
14
16
18
VCM (V)
VS (±V)
Figure 19.
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
Figure 20.
QUIESCENT CURRENT vs TEMPERATURE
6
5
4
3
2
1
0
150
-IB
VS = 36V
3 Typical Units Shown
+IB
100
50
Unit 1
Unit 2
0
-50
-100
-150
Unit 3
Common-Mode Range
-75 -50 -25
0
25 50 75 100 125 150 175 200
Temperature (°C)
1
5
10
15
20
25
30
35
VCM (V)
Figure 21.
Figure 22.
QUIESCENT CURRENT vs
SUPPLY VOLTAGE
NORMALIZED QUIESCENT CURRENT
vs TIME
0.05
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
Average of 10 Typical Units
0
60 120 180 240 300 360 420 480 540 600
Time (s)
0
4
8
12
16
20
24
28
32
36
VS (V)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
SHORT-CIRCUIT CURRENT
vs TEMPERATURE
SMALL-SIGNAL STEP RESPONSE
(100mV)
60
50
G = -1
CL = 10pF
40
30
Sourcing
CF
20
5.6pF
10
RI
RF
0
604W
604W
-10
-20
-30
-40
-50
-60
+18V
OPA211
-18V
CL
Sinking
Time (0.1ms/div)
-75 -50 -25
0
25 50 75 100 125 150 175 200
Temperature (°C)
Figure 25.
Figure 26.
SMALL-SIGNAL STEP RESPONSE
(100mV)
SMALL-SIGNAL STEP RESPONSE
(100mV)
G = +1
RL = 600W
G = -1
CL = 100pF
CL = 10pF
CF
5.6pF
+18V
OPA211
-18V
RI
RF
604W
604W
+18V
OPA211
-18V
RL
CL
CL
Time (0.1ms/div)
Time (0.1ms/div)
Figure 27.
Figure 28.
SMALL-SIGNAL STEP RESPONSE
(100mV)
SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD (100mV Output Step)
60
50
40
30
20
10
0
G = +1
RL = 600W
G = +1
CL = 100pF
G = -1
+18V
OPA211
-18V
G = 10
RL
CL
Time (0.1ms/div)
0
200
400
600
800
1000 1200 1400
Capacitive Load (pF)
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
G = +1
CL = 100pF
G = -1
CL = 100pF
RL = 600W
RF = 0W
RL = 600W
RF = 100W
Note: See the
Applications Information
section, Input Protection.
Time (0.5ms/div)
Time (0.5ms/div)
Figure 31.
Figure 32.
LARGE-SIGNAL POSITIVE SETTLING TIME
(10VPP, CL = 100pF)
LARGE-SIGNAL POSITIVE SETTLING TIME
(10VPP, CL = 10pF)
1.0
0.8
0.010
1.0
0.8
0.010
0.008
0.006
0.004
0.002
0
0.008
0.006
0.004
0.002
0
0.6
0.6
0.4
0.4
16-Bit Settling
16-Bit Settling
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.002
-0.004
-0.006
-0.008
-0.010
-0.2
-0.4
-0.6
-0.8
-1.0
-0.002
-0.004
-0.006
-0.008
-0.010
(±1/2 LSB = ±0.00075%)
(±1/2 LSB = ±0.00075%)
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
Figure 33.
Figure 34.
LARGE-SIGNAL NEGATIVE SETTLING TIME
(10VPP, CL = 100pF)
LARGE-SIGNAL NEGATIVE SETTLING TIME
(10VPP, CL = 10pF)
1.0
0.8
1.0
0.8
0.010
0.010
0.008
0.006
0.004
0.002
0
0.008
0.006
0.004
0.002
0
0.6
0.6
0.4
0.4
16-Bit Settling
16-Bit Settling
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.002
-0.004
-0.006
-0.008
-0.010
-0.2
-0.4
-0.6
-0.8
-1.0
-0.002
-0.004
-0.006
-0.008
-0.010
(±1/2 LSB = ±0.00075%)
(±1/2 LSB = ±0.00075%)
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
NEGATIVE OVERLOAD RECOVERY
POSITIVE OVERLOAD RECOVERY
G = -10
G = -10
VIN
10kW
VOUT
1kW
0V
VOUT
OPA211
VIN
10kW
1kW
VOUT
OPA211
VIN
0V
VOUT
VIN
Time (0.5ms/div)
Time (0.5ms/div)
Figure 37.
Figure 38.
OUTPUT VOLTAGE vs OUTPUT CURRENT
NO PHASE REVERSAL
20
15
0°C
Output
+85°C
+125°C
-55°C
10
5
+125°C
0
+150°C
0°C
-5
+18V
OPA211
-10
-15
-20
Output
+85°C
37VPP
-18V
(±18.5V)
0.5ms/div
0
10
20
30
40
50
60
70
IOUT (mA)
Figure 39.
TURN-OFF TRANSIENT
Figure 40.
TURN-ON TRANSIENT
20
15
20
15
Shutdown Signal
10
10
Output Signal
5
5
0
0
Output Signal
-5
-5
-10
-15
-20
-10
-15
-20
Shutdown Signal
VS = ±15V
VS = ±15V
Time (2ms/div)
Time (2ms/div)
Figure 41.
Figure 42.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
TURN-ON/TURN-OFF TRANSIENT
20
15
1.6
Shutdown Signal
1.2
10
0.8
5
0.4
0
0
Output
-5
-0.4
-0.8
-1.2
-1.6
-10
-15
-20
VS = ±15V
Time (100ms/div)
Figure 43.
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APPLICATION INFORMATION
negative output voltage swing. With the OPA211
The OPA211 and OPA2211 are unity-gain stable,
series, power-supply voltages do not need to be
precision op amps with very low noise. Applications
equal. For example, the positive supply could be set
with noisy or high-impedance power supplies require
to +25V with the negative supply at –5V or
decoupling capacitors close to the device pins. In
vice-versa.
most cases, 0.1µF capacitors are adequate.
Figure 44 shows a simplified schematic of the
OPA211. This die uses a SiGe bipolar process and
contains 180 transistors.
The common-mode voltage must be maintained
within the specified range. In addition, key
parameters are assured over the specified
temperature range, TA
=
–40°C to +125°C.
Parameters that vary significantly with operating
voltage or temperature are shown in the Typical
Characteristics.
OPERATING VOLTAGE
OPA211 series op amps operate from ±2.25V to
±18V
supplies
while
maintaining
excellent
performance. The OPA211 series can operate with as
little as +4.5V between the supplies and with up to
+36V between the supplies. However, some
applications do not require equal positive and
V+
Pre-Output Driver
OUT
IN+
IN-
V-
Figure 44. OPA211 Simplified Schematic
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INPUT PROTECTION
NOISE PERFORMANCE
The input terminals of the OPA211 are protected from
excessive differential voltage with back-to-back
diodes, as shown in Figure 45. In most circuit
applications, the input protection circuitry has no
consequence. However, in low-gain or G = 1 circuits,
fast ramping input signals can forward bias these
diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. This effect
is illustrated in Figure 32 of the Typical
Characteristics. If the input signal is fast enough to
create this forward bias condition, the input signal
current must be limited to 10mA or less. If the input
signal current is not inherently limited, an input series
resistor can be used to limit the signal input current.
This input series resistor degrades the low-noise
performance of the OPA211, and is discussed in the
Noise Performance section of this data sheet.
Figure 46 shows total circuit noise for varying source
impedances with the op amp in
a unity-gain
configuration (no feedback resistor network, and
therefore no additional noise contributions). Two
different op amps are shown with total circuit noise
calculated. The OPA211 has very low voltage noise,
making it ideal for low source impedances (less than
2kΩ). A similar precision op amp, the OPA227, has
somewhat higher voltage noise but lower current
noise. It provides excellent noise performance at
moderate source impedance (10kΩ to 100kΩ). Above
100kΩ, a FET-input op amp such as the OPA132
(very low current noise) may provide improved
performance. The equation in Figure 46 is shown for
the calculation of the total circuit noise. Note that en =
voltage noise, In = current noise, RS = source
impedance, k = Boltzmann’s constant = 1.38 × 10–23
J/K, and T is temperature in degrees Kelvin.
Figure 45 shows an example implementing
current-limiting feedback resistor.
a
VOLTAGE NOISE SPECTRAL DENSITY
vs SOURCE RESISTANCE
RF
10k
EO
-
1k
RS
OPA227
OPA211
OPA211
Output
100
RI
+
Input
Resistor Noise
10
EO2 = en2 + (in RS)2 + 4kTRS
Figure 45. Pulsed Operation
1
100
1k
10k
100k
1M
Source Resistance, RS (W)
SHUTDOWN
The shutdown (enable) function of the OPA211 is
referenced to the positive supply voltage of the
operational amplifier. A valid high disables the op
amp. A valid high is defined as (V+) – 0.35V of the
positive supply applied to the shutdown pin. A valid
low is defined as (V+) – 3V below the positive supply
pin. For example, with VCC at ±15V, the device is
enabled at or below 12V. The device is disabled at or
above 14.65V. If dual or split power supplies are
used, care should be taken to ensure the valid high
or valid low input signals are properly referred to the
positive supply voltage. This pin must be connected
to a valid high or low voltage or driven, and not left
open-circuit. The enable and disable times are
provided in the Typical Characteristics section (see
Figure 41 through Figure 43). When disabled, the
output assumes a high-impedance state.
Figure 46. Noise Performance of the OPA211 and
OPA227 in Unity-Gain Buffer Configuration
BASIC NOISE CALCULATIONS
Design of low-noise op amp circuits requires careful
consideration of
a
variety of possible noise
contributors: noise from the signal source, noise
generated in the op amp, and noise from the
feedback network resistors. The total noise of the
circuit is the root-sum-square combination of all noise
components.
The resistive portion of the source impedance
produces thermal noise proportional to the square
root of the resistance. This function is plotted in
Figure 46. The source impedance is usually fixed;
consequently, select the op amp and the feedback
resistors to minimize the respective contributions to
the total noise.
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Figure 46 depicts total noise for varying source
impedances with the op amp in unity-gain
Therefore, the lowest noise op amp for a given
application depends on the source impedance. For
low source impedance, current noise is negligible and
voltage noise generally dominates. For high source
impedance, current noise may dominate.
a
configuration (no feedback resistor network, and
therefore no additional noise contributions). The
operational amplifier itself contributes both a voltage
noise component and a current noise component.
The voltage noise is commonly modeled as a
time-varying component of the offset voltage. The
current noise is modeled as the time-varying
component of the input bias current and reacts with
the source resistance to create a voltage component
of noise.
Figure 47 illustrates both inverting and noninverting
op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network
resistors also contribute noise. The current noise of
the op amp reacts with the feedback resistors to
create additional noise components. The feedback
resistor values can generally be chosen to make
these noise sources negligible. The equations for
total noise are shown for both configurations.
Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
R2
R1
R2
R1
2
EO
R1
=
1 +
en2 + e12 + e22 + (inR2)2 + eS2 + (inRS)2 1 +
EO
R2
Where eS = Ö4kTRS
e1 = Ö4kTR1
´
= thermal noise of RS
1 +
R1
RS
R2
R1
´
= thermal noise of R1
VS
e2 = Ö4kTR2 = thermal noise of R2
Noise in Inverting Gain Configuration
Noise at the output:
R2
2
R2
2
EO
2
=
1 +
en2 + e12 + e22 + (inR2)2 + eS
R1
R1 + RS
EO
RS
R2
Where eS = Ö4kTRS
´
= thermal noise of RS
= thermal noise of R1
R1 + RS
VS
R2
e1 = Ö4kTR1
´
R1 + RS
e2 = Ö4kTR2 = thermal noise of R2
For the OPA211 series op amps at 1kHz, en = 1.1nV/ÖHz and in = 1.7pA/ÖHz.
Figure 47. Noise Calculation in Gain Configurations
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TOTAL HARMONIC DISTORTION
MEASUREMENTS
Audio Precision System Two distortion/noise
analyzer, which greatly simplifies such repetitive
measurements. The measurement technique can,
however, be performed with manual distortion
measurement instruments.
OPA211 series op amps have excellent distortion
characteristics. THD + Noise is below 0.0002% (G =
+1, VOUT = 3VRMS) throughout the audio frequency
range, 20Hz to 20kHz, with a 600Ω load.
ELECTRICAL OVERSTRESS
The distortion produced by OPA211 series op amps
is below the measurement limit of many commercially
available distortion analyzers. However, a special test
circuit illustrated in Figure 48 can be used to extend
the measurement capabilities.
Designers often ask questions about the capability of
an operational amplifier to withstand electrical
overstress. These questions tend to focus on the
device inputs, but may involve the supply voltage pins
or even the output pin. Each of these different pin
functions have electrical stress limits determined by
the voltage breakdown characteristics of the
particular semiconductor fabrication process and
specific circuits connected to the pin. Additionally,
internal electrostatic discharge (ESD) protection is
built into these circuits to protect them from
accidental ESD events both before and during
product assembly.
Op amp distortion can be considered an internal error
source that can be referred to the input. Figure 48
shows a circuit that causes the op amp distortion to
be 101 times greater than that normally produced by
the op amp. The addition of R3 to the otherwise
standard noninverting amplifier configuration alters
the feedback factor or noise gain of the circuit. The
closed-loop gain is unchanged, but the feedback
available for error correction is reduced by a factor of
101, thus extending the resolution by 101. Note that
the input signal and load applied to the op amp are
the same as with conventional feedback without R3.
The value of R3 should be kept small to minimize its
effect on the distortion measurements.
It is helpful to have a good understanding of this
basic ESD circuitry and its relevance to an electrical
overstress event. See Figure 49 for an illustration of
the ESD circuits contained in the OPA211 (indicated
by the dashed line area). The ESD protection circuitry
involves several current-steering diodes connected
from the input and output pins and routed back to the
internal power-supply lines, where they meet at an
absorption device internal to the operational amplifier.
This protection circuitry is intended to remain inactive
during normal circuit operation.
Validity of this technique can be verified by
duplicating measurements at high gain and/or high
frequency where the distortion is within the
measurement capability of the test equipment.
Measurements for this data sheet were made with an
R1
R2
SIG. DIST.
R1
R2
R3
GAIN GAIN
1
101
¥
1kW
10W
11W
R3
OPA211
VOUT
11
101 100W 1kW
R2
R1
Signal Gain = 1+
R2
Distortion Gain = 1+
R1 II R3
Generator
Output
Analyzer
Input
Audio Precision
System Two(1)
Load
with PC Controller
(1) For measurement bandwidth, see Figure 3, Figure 4, and Figure 5.
Figure 48. Distortion Test Circuit
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RF
+VS
+V
OPA211
RI
ESD Current-
Steering Diodes
-In
Out
Op-Amp
Core
+In
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
-V
-VS
(1) VIN = +VS + 500mV.
Figure 49. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application
An ESD event produces short duration,
a
Figure 49 depicts a specific example where the input
voltage, VIN, exceeds the positive supply voltage
(+VS) by 500mV or more. Much of what happens in
the circuit depends on the supply characteristics. If
+VS can sink the current, one of the upper input
steering diodes conducts and directs current to +VS.
Excessively high current levels can flow with
increasingly higher VIN. As a result, the datasheet
specifications recommend that applications limit the
input current to 10mA.
high-voltage pulse that is transformed into a short
duration, high-current pulse as it discharges through
a semiconductor device. The ESD protection circuits
are designed to provide a current path around the
operational amplifier core to prevent it from being
damaged. The energy absorbed by the protection
circuitry is then dissipated as heat.
When an ESD voltage develops across two or more
of the amplifier device pins, current flows through one
or more of the steering diodes. Depending on the
path that the current takes, the absorption device
may activate. The absorption device has a trigger, or
threshold voltage, that is above the normal operating
voltage of the OPA211 but below the device
breakdown voltage level. Once this threshold is
exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a
safe level.
If the supply is not capable of sinking the current, VIN
may begin sourcing current to the operational
amplifier, and then take over as the source of positive
supply voltage. The danger in this case is that the
voltage can rise to levels that exceed the operational
amplifier absolute maximum ratings. In extreme but
rare cases, the absorption device triggers on while
+VS and –VS are applied. If this event happens, a
direct current path is established between the +VS
and –VS supplies. The power dissipation of the
absorption device is quickly exceeded, and the
extreme internal heating destroys the operational
amplifier.
When the operational amplifier connects into a circuit
such as that illustrated in Figure 49, the ESD
protection components are intended to remain
inactive and not become involved in the application
circuit operation. However, circumstances may arise
where an applied voltage exceeds the operating
voltage range of a given pin. Should this condition
occur, there is a risk that some of the internal ESD
protection circuits may be biased on, and conduct
current. Any such current flow occurs through
steering diode paths and rarely involves the
absorption device.
Another common question involves what happens to
the amplifier if an input signal is applied to the input
while the power supplies +VS and/or –VS are at 0V.
Again, it depends on the supply characteristic while at
0V, or at a level below the input signal amplitude. If
the supplies appear as high impedance, then the
operational amplifier supply current may be supplied
by the input source via the current steering diodes.
This state is not a normal bias condition; the amplifier
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most likely will not operate normally. If the supplies
are low impedance, then the current through the
steering diodes can become quite high. The current
level depends on the ability of the input source to
deliver current, and any resistance in the input path.
DFN packages are physically small, and have a
smaller routing area, improved thermal performance,
and improved electrical parasitics. Additionally, the
absence of external leads eliminates bent-lead
issues.
The DFN package can be easily mounted using
standard printed circuit board (PCB) assembly
techniques. See Application Note QFN/SON PCB
Attachment (SLUA271) and Application Report Quad
Flatpack No-Lead Logic Packages (SCBA017), both
available for download at www.ti.com.
THERMAL CONSIDERATIONS
A primary issue with all semiconductor devices is
junction temperature (TJ). The most obvious
consideration is assuring that TJ never exceeds the
absolute maximum rating specified for the device.
However, addressing device thermal dissipation has
benefits beyond protecting the device from damage.
Even modest increases in junction temperature can
The exposed leadframe die pad on the bottom of
the package must be connected to V–. Soldering
the thermal pad improves heat dissipation and
enables specified device performance.
decrease
temperature-related
op
amp
errors
performance,
and
can accumulate.
Understanding the power generated by the device
within the specific application and assessing the
thermal effects on the error tolerance lead to a better
DFN LAYOUT GUIDELINES
The exposed leadframe die pad on the DFN package
should be soldered to a thermal pad on the PCB. A
mechanical drawing showing an example layout is
attached at the end of this data sheet. Refinements to
this layout may be necessary based on assembly
process requirements. Mechanical drawings located
at the end of this data sheet list the physical
dimensions for the package and pad. The five holes
in the landing pattern are optional, and are intended
for use with thermal vias that connect the leadframe
die pad to the heatsink area on the PCB.
understanding
of
system
performance
and
thermal-dissipation needs. For dual-channel products,
the worst-case power resulting from both channels
must be determined. Products with a thermal pad
(DFN and PowerPAD devices) provide the best
thermal conduction away from the junction; see the
Thermal Resistance from Junction to Pad parameter
(θJP) in the Electrical Characteristics section. The use
of packages with a thermal pad improves thermal
dissipation. The device achieves its optimal
performance through careful board and system
design that considers characteristics such as board
thickness, metal layers, component spacing, airflow,
and board orientation. Refer to these application
notes (available for download at www.ti.com) for
additional details: SZZA017A, SCBA017, and
SPRA953A. For unusual loads and signals, see
SBOA022.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests.
Even with applications that have low-power
dissipation, the exposed pad must be soldered to the
PCB to provide structural integrity and long-term
reliability.
DFN PACKAGE
The OPA211 is offered in an DFN-8 package (also
known as SON). The DFN package is a QFN
package with lead contacts on only two sides of the
bottom of the package. This leadless package
maximizes board space and enhances thermal and
electrical characteristics through an exposed pad.
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GENERAL POWERPAD DESIGN
CONSIDERATIONS
example thermal land pattern mechanical drawing
is attached to the end of this data sheet.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad area
to help dissipate the heat generated by the
OPA2211 SO-8. These additional vias may be
larger than the 13-mil diameter vias directly under
the thermal pad. They can be larger because
they are not in the thermal pad area to be
soldered; thus, wicking is not a problem.
The OPA2211 is available in a thermally-enhanced
SO-8 PowerPAD package. This package is
constructed using a downset leadframe upon which
the die is mounted, as Figure 50(a) and Figure 50(b)
illustrate. This arrangement results in the lead frame
being exposed as a thermal pad on the underside of
the package, as shown in Figure 50(c). This thermal
pad has direct thermal contact with the die; thus,
excellent thermal performance is achieved by
providing a good thermal path away from the thermal
pad.
4. Connect all holes to the internal plane that is at
the same voltage potential as the V– pin.
5. When connecting these holes to the internal
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This configuration makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the OPA2211
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
must be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either
a ground plane or other
heat-dissipating device. Soldering the PowerPAD to
the printed circuit board (PCB) is always required,
even with applications that have low power
dissipation. This technique provides the necessary
thermal and mechanical connection between the lead
frame die pad and the PCB.
PowerPAD
package
should
make
their
connection to the internal plane with a complete
connection around the entire circumference of the
plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its six holes exposed. The bottom-side
solder mask should cover the holes of the
thermal pad area. This masking prevents solder
from being pulled away from the thermal pad
area during the reflow process.
The PowerPAD must be connected to the most
negative supply voltage on the device (V–).
1. Prepare the PCB with a top-side etch pattern.
There should be etching for the leads as well as
etch for the thermal pad.
2. Place recommended holes in the area of the
thermal pad. Ideal thermal land size and thermal
via patterns for the SO-8 DDA package can be
seen in the technical brief, PowerPAD
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, simply
place the OPA2211 SO-8 IC in position and run
the chip through the solder reflow operation as
any standard surface-mount component. This
preparation results in a properly installed part.
Thermally-Enhanced
Package
(SLMA002),
available for download at www.ti.com. These
holes should be 13 mils (0,33mm) in diameter.
Keep them small, so that solder wicking through
the holes is not a problem during reflow. An
20
Submit Documentation Feedback
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): OPA211 OPA2211
OPA211
OPA2211
www.ti.com ...................................................................................................................................................... SBOS377G–OCTOBER 2006–REVISED MAY 2009
Leadframe (Copper Alloy)
IC (Silicon)
Die Attach (Epoxy)
Leadframe Die Pad
Thermal
Pad
Exposed at Base of the Package
(Copper Alloy)
Mold Compound (Plastic)
(a) Cutaway View: DDA Package (SO-8)
Thermal
Pad
Mold Compound
(Plastic)
DDA Package
(SO-8)
DRG Package
(DFN-8)
Die
(c) Bottom View
Terminal
Leadframe
(Copper Alloy)
Exposed at Base of Package
Die Attach (Epoxy)
(b) Cutaway View: DRG Package (DFN-8)
Figure 50. Views of Thermally-Enhanced SO-8 and DFN-8 Packages
Copyright © 2006–2009, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): OPA211 OPA2211
OPA211
OPA2211
SBOS377G–OCTOBER 2006–REVISED MAY 2009...................................................................................................................................................... www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November, 2008) to Revision G .......................................................................................... Page
•
•
•
Changed orderable status of OPA2211 device packages to released from product preview throughout document............ 2
Revised description of NC pin ............................................................................................................................................... 3
Added Input Offset Voltage, Input Bias Current, Open-Loop Gain, and Thermal Resistance specifications to indicate
performance for OPA2211 device ......................................................................................................................................... 4
•
•
•
•
•
•
•
•
•
•
•
•
•
Corrected Temperature Range parametric symbol location for specified and operating range specifications ..................... 5
Added footnote (4) to Electrical Characteristics table............................................................................................................ 5
Updated Figure 3 ................................................................................................................................................................... 6
Added information to legend in Figure 4................................................................................................................................ 6
Added Figure 5 ..................................................................................................................................................................... 6
Added Figure 6 ...................................................................................................................................................................... 6
Changed title of Figure 12 for clarification............................................................................................................................. 7
Corrected circuit drawing in Figure 26................................................................................................................................. 10
Corrected circuit drawing in Figure 27................................................................................................................................. 10
Changed first paragraph of Total Harmonic Distortion Measurements section................................................................... 17
Updated Figure 48 ............................................................................................................................................................... 17
Added Thermal Considerations section............................................................................................................................... 19
Added General PowerPAD Design Considerations section ................................................................................................ 20
22
Submit Documentation Feedback
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): OPA211 OPA2211
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OPA211AID
ACTIVE
SOIC
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
A
OPA211AIDG4
ACTIVE
D
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
A
OPA211AIDGKR
OPA211AIDGKRG4
OPA211AIDGKT
OPA211AIDGKTG4
OPA211AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
8
2500
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU | Call TI Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OBCQ
OBCQ
OBCQ
OBCQ
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
2500
Green (RoHS
& no Sb/Br)
OPA
211
A
OPA211AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
A
OPA211AIDRGR
OPA211AIDRGRG4
OPA211AIDRGT
OPA211AIDRGTG4
OPA211ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
DRG
DRG
DRG
DRG
D
8
8
8
8
8
8
8
1000
1000
250
250
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OBDQ
OBDQ
OBDQ
OBDQ
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
SOIC
VSSOP
VSSOP
Green (RoHS
& no Sb/Br)
OPA
211
OPA211IDGKR
OPA211IDGKT
DGK
DGK
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI Level-2-260C-1 YEAR
CU NIPDAU | Call TI Level-2-260C-1 YEAR
OBCQ
Green (RoHS
& no Sb/Br)
OBCQ
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OPA211IDR
OPA211IDRGR
OPA211IDRGT
OPA2211AIDDA
ACTIVE
SOIC
SON
SON
D
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
OPA
211
ACTIVE
ACTIVE
DRG
DRG
DDA
3000
250
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
OBDQ
Green (RoHS
& no Sb/Br)
CU NIPDAU
OBDQ
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
OPA
2211
A
OPA2211AIDDAR
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
-40 to 125
OPA
2211
A
OPA2211AIDRGR
OPA2211AIDRGT
ACTIVE
ACTIVE
SON
SON
DRG
DRG
8
8
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
OBHQ
Green (RoHS
& no Sb/Br)
OBHQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA211 :
Enhanced Product: OPA211-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA211AIDGKR
OPA211AIDGKT
OPA211AIDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
8
8
8
8
8
8
2500
250
330.0
180.0
330.0
330.0
180.0
330.0
180.0
330.0
330.0
180.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
6.4
3.3
3.3
5.3
5.3
6.4
3.3
3.3
6.4
3.4
3.4
5.2
3.3
3.3
3.4
3.4
5.2
3.3
3.3
5.2
1.4
1.4
2.1
1.1
1.1
1.4
1.4
2.1
1.1
1.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q2
Q2
Q1
Q1
Q1
Q2
Q2
Q1
2500
1000
250
OPA211AIDRGR
OPA211AIDRGT
OPA211IDGKR
OPA211IDGKT
OPA211IDR
SON
DRG
DRG
DGK
DGK
D
SON
VSSOP
VSSOP
SOIC
2500
250
2500
3000
250
OPA211IDRGR
OPA211IDRGT
OPA2211AIDDAR
SON
DRG
DRG
DDA
SON
SO
Power
PAD
2500
OPA2211AIDRGR
OPA2211AIDRGT
SON
SON
DRG
DRG
8
8
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA211AIDGKR
OPA211AIDGKT
OPA211AIDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
8
8
8
8
8
8
8
8
2500
250
367.0
210.0
367.0
367.0
210.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
185.0
367.0
367.0
185.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
2500
1000
250
OPA211AIDRGR
OPA211AIDRGT
OPA211IDGKR
OPA211IDGKT
OPA211IDR
SON
DRG
DRG
DGK
DGK
D
SON
VSSOP
VSSOP
SOIC
2500
250
2500
3000
250
OPA211IDRGR
OPA211IDRGT
OPA2211AIDDAR
OPA2211AIDRGR
OPA2211AIDRGT
SON
DRG
DRG
DDA
DRG
DRG
SON
SO PowerPAD
SON
2500
3000
250
SON
Pack Materials-Page 2
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