PTPS74801AQWDRCRQ1 [TI]
具有电源正常指示和使能功能的汽车类 1.5A、0.8V 低噪声可调节 LDO 稳压器 | DRC | 10 | -40 to 150;型号: | PTPS74801AQWDRCRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有电源正常指示和使能功能的汽车类 1.5A、0.8V 低噪声可调节 LDO 稳压器 | DRC | 10 | -40 to 150 稳压器 |
文件: | 总35页 (文件大小:1952K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
TPS748A-Q1 具有可编程软启动功能的汽车类1.5A 低压降线性稳压器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准:
TPS748A-Q1 低压降 (LDO) 线性稳压器可面向多种应
用提供易于使用的稳健型电源管理解决方案。用户可编
程软启动通过减少启动时的电容涌入电流,最大限度地
减少了输入电源上的应力。软启动具有单调性,旨在为
各类处理器和专用集成电路 (ASIC) 供电。借助使能输
入和电源正常输出,可通过外部稳压器轻松实现上电排
序。凭借全方位的灵活性,该器件可为现场可编程门阵
列(FPGA)、数字信号处理器 (DSP) 和其他具有特殊启
动要求的应用配置可满足其时序要求的解决方案。
– 温度等级1:–40°C ≤TA ≤+125°C
– HBM ESD 分类等级2
– CDM ESD 分类等级C4A
• 扩展结温(TJ) 范围:
– –40°C 至+150°C
• 输入电压范围:
– IN: VIN + VDO 至6.0V
– BIAS:VOUT + VDO(BIAS) 至6.0V
• VOUT 范围:0.8V 至3.6V
• 低压降:1.5A、VBIAS = 5V 下的典型值为60mV
• 电源正常(PG) 输出可实现电源监视或为其他电源
提供时序信号
• 线路、负载和温度范围内的精度为2%
• 可编程软启动可提供线性电压启动
• VBIAS 支持低VIN 运行,具有良好的瞬态响应
• 与≥2.2μF 的任何输出电容器一起工作时可保持
稳定
该器件还具有高精度的参考电压电路和误差放大器,可
在整个负载、线路、温度和过程范围内提供2% 精度。
该器件在使用大于或等于 2.2μF 的任何类型的电容器
时都能保持稳定运行,并具有 TJ = –40°C 至 +150°C
的额定结温范围。TPS748A-Q1 采用小型 3mm ×
3mm VSON-10 封装,可实现高度紧凑的解决方案总
尺寸。
封装信息
封装(1)
封装尺寸(2)
器件型号
• 采用小型3mm × 3mm × 1mm VSON-10 封装
TPS748A-Q1
DRC(VSON,10) 3.00mm × 3.00mm
2 应用
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸(长× 宽)为标称值,并包括引脚(如适用)。
• 远程信息处理控制单元
• 信息娱乐系统与仪表组
• 成像雷达
VIN
IN
OUT
VOUT
COUT
CIN
EN
R1
VBIAS
CBIAS
BIAS
SS
FB
TPS748A-Q1
R2
VOUT
CSS
RPG
PG
PG
GND
典型应用电路(可调节)
输出电压噪声密度与频率间的关系
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBVS425
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................16
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 21
8.3 Power Supply Recommendations.............................22
8.4 Layout....................................................................... 22
9 Device and Documentation Support............................25
9.1 接收文档更新通知..................................................... 25
9.2 支持资源....................................................................25
9.3 Trademarks...............................................................25
9.4 静电放电警告............................................................ 25
9.5 术语表....................................................................... 25
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics: IOUT = 50 mA.........................7
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
Information.................................................................... 25
10.1 Tape and Reel Information......................................26
10.2 Mechanical Data..................................................... 28
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2022) to Revision A (May 2023)
Page
• 将文档状态从预告信息 更改为量产数据 ............................................................................................................ 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS425
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5 Pin Configuration and Functions
IN
IN
1
2
3
4
5
10
9
OUT
OUT
FB
Thermal
Pad
PG
BIAS
EN
8
7
SS
6
GND
图5-1. DRC Package, 10-Pin VSON With Thermal Pad (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
BIAS
VSON
Bias input voltage for the error amplifier, reference, and internal control circuits. Use a 1-µF or
larger input capacitor for optimal performance. If IN is connected to BIAS, a 4.7-µF or larger
capacitor must be used.
4
I
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode. This pin must not be left unconnected.
EN
FB
5
8
I
I
Feedback pin. This pin is the feedback connection to the center tap of an external resistor divider
network that sets the output voltage. This pin must not be left floating.
GND
IN
6
Ground
—
1, 2
I
Input to the device. Use a 1-µF or larger input capacitor for optimal performance.
No connection. This pin can be left floating or connected to GND to allow better thermal contact
to the top-side plane.
NC
N/A
—
Regulated output voltage. A small capacitor (total typical capacitance ≥2.2 μF, ceramic) is
needed from this pin to ground to assure stability.
OUT
9, 10
O
Power-good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT
exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is
below this threshold the pin is driven to a low-impedance state. Connect a pullup resistor (10 kΩ
to 1 MΩ) from this pin to a supply of up to 6.0 V. The supply can be higher than the input voltage.
Alternatively, the PG pin can be left unconnected if output monitoring is not necessary.
PG
3
7
O
Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left
unconnected, the regulator output soft-start ramp time is typically 200 μs.
SS
—
—
Must be soldered to the ground plane for increased thermal performance. Internally connected to
ground.
Thermal pad
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English Data Sheet: SBVS425
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
6.5
UNIT
IN, BIAS
EN
6.5
PG
6.5
Voltage
SS
V
6.5
VBIAS
FB
–0.3
OUT
PG
VIN + 0.3
1.5
–0.3
0
mA
OUT
Current
Internally limited
Indefinite
Output short-circuit duration
Continuous total power dissipation, PDISS
See Thermal Information
Junction, TJ
Temperature
150
150
–40
–55
°C
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC specification Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
VOUT + 0.3
VIN
MAX
6.0
UNIT
VOUT + VDO
VIN
Input supply voltage
Enable supply voltage
BIAS supply voltage
V
V
V
(VIN
)
VEN
VBIAS
6.0
VOUT + VDO
(VBIAS)(1)
VOUT +
6.0
1.6(1)
VOUT
IOUT
COUT
CIN
Output voltage
0.8
0
3.3
1.5
V
Output current
A
Output capacitor (3)
Input capacitor (1) (2)
Bias capacitor
10
1
µF
µF
µF
nF
CBIAS
CSS
TJ
0.1
1
1
Soft-start capacitor
Operating junction temperature
10
100
150
–40
℃
(1) VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher.
(2) If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.
(3) A maximum capacitor derating of 25% is considered for minimum capacitance
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English Data Sheet: SBVS425
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6.4 Thermal Information
TPS748A-Q1
THERMAL METRIC(1)
DRC (VSON)
10 PINS
47.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
63.7
Junction-to-board thermal resistance
19.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.2
ψJT
19.4
ψJB
RθJC(bot)
3.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.5 Electrical Characteristics
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CSS = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V (4), and TJ
= –40°C to 150°C, (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT
+
VIN
Input voltage range
6.0
V
VDO
VBIAS
BIAS pin voltage range
2.7
0.796
1.0
6.0
0.804
1.75
V
V
V
VREF
Internal reference (Adj.) TA = +25°C
Rising bias supply UVLO
0.8
VBIAS(UVLO)
1.25
VBIAS(UVLO),
Bias supply UVLO
hysteresis
20
43
65
mV
HYST
Output voltage range
Accuracy (1) (5)
VIN = 5 V, IOUT = 1.5 A
VREF
3.6
V
%
ΔVOUT (ΔVIN)
±0.5
0.03
0.09
75
1.25
2.97 V ≤VBIAS ≤5.5 V, 50 mA ≤IOUT ≤1.5 A
VOUT(nom) + 0.3 ≤VIN ≤5.5 V
50 mA ≤IOUT ≤1.5 A
–1.25
Line regulation
%/V
%/A
mV
V
ΔVOUT (ΔIOUT)
VOUT
Load regulation
IOUT = 1.5 A, VBIAS –VOUT(nom) ≥3.25 V(3)
IOUT = 1.5 A, VIN = VBIAS
VDO(IN)
VDO(BIAS)
ICL
VIN dropout voltage(2)
VBIAS dropout voltage(2)
Output current limit
BIAS pin current
150
1.35
3.1
1.14
VOUT = 80% × VOUT(nom)
2.3
A
IBIAS
IOUT = 50 mA
0.67
0.9
1.1
mA
Shutdown supply current
ISHDN
IFB
15
µA
VEN ≤0.4 V, VIN = 1.1 V, VOUT = 0.8 V
(IGND
)
Feedback pin current
±0.12
69
0.22
µA
dB
dB
dB
dB
–0.22
1 kHz, IOUT = 1.5 A, VIN = 1.1 V, VOUT = 0.8 V
300 kHz, IOUT = 1.5 A, VIN = 1.1 V, VOUT = 0.8 V
1 kHz, IOUT = 1.5 A, VIN = 1.1 V, VOUT = 0.8 V
300 kHz, IOUT = 1.5 A, VIN = 1.1 V, VOUT = 0.8 V
Power-supply rejection
(VIN to VOUT
)
30
PSRR
59
Power-supply rejection
(VBIAS to VOUT
)
33
μVrms x
Vout
Vn
Output noise voltage
Minimum startup time
BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF
RLOAD for IOUT = 1.0 A, CSS = open
VSS = 0.4 V
7
170
7.5
1.2
tSTR
ISS
µs
Soft-start charging
current
µA
tSS
Soft-start time
Css = 10 nF
ms
V
VEN(hi)
VEN(lo)
VEN(hys)
Enable input high level
Enable input low level
Enable pin hysteresis
1.1
0
5.5
0.4
V
55
mV
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English Data Sheet: SBVS425
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
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6.5 Electrical Characteristics (continued)
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CSS = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V (4), and TJ
= –40°C to 150°C, (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VEN(dg)
IEN
Enable pin deglitch time
Enable pin current
PG trip threshold
17
µs
VEN = 5 V
0.1
90
0.3
µA
VIT
VOUT decreasing
85
94 %VOUT
%VOUT
VHYS
VPG(lo)
IPG(lkg)
PG trip hysteresis
PG output low voltage
PG leakage current
2.5
IPG = 1 mA (sinking), VOUT < VIT
VPG = 5.25 V, VOUT > VIT
0.125
V
0.01
0.1
µA
Operating junction
temperature
TJ
125
–40
℃
℃
Shutdown, temperature increasing
Reset, temperature decreasing
165
140
Thermal shutdown
temperature
TSD
(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 12.
(4) VBIAS = VDO_MAX(BIAS) + VOUT for VOUT ≥3.4 V
(5) The device is not tested under conditions where VIN > VOUT + 1.65 V and IOUT = 1.5 A, because the power dissipation is higher than
the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the
power dissipation limit of the package under test.
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English Data Sheet: SBVS425
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6.6 Typical Characteristics: IOUT = 50 mA
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF
(unless otherwise noted)
VOUT = 0.8 V, IOUT = 1.5 A, CBIAS = 0.1 μF, COUT = 10 μF,
VIN = 1.1 V, VOUT = 0.8 V, IOUT = 1.5 A, CBIAS = 0.1 μF,
COUT = 10 μF, VEN = VBIAS = 6 V
CSS = 10 nF, VEN = VBIAS = 6 V
图6-1. IN PSRR vs Frequency and VIN
图6-2. IN PSRR vs Frequency and CSS
VIN = 1.1 V, VOUT = 0.8 V, CBIAS = 0.1 μF, COUT = 10 μF,
VIN = 2.1 V, VOUT = 1.8 V, CBIAS = 0.1 μF, COUT = 10 μF,
CSS = 10 nF, VEN = VBIAS = 6 V
CSS = 10 nF, VEN = VBIAS = 6 V
图6-3. IN PSRR vs Frequency and IOUT for VOUT = 0.8 V
图6-4. PSRR vs Frequency and IOUT for VOUT = 1.8 V
VIN = 3.6 V, VOUT = 3.3 V, CBIAS = 0.1 μF, COUT = 10 μF,
VIN = 1.1 V, VOUT = 0.8 V, IOUT = 1.5 A, CBIAS = 0.1 μF,
CSS = 10 nF, VEN = VBIAS = 6 V
CSS = 10 nF, VEN = VBIAS = 6 V
图6-5. IN PSRR vs Frequency and IOUT for VOUT = 3.3 V
图6-6. IN PSRR vs Frequency and COUT
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6.6 Typical Characteristics: IOUT = 50 mA (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF
(unless otherwise noted)
VEN = VIN = 1.1 V, VOUT = 0.8 V, IOUT = 1.5 A, CIN = 10 μF,
VIN = 1.1 V, VOUT = 0.8 V, IOUT = 1.5 A, CIN = 10 μF,
COUT = 10 μF, CSS = 10 nF, VBIAS = 6 V
COUT = 10 μF, CSS = 10 nF, VEN = 6 V
图6-8. BIAS PSRR vs Frequency and IOUT
图6-7. BIAS PSRR vs Frequency and VBIAS
VEN = VBIAS, VIN = 1.1 V, VOUT = 0.8 V, IOUT = 1.5 A,
VEN = VBIAS, VIN = 1.1 V, VOUT = 0.8 V, CIN = 10 μF,
COUT = 10 μF, CSS = 10 nF, CBIAS = 0.1 μF
CIN = 10 μF, COUT = 10 μF, CSS = 10 nF, CBIAS = 0.1 μF
图6-9. Output Voltage Noise Density vs Frequency and VBIAS
图6-10. Output Voltage Noise Density vs Frequency and IOUT
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6.6 Typical Characteristics: IOUT = 50 mA (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF
(unless otherwise noted)
VBIAS = 5 V, VOUT = 0.8 V
VIN = 1.1 V, VOUT = 0.8 V
图6-11. IN-to-OUT Dropout Voltage vs IOUT and Temperature (TJ) 图6-12. BIAS-to-OUT Dropout Voltage vs IOUT and Temperature
(TJ)
VIN = 1.1 V, VBIAS = 5 V, VOUT = 0.8 V
VIN = 1.1 V, VBIAS = 5 V, VOUT = 0.8 V
图6-14. Load Regulation vs ≥50-mA Output Current
图6-13. Load Regulation vs 0-mA to 50-mA Output Current
VOUT = 0.8 V, VBIAS = 5 V, IOUT = 50 mA
VBIAS = 5 V, VOUT = 0.8 V, IOUT = 50 mA
图6-15. Line Regulation vs Input Voltage
图6-16. Output Voltage vs Bias Voltage
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6.6 Typical Characteristics: IOUT = 50 mA (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF
(unless otherwise noted)
VOUT = 0.8 V, VBIAS = 5.0 V
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 50 mA
图6-18. IN Pin Quiescent Current vs Output Current
图6-17. IN Pin Quiescent Current vs Input Voltage
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 1.5 A
VIN = 1.1 V, VOUT = 0.8 V, VBIAS = 5.0 V
图6-19. BIAS Pin Quiescent Current vs Input Voltage
图6-20. BIAS Pin Quiescent Current vs Output Current
VBIAS = 5 V, VEN = 0 V
VIN = 1.1 V, VEN = 0 V
图6-21. Shutdown Current (GND Pin) vs Input Voltage
图6-22. Shutdown Current (GND Pin) vs Bias Voltage
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6.6 Typical Characteristics: IOUT = 50 mA (continued)
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF
(unless otherwise noted)
图6-23. Current Limit vs Output Voltage
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7 Detailed Description
7.1 Overview
The TPS748A-Q1 is a low-input, low-output (LILO), low-quiescent-current linear regulator optimized to support
excellent transient performance. This regulator uses a low-current bias rail to power all internal control circuitry,
allowing the n-type field effect transistor (NMOS) pass transistor to regulate very-low input and output voltages.
Using an NMOS pass transistor offers several critical advantages for many applications. Unlike a p-channel
metal-oxide-semiconductor field effect transistor (PMOS) topology device, the output capacitor has little effect on
loop stability. This architecture allows the TPS748A-Q1 to be stable with any ceramic capacitor 10 μF or
greater. Transient response is also superior to PMOS topologies, particularly for low VIN applications.
The TPS748A-Q1 features a programmable, voltage-controlled, soft-start circuit that provides a smooth,
monotonic start-up and limits start-up inrush currents that can be caused by large capacitive loads. An enable
(EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low
VIN and VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the
multiple supply voltages often required by processor-intensive systems.
7.2 Functional Block Diagram
OUT
VOUT
IN
500 ꢀ
BIAS
UVLO
Thermal &
Current
Limit
7.5 µA
R1
SS
CSS
Soft-Start
Discharge
0.8-V
Reference
FB
120 ꢀ
Hysteresis
and Deglitch
R2
EN
VOUT
œ
Delay(B)
+
10 kꢀ
0.9 x
VREF
V
PG
GND
7.3 Feature Description
7.3.1 Enable and Shutdown
The enable (EN) pin is active high and compatible with standard digital-signaling levels. Setting VEN below 0.4 V
turns the regulator off, and setting VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable
circuitry has hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration
allows the device to be enabled by connecting the output of another supply to the EN pin. The enable circuitry
typically has 70 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in
the VEN signal.
The enable threshold is typically 0.75 V and varies with temperature and process variations. Temperature
variation is approximately –1.2 mV/°C; process variation accounts for most of the remaining variation to the 0.4-
V and 1.1-V limits. If precise turn-on timing is required, a fast rise-time signal must be used.
If not used, EN can be connected to BIAS. Place the connection as close as possible to the bias capacitor.
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7.3.2 Active Discharge
The TPS748A-Q1 has an internal active pulldown circuits on the OUT pin.
Each active discharge function uses an internal metal-oxide-semiconductor field-effect transistor (MOSFET) that
connects a resistor (RPULLDOWN) to ground when the low-dropout resistor (LDO) is disabled in order to actively
discharge the output voltage. The active discharge circuit is activated when the device is disabled by driving EN
to logic low, when the voltage at IN or BIAS is below the UVLO threshold, or when the regulator is in thermal
shutdown.
The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the pulldown resistor.
The first active pulldown circuit connects the output to GND through a 600-Ω resistor when the device is
disabled.
The second circuit connects FB to GND through a 120-Ω resistor when the device is disabled. This resistor
discharges the FB pin. 方程式 1 calculates the output capacitor discharge time constant when OUT is shorted to
FB, or when the output voltage is set to 0.65 V.
τOUT = (600 || 120 × RL / (600 || 120 + RL) × COUT
(1)
If the LDO is set to an output voltage greater than 0.65 V, a resistor divider network is in place and minimizes the
FB pin pulldown. 方程式2 and 方程式3 calculate the time constants set by these discharge resistors.
RDISCHARGE = (120 || R2) + R1
(2)
(3)
τOUT = RDISCHARGE × RL / (RDISCHARGE + RL) × COUT
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input and can cause damage to
the device. Limit reverse current to no more than 5% of the device-rated current.
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7.3.3 Power-Good Output (PG)
The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals
when the output nears the nominal value. PG can be used to signal other devices in a system when the output
voltage is near, at, or above the set output voltage (VOUT(nom)). 图7-1 shows a simplified schematic.
The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active
high. The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.
Using a large feed-forward capacitor (CFF) delays the output voltage and, because the PG circuit monitors the
FB pin, the PG signal can indicate a false positive.
VPG
VBG
VIN
œ
VFB
+
GND
GND
UVLOBIAS
EN
GND
图7-1. Simplified PG Circuit
7.3.4 Internal Current Limit
The device has an internal current-limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a
brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL). When
the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current when the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK is approximately 60% × VOUT(nom)
.
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The output voltage is not regulated when the device is in current limit. When a current-limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in a brick-wall current
limit, the pass transistor dissipates power [(VIN –VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. When the device sufficiently cools down, the internal thermal shutdown circuit turns the
device back on. If the output current fault condition continues, the device cycles between current limit and
thermal shutdown. For more information on current limits, see the Know Your Limits application note. 图 7-2
shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0 V
IOUT
IRATED
0 mA
ISC
ICL
图7-2. Foldback Current Limit
7.3.5 Thermal Shutdown Protection (TSD
)
The internal thermal shutdown protection circuit disables the output when the thermal junction temperature (TJ )
of the pass transistor rises to the thermal shutdown temperature threshold, TSD(shutdown) (typical). The thermal
shutdown circuit hysteresis makes sure that the LDO resets (turns on) when the temperature falls to
TSD(reset) (typical)
.
The thermal time constant of the semiconductor die is fairly short; thus, the device can cycle on and off when
thermal shutdown is reached until the power dissipation is reduced. Power dissipation during start up can be
high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed operational
specifications. Although the internal protection circuitry is designed to protect against thermal overload
conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the regulator into
thermal shutdown, or above the maximum recommended junction temperature, reduces long-term reliability.
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7.4 Device Functional Modes
表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table
for parameter values.
表7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VBIAS
VEN
IOUT
TJ
VIN ≥VOUT (nom)
VDO(IN) and VIN ≥
+
TJ < TSD for
shutdown
V
BIAS ≥VOUT +
VDO(BIAS)
Normal mode
Dropout mode
IOUT < ICL
VEN ≥VHI(EN)
VIN(min)
VIN(min) < VIN < VOUT
(nom) + VDO(IN)
TJ < TSD for
shutdown
VBIAS < VOUT + VDO(BIAS)
VEN > VHI(EN)
IOUT < ICL
Disabled mode
(any true condition
disables the device)
TJ ≥TSD for
shutdown
VIN < VUVLO(IN)
VBIAS < VBIAS(UVLO)
VEN < VLO(EN)
—
7.4.1 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO(IN)
)
• The bias voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO(BIAS)
• The output current is less than the current limit (IOUT < ICL)
)
• The device junction temperature is less than the thermal shutdown temperature ( TJ < TSD(shutdown)
)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. Similarly, if the bias voltage is
lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for
normal operation, the device operates in dropout mode as well. In this mode, the output voltage tracks the input
voltage. During this mode, the transient performance of the device becomes significantly degraded because the
pass transistor is in the ohmic or triode region, and functions as a switch. Line or load transients in dropout can
result in large output voltage deviations.
When the device is in a steady dropout state, defined as when the device is in dropout (VIN < VOUT + VDO(IN) or
VBIAS < VOUT + VDO(BIAS) directly after being in normal regulation state, but not during start up), the pass
transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or
equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO(IN)), the output voltage can
overshoot for a short time when the device pulls the pass transistor back into the linear region.
7.4.3 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than VIL(EN) (see the
Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown,
and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.
The device is disabled under the following conditions:
• The input or bias voltages are below the respective minimum specifications
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold
• The device junction temperature is greater than the thermal shutdown temperature
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS748A-Q1 is a low-input, low-output (LILO), low-dropout regulator (LDO) that features soft-start
capability. This regulator uses a low-current bias input to power all internal control circuitry, allowing the NMOS
pass transistor to regulate very low input and output voltages.
Using an NMOS pass transistor offers several critical advantages for many applications. Unlike a PMOS
topology device, the output capacitor has little effect on loop stability. This architecture allows stability with
ceramic capacitors of 10 μF or greater. Transient response is also superior to PMOS topologies, particularly for
low VIN applications.
A programmable voltage-controlled, soft-start circuit provides a smooth, monotonic start-up and limits start-up
inrush currents that can be caused by large capacitive loads. An enable (EN) pin with hysteresis and deglitch
allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for
inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required
by processor-intensive systems.
8.1.1 Input, Output, and Bias Capacitor Requirements
The device is designed to be stable for ceramic capacitor of values ≥ 10 μF. The device is also stable with
multiple capacitors in parallel, which can be of any type or value.
The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To
counteract any inductance in the input, the minimum recommended capacitor for VIN is 1 μF and the minimum
recommended capacitor for VBIAS is 0.1 µF. If VIN and VBIAS are connected to the same supply, the
recommended minimum capacitor for VBIAS is 4.7 μF. Use good quality, low equivalent series resistance (ESR)
and equivalent series inductance (ESL) capacitors on the input; ceramic X5R and X7R capacitors are preferred.
Place these capacitors as close the pins as possible for optimum performance.
Low ESR and ESL capacitors improve high-frequency PSRR.
8.1.2 Dropout Voltage
The TPS748A-Q1 offers very low dropout performance, making the device designed for high-current, low VIN
and low VOUT applications. The low dropout allows the device to be used in place of a dc/dc converter and still
achieve good efficiency. 方程式4 provides a quick estimate of the efficiency.
V
OUT ´ IOUT
VOUT
VIN
at IOUT >> IQ
»
Efficiency »
VIN ´ (IIN + IQ)
(4)
This efficiency provides designers with the power architecture for applications to achieve the smallest, simplest,
and lowest cost solutions.
For this architecture, there are two different specifications for dropout voltage. The first specification (see 图
6-11 ) is referred to as VIN dropout and is used when an external bias voltage is applied to achieve low dropout.
This specification assumes that VBIAS is at least 2.8 V above VOUT, which is the case for VBIAS when powered by
a 5.0-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT + 2.8 V, the VIN dropout is less
than specified.
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备注
2.8 V is a test condition of this device and can be adjusted by referring to the Electrical Characteristics
table.
The second specification (illustrated in 图6-12 ) is referred to as VBIAS dropout and applies to applications where
IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias
voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because
VBIAS provides the gate drive to the pass transistor; therefore, VBIAS must be 1.9 V above VOUT. Because of this
usage, having IN and BIAS tied together become a highly inefficient solution that can consume large amounts of
power. Pay attention not to exceed the power rating of the device package.
8.1.3 Output Noise
The TPS748A-Q1 provides low output noise when a soft-start capacitor is used. When the device reaches the
end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 10-nF,
soft-start capacitor, the output noise is reduced by half and is typically 7.1 μVRMS for a 0.8-V output (10 Hz to
100 kHz). Increasing CSS has no effect on noise. Because most of the output noise is generated by the internal
reference, the noise is a function of the set output voltage. 方程式 5 gives the RMS noise with a 10-nF, soft-start
capacitor:
ꢀV
≈
∆
∆
«
’
÷
÷
◊
RMS
V
V ( ꢀVRMS ) = 7.1∂
∂VOUT (V)
N
(5)
The low output noise makes this LDO a good choice for powering transceivers, phase-locked loops (PLLs), or
other noise-sensitive circuitry.
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8.1.4 Estimating Junction Temperature
By using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature
can be estimated with corresponding formulas (given in 方程式 6). For backwards compatibility, an older θJC(top)
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(6)
where:
• PD is the power dissipation
• TT is the temperature at the center-top of the package
• TB is the PCB temperature measured 1 mm away from the package on the PCB surface
备注
Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared
thermometer).
For more information about measuring TT and TB, see the Using New Thermal Metrics application note,
available for download at www.ti.com.
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal
characteristics, see the Using New Thermal Metrics application note, available for download at www.ti.com. For
further information, see the Semiconductor and IC Package Thermal Metrics application note, also available on
the TI website.
8.1.5 Soft Start, Sequencing, and Inrush Current
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO
achieve threshold voltage. The soft start current is fixed for fixed output voltage versions.
Although the device does not have any sequencing requirement, following the sequencing order of BIAS, IN, and
EN makes sure that the soft start starts from zero.
图 8-1 shows an example of the device behavior when the EN pin is enabled prior to having either power supply
up. Under this condition, the output jumps from 0 V to approximately 0.3 V almost instantly when the IN voltage
is sufficient to power the circuit.
图8-1. Sequencing and Soft-Start Behavior for VOUT = 1 V
Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to
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measure because the input capacitor must be removed, which is not recommended. However, 方程式 7 can
estimate this soft-start current:
C
OUT ´ dVOUT(t)
VOUT(t)
RLOAD
IOUT(t)
=
+
dt
(7)
where:
• VOUT(t) is the instantaneous output voltage of the turn-on ramp
• dVOUT(t) / dt is the slope of the VOUT ramp
• RLOAD is the resistive load impedance
8.1.6 Power-Good Operation
For proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ.
The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the
upper limit of 100 kΩresults from the maximum leakage current at the power-good node. If the pullup resistor is
outside of this range, then the power-good signal can possibly not read a valid digital logic level.
The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO
events and at light loads, power-good does not assert because the output voltage is sustained by the output
capacitance.
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8.2 Typical Application
This section discusses the implementation of the TPS748A-Q1 to regulate a 1-A load requiring good PSRR at
high frequency with low noise. 图8-2 provides a schematic for this typical application circuit.
VIN
IN
OUT
VOUT
COUT
CIN
EN
R1
VBIAS
CBIAS
BIAS
SS
FB
TPS748A-Q1
R2
VOUT
CSS
RPG
PG
PG
GND
图8-2. Typical ADJ Voltage Application
8.2.1 Design Requirements
For this design example, use the parameters listed in 表8-1 as the input parameters.
表8-1. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
2.1 V, ±3%, provided by the dc/dc converter switching at 500 kHz
Bias voltage
5.0 V
1.8 V, ±1%
Output voltage
Output current
1.0 A (maximum), 10 mA (minimum)
< 10 µVRMS
RMS noise, 10 Hz to 100 kHz
PSRR at 500 kHz
Start-up time
> 40 dB
< 25 ms
8.2.2 Detailed Design Procedure
At 1.0 A and 1.8 VOUT, the dropout of the TPS748A-Q1 has a 105-mV maximum dropout over temperature; thus,
a 300-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and high
temperature on some devices, the TPS748A can enter dropout if both the input and output supply are beyond
the edges of the respective accuracy specification.
To satisfy the required start-up time and still maintain low noise performance, a 10-nF CSS is selected. 方程式 8
calculates this value.
tSS = (VSS × CSS) / ISS
(8)
At the 1.0-A maximum load, the internal power dissipation is 0.3 W and corresponds to a 13.3°C junction
temperature rise for the DRC package on a standard JEDEC board. With an 55°C maximum ambient
temperature, the junction temperature is at 68.3°C.
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8.2.3 Application Curve
图8-3. PSRR vs Frequency for
VOUT = 1.8 V
8.3 Power Supply Recommendations
The TPS748A-Q1 is designed to operate from an input voltage up to 6.0 V, provided the bias rail is at least 1.3 V
higher than the input supply and dropout requirements are met. The bias rail and the input supply must both
provide adequate headroom and current for the device to operate normally. Connect a low output impedance
power supply directly to the IN pin. This supply must have at least 1 μF of capacitance near the IN pin for
optimal performance. A supply with similar requirements must also be connected directly to the BIAS rail with a
separate 0.1 μF or larger capacitor. If the IN pin is tied to the BIAS pin, a minimum 4.7-μF capacitor is required
for performance. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or ferrite bead
before the input capacitor.
8.4 Layout
8.4.1 Layout Guidelines
An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on
the input of the device during load transients, the capacitance on IN and BIAS must be connected as close as
possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the
input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the
top side of R1 in 图 8-2 must be connected as close as possible to the load. If BIAS is connected to IN, connect
BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on
BIAS during transient conditions and can improve the turn-on response.
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal
pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device can
be calculated using 方程式9 and depends on input voltage and load conditions.
PD = (VIN - VOUT) ´ IOUT
(9)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the VSON (DRC) package, the primary conduction path for heat is through the exposed pad to the printed
circuit board (PCB). The pad can be connected to ground or left floating; however, the thermal pad must be
attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum
junction-to-ambient thermal resistance can be calculated using 方程式 10 and depends on the maximum
ambient temperature, maximum device junction temperature, and power dissipation of the device.
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(+125°C - TA)
RqJA
=
PD
(10)
The minimum amount of PCB copper area needed for appropriate heat sinking (which can be estimated using 图
8-4) is determined by knowing the maximum RθJA
.
140
120
100
80
DRC
RGW
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
The RθJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.
图8-4. RθJA vs Board Size
图 8-4 shows the variation of RθJA as a function of ground plane copper area in the board. This figure is
intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and is not intended
to be used to estimate actual thermal performance in real application environments.
备注
When the device is mounted on an application PCB, use ΨJT and ΨJB, as explained in the Estimating
Junction Temperature section.
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8.4.2 Layout Example
TOP View
GND Plane
CIN
COUT
IN
IN
IN
OUT
OUT
R2
PG
FB
RPG
R1
BIAS
EN
SS
Thermal vias
GND Plane
CBIAS
CSS
GND
BIAS
Represents a via
图8-5. Example Layout
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9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPS748A-Q1
English Data Sheet: SBVS425
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
10.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TPS74801AQWDRCRQ
1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS425
26
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Product Folder Links: TPS748A-Q1
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
TPS74801AQWDRCRQ1
Package Type
Package Drawing Pins
DRC 10
SPQ
Length (mm) Width (mm)
367.0 367.0
Height (mm)
VSON
3000
35.0
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS748A-Q1
English Data Sheet: SBVS425
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
10.2 Mechanical Data
PACKAGE OUTLINE
DRC0010W
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.07 MIN
(0.13)
S
C
A
S
E
C
30.0
OI
0
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
4X (0.25)
(0.2) TYP
EXPOSED
THERMAL PAD
5
6
(0.16) TYP
A
A
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.3
0.2
10X
SYMM
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
0.5
0.3
10X
4228236/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS425
28
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Product Folder Links: TPS748A-Q1
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DRC0010W
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.25)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4228236/A 12/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS748A-Q1
English Data Sheet: SBVS425
TPS748A-Q1
ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DRC0010W
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.25)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4228236/A 12/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS425
30
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Product Folder Links: TPS748A-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS74801AQWDRCRQ1
TPS74801AQWDRCRQ1
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
3000
TBD
Call TI
Call TI
-40 to 150
-40 to 150
Samples
Samples
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
74801A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2023
OTHER QUALIFIED VERSIONS OF TPS748A-Q1 :
Catalog : TPS748A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS74801AQWDRCRQ1 VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON DRC 10
SPQ
Length (mm) Width (mm) Height (mm)
360.0 360.0 36.0
TPS74801AQWDRCRQ1
3000
Pack Materials-Page 2
重要声明和免责声明
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不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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