PTPS7A9601DSCR_技术文档

TPS7A96

ZHCSO36 –APRIL 2023

TPS7A96 2A 超低噪声、超高PSRR RF 稳压器

1 特性

3 说明

• 超低输出噪声：

– 0.46μV_RMS（典型值10Hz 至100kHz）

• 高电源纹波抑制(PSRR)：

TPS7A96 是一款超低噪声 (0.46µV_RMS)、低压降

(LDO) 稳压器，能够以仅 200mV 的压降提供 2A 电

流。低压降与宽带宽误差放大器相结合，可在低工作裕

量 (500mV) 和高输出电流 (1.75 A) 下实现非常高的

PSRR（1kHz 时为110dB，1MHz 时为50dB）。

– 100Hz 时为102dB

– 1 kHz 时为110 dB

– 10 kHz 时为95 dB

– 100 kHz 时为78 dB

– 在1MHz 时为50dB

该器件的输出可通过外部电阻进行调节，范围为 0V 至

5.5 V。该器件具有宽输入电压范围，支持低至1.9V 和

高达 5.7V 的工作电压。该器件具有可编程电流限制、

可编程PG 阈值和精密使能功能，从而能够在应用中进

行更好的控制。

• 整个线路、负载和温度范围内的精度：1%

• 低压降：150 mV (1 A)

• 宽输入电压范围：1.9 V 至5.7 V

• 宽输出电压范围：0 V 至5.5 V

• 并行通道，可实现更低的噪声和更高的电流

• 快速瞬态响应

该器件凭借高精度基准和宽带宽拓扑，可以轻松并联以

实现更低的噪声和更高的电流。

该器件具有1% 的输出电压精度（在线路、负载和温度

范围内）和可降低浪涌电流的软启动功能，专为敏感模

拟低压器件供电而设计。

• 精密使能和UVLO

• 可编程电流限制

• 可编程PG 阈值

• 可调启动浪涌控制

• 开漏电源正常状态(PG) 输出

• 封装：3.00mm × 3.00mm 10 引脚WSON：

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPS7A96

DSC（WSON，10） 3.00mm × 3.00mm

– JEDEC R_θJA：46.1°C/W

– EVM R_θJA：25.6°C/W

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 宏远程无线电单元(RRU)

• 室外回程单元

• 有源天线系统mMIMO (AAS)

• 超声波扫描仪

• 实验室和现场仪表

• 传感器、成像和雷达

ENABLE

R_PG

R_{FB_PG(BOTTOM)}

R_{FB_PG(TOP)}

Clock

PG

FB_PG

V_IN

IN

C_IN

OUT

SNS

VDD_VCO

C_OUT

GND

TPS7A96

V_{EN_UV}

EN_UV

NR/SS

GND

VDD

SCLK

ADC

R_NR/SS

C_NR/SS

ADC

GND

典型应用电路

与输出电压无关的超低输出噪声(10Hz –100kHz)

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS415

TPS7A96

ZHCSO36 –APRIL 2023

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................21

8 Application and Implementation..................................22

8.1 Application Information............................................. 22

8.2 Typical Application.................................................... 45

8.3 Power Supply Recommendations.............................47

8.4 Layout....................................................................... 48

9 Device and Documentation Support............................50

9.1 Device Support......................................................... 50

9.2 Documentation Support............................................ 50

9.3 接收文档更新通知..................................................... 50

9.4 支持资源....................................................................50

9.5 Trademarks...............................................................51

9.6 静电放电警告............................................................ 51

9.7 术语表....................................................................... 51

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics................................................8

7 Detailed Description......................................................17

7.1 Overview...................................................................17

7.2 Functional Block Diagram.........................................18

7.3 Feature Description...................................................18

Information.................................................................... 51

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

April 2023

*

Initial Release

2

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English Data Sheet: SBVS415

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5 Pin Configuration and Functions

IN

1

2

3

4

5

10

9

OUT

SNS

Thermal

Pad

EN_UV

PG

8

7

NR/SS

GND

FB_PG

6

Not to scale

图5-1. DSC Package, 10-Pin WSON (Top View)

Pin Functions

WSON

TYPE⁽¹⁾

DESCRIPTION

NAME

EN_UV

Precision enable and undervoltage lockout pin; see the Precision Enable and UVLOs section for

3

I

details.

Power-good feedback pin. This pin has a dual function. This pin programs the PG pin output

threshold and scales the factory-programmed current limit value specified in the Electrical

Characteristics table to either 100%, 80%, or 60%. See the Power-Good Feedback (FB_PG Pin)

and Power-Good Threshold (PG Pin) section for details.

FB_PG

5

I

GND

IN

6

G

P

Ground pin; see the Layout Guidelines section for details.

Input voltage supply pin; see the Recommended Capacitor Types section and the Recommended

Operating Conditions table for additional information.

1, 2

Output voltage set and noise-reduction pin; see the Programmable Soft-Start and Noise-

Reduction (NR/SS Pin) section for details.

NR/SS

OUT

PG

7

9, 10

4

I

O

Regulated output pin; see the Load Transient Response section for additional information.

Open-drain, power-good indicator pin for the LDO output voltage. See the Power-Good Feedback

(FB_PG Pin) and Power-Good Threshold (PG Pin) section for additional information.

Output sense pin. This pin is the input to the noninverting terminal of the error amplifier; see the

Layout Guidelines section for details.

SNS

8

I

The thermal pad is electrically connected to the GND pin; see the Layout Guidelines section for

details.

Thermal pad

G

(1) I = input, O = output, I/O = input or output, G = ground, P = power.

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English Data Sheet: SBVS415

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6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range and all voltages with respect to GND(unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

IN, PG, EN_UV

FB_PG

6.0

1.5

–0.3

Voltage

V

OUT

V_IN+ 0.3

6.0

NR/SS, SNS

OUT

Internally limited

A

Current

PG (sink current into the device)

Operating junction, T_J

Storage, T_stg

5

150

mA

–55

Temperature

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per per ANSI/ESDA/JEDEC JS-002⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

English Data Sheet: SBVS415

4

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6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

MIN

1.9

0.4

0

NOM

MAX

5.7

UNIT

V

V_IN

Input supply voltage range

Output voltage range

Output current

V_OUT

I_OUT

V_IN- V_DO

2

V

A

C_IN

Input capacitor

4.7

1

10

1000

20

µF

mΩ

nH

µF

kΩ

°C

C_OUT

C_{OUT_ESR}

Z_{OUT_ESL}

C_NR/SS

R_PG

Output capacitor

Output capacitor ESR

Total output loop impedance

Noise-reduction capacitor

Power-good pull-up resistance

Junction temperature

2

1

10

4.7

100

T_J

125

–40

6.4 Thermal Information

TPS7A96

DSC (WSON) DSC (WSON)

THERMAL METRIC⁽¹⁾

UNIT

(2)

(3)

10 PINS

46.1

35.2

19.1

0.5

10 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

25.6

°C/W

R_θJC(top)

R_θJB

-

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

11.5

-

ψ_JT

19

ψ_JB

R_θJC(bot)

3.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application

report.

(2) JEDEC standard. (2s2p)

(3) EVM thermal model using JEDEC measurement methodology, see TPS7A94EVM-046 thermal analysis.

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6.5 Electrical Characteristics

over operating temperature range (T_J= –40°C to +125°C), V_IN(NOM)= V_OUT(NOM)+ 0.5 V, V_OUT(NOM)= 3.3 V, I_OUT= 1 mA,

V_EN= 1.8 V, C_IN= C_OUT= 10 μF, C_NR/SS= 0 nF, and PG pin pulled up to V_INwith 100 kΩ ⁽⁴⁾(unless otherwise noted); typical

values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Input supply voltage range

Input supply UVLO

1.9

5.7

V

V_UVLO

V_HYS(UVLO)

V_INrising, no load

No load

1.6

53

1.7

V

Input supply UVLO hysteresis

40

mV

µA

V_IN= 1.9 V, I_OUT= 1 mA, V_OUT= 1.2 V

150

1.9 V ≤V_IN≤5.5 V, 0.4 V ≤V_OUT< 1.2 V, 1 mA ≤

1.5

1

–1.5

–1

I_NR/SS

NR/SS pin current

I

_OUT≤2A

1.9 V ≤V_IN≤5.5 V, 1.2 V ≤V_OUT≤5.1 V, 1 mA ≤

_OUT≤2A

%

I

2.1

1.5

V_NR/SS= GND, V_IN≥2.5 V, V_{FB_PG}< 0.2 V, I_OUT= 0 mA

NR/SS fast start-up charging

current

I_{FAST_SS}

V_OUT

mA

V

V_NR/SS= GND, V_IN= 1.9 V, V_{FB_PG}< 0.2 V, I_OUT= 0 mA

Output voltage range

0

5.5

2

1.9 V ≤V_IN≤5.7 V, 1.2 V ≤V_OUT≤5.1 V,

1 mA ≤I_OUT≤2 A

±0.1

±0.2

–2

Output offset voltage (V_NR/SS

V_OUT

–

V_OS

mV

)

1.9 V ≤V_IN≤5.7 V, 0.4 V ≤V_OUT< 1.2 V,

1 mA ≤I_OUT≤2 A

5

–5

0.4 V ≤V_OUT< 1.2 V, I_OUT= 1 mA,

V_IN= (V_OUT+ 0.5 V) to 5.7 V

–0.9

2

nA/V

Line regulation: ΔI_NR/SS

V_OUT= 1.2 V and V_OUT= 3.3 V, I_OUT= 1mA,

V_IN= (V_OUT+ 0.5V) to 5.7 V

ΔV_OUT(ΔVIN)

0.4 V ≤V_OUT< 1.2 V, I_OUT= 1 mA,

–4.5

2.1

V_IN= (V_OUT+ 0.5 V) to 5.7 V

µV/V

nA

Line regulation: ΔV_OS

V_OUT= 1.2 V & V_OUT= 3.3 V, I_OUT= 1 mA,

V_IN= (V_OUT+ 0.5 V) to 5.7 V

2.3

–3.6

–21

V_IN= 1.9 V, V_OUT= 1.2 V, 1 mA ≤I_OUT≤2 A

V_IN= 3.8 V, V_OUT= 3.3 V, 1 mA ≤I_OUT≤2 A

V_IN= 5.6 V, V_OUT= 5.1 V, 1 mA ≤I_OUT≤2 A

V_IN= V_OUT(NOM)+ 0.5 V, 1.2V ≤V_OUT≤5.1 V, 1 mA ≤

(1)

Load regulation: ΔI_NR/SS

ΔV_OUT(ΔIOUT)

((1))

0.03

mV

nA

Load regulation: ΔV_OS

I_OUT≤2 A

6.3

–3.3

0.033

0.013

0.4 V ≤V_NR/SS≤1.5 V, V_IN= 5.7 V, I_OUT= 1 mA

1.5 V ≤V_NR/SS≤5 V, V_IN= 5.7 V, I_OUT= 1 mA

0.4 V ≤V_NR/SS≤1.5 V, V_IN= 5.7 V, I_OUT= 1 mA

1.5 V ≤V_NR/SS≤5 V, V_IN= 5.7 V, I_OUT= 1 mA

ΔI_NR/

Change in I_NR/SSvs V_NR/SS

Change in V_OSvs V_NR/SS

SS(ΔVNR/SS)

mV

ΔV_OS(ΔVNR/SS)

1.9 V ≤V_IN< 2.0 V, I_OUT= 1 mA,

V_OUT= 99% x V_OUT(NOM)

160

215

140

160

1.9 V ≤V_IN< 2.4 V, I_OUT= 2 A,

V_OUT= 99% x V_OUT(NOM)

350

V_DO

Dropout voltage⁽²⁾

mV

V_IN≥2.0 V, I_OUT= 1 mA,

V_OUT= 99% x V_OUT(NOM)

V_IN≥2.4 V, I_OUT= 2 A,

V_OUT= 99% x V_OUT(NOM)

250

2.8

V_OUTforced at 90% of V_OUT(NOM)

,

V_IN= V_OUT(NOM)+ 200 mV or V_IN= 1.9 V whichever is

greater, V_OUT(NOM)≥1.2 V, R_PGFB-to-GND≤12.5 kΩ

(±1%)

2.4

2.6

V_OUTforced at 90% of V_OUT(NOM)

V_IN= V_OUT(NOM)+ 200 mV or V_IN= 1.9 V whichever is

greater, V_OUT(NOM)≥1.2 V, R_PGFB-to-GND= 50 kΩ (±1%)

,

I_LIM

Output current limit

A

1.92

1.44

2.07

2.24

1.68

V_OUTforced at 90% of V_OUT(NOM)

V_IN= V_OUT(NOM)+ 200 mV or V_IN= 1.9 V whichever is

greater, V_OUT(NOM)≥1.2 V, R_PGFB-to-GND= 100 kΩ (±1%)

,

1.55

5.5

Short-circuit current-limit

variation ⁽⁽³⁾⁾

V_IN= V_OUT(NOM)+ 200 mV or V_IN= 1.9 V whichever is

greater, V_OUT= 0 V

%

ΔI_SC

English Data Sheet: SBVS415

6

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6.5 Electrical Characteristics (continued)

over operating temperature range (T_J= –40°C to +125°C), V_IN(NOM)= V_OUT(NOM)+ 0.5 V, V_OUT(NOM)= 3.3 V, I_OUT= 1 mA,

V_EN= 1.8 V, C_IN= C_OUT= 10 μF, C_NR/SS= 0 nF, and PG pin pulled up to V_INwith 100 kΩ ⁽⁴⁾(unless otherwise noted); typical

values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

V_IN= 5.7 V, V_OUT= 5.1 V, I_OUT= 0.1 mA

V_IN= 1.9 V, I_OUT= 2 A, V_OUT= 1.2 V

PG = (open), V_IN= 5.7 V, V_{EN_UV}= 0.4 V

V_IN= 5.7 V, 0 V ≤V_{EN_UV}≤5.5 V

MIN

TYP

MAX

UNIT

8

15

22

I_GND

GND pin current

mA

40

49

59

I_SDN

Shutdown GND pin current

EN_UV pin current

0.1

30

µA

V

I_{EN_UV}

1

–1

V_{IH(EN_UV)}

V_{HYS(EN_UV)}

EN_UV trip point rising (turn-on) V_IN= 1.9 V, no load

1.20

1.22

150

1.25

EN_UV trip point hysteresis

PG delay time rising

V_IN= 1.9 V, no load

mV

Time from V_OUTcrossing PG threshold% to PG reaching

20% of its value

t_PGDH

1.1

ms

t_PGDL

PG delay time falling

Time from 90% of V_OUTto 80% of PG

1.9 V ≤V_IN≤5.7 V

3

0.2

6

µs

V

V_{FB_PG}

FB_PG pin trip point (rising)

FB_PG pin hysteresis

0.19

0.21

0.4

V_{HYS(FB_PG)}

mV

1.9 V ≤V_IN≤5.7 V

V_IN= 1.9 V, V_OUT< V_{FB_PG(threshold)}, I_PG= –1 mA

(current into device)

V_OL(PG)

PG pin low-level output voltage

V

I_PG(LKG)

I_{FB_PG}

PG pin leakage current

V_IN= 5.7 V, V_OUT> V_{FB_PG(threshold)}, V_PG= 5.5 V

V_IN= 5.7 V, V_{FB_PG}= 0.2 V

1

µA

nA

FB_PG pin leakage current

100

–100

f = 1 MHz, V_IN= 3.8 V, V_OUT(NOM)= 3.3 V,

I_OUT= 750 mA, C_NR/SS= 4.7 µF

PSRR

Power-supply ripple rejection

Output noise voltage

51

0.46

0.835

6.6

dB

BW = 10 Hz to 100 kHz, 1.9 V ≤V_IN≤5.7 V,

V_OUT(NOM)= 1.2 V, I_OUT= 2.0 A, C_NR/SS= 4.7 µF

V_n

µV_RMS

BW = 10 Hz to 100 kHz, V_IN= 2 V, V_OUT(NOM)= 0.8 V,

I_OUT= 2.0 A, C_NR/SS= 4.7 µF

f = 100 Hz, 1.9 V ≤V_IN≤5.7 V, V_OUT(NOM)= 1.2 V,

I_OUT= 1.0 A, C_NR/SS= 4.7 µF

f = 1 kHz, 1.9 V ≤V_IN≤5.7 V, V_OUT(NOM)= 1.2 V,

I_OUT= 1.0 A, C_NR/SS= 4.7 µF

Noise spectral density

1.3

nV/√Hz

f = 10 kHz, 1.9 V ≤V_IN≤5.7 V, V_OUT(NOM)= 1.2 V,

I_OUT= 1.0 A, C_NR/SS= 4.7 µF

1.1

NRSS active discharge

resistance

R_{PULLDOWN_NRSS}

V_IN= 1.9 V, V_{EN_UV}= GND

15

Ω

Output active discharge

resistance

R_PULLDOWN

195

175

160

TSD(shutdown) Thermal shutdown temperature Shutdown, temperature increasing

Thermal shutdown reset

°C

TSD(reset)

Reset, temperature decreasing

temperature

(1) The device is not tested under conditions where V_IN> V_OUT(NOM)+ 2.5 V and I_OUT= 1 A because the junction temperature is higher

than +125°C. Also, this accuracy specification does not apply on any application condition that exceeds the maximum junction

temperature.

(2) Measured when output voltage drops 1% below targeted value.

(3) Brick-wall current limit: I_{CL_%}= (I_SC- I_{CL_@0.9xVOUT}) / I_{CL_@0.9xVOUT}x 100.

(4) Additional information on setting the PG pullup resistor can be found in the application section.

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6.6 Typical Characteristics

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

V_IN= 1.7 V

V_IN= 3.8 V

图6-1. PSRR vs Frequency and I_OUTfor V_OUT= 1.2 V

图6-2. PSRR vs Frequency and I_OUTfor V_OUT= 3.3 V

C_NR/SS= 4.7 μF (10 Hz–100 kHz)

图6-3. Output Voltage Noise Density vs Frequency for I_OUTand 图6-4. Output Voltage Noise Density vs Frequency for I_OUTand

V_OUT= 1.2 V

V_OUT= 3.3 V

I_OUT= 0 mA (10 Hz–100 kHz)

V_IN= 1.7 V, SR = 1 A/μs

图6-5. Output Voltage Noise Density vs Frequency and I_OUTfor

图6-6. Load Transient Response for

V_OUT= 3.3 V

V_OUT= 1.2 V, I_OUT= 100 mA to 500 mA

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

V_IN= 1.7 V, SR = 1 A/μs

V_IN= 3.8 V, SR = 1 A/μs

图6-7. Load Transient Response for

图6-8. Load Transient Response for

V_OUT= 1.2 V, I_OUT= 100 mA to 1 A

V_OUT= 3.3 V, I_OUT= 100 mA to 500 mA

V_IN= 3.8 V, SR = 1 A/μs

V_IN= 5.7 V, SR = 1 A/μs

图6-9. Load Transient Response for

图6-10. Load Transient Response for

V_OUT= 3.3 V, I_OUT= 100 mA to 1 A

V_OUT= 5.2 V, I_OUT= 100 mA to 500 mA

V_IN= 5.7 V, SR = 1 A/μs

图6-12. Line Transient Response for V_OUT= 1.2 V, I_OUT= 500 mA

图6-11. Load Transient Response for

V_OUT= 5.2 V, I_OUT= 100 mA to 1 A

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

图6-13. Line Transient Response for V_OUT= 1.2 V,

图6-14. Line Transient Response for V_OUT= 3.3 V,

I_OUT= 1 A

I_OUT= 500 mA

V_OUT= 3.3 V

图6-15. Line Transient Response for V_OUT= 3.3 V, I_OUT= 1 A

图6-16. Start-Up Waveform for I_OUT= 500 mA

V_OUT= 3.3 V

图6-17. Start-Up Waveform for I_OUT= 1 A

图6-18. Shutdown Waveform for UVLO_(IN)

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

V_OUT= 3.3 V

I_OUT= 0 mA, V_IN= 3.8 V, V_OUT= 3.3 V

图6-19. Shutdown Waveform With EN

图6-20. Inrush Current for C_NR/SS= 1.0 μF

I_OUT= 0 mA, V_IN= 3.8 V, V_OUT= 3.3 V

图6-21. Inrush Current for C_NR/SS= 2.2 μF

图6-22. Inrush Current for C_NR/SS= 4.7 μF

I_OUT= 0 mA, V_IN= 3.8 V, V_OUT= 3.3 V

V_IN= 5.7 V

图6-23. Inrush Current for C_NR/SS= 10 μF

图6-24. I_NR/SSDistribution

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

V_IN= 5.7 V, V_OUT= 5.1 V

图6-25. V_OSDistribution

图6-26. I_NR/SSLine Regulation

I_OUT= 0 mA

图6-27. V_OSLine Regulation

图6-28. I_NR/SSvs V_NR/SSand Temperature

图6-29. V_OSvs V_NR/SSand Temperature for I_OUT

图6-30. V_OSvs V_INand Temperature for V_OUT= 1.2 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

图6-31. I_NR/SSvs V_INand Temperature for V_OUT= 1.8 V

图6-32. V_OSvs V_INand Temperature for V_OUT= 1.8 V

图6-33. I_NR/SSvs V_INand Temperature for V_OUT= 3.3 V

图6-34. V_OSvs V_INand Temperature for V_OUT= 3.3 V

图6-35. I_NR/SSvs V_INand Temperature for V_OUT= 5.1 V

图6-36. V_OSvs V_INand Temperature for V_OUT= 5.1 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

图6-37. I_NR/SSvs Temperature for V_{IN_Min}, V_OpHr= 0.2 V

图6-38. V_OSvs Temperature for V_{IN_Min}, V_OpHr= 0.2 V

V_IN= 5.7 V

图6-39. I_NR/SSFast-Start vs V_INand Temperature

图6-40. GND Pin Current vs V_NR/SSand Temperature

V_OpHr= 500 mV

I_OUT= 0 mA, V_OUT= 3.3 V

图6-41. GND Pin Current vs V_INand Temperature for

图6-42. GND Pin Current vs V_ENand Temperature for

I_OUT= 1 mA

V_IN= 1.7 V (Dropout Operation)

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

I_OUT= 0 mA, V_OUT= 3.3 V

I_OUT= 0 mA

图6-43. GND Pin Current vs V_ENand Temperature for

图6-44. UVLO_INvs Temperature

V_IN= 5.7 V

I_OUT= 0 mA

图6-45. V_ENHysteresis and Threshold vs Temperature

图6-46. EN Pin Current vs V_ENand Temperature for

V_IN= 1.7 V

I_OUT= 0 mA

图6-47. EN Pin Current vs V_ENand Temperature for

图6-48. V_{FB_PG}Hysteresis and Threshold vs Temperature

V_IN= 5.7 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.5 V, V_EN= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 10 μF, and I_OUT= 1 mA (unless otherwise

noted); typical values are at T_J= 25°C

I_OUT= 0 mA

I_PG= –1 mA, V_IN= 1.7 V, I_OUT= –1 mA

图6-49. FB_PG Pin Current vs V_INand Temperature

图6-50. V_PGLow-Level Output Voltage vs Temperature

I_OUT= 0 mA

图6-51. PG Pin Current vs V_INand Temperature

图6-52. FB_PG to PG Pin Rising and Falling Delay vs

Temperature

I_OUT= 0 mA

图6-53. NR/SS and OUT Pulldown Resistors vs Temperature

图6-54. Shutdown Current vs V_INand Temperature

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7 Detailed Description

7.1 Overview

The TPS7A96 is an ultra-low noise (0.46 μV_RMSover 10-Hz to 100-kHz bandwidth), ultra-high PSRR (> 50 dB

to 2 MHz), high-accuracy (1%), low-dropout (LDO) linear voltage regulator with an input range of 1.7 V to 5.7 V

and an output voltage range from 0 V to V_IN– V_DOand is fully specified above 0.4 V_OUT. This LDO regulator

uses innovative circuitry to achieve wide bandwidth and high loop gain, resulting in ultra-high PSRR even when

operating under very low operational headroom (V_IN– V_OUT). At a high level, the device has two main blocks

(the current reference and the unity-gain LDO buffer) and a few secondary features (such as the precision

enable, current limit, and PG pin).

The current reference is controlled by the NR/SS pin. This pin sets the output voltage with a single resistor, sets

the start-up time, and filters the noise generated by the reference and external set resistor.

The unity-gain LDO buffer is controlled by the OUT pin. The ultra-low noise does not increase with output

voltage and provides wideband PSRR. As such, the SNS pin is only used for remote sensing of the load.

The EN_UV pin sets the precision enable feature. Select the optimal input voltage at which the LDO starts at.

There are two independent UVLO voltages in this device: the internal IN rail UVLO and the EN_UV pin.

The FB_PG pin sets the current limit and power-good (PG) features. A voltage divider on this pin programs both

the current limit and the PG trip point.

An ultra-low-noise current reference (150 μA, typical) is used in conjunction with an external resistor (R_NR/SS) to

set the output voltage. This process allows the output voltage range to be set from 0.4 V to (V_IN– V_DO). To

achieve this ultra-low noise, an external capacitor C_NR/SS(typically 4.7 μF) is placed in parallel to the R_NR/SS

resistor used to set the output voltage. The unity-gain architecture provides ultra-high PSRR over a wide

frequency range without compromising load and line transients.

This regulator offers programmable current-limit, thermal protection, is fully specified from –40°C to +125°C

above 0.4 V_OUT, and is offered in a thermally efficient 10-pin, 3-mm × 3-mm WSON package.

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7.2 Functional Block Diagram

Thermal

Shutdown

UVLO

Output

overshoot

recovery

Current

Limit

IN

OUT

Prog.

Current Limit

150µA

(A)

R_PULLDOWN

Logic

œ

+

UVLO

NR/SS

Dropout

Current Limit

V_NR/SS

Logic

Output discharge

Thermal Shutdown

Logic

SNS

NR/SS discharge

Precision

EN

Band Gap

{60%, 80%, 100%} . I_{CL_NO M}

Prog. Current

Limit

FB_PG

PG

Programmable Power Good

œ

Delay^(B)

+

200mV

V

GND

A. See the R_PULLDOWNoutput active discharge resistance value in the Electrical Characteristics table.

B. See the delay value in the Electrical Characteristics table.

7.3 Feature Description

7.3.1 Output Voltage Setting and Regulation

图 7-1 illustrates a simplified regulation circuit, where the input signal (V_NR/SS) is generated by the internal

current source (I_NR/SS) and the external resistor (R_NR/SS). Because the error amplifier is always operating in

unity-gain configuration, the LDO output voltage is directly programmed by the NR/SS pin voltage (V_NR/SS). The

V_NR/SSreference voltage is generated by an internal low-noise current source driving the R_NR/SSresistor and is

designed to have very low bandwidth at the input to the error amplifier through the use of a low-pass filter

(C_NR/SS|| R_NR/SS).

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V_OUT

V_IN

I_{FAST_SS}

I_NR/SS= 150µA

Error Amplifier

driving passFET

œ

+

V_SNS

V_NR/SS

R_{PULLDOWN_NR/SS}

C_NR/SS

R_NR/SS

NR/SS discharge

GND

Logic

GND

V_OUT= I_NR/SS× R_NR/SS

.

图7-1. Simplified Regulation Circuit

This unity-gain configuration, along with the highly accurate I_NR/SSreference current, enables the device to

achieve excellent output voltage accuracy. However, the R_NR/SSaccuracy can become the limiting factor when

operating at low output voltage. The low-dropout voltage (V_DO) provides reduced thermal dissipation and

achieves robust performance. This combination of features makes this device an excellent voltage source for

powering sensitive analog low-voltage devices.

7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)

The architecture features a highly accurate, high-precision, low-noise current reference followed by a state-of-

the-art error amplifier (1.1 nV/√Hz at 10-kHz noise for V_OUT≥ 1.2 V) comparable to, if not better than, that of a

precision amplifier. The unity-gain configuration provides ultra-low noise over the entire output voltage range.

Additional noise reduction and higher output current can be achieved by placing multiple TPS7A96 LDOs in

parallel.

7.3.3 Programmable Current Limit and Power-Good Threshold

The brick-wall current limit can be programmed to either 100%, 80%, or 60% of the nominal factory-programmed

value by setting the input impedance for the FB_PG pin. Similarly, the power-good indication threshold can also

be adjusted between 85% and 95% of the nominal output voltage by changing the FB_PG resistor divider ratio;

see the Adjusting the Factory-Programmed Current Limit section for details.

7.3.4 Programmable Soft-Start (NR/SS Pin)

The device features a programmable, monotonic, voltage-controlled, soft-start circuit that uses the C_NR/SS

capacitor to minimize inrush current into the output capacitor and load during start up. This circuitry can also

reduce the start-up time for some applications that require the output voltage to reach at least 90% of the set

value for fast system start-up. See the Programmable Soft-Start and Noise-Reduction (NR/SS Pin) section for

more details.

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7.3.5 Precision Enable and UVLOs

Two independent undervoltage lockout (UVLO) voltage circuits are present. An internally set UVLO on the input

supply (IN pin) automatically disables the LDO when the input voltage reaches the minimum threshold. A

precision EN function (EN_UV pin) can also be used as a user-programmable UVLO.

• The input supply voltage UVLO circuit prevents the regulator from turning on when the input voltage is not

high enough; see the Electrical Characteristics table for more details.

• The precision enable circuit allows for a simple sequencing of multiple power supplies with a resistor divider

from another supply. This enable circuit can be used to set an external UVLO voltage at which the device is

enabled using a resistor divider on the EN_UV pin; see the Precision Enable (External UVLO) section for

more details.

7.3.6 Active Discharge

The device incorporates two internal pulldown metal-oxide semiconductor field effect transistors (MOSFETs).

The first pulldown MOSFET connects a resistor (R_PULLDOWN) from OUT to ground when the device is disabled to

actively discharge the output capacitor. The second pulldown MOSFET connects a resistor (R_{PULLDOWN_NR/SS}

)

from NR/SS to ground when the device is disabled and discharges the NR/SS capacitor. Both pulldown

MOSFETs are activated by any one or more of the following:

• Driving the EN_UV pin below the V_EN(LOW)threshold

• The IN pin voltage falling below the undervoltage lockout V_UVLOthreshold

• Having the output voltage greater than the input voltage

7.3.7 Thermal Shutdown Protection (T_SD

)

A thermal shutdown protection circuit disables the LDO when the junction temperature (T_J) of the pass transistor

rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis makes sure the device resets (turns on) when the

temperature falls to T_SD(reset)(typical). The thermal time constant of the semiconductor die is fairly short, thus the

device can cycle off and on when thermal shutdown is reached until power dissipation is reduced. Power

dissipation during start-up can be high from large V_IN– V_OUTvoltage drops across the device or from high

inrush currents charging large output capacitors.

Under some conditions, the thermal shutdown protection can disable the device before start-up completes. For

reliable operation, limit the junction temperature to the maximum listed in the Electrical Characteristics table.

Operation above this maximum temperature causes the device to exceed operational specifications. Although

the internal protection circuitry of the device is designed to protect against thermal overload conditions, this

circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or

above the maximum recommended junction temperature reduces long-term reliability.

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7.4 Device Functional Modes

表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table

for parameter values.

表7-1. Device Functional Mode Comparison

OPERATING MODE

PARAMETER

V_IN

V_{EN_UV}

I_OUT

T_J

V_IN> V_OUT(nom)+ V_DOand V_IN

V_IN(min)

>

Normal operation

Dropout operation

V_{EN_UV}> V_{IH(EN_UV)}

I_OUT< I_OUT(max)

T_J< TSD_(shutdown)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_IN< V_UVLOor

Disabled (any true

condition disables the

device)

V_IN< V_OUT+ 90 mV or

V_IN< V_NR/SS+ 20 mV

V_{EN_UV}< V_{IL(EN_UV)}

Not applicable

T_J> TSD_(shutdown)

V_IN> V_OUT(nom)+ V_DOand V_IN

V_IN(min)

>

Current-limit operation

V_{EN_UV}> V_{IH(EN_UV)}

T_J< TSD_(shutdown)

I_OUT≥I_CL(min)

7.4.1 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

• The output current is less than the current limit (I_OUT< I_CL)

)

• The device junction temperature is less than the thermal shutdown temperature (T_J< TSD_(shutdown)

)

• The voltage on the EN_UV pin has previously exceeded the V_{IH(EN_UV)}threshold voltage and has not yet

decreased to less than the V_{IL(EN_UV)}falling threshold

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

备注

While in dropout, if a heavy load transient event forces V_IN< V_OUT(NOM)+ 90 mV or V_IN< V_NR/SS

+

20 mV, the device restarts to prevent the output voltage from overshooting to protect the device and

load.

When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout

voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time while the device pulls the

pass transistor back into the linear region.

For additional information, see the Output Voltage Restart (Overshoot Prevention Circuit) section.

7.4.3 Disabled

The output of the device can be shutdown by forcing the voltage of the EN_UV pin to less than the V_{IL(EN_UV)}

threshold (see the Electrical Characteristics table). When disabled, the pass transistor is turned off, internal

circuits are shutdown, and both the NR/SS pin and OUT pin voltages are actively discharged to ground by

internal discharge circuits to ground when the IN pin voltage is higher than or equal to a diode-drop voltage.

7.4.4 Current-Limit Operation

If the output current is greater than or equal to the minimum current limit, (I_CL(Min)), then the device operates in

current-limit mode. The current limit is brick-wall scheme and is programmable with the PG_FB pin. For

additional information, see the Adjusting the Factory-Programmed Current Limit section.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement them to achieve a reliable design.

8.1.1 Output Voltage Restart (Overshoot Prevention Circuit)

Wide bandwidth linear regulators suffer from an undesirable excessive overshooting of the output voltage during

restart events that occur when the C_NR/SSand C_OUTcapacitors are not fully discharged. In this device, and as

shown in 图 8-1, this undesirable behavior is mitigated by implementing low hysteresis circuitry consisting of two

ORed comparators to detect when the input voltage is either 20 mV (typical) lower than the V_NR/SSreference

voltage or 300 mV (typical) lower than V_OUT

.

Detects if VNR/SS > VIN

+

VNR/SS

Logic

œ

+

VOUT

+

Offset = 20 mV

œ

+

VIN

Offset = 90 mV

VIN

œ

Detects if VOUT > VIN

图8-1. Overshoot Prevention Circuit

When the device is operating in dropout, transient events (such as an input voltage brownout, heavy load

transient, or short-circuit event) can force the device in a reversed bias condition where the input voltage is either

20 mV (typical) lower than the V_NR/SSreference voltage or 300 mV (typical) lower than V_OUT. The output

overshoot prevention circuit can be triggered, as shown in 图 8-2, thus forcing the device to shutdown and

restart, thereby preventing output voltage overshoot. If the device is still operating in dropout and the error

condition that triggered this circuit is still present, an additional restart can occur until these conditions are

removed or the device is no longer in dropout. The restart always occurs from a discharged state and always

has the same characteristics as the initial LDO power-up, so the start-up time, V_OUTramp rate, and V_OUT

monotonicity are all predictable.

t_brownout

t_{brownout ≥ 1.5µs}

t_{brownout ≥ 1.5µs will force LDO to restart}

V_IN

V_NR/SS

V_OUT

V_NR/SS

V_OUT

V_(UVLO)

Time

图8-2. Device Behavior in Dropout

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图8-3 and 图8-4 show examples of a soft brownout and a brownout event, respectively.

The brownout overshoot is present with higher V_INslew rates. A 1-V/μs slew rate was used in 图8-5.

图8-3. Example: Soft Brownout to V_NR/SS

图8-4. Example: Brownout

图8-5. Example: Brownout With Overshoot Recovery

The overshoot prevention circuit is implemented to provide a predictable start-up and shutdown of the device

without output overshoot if the EN_UV external UVLO is not used as described in this section. This circuit can be

prevented from triggering by:

1. Using an input supply capable of handling heavy load transients or a larger value input capacitor

2. Increasing the operating headroom between V_INand V_OUT(for example, when using a battery as an input

supply to make sure that V_INstays higher than V_OUTeven when the battery is near the full discharge state)

3. Using an input supply with a ramp rate faster than the set output voltage time constant formed by C_NR/SS||

R_NR/SS

4. Discharging the input supply slower than the discharge time formed by C_OUT|| (Load || R_PULLDOWN) or by the

C_NR/SS|| (R_NR/SS|| R_{PULLDOWN_NR/SS}

)

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8.1.2 Precision Enable (External UVLO)

The precision enable circuit is used to turn the device on and off. This circuit can be used to set an external

undervoltage lockout (UVLO) voltage (图 8-6) to turn on and off the device using a resistor divider between IN,

EN_UV, and GND.

If V_{EN_UV}≥ V_{IH(EN_UV)}, the regulator is enabled. If V_{EN_UV}≤ V_{IL(EN_UV)}, the regulator is disabled. The EN_UV

pin does not incorporate an internal pulldown resistor to GND and must not be left floating. Use the precision

enable circuit for this pin to set an external UVLO input supply voltage to turn on and off the device with a

resistor divider between IN, EN_UV, and GND.

图8-6. Precision EN Used as External UVLO

This external UVLO configuration prevents the LDO from turning on when the input supply voltage is insufficient

and places the device in dropout operation.

Using the EN_UV pin as an externally set UVLO allows simple sequencing of cascaded power supplies. An

additional benefit is that the EN_UV pin is never left floating. The EN_UV pin does not have an internal pulldown

resistor. In addition to the resistor divider, a zener diode can be needed between the EN_UV pin and ground to

comply with the absolute maximum ratings on this pin.

When V_INexceeds the targeted V_ONvoltage and the R_(BOTTOM)resistor is set, 方程式1 and 方程式2 provide the

R_(TOP)resistor value and the V_OFFvoltage at which the input voltage must drop below to disable the LDO.

R

_(TOP)≤R_(BOTTOM)× (V_ON/ V_{IH(EN_UV)}–1)

(1)

(2)

V_OFF< [1 + R_(TOP)/ R_(BOTTOM)] × (V_{IH(EN_UV)}–V_{HYS(EN_UV)}

)

where:

• V_OFFis the input voltage where the regulator shuts off

• V_ONis the voltage where the regulator turns on

Consider the EN_UV current pin when selecting the R_(TOP)and R_(BOTTOM)values.

8.1.3 Undervoltage Lockout (UVLO) Operation

The UVLO circuit, present on the IN pin, makes sure that the device remains disabled before the input supply

reaches the minimum operational voltage range, and that the device shuts down when the input supply falls too

low.

The UVLO_INcircuit has a minimum response time of several microseconds to fully assert. During this time, a

downward line transient below approximately 1.6 V causes the input supply UVLO to assert for a short time.

However, the UVLO_INcircuit can possibly not have enough stored energy to fully discharge the internal circuits

inside of the device. When the UVLO_INcircuit does not fully discharge, internal circuitry is not fully disabled.

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The effect of the downward line transient can trigger the overshoot prevention circuit and can be easily mitigated

by using the solution proposed in the Precision Enable (External UVLO) section.

图 8-7 shows the UVLO_INcircuit response to various input voltage events. This diagram can be separated into

the following regions:

• Region A: The device does not turn on until the input reaches the UVLO rising threshold.

• Region B: Normal operation with a regulated output.

• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold –UVLO hysteresis).

The output can fall out of regulation but the device is still enabled.

• Region D: Normal operation with a regulated output.

• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is re-enabled when the UVLO rising

threshold is reached by the input voltage and a normal start-up then follows.

• Region F: Normal operation followed by the input falling to the UVLO falling threshold.

• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

C

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

图8-7. Typical UVLO Operation

8.1.4 Dropout Voltage (V_DO

)

Dropout voltage refers to the minimum voltage difference between the input and output voltage (V_DO= V_IN–

V_OUT) that is required for regulation. When the input voltage (V_IN) drops to or below the maximum dropout

voltage (V_DO(Max)) for the given load current, see the Electrical Characteristics table, the device functions as a

resistive switch and does not regulate the output voltage. When the device is operating in dropout, the output

voltage tracks the input voltage. For high current, the dropout voltage (V_DO) is proportional to the output current

because the device is operating as a resistive switch. For low current, internal nodes are saturating and the

dropout plateaus to the minimum value. As mentioned in the Output Voltage Restart (Overshoot Prevention

Circuit) section, transient events such as an input voltage brownout, heavy load transient, or short-circuit event

can trigger the overshoot prevention circuit. Operating the device at or near dropout significantly degrades both

transient performance and PSRR, and can also trigger the overshoot prevention circuit. Maintaining sufficient

operating headroom (V_OpHr= V_IN– V_OUT) significantly improves the device transient performance and PSRR,

and prevents triggering the overshoot prevention circuit.

备注

For this device, the pass transistor is not the limiting dropout voltage factor. Because the reference

voltage is generated by a current source and the NR/SS resistor, and because the operating

headroom is reducing (even at low load), the internal current source (I_NR/SS) saturates faster than the

pass transistor. This behavior is described in the dropout voltage plot. Notice that the dropout does not

go to 0 V at light loads.

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8.1.5 Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)

For proper device operation, the resistor divider network input to the FB_PG pin must be connected. The FB_PG

pin must not be left floating because this pin represents an analog input to the device internal logic and the input

impedance is sampled during device start up.

The PG pin is an output indicating whether the LDO is ready to provide power. This pin is implemented using an

open-drain architecture. The FB_PG pin programs the PG pin and serves a dual purpose of programming the

PG threshold assert voltage and adjusting the current limit, I_CL.

The PG pin must use the minimum value or larger pullup resistor from PG to IN, as shown in 图 8-8, or the

external rail as listed in the Electrical Characteristics table. If PG functionality is not used, leave this pin floating

or connected to GND.

The FB_PG pin uses the parallel impedance formed by the resistor divider R_{FB_PG(TOP)}and R_{FB_PG(BOTTOM)}to

program the current limit value during LDO initialization. If this impedance is less than 12.5 kΩ, then the nominal

factory-programmed, current-limit value is selected. If the input impedance is less than 50 kΩ, but greater than

12.5 kΩ, then 80% of the nominal factory-programmed current limit is selected. If the input impedance is less

than 100 kΩ, but greater than 50 kΩ, then 60% of the nominal factory-programmed current limit is selected.

Connect the R_{FB_PG(TOP)}and R_{FB_PG(BOTTOM)}resistors as indicated in this section for proper operation of the

LDO. Do not float this pin.

When initialization is complete, the voltage divider provides the necessary feedback to the PG pin by setting the

PG assert threshold voltage.

To properly select the values of the R_{FB_PG(TOP)}and R_{FB_PG(BOTTOM)}resistors, see the Adjusting the Factory-

Programmed Current Limit section for detailed explanation and calculation.

备注

The R_{FB_PG(TOP)}and R_{FB_PG(BOTTOM)}resistor divider ratio sets the power-good assert threshold

voltage between 85% to 95% of the V_{FB_PG}voltage for 60% and 80% of the nominal factory-

programmed current limit.

If the current limit is set for 100% of the nominal factory-programmed current limit, the PG threshold

range is not limited. A PG threshold greater than 80% is common for systems where start-up inrush

current must be minimized. Lower PG thresholds can be needed in systems with fast start-up time

constraints.

Setting the PG threshold based off the V_{FB_PG}voltage sets the PG to assert when the output voltage

reaches the corresponding percentage level of V_{FB_PG}because V_{FB_PG}is a scaled version of the

output voltage.

图8-8 shows the internal circuitry for both the FB_PG and PG pins.

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VOUT

VIN

{60%, 80%, 100%} . I_{CL(NO M)}

Prog. Current

Limit

Logic

RFB_PG(TOP)

RPG

FB_PG

PG

œ

VPG

Delay

+

RFB_PG(BOTTOM)

Ref. = 200 mV

V

GND

图8-8. Programmable Power-Good Threshold Simplified Schematic

The PG pin pullup resistor value must be between 10 kΩand 100 kΩ. The lower limit of 10 kΩresults from the

maximum pulldown strength of the power-good transistor, and the upper limit of 100 kΩ results from the

maximum leakage current at the power-good node. If the pullup resistor is outside of this range, then the power-

good signal can possibly not read a valid digital logic level.

The state of the PG signal is only valid when the FB_PG pin resistor divider network is set properly and the

device is in normal operating mode.

8.1.6 Adjusting the Factory-Programmed Current Limit

The current limit is a brick-wall scheme and the factory-programmed current limit value can be programmed to a

set of discrete values (100%, 80%, or 60% of the default value), as specified in the Electrical Characteristics

table. This adjustment can be done by changing the input impedance of the FB_PG pin represented by the

parallel resistance of R_{FB_PG(TOP)}|| R_{FB_PG(BOTTOM)}. The FB_PG pin has dual functionality of adjusting the I_CL

value and setting the power-good (PG) assert threshold.

Prior to start-up, the input impedance of the FB_PG pin is sampled and the I_CLvalue is adjusted based on the

input impedance.

Current limit programmability is dependent on the output voltage. For voltages below 0.4 V, the current limit

cannot be programmed. For voltages between 0.4 V and 1.2 V, the current limit cannot be adjusted and is

always set to 100%. 表8-1 describes this behavior.

表8-1. Programmable Current Limit vs Output Voltage

NOMINAL OUTPUT

VOLTAGE (V)

I_CLSETTING

(%)

R_{FB_PG(BOTTOM)}(kΩ)

R_{FB_PG(TOP)}(kΩ)

100

80

R_{FB_PG(BOTTOM)}= 0.2 V / 16 μA

R_{FB_PG(BOTTOM)}= 0.2 V / 4 μA

R_{FB_PG(BOTTOM)}= 0.2 V / 2 μA

R_{FB_PG(BOTTOM)}= 0.2 V / 6 μA

N/A

R_{FB_PG(TOP)}= R_{FB_PG(BOTTOM)}

( V_OUT(nom)/ 0.2 V × K –1) with K = PG

×

V

_OUT(nom)≥1.2 V

60

threshold (%V_OUT

)

100

N/A

0.4 V ≤V_OUT(nom)< 1.2 V

V_OUT(nom)< 0.4 V

N/A

表8-2 provides values for various output voltages using 1% resistors.

表8-2. Programmable Current Limit Voltage-Divider Current Settings

NOMINAL OUTPUT VOLTAGE (V)

I_CLSETTING (%)

PG THRESHOLD (%)

R_{FB_PG(BOTTOM)}(kΩ)

R_{FB_PG(TOP)}(kΩ)

12.4

49.9

100

51.1

205

412

100

80

85

V_OUT(nom)= 1.2 V

60

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表8-2. Programmable Current Limit Voltage-Divider Current Settings (continued)

NOMINAL OUTPUT VOLTAGE (V)

I_CLSETTING (%)

PG THRESHOLD (%)

R_{FB_PG(BOTTOM)}(kΩ)

R_{FB_PG(TOP)}(kΩ)

12.4

49.9

100

187

732

100

80

95

V_OUT(nom)= 3.3 V

1470

287

60

12.4

49.9

100

80

V_OUT(nom)= 5.1 V

1150

2320

60

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图8-9 shows the different I_CLsettings for a nominal 3.3-V output voltage.

3.5

3

2.5

2

1.5

1

100% Current Limit

0.5

80% Current Limit

60% Current Limit

0

0.2

0.4

0.6

0.8

Current Limit Threshold (A)

1

1.2

1.4

图8-9. Programmable Current Limit Behavior (Typical) for a 3.3-V_OUT(nom)

8.1.7 Programmable Soft-Start and Noise-Reduction (NR/SS Pin)

The NR/SS pin is the input to the inverting terminal of the error amplifier, see the Functional Block Diagram. A

resistor connected from this pin to GND sets the output voltage by the pin internal reference current I_NR/SS, as

given in the following equation:

V_OUT= I_NR/SS× R_NR/SS

(3)

Connecting a capacitor from this pin to GND significantly reduces the output noise, limits the input inrush-

current, and soft-starts the output voltage. Use the minimum value or larger capacitor from NR/SS to ground as

listed in the Electrical Characteristics table and place the NR/SS capacitor as close to the NR/SS and GND pins

of the device as possible.

The device features a programmable, monotonic, voltage-controlled, soft-start circuit that is set to work with an

external capacitor (C_NR/SS). In addition to the soft-start feature, the C_NR/SScapacitor also lowers the output

voltage noise of the LDO. The soft-start feature can be used to eliminate power-up initialization problems. The

controlled output voltage ramp also reduces peak inrush current during start-up, minimizing start-up transients to

the input power bus.

To achieve a monotonic start-up, the device output voltage tracks the V_NR/SSreference voltage until this

reference reaches the set value (the set output voltage). The V_NR/SSreference voltage is set by the R_NR/SS

resistor and, during start-up, using a fast charging current (I_{FAST_SS}) in addition to the I_NR/SScurrent, as

illustrated in 图8-10, to charge the C_NR/SScapacitor.

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V_OUT

V_IN

I_{FAST_SS}

I_NR/SS= 150µA

Error Amplifier

driving passFET

œ

+

V_SNS

V_NR/SS

R_{PULLDOWN_NR/SS}

C_NR/SS

R_NR/SS

NR/SS discharge

GND

Logic

GND

图8-10. Simplified Soft-Start Circuit

The 2.1-mA (typical) I_{FAST_SS}current and 150-μA (typical) I_NR/SScurrent quickly charge C_NR/SSuntil the voltage

reaches approximately 93% of the set output voltage, then the I_{FAST_SS}current disengages and only the I_NR/SS

current continues to charge C_NR/SSto the set output voltage level. If there is any error during start-up or the

output overshoot prevention circuit is triggered, the NR/SS discharge FET turns on, thus discharging the C_NR/SS

capacitor to protect both the LDO and the load.

The soft-start ramp time depends on the fast start-up (I_{FAST_SS}) charging current, the reference current (I_NR/SS),

C_NR/SScapacitor value, and the set (targeted) output voltage (V_OUT(target)). 方程式4 calculates the soft-start ramp

time.

Soft-Start Time (t_SS) = (V_OUT(target)× C_NR/SS) / (I_NR/SS+ I_{FAST_SS}

)

(4)

The I_NR/SScurrent is provided in the Electrical Characteristics table and has a value of 150 μA (typical). The

I_{FAST_SS}current has a value of 2 mA (typical) for V_IN> 2.5 V. 图 8-11 and 图 8-12 show the I_NR/SSand I_{FAST_SS}

current versus V_INand temperature.

图8-11. I_NR/SSReference vs Input Voltage and

图8-12. I_{FAST_SS}Reference vs Input Voltage and

Temperature for V_OUT= 3.3 V

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Because the error amplifier is always operating in unity-gain configuration, the output voltage noise can only be

adjusted by increasing the C_NR/SScapacitor. The C_NR/SScapacitor and R_NR/SSresistor form a low-pass filter

(LPF) that filters out noise from the V_NR/SSvoltage reference, thereby reducing the device noise floor. The LPF is

a single-pole filter and 方程式 5 calculates the LPF cutoff frequency. Increasing the C_NR/SScapacitor can

significantly lower output voltage noise; however, doing so greatly lengthens start-up time. For low-noise

applications, use a 4.7-μF C_NR/SSfor optimal noise and start-up time trade off.

Cutoff Frequency (f_cutoff) = 1 / (2 × π× R_NR/SS× C_NR/SS

)

(5)

The Typical Characteristics section illustrates the impact of the C_NR/SScapacitor on the LDO output voltage

noise.

图8-13 shows the relationship, timing, and output voltage value during the start-up phase.

t₂

t₁

DV ∂C_{NR_SS}

=

V

∂C_{NR_SS}

OUT

PG_threshold

(

DV_OUT∂C_NR/SS

=

V_{OUT_target}-V_{PG_Threshold}∂C_NR/SS

)

t₁

=

t₂

=

I_{FAST_SS}

I_NR/SS

I_SS= 2 mA

t₁: C_NR/SScharges with

constant current

(I_{FAS T_SS}= 2 mA)

I_NR/SS= 150 mA

Threshold voltage

programmable

using PG_FB pin

time

图8-13. Relationship Between Threshold Voltage, Output Voltage, I_{FAST_SS}, and I_NR/SSDuring Start-Up

8.1.8 Inrush Current

Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists

primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to

measure because the input capacitor must be removed. Operating without an input capacitor is not

recommended because this capacitor is required for stability. However, 方程式 6 can be used to estimate this

current.

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C

_OUT´ dV_OUT(t)

V_OUT(t)

R_LOAD

I_OUT(t)

=

+

dt

(6)

where:

• V_OUT(t) is the instantaneous output voltage of the turn-on ramp

• dV_OUT(t) / dt is the slope of the V_OUTramp

• R_LOADis the resistive load impedance

As illustrated in 图 8-10, the external capacitor at the NR/SS pin (C_NR/SS) sets the output start-up time by setting

the rise time of the V_NR/SSreference voltage.

Inrush current for a no-load condition is given in 图6-20 to 图6-23.

8.1.9 Optimizing Noise and PSRR

Noise can be generally defined as any unwanted signal combining with the desired signal (such as the regulated

LDO output). Noise can easily be noticed in audio as a hissing or popping sound. Noise produced from an

external circuit or the 50- to 60-hertz power-line noise (spikes), along with the harmonics, is an excellent

representative of extrinsic noise. Intrinsic noise is produced by components within the device circuitry, such as

resistors and transistors. The two dominating sources of intrinsic noise are the error amplifier and the internal

reference voltage (V_NR/SS). Extrinsic noise, including the switching mode power-supply ac ripple voltage, coupled

onto the input supply of the LDO is attenuated by the LDO power-supply rejection ratio, or PSRR. PSRR is a

measurement of the noise attenuation from the input to the output of the LDO.

Optimize the intrinsic noise and PSRR by carefully selecting:

• C_NR/SSfor the low-frequency range up to the device bandwidth

• C_OUTfor the high-frequency range close to and higher than the device bandwidth

• Operating headroom, V_IN–V_OUT(V_DO), mainly for the low-frequency range up to the device bandwidth, but

also for higher frequencies to a lesser effect

These behaviors are described in the Typical Characteristics curves.

图 8-14 and 图 8-15 show the measured 10-Hz to 100-kHz RMS noise for a 3.3-V device output voltage with a

0.5-V headroom for different C_NR/SSand C_OUTcapacitors and a 1-A load current. 表 8-3 lists the typical output

noise for these capacitors.

图8-14. PSRR vs Frequency and I_OUTfor V_OUT= 3.3 图8-15. PSRR vs Frequency and I_OUTfor V_OUT= 3.3

V, C_OUT= 10 μF

V, C_OUT= 4.7 μF || 4.7 μF|| 1.0 μF

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表8-3. Typical Output Noise for 3.3-V_OUTvs C_NR/SS, C_OUT, and Typical Start-Up Time

C_NR/SS(µF)

C_OUT(µF)

START-UP TIME (ms)

V_n(μV_RMS), 10-Hz to 100-kHz BW

0.98

0.62

0.46

0.42

1

10

3.73

6.21

2.2

4.7

10

13.97

28.21

PSRR can be viewed as being simply the ratio of the output capacitor impedance by the LDO output impedance.

At low frequency, the output impedance is very low whereas the output impedance of the capacitor is high,

resulting in high PSRR. As the frequency increases, the output capacitor impedance reduces and reaches a

minima set by the ESR.

As given in 图 8-14 and 图 8-15, and in order to achieve high PSRR at high frequencies, make sure that the

output capacitor equivalent series resistance (ESR) and equivalent series inductance (ESL) are minimal. These

figures compare the use of a single 10-μF output capacitor with a 4.7-μF || 4.7-μF || 1.0-μF implementation.

Notice that below 200 kHz, there is no impact on performance but above 200 kHz, the PSRR improves by 5 dB

to 7 dB.

Minimizing the ESR- and ESL-generated resonance point in the output capacitance allows for a smoother

transition between the LDO active PSRR component to the passive PSRR of the capacitors.

备注

The TPS7A96 is optimized for the 1-A to 2-A output current range. For current outside this range,

consider the TPS7A94 device.

8.1.10 Adjustable Operation

As shown in 图8-16, the output voltage of the device can be set using a single external resistor (R_NR/SS). 方程式

7 calculates the output voltage.

V_OUT= I_NR/SS(NOM)× R_NR/SS

(7)

ENABLE

R_PG

R_{FB_PG(BOTTOM)}

R_{FB_PG(TOP)}

Clock

PG

FB_PG

V_IN

IN

C_IN

OUT

SNS

VDD_VCO

C_OUT

GND

TPS7A96

V_{EN_UV}

EN_UV

NR/SS

GND

VDD

SCLK

ADC

R_NR/SS

C_NR/SS

ADC

GND

图8-16. Typical Circuit

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表 8-4 lists the recommended R_NR/SSresistor values to achieve several common rails using a standard 1%-

tolerance resistor.

表8-4. Recommended R_NR/SSValues

TARGETED OUTPUT VOLTAGE

(V)

CALCULATED OUTPUT VOLTAGE

(V)

R_NR/SS(kΩ)

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.2

1.5

2.5

3.0

3.3

3.6

4.7

5.0

2.67

3.32

4.02

4.64

5.36

6.04

6.65

8.06

10.0

16.5

20.0

22.1

24.3

31.6

33.2

0.4005

0.498

0.603

0.696

0.804

0.906

0.9975

1.209

1.5

2.475

3.0

3.315

3.645

4.74

4.98

备注

To avoid engaging the current limit during start-up with a large C_OUTcapacitor, make sure that:

• A minimum NR/SS capacitor of 1 μF is used

• When the output capacitor is greater than 100 μF, maintain a C_OUTto C_NR/SSratio < 100

Because the set resistor is also placed on the NR/SS pin, consider using a thin-film resistor and

provide enough resistor temperature drift to provide the targeted accuracy.

8.1.11 Paralleling for Higher Output Current and Lower Noise

Achieving higher output current and lower noise is achievable by paralleling two or more LDOs. Implementation

must be carefully planned out to optimize performance and minimize output current imbalance.

Because the TPS7A96 output voltage is set by a resistor driven by a current source, the NR/SS resistor and

capacitor must be adjusted as per the following:

R_{NR/SS_parallel}= V_{OUT_TARGET}/ (n × I_NR/SS

C_{NR/SS_parallel}= n × C_{NR/SS_single}

)

(8)

(9)

where:

• n is the number of LDOs in parallel

• I_NR/SSis the NR/SS current as provided in the data sheet Electrical Characteristics table

• C_NR/SS_single is the NR/SS capacitor for a single LDO

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When connecting the input and NR/SS pin together, and with the LDO being a buffer, the current imbalance is

only affected by the error offset voltage of the error amplifier. As such, the current imbalance can be expressed

as:

2

ε_I= V_OS× 2 × R_BALLAST/ (R_BALLAST²–ΔR_BALLAST

)

(10)

where:

• ε_Iis the current imbalance

• V_OSis the LDO error offset voltage

• R_BALLASTis the ballast resistor

• ΔR_BALLASTis the deviation of the ballast resistor value from the nominal value

With the typical offset voltage of 200 μV, considering no error from the design of the PCB ballast resistor

(ΔR_BALLAST= 0) and a 100-mA maximum current imbalance, the ballast resistor must be 4 mΩ or greater; see

图8-17.

Using the configuration described, the LDO output noise is reduced by:

e_{O_parallel}= (1 / √n) × e_{O_single}

(11)

where:

• n is the numbers of LDOs in parallel

• e_{O_single}is the output noise density from a single LDO

• e_{O_parallel}is the output noise density for the resulting parallel LDO

In 图8-17, the noise is reduced by 1 / √2.

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图8-17. Paralleling Multiple TPS7A94 Devices

8.1.12 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) and low equivalent series

inductance (ESL) ceramic capacitors at the input, output, and noise-reduction pin. Multilayer ceramic capacitors

have become the industry standard for these applications and are recommended, but must be used with good

judgment. Ceramic capacitors that employ X7R-, X5R-rated, or better dielectric materials provide relatively good

capacitive stability across temperature. The use of Y5V-rated capacitors is discouraged because of large

variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature. The input and output capacitors recommended herein account for a capacitance derating of

approximately 50%, but at high V_INand V_OUTconditions (V_IN= 5.5 V to V_OUT= 5.0 V), the derating can be

greater than 50%, which must be taken into consideration.

The device requires input, output, and noise-reduction capacitors for proper operation of the LDO. Use the

nominal or larger than the nominal input and output capacitors, as specified in the 节 6.3 table. Place input and

output capacitors as close as possible to the corresponding pin and make the capacitor GND connections as

close as possible to the device GND pin to minimize PCB loop inductance, thus reducing transient voltage

spikes during a load step.

As illustrated in #none#, multiple parallel capacitors can be used to lower the impedance present on the line.

This capacitor counteracts input trace inductance, improves transient response, and reduces input ripple and

noise. Using an output capacitor larger than the typical value can also improve the transient response.

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8.1.13 Load Transient Response

备注

For best transient response, use the nominal value or larger capacitor from OUT to ground as listed in

the Recommended Operating Conditions table. Place the output capacitor as close to the OUT and

GND pins of the device as possible.

For best transient response and to minimize input impedance, use the nominal value or larger

capacitor from IN to ground as listed in the Recommended Operating Conditions table. Place the input

capacitor as close to the IN and GND pins of the device as possible.

The load-step transient response is the LDO output voltage response to load current changes. There are two

key transitions during a load transient response: the transition from a light to a heavy load, and the transition

from a heavy to a light load. The regions shown in 图 8-18 are broken down in this section. Regions A, E, and H

are where the output voltage is in steady-state regulation.

A

C

D

E

G

H

V_OUT

B

F

Time (µs)

Current slew rate (rise = fall)

Max output current

Minimum output current

I_OUT

Time (µs)

图8-18. Load Transient Waveform

During transitions from a light load to a heavy load:

• The initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to

the output capacitor (region B)

• Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load:

• The initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge

to increase (region F)

• Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load

discharging the output capacitor (region G)

Transitions between current levels changes the internal power dissipation because the device is a high-current

device (region D). The change in power dissipation changes the die temperature during these transitions, and

leads to a slightly different voltage level. This temperature-dependent output voltage level shows up in the

various load transient responses.

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

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8.1.14 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. 方程式12 calculates P_D:

P_D= (V_OUT- V_IN) ´ I_OUT

(12)

备注

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the

system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be

obtained. The low dropout of the device allows for maximum efficiency across a wide range of output

voltages.

The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad

to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any

inner plane areas or to a bottom-side copper plane.

The power dissipation by the device determines the junction temperature (T_J) for the device. Power dissipation

and junction temperature are most often related by the junction-to-ambient thermal resistance (R_θJA) of the

combined PCB and device package and the temperature of the ambient air (T_A), according to 方程式 13. This

equation is rearranged for output current in 方程式14.

T_J= T_A= (R_θJA× P_D)

(13)

(14)

I_OUT= (T_J–T_A) / [R_θJA× (V_IN–V_OUT)]

This thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

R_θJArecorded in the Thermal Information table is determined by the JEDEC standard, PCB, and copper-

spreading area, and is only used as a relative measure of package thermal performance. For a well-designed

thermal layout, R_θJAis actually the sum of the DSC package junction-to-case (bottom) thermal resistance

(R_θJCbot) plus the thermal resistance contribution by the PCB copper.

8.1.15 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with 方程式15 and are given in the Thermal Information table.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

(15)

where:

• P_Dis the power dissipated as explained in the Power Dissipation (P_D) section

• T_Tis the temperature at the center-top of the device package

• T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

English Data Sheet: SBVS415

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8.1.16 TPS7A96EVM-106 Thermal Analysis

The TPS7A94EVM-046 evaluation board was used to develop the TPS7A9401DRC thermal model. The DRC

package is a 3-mm × 3-mm, 10-pin VQFN with 25-µm plating on each via. The EVM is a 2.85-inch × 3.35-inch

(72.39 mm × 85.09 mm) PCB comprised of four layers. 表 8-5 lists the layer stackup for the EVM. 图 8-19 to 图

8-23 illustrate the various layer details for the EVM.

表8-5. TPS7A96EVM-106 PCB Stackup

LAYER

NAME

Top overlay

Top solder

Top layer

MATERIAL

THICKNESS (mil)

1

2

—

0.4

2.8

10

Solder resist

Copper

3

4

Dielectric 1

Mid layer 1

Dielectric 2

Mid layer 2

Dielectric 3

Bottom layer

Bottom solder

FR-4 high Tg

Copper

5

2.8

30

6

FR-4 high Tg

Copper

7

2.8

10

8

FR-4 high Tg

Copper

9

2.8

0.4

10

Solder resist

图8-19. Top Composite View

图8-20. Top Layer Routing

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图8-21. Mid Layer 1 Routing

图8-22. Mid Layer 2 Routing

图8-23. Bottom Layer Routing

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图 8-24 to 图 8-26 show the thermal gradient on the PCB and device that results when a 1-W power dissipation

is used through the pass transistor with a 25°C ambient temperature. 表 8-6 shows thermal simulation data for

the TPS7A94EVM-046.

表8-6. TPS7A96EVM-106 Thermal Simulation Data

DUT

R_θJA(°C/W)

⍦

_JB(°C/W)

⍦_JT(°C/W)

TPS7A96EVM-106

25.6

11.5

0.3

图8-24. TPS7A96EVM-106 3D View

图8-25. TPS7A96EVM-106 PCB Thermal Gradient

图8-26. TPS7A96EVM-106 Device Thermal Gradient

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8.1.17 TPS7A96EVM-106 Thermal Analysis

The TPS7A96EVM-106 evaluation module was used to develop the TPS7A9601DRC thermal model. The DRC

package is a 3-mm × 3-mm, 10-pin VQFN with 25-µm plating on each via. The EVM is a 2.85-inch × 3.35-inch

(72.39 mm × 85.09 mm) PCB comprised of four layers. 表 8-7 lists the layer stackup for the EVM. 图 8-27 to 图

8-31 illustrate the various layer details for the EVM.

表8-7. TPS7A96EVM-106 PCB Stackup

LAYER

NAME

Top overlay

Top solder

Top layer

MATERIAL

THICKNESS (mil)

1

2

—

0.4

2.8

10

Solder resist

Copper

3

4

Dielectric 1

Mid layer 1

Dielectric 2

Mid layer 2

Dielectric 3

Bottom layer

Bottom solder

FR-4 high Tg

Copper

5

2.8

30

6

FR-4 high Tg

Copper

7

2.8

10

8

FR-4 high Tg

Copper

9

2.8

0.4

10

Solder resist

图8-27. Top Composite View

图8-28. Top Layer Routing

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图8-29. Mid Layer 1 Routing

图8-30. Mid Layer 2 Routing

图8-31. Bottom Layer Routing

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图 8-32 to 图 8-34 show the thermal gradient on the PCB and device that results when a 1-W power dissipation

is used through the pass transistor with a 25°C ambient temperature. 表 8-8 shows thermal simulation data for

the TPS7A94EVM-046.

表8-8. TPS7A96EVM-106 Thermal Simulation Data

DUT

R_θJA(°C/W)

⍦

_JB(°C/W)

⍦_JT(°C/W)

TPS7A96EVM-106

25.6

11.5

0.3

图8-32. TPS7A96EVM-106 3D View

图8-33. TPS7A96EVM-106 PCB Thermal Gradient

图8-34. TPS7A96EVM-106 Device Thermal Gradient

English Data Sheet: SBVS415

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8.2 Typical Application

图8-35. Typical Application Circuit

图8-36. Typical Application Circuit With Added Pi-Filter

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8.2.1 Design Requirements

表8-9 lists the required application parameters for this design example.

表8-9. Design Parameters

PARAMETER

DESIGN REQUIREMENT

Input voltage

Output voltage

Output current

Current limit

V_IN≥5 V, ±3%, provided by the dc/dc converter switching at 1 MHz

3.3 V, ±1%

1.5 A (maximum), 800 mA (minimum)

2 A

PG threshold

95%

Targeted noise compliance mask

Zone 1 (10 Hz to 100 Hz): Spectral noise ≤100 nV/√Hz

Targeted spectral noise

Zone 2 (100 Hz to 1 kHz): Spectral noise ≤10 nV/√Hz

Zone 3 (> 1 kHz): Spectral noise ≤3 nV/√Hz

PSRR at 1 MHz

> 50 dB at max load current

Device to be enabled when V_IN≥80% × V_{IN_Target}

Start-up environment

Device to be disabled when V_IN< 80% × V_{IN_Target}

Start-up time < 25 ms

8.2.2 Detailed Design Procedure

In this design example, the device is powered by a dc/dc convertor switching at 1 MHz. The load requires a 3.3-

V clean rail with the spectral noise mask versus frequency shown in 图 8-37 and a maximum load of 500 mA.

The typical 10-μF input and output capacitors and 4.7-μF NR/SS capacitors are used to achieve a good

balance between fast start-up time and excellent noise and PSRR performance.

Zone 3

Frequency (Hz)

图8-37. Noise Compliance Mask

The output voltage is set using a 22.1-kΩ, thin-film resistor value calculated as described in the Adjustable

Operation section. To set the current limit to a value close to the 750 mA required by the application, and to set

the PG threshold to 95%, use 表 8-2 to set the R_{FB_PG}top and bottom resistors values at 1.47 MΩ and 100 kΩ,

respectively.

Setting R_Bto 100 kΩ and using a 4-V V_ONand 方程式1 provides the R_Tvalue of 226 kΩ. V_OFFis calculated with

方程式2 to be 3.5 V.

English Data Sheet: SBVS415

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图 8-38 shows that the device meets all design noise requirements except for the noise peaking at 900 kHz.

However, this noise peaking can be easily attenuated to the required noise level by means of a pi-filter

positioned after the LDO. 图 8-39 shows that this design is very close to the PSRR level at 1 MHz and can

require more margin. Fortunately, both requirements are easily achieved by inserting a pi-filter consisting of a

ferrite bead and a small capacitor beyond the LDO and before the load; see 图8-36.

The ferrite bead was selected to have a very small dc resistance of less than 50 mΩ, 1 A of current rating, and a

relatively small footprint. The added pi-filter components have almost no impact on the LDO accuracy

performance and no significant increase in the design total cost.

200

100

50

140

120

100

80

20

10

5

60

2

1

40

0.5

20

0.2

0.1

0

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

图8-38. Output Noise vs Frequency

图8-39. PSRR vs Frequency

8.2.3 Application Curves

图8-40 and 图8-41 show the design noise and PSRR performance after inserting the pi-filter.

200

100

50

140

120

100

80

Non-Filtered (nV/vHz)

Filtered (nV/vHz)

Filtered

Non-Filtered

20

10

5

60

2

1

40

0.5

20

0.2

0.1

0

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

10

100

1k

10k

Frequency (Hz)

100k

1M

10M

图8-40. Noise vs Frequency

图8-41. PSRR vs Frequency

8.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply ranging from 1.7 V to 5.7 V. Make sure that the

input voltage range provides adequate operational headroom for the device to have a regulated output. This

input supply must be well regulated. If the input supply is noisy, use additional input capacitors with low ESR and

increase the operating headroom to achieve the desired output noise, PSRR, and load transient performance.

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8.4 Layout

8.4.1 Layout Guidelines

For good thermal performance, connect the thermal pad to a large-area GND plane.

Kelvin connects the SNS pin through a low-impedance connection to the output capacitor and load for optimal

transient performance. Do not float this pin.

Connect the GND pin to the device thermal pad and connect both this pin and the thermal pad to the ground on

the board through a low-impedance connection.

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,

copper surface. To avoid negative system performance, do not use vias or long traces to the input and output

capacitors. The grounding and layout scheme described in 图 8-42 minimizes inductive parasitics, and thereby

reduces load-current transients, minimizes noise, and increases circuit stability.

To improve performance, use a ground reference plane, either embedded in the printed circuit board (PCB) or

placed on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy

of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO

device when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal

requirements.

English Data Sheet: SBVS415

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8.4.2 Layout Example

TOP View

CIN

COUT

GND Plane

IN

OUT

IN

OUT

IINN

EN_UV

PG

SNS

RPG

Thermal vias

GND Plane

NR/SS

PG

C_NR/SS

R_NR/SS

FB_PG

GND

R

FB_PG(TOP)

R

FB_PG(BOTTOM)

OUT

图8-42. Example Layout

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

9.1.1.1 Evaluation Modules

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the

TPS7A96. The summary information for this fixture is shown in 表9-1.

表9-1. Design Kits and Evaluation Modules

NAME

LITERATURE NUMBER

TPS7A9601EVM-106 evaluation module

SBVU081

The EVM can be requested at the Texas Instruments web site through the TPS7A94 product folder.

9.1.1.2 Spice Models

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of

analog circuits and systems. A SPICE model for the TPS7A96 is available through the TPS7A96 product folder

under simulation models.

9.1.2 Device Nomenclature

表9-2. Ordering Information⁽¹⁾

PRODUCT

DESCRIPTION

yyy is the package designator.

z is the package quantity.

TPS7A9601yyyz

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the

device product folder at www.ti.com.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, TPS3702 High-Accuracy, Overvoltage and Undervoltage Monitor data sheet

• Texas Instruments, TPS7A94EVM-046 Evaluation Module user guide

• Texas Instruments, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator

application note

• Texas Instruments, Parallel LDO Architecture Design Using Ballast Resistors

• Texas Instruments, TPS7A57 evaluation module for 5-A low-noise high-accuracy low-dropout (LDO) voltage

regulator

• Texas Instruments, Parallel low-dropout (LDO) calculator

9.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

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9.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

9.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

DSC0010J

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

3.1

2.9

C

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

EXPOSED

THERMAL PAD

4X (0.25)

5

6

2X

2

11

SYMM

2.4 0.1

10

1

8X 0.5

0.30

0.18

10X

SYMM

PIN 1 ID

0.1

C A B

C

(OPTIONAL)

0.05

0.5

0.3

10X

4221826/D 08/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DSC0010J

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

1

10

10X (0.24)

11

(2.4)

(3.4)

SYMM

(0.95)

8X (0.5)

6

5

(R0.05) TYP

(

0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221826/D 08/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DSC0010J

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

11

10X (0.6)

1

10

(1.53)

10X (0.24)

2X

(1.06)

SYMM

(0.63)

8X (0.5)

6

5

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4221826/D 08/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	PTPS7A9601DSCR
厂家：	TEXAS INSTRUMENTS
描述：	2A 超低噪声、超高 PSRR 射频稳压器 \| DSC \| 10 \| -40 to 125 射频稳压器
文件：	总57页 (文件大小：3712K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PTPS7A9601DSCR [TI]

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