RF430CL331H [TI]
用于大型文件传输的动态 NFC 接口应答器;
| 型号： | RF430CL331H |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于大型文件传输的动态 NFC 接口应答器 |
| 文件： | 总63页 (文件大小：1798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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RF430CL331H
ZHCSE57A –SEPTEMBER 2015–REVISED NOVEMBER 2015
RF430CL331H NFC 类型 4B 动态双接口应答器
1 器件概述
1.1 特性
1
• 通过直通操作向主机控制器发送数据更新和请求
• I2C 接口允许对内部静态随机存取存储器 (SRAM)
进行读写操作
• 最高可自动处理层 4 上的所有射频 (RF) 通信
• 支持最大的 NFC 数据交换格式 (NDEF) 消息
• 符合 ISO/IEC 14443B 标准
• 预取、缓存和自动应答 特性 提高数据吞吐量
• 支持数据流
• 支持高达 848kbps 的传输速率
1.2 应用
•
•
无线固件更新
Wi-Fi®和 Bluetooth®配对
•
•
服务接口
无线传感器接口
1.3 说明
德州仪器 (TI) 动态近场通信 (NFC)/射频识别 (RFID) 接口应答器 RF430CL331H 是一款 NFC 标签类型 4 器
件，可结合一个非接触式 NFC/RFID 接口和一个有线 I2C 接口将器件连接到主机。NDEF 消息可通过集成的
I2C 串行通信接口读写，也可通过支持高达 848kbps 速率的集成 ISO/IEC 14443 标准类型 B RF 接口进行非
接触式访问或更新。
该器件按主机控制器的需求请求响应 NFC 类型 4 命令，每次仅在其缓存中存储部分 NDEF 消息。这使得
NDEF 消息的大小仅受主机控制器的存储器容量以及规范的限制。
该器件支持读缓存、预取和写自动确认 功能， 可提高数据吞吐量。
该器件可利用简单而直观的 NFC 连接切换来替代载波方式，只需一次点击操作即可完成诸如 Bluetooth®，
Bluetooth®低功耗 (BLE) 或 Wi-Fi 的配对过程或认证过程。
作为一个常见 NFC 接口，RF430CL331H 使得终端设备能够与启用 NFC 的智能手机、平板电脑和笔记本电
脑这类快速发展的基础设施进行通信。
(1)
器件信息
封装
(2)
部件号
RF430CL331HIPW
RF430CL331HRGT
封装尺寸
TSSOP (14)
VQFN (16)
5mm x 4.4mm
3mm x 3mm
(1) 要获得所有可用器件的最新部件、封装和订购信息，请参见封装选项附录（节 8）或浏览 TI 网站
www.ti.com。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 8中）。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASE18
RF430CL331H
ZHCSE57A –SEPTEMBER 2015–REVISED NOVEMBER 2015
www.ti.com.cn
1.4 典型应用
图 1-1 给出了典型应用。
I2C
RF430
NFC/RFID
Tag
I2C Bus
Microcontroller
NFC/RFID
Reader
Flow Control
INTO
图 1-1. 典型应用
2
器件概述
版权 © 2015, Texas Instruments Incorporated
RF430CL331H
www.ti.com.cn
ZHCSE57A –SEPTEMBER 2015–REVISED NOVEMBER 2015
内容
1
器件概述.................................................... 1
5.1 Overview ............................................ 12
5.2 Functional Block Diagram........................... 12
5.3 Terms and Acronyms ............................... 12
5.4 Serial Communication Interface..................... 12
5.5 Communication Protocol ............................ 13
5.6 I2C Protocol ......................................... 13
5.7 NFC Type 4B Tag Platform ......................... 16
5.8 NDEF Structure ..................................... 19
5.9 Typical Operation.................................... 21
5.10 RF Command Response Timing Limits............. 33
5.11 Registers ............................................ 35
5.12 Identification ......................................... 48
Applications, Implementation, and Layout........ 49
6.1 Application Diagram................................. 49
6.2 References .......................................... 49
器件和文档支持 .......................................... 50
7.1 器件支持............................................. 50
7.2 文档支持............................................. 51
7.3 社区资源............................................. 51
7.4 商标.................................................. 51
7.5 静电放电警告 ........................................ 52
7.6 出口管制提示 ........................................ 52
7.7 Glossary ............................................. 52
机械、封装和可订购信息................................ 52
1.1 特性 ................................................... 1
1.2 应用 ................................................... 1
1.3 说明 ................................................... 1
1.4 典型应用 .............................................. 2
修订历史记录............................................... 3
Terminal Configuration and Functions.............. 4
3.1 Pin Diagrams ......................................... 4
3.2 Pin Attributes ......................................... 5
3.3 Signal Descriptions ................................... 6
3.4 Pin Multiplexing....................................... 6
3.5 Connections for Unused Pins ........................ 6
Specifications ............................................ 7
4.1 Absolute Maximum Ratings .......................... 7
4.2 ESD Ratings.......................................... 7
4.3 Recommended Operating Conditions ................ 7
2
3
4
6
7
4.4
Recommended Operating Conditions, Resonant
Circuit ................................................. 7
4.5 Supply Currents ...................................... 8
4.6
Electrical Characteristics, Digital Inputs .............. 8
Electrical Characteristics, Digital Outputs ............ 8
4.7
4.8 Thermal Characteristics .............................. 9
4.9 Timing and Switching Characteristics............... 10
Detailed Description ................................... 12
5
8
2 修订历史记录
Changes from September 29, 2015 to November 30, 2015
Page
•
•
Deleted "Suggested to be set to 0x3B" from Step 7(a) ........................................................................ 34
Deleted "The recommended setting is maximum possible value, which is 0x3B" in the paragraph that starts
"When the internal state machine determines..."................................................................................ 46
Copyright © 2015, Texas Instruments Incorporated
修订历史记录
3
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3 Terminal Configuration and Functions
3.1 Pin Diagrams
Figure 3-1 shows the pinout for the 14-pin PW package.
VCC
ANT1
ANT2
RST
E0
1
2
3
4
5
6
7
14
13
12
11
10
9
VSS
VCORE
SDA
SCL
I2C_SIGNAL
I2C_READY
INTO
E1
E2
8
Figure 3-1. 14-Pin PW Package (Top View)
Figure 3-2 shows the pinout for the 16-pin RGT package.
16 15 14 13
12
ANT1
ANT2
RST
E0
1
2
3
4
VCORE
SDA
Exposed
Thermal
Pad
11
10
9
SCL
I2C_SIGNAL
5
6
7
8
Figure 3-2. 16-Pin RGT Package (Top View)
4
Terminal Configuration and Functions
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3.2 Pin Attributes
Table 3-1. Pin Attributes
PIN NUMBER
(1)
(2)
(3)
SIGNAL NAME
VCC
SIGNAL TYPE
BUFFER TYPE
POWER SOURCE
RESET STATE
PW
1
RGT
15
1
PWR
Power
Analog
Analog
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Power
VCC
–
N/A
N/A
2
ANT1
ANT2
RST
RF
3
2
RF
–
N/A
4
3
I
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
–
PU
5
4
E0
I
I
OFF
OFF
OFF
OFF
DRIVE1
DRIVE1
OFF
OFF
N/A
6
5
E1
7
6
E2
I
8
7
INTO
I2C_READY
I2C_SIGNAL
SCL
O
9
8
O
10
11
12
13
14
–
9
O
10
11
12
13
14
16
I/O
I/O
PWR
PWR
–
SDA
VCORE
VSS
Power
N/A
NC
–
–
–
NC
–
–
–
–
(1) Signal Types: I = Input, O = Output, I/O = Input or Output, PWR = Power, RF = Radio frequency
(2) Buffer Types: See Table 3-3 for details.
(3) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
DRIVE0 = Drive output low
DRIVE1 = Drive output high
N/A = Not applicable
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Terminal Configuration and Functions
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3.3 Signal Descriptions
Table 3-2 describes the signals.
Table 3-2. Signal Descriptions
(1)
FUNCTION
SIGNAL NAME
PIN NUMBER
I/O
DESCRIPTION
PW
1
RGT
15
12
13
1
VCC
PWR
3.3-V power supply
Power
VCORE
VSS
ANT1
ANT2
E0
13
14
2
PWR
Regulated core supply voltage
Ground supply
PWR
RF
Antenna input 1
RF
3
2
RF
Antenna input 2
5
4
I
I
I
I2C address select 0
I2C address select 1
I2C address select 2
E1
6
5
E2
7
6
High indicates that I2C communication can be started. Low indicates
Serial
communication
I2C_READY
I2C_SIGNAL
9
8
9
O
O
that I2C communication must not be started.
Low indicates that a wait time extension command is automatically
being sent. I2C communication does not have to be stopped.
10
SCL
SDA
INTO
RST
11
12
8
10
11
7
I/O
I/O
O
I2C clock
I2C data
Interrupt output
System
(2)
4
3
I
Reset input (active low)
14
16
No connect
NC
–
–
Leave open, no connection
(1) I = Input, O = Output, PWR = Power, RF = RF antenna
(2) With integrated pullup
3.4 Pin Multiplexing
None of the pins on this device are multiplexed.
Table 3-3. Buffer Type
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
OTHER
CHARACTERISTICS
HYSTERESIS
PU OR PD
See Section 4.6, See Section 4.7,
Electrical Electrical
Characteristics, Characteristics,
LVCMOS
3.3 V
Y
N/A
Digital Inputs
Digital Outputs
See analog modules in
Section 4, Specifications,
for details
Analog, RF
Power
3.3 V
3.3 V
N
N/A
N/A
N/A
N/A
N/A
Y with SVS on
N/A
3.5 Connections for Unused Pins
Leave no connect (NC) pins unconnected.
Leave unused outputs unconnected.
Drive or pull unused inputs high or low.
6
Terminal Configuration and Functions
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4 Specifications
(1) (2)
4.1 Absolute Maximum Ratings
MIN
–0.3
–0.3
–0.3
MAX
4.1
UNIT
V
Voltage applied at VCC referenced to VSS (VAMR
)
Voltage applied at VANT referenced to VSS (VAMR
)
4.1
V
Voltage applied to any pin (references to VSS
)
VCC + 0.3
±2
V
Diode current at any device pin
mA
°C
(3)
Storage temperature, Tstg
–40
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are referenced to VSS.
(3) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
4.2 ESD Ratings
VALUE
±2000
±500
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
V(ESD)
Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4.3 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
3.0
NOM
3.3
3.3
0
MAX
3.6
UNIT
During program execution no RF field present
During program execution with RF field present
VCC
Supply voltage
V
2.0
3.6
VSS
TA
Supply voltage (GND reference)
Operating free-air temperature
V
–40
0.1
85
1
°C
µF
µF
µF
(1)
C1
Decoupling capacitor on VCC
0.1
1
(1)
C2
Decoupling capacitor on VCC
(1)
CVCORE
Capacitor on VCORE
0.47
(1) Low ESR (equivalent series resistance) capacitor
4.4 Recommended Operating Conditions, Resonant Circuit
MIN
NOM
MAX
UNIT
MHz
V
fc
Carrier frequency
13.56
VANT_peak Antenna input voltage
3.6
Z
Impedance of LC circuit
6.5
15.5
kΩ
LRES
CRES
CTune
QT
Coil inductance(1)
2.66
51.8
µH
pF
Total resonance capacitance(1), CRES = CIN + CTune
External resonance capacitance
Tank quality factor
(2)
CRES – CIN
30
pF
(1) The coil inductance of the antenna LRES with the external capacitance CTune plus the device internal capacitance CIN is a resonant
circuit. The resonant frequency of this LC circuit must be close to the carrier frequency fc:
fRES = 1 / [2π(LRESCRES)
1/2] = 1 / [2π(LRES(CIN+CTune))1/2] ≈ fc
(2) For CIN refer to Section 4.9.3.
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4.5 Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX UNIT
ICC(I2C)
I2C, 400 kHz, Writing into NDEF memory
3.3 V
3.3 V
250
40
µA
µA
ICC(RF enabled) RF enabled, no RF field present
Standby enable = 0, RF disabled, no serial
communication
ICC(Inactive)
3.3 V
15
10
µA
Standby enable = 1, RF disabled, no serial
communication
ICC(Standby)
3.3 V
45
160
0
µA
µA
µA
Additional current consumption with strong RF field
present
ΔICC(StrongRF)
3.0 V to 3.6 V
2.0 V to 3.0 V
Current drawn from VCC < 3.0 V with RF field present
(passive operation)
ICC(RF,lowVCC)
4.6 Electrical Characteristics, Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
0.3 ×
V
VIL
Low-level input voltage
VCC
0.7 ×
VCC
VIH
High-level input voltage
Input hysteresis
V
V
0.1 ×
VCC
VHYS
IL
High-impedance leakage current
Integrated RST pullup resistor
3.3 V
–50
20
50
50
nA
RPU(RST)
35
kΩ
4.7 Electrical Characteristics, Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
MIN
MAX UNIT
0.4
VOL
Output low voltage
IOL = 3 mA
3.3 V
3.6 V
3 V
0.4
0.4
V
V
2.6
2.9
3.2
VOH
Output high voltage
IOH = –3 mA
3.3 V
3.6 V
8
Specifications
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4.8 Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VALUE
116.0
45.1
57.6
57.0
4.6
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance, still air(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
RθJC(TOP)
RθJB
TSSOP-14 (PW)
VQFN-16 (RGT)
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-ambient thermal resistance, still air(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-case (bottom) thermal resistance(4)
Junction-to-board thermal resistance(3)
ΨJT
RθJA
48.8
60.8
7.1
RθJC(TOP)
RθJC(BOT)
RθJB
21.9
21.9
1.5
ΨJB
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
ΨJT
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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4.9 Timing and Switching Characteristics
4.9.1 Reset Timing
Table 4-1. I2C Power-up Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
MAX UNIT
20 ms
tReady
Time after power up or reset until device is ready to communicate using I2C(1)
(1) The device is ready to communicate after tReady(MAX) at the latest.
4.9.2 Serial Communication Protocol Timing
Table 4-2. I2C Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
SCL clock frequency (with Master supporting clock stretching
according to I2C standard, or when the device is not being
addressed)
3.3 V
0
400
fSCL
kHz
120
Write
Read
SCL ≤ 100 kHz
fSCL > 100 kHz
SCL ≤ 100 kHz
fSCL > 100 kHz
3.3 V
3.3 V
0
0
SCL clock frequency (device being addressed by Master not
supporting clock stretching)
100
f
4
tHD,STA
Hold time (repeated) START
3.3 V
3.3 V
µs
0.6
4.7
0.6
0
f
tSU,STA
Setup time for a repeated START
µs
tHD,DAT
tSU,DAT
tSU,STO
tSP
Data hold time
3.3 V
3.3 V
3.3 V
3.3 V
ns
ns
µs
Data setup time
250
4
Setup time for STOP
Pulse duration of spikes suppressed by input filter
6.25
75
ns
tHD,STA
tSU,STA tHD,STA
SDA
SCL
1/fSCL
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 4-1. I2C Mode Timing
10
Specifications
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4.9.3 RF143B NFC/RFID Analog Front End
Table 4-3. Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Antenna rectified voltage
Antenna load current
Input capacitance
TEST CONDITIONS
Peak voltage limited by antenna limiter
RMS, without limiter current
MIN
TYP
MAX
3.6
UNIT
V
VDDH
IDDH
CIN
3.0
3.3
100
38.5
µA
pF
ANT1 to ANT2, 2 V RMS
31.5
35
Table 4-4. ISO/IEC 14443B ASK Demodulator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
848
UNIT
DR10
m10
Input signal data rate 10% downlink modulation, 7% to 30% ASK, ISO1443B
Modulation depth 10%, tested as defined in ISO/IEC 10373-6
106
kbps
7%
30%
Table 4-5. ISO/IEC 14443B-Compliant Load Modulator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Uplink subcarrier modulation frequency
MIN
0.2
TYP
MAX
UNIT
MHz
V
fPICC
1
VA_MOD
VSUB14
Modulated antenna voltage, VA_unmod = 2.3 V
0.5
22/H0.5
Uplink modulation subcarrier level, ISO/IEC 14443B: H = 1.5 to 7.5 A/m
mV
Table 4-6. Power Supply
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Limiter clamping voltage
Maximum limiter current
TEST CONDITIONS
MIN
TYP
MAX
3.6
UNIT
Vpk
VLIM
ILIM ≤ 70 mA RMS, f = 13.56 MHz
3.0
ILIM,MAX
70
mA
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5 Detailed Description
5.1 Overview
图 5-1 shows the functional block diagram.
5.2 Functional Block Diagram
RST
VCC
Buffer
Memory
(SRAM)
VSS
VCORE
SCL
ANT1
ANT2
Processing
Unit
(MSP430-
based)
NFC Type 4B
Tag Platform
ISO/IEC 14443
RF Interface
SDA
I2C
Interface
I2C_READY
I2C_SIGNAL
E0 E1 E2
INTO
图 5-1. Functional Block Diagram
5.3 Terms and Acronyms
表 5-1 describes the terms and acronyms used in this document.
表 5-1. Term Definitions
NAME
DESCRIPTION
PCD
Proximity coupling device, such as NFC enabled handset, NFC/RFID reader/writer devices
Proximity integrated circuit card, dynamic tag, RF430CL331H IC
PICC
NFC Type 4 command
PICC Buffer
See the NFC Forum Type 4 Tag Operation Specification (http://nfc-forum.org/) for details
This is a memory range (0 through 2999) that is accessible through the I2C bus, where buffer data is stored.
This is a MCU or processor connected to the PICC through the I2C bus. It responds to all the of Type 4 data
requests that come from the PICC.
Host Controller
SW
Type 4 command acknowledgments, referred also as SW1 and SW2 (status word). Refer to NFC/RFID and
ISO14443-B specifications for details.
Frame wait time extension. When the RF430CL331H cannot respond to a command that PCD sends, it must
send a S(WTX) request indicating that it needs more time. The PCD then responds and the RF430CL331H has
the negotiated time that it requested.
SWTX or S(WTX)
5.4 Serial Communication Interface
The serial interface of this device is I2C. The serial interface allows a connected MCU to configure the
device and write to and read from the available registers and the RAM buffer on the RF430CL331H.
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5.5 Communication Protocol
The tag is programmed and controlled by writing data into and reading data from the address map shown
in 表 5-2 through the I2C serial interface.
表 5-2. User Address Map
RANGE
ADDRESS
0xFFFE
SIZE
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
2 B
DESCRIPTION
Control register
0xFFFC
Status register
0xFFFA
Interrupt Enable
Interrupt Flags
0xFFF8
0xFFF6
CRC Result (16-bit CCITT)
CRC Length
0xFFF4
0xFFF2
CRC Start Address
0xFFF0
Communication Watchdog Control register
0xFFEE
Version
Registers
0xFFEC
NDEF File ID register
0xFFEA
Host Response register
0xFFE8
NDEF Block Length register
0xFFE6
NDEF File Offset register
0xFFE4
Buffer Start register
0xFFE2
Reserved
0xFFE0
Reserved
0xFFDE
SWTX register
0xFFDC
Reserved
0xFFDA
Custom SW1 and SW2 Response
0x4000 to 0xFFDF
0x0BB8 to 0x3FFF
0x0000 to 0x0BB7
Reserved
Reserved
Buffer
13KB
Reserved (for example, for future extension of NDEF Memory size)
Buffer Memory
3000 B
注
Crossing range boundaries causes writes to be ignored and reads to return undefined data.
5.6 I2C Protocol
A command is always initiated by the master by addressing the device using the specified I2C device
address. The device address is a 7-bit I2C address. The upper 4 bits are hard-coded, and the lower 3 bits
are programmable by the input pins E0, E1, and E2 (see 表 5-3).
表 5-3. I2C Device Address
BIT 6
0
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
E0
0
1
1
E2
E1
MSB
LSB
To write data, the device is addressed using the specified I2C device address with R/W = 0, followed by
the upper 8 bits of the first address to be written and the lower 8 bits of that address. Next (without a
repeated START), the data to be written starting at the specified address is received. With each data byte
received, the address is automatically incremented by 1. The write access is terminated by the STOP
condition on the I2C bus.
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Device Address
SDA
Address Bits 15-8
Address Bits 7-0
Driven by:
Master
Slave (NFC Tag)
Data @ Addr + 0
Data @ Addr + 1
Data @ Addr + n
SDA
Driven by:
Master
Slave (NFC Tag)
图 5-2. I2C Write Access
注
The minimum I2C write transaction is 2 address bytes and 2 data bytes. Writes with only one
1 byte cause the data to be ignored. Avoid a transaction less than 1 data byte, as it results in
an error.
To read data, the device is addressed using the specified I2C device address with R/W = 0, followed by
the upper 8 bits of the first address to be read and then the lower 8 bits of that address. Next, a repeated
START condition is expected with the I2C device address and R/W = 1. The device then transmit data
starting at the specified address until a not acknowledge (NACK) and a STOP condition are received.
Device Address
Address Bits 15-8
Address Bits 7-0
Device Address
SDA
Driven by:
Master
Slave (NFC Tag)
Data @ Addr + 0
Data @ Addr + 1
Data @ Addr + n
SDA
Driven by:
Master
Slave (NFC Tag)
图 5-3. I2C Read Access
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5.6.1 I2C Examples
图 5-4 and 图 5-5 show examples of I2C accesses to the Control and Status registers, respectively.
Comments are provided on the tags in the figures.
5.6.1.1 I2C Write
.
/
9
!
5
图 5-4. I2C Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x16 (RF Enable
= 1)
A. I2C_READY signal, by being high indicates that I2C communication can be started.
B. The device address (18h because E0 = E1 = E2 = 0) is being transmitted out.
C. Register address is 0xFFFEh (which is the Control register).
D. I2C_READY line is now low, new I2C communication should not be started.
E. The data to write is transmitted (0016h).
5.6.1.2 I2C Read
.
/
5
D
9
!
C
I
图 5-5. I2C Access Example: Read of the Status Register at Address 0xFFFC, Responds With 0x00, 0x01
(Device_Ready = 1)
A. I2C_READY signal, by being high indicates that I2C communication can be started.
B. Packet has started: the device address (18h because E0 = E1 = E2 = 0) is being sent out.
C. Address FFFCh next is transmitted, which is the address of the status register.
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D. An I2C restart was done and device address sent with a read selection.
E. Clock stretching is being used by the RF430CL331H when it needs more time to respond due to
unfinished internal processing.
F. I2C_READY line is now low, new I2C communication should not be started.
G. RF430CL331H drives the SDA line and returns the value of the status register, which is 0001h.
H. I2C_READY signal has returned to high, indicating communication can be started. This occurs after a
short period of time after a STOP condition (in square red). This brief time is necessary for the
RF430CL331H to finish internal processing.
5.6.2 BIP-8 Communication Mode With I2C
The BIP-8 communication mode is enabled by setting the BIP-8 bit in the General Control register. All
communication after setting this bit uses the following conventions with exactly 2 address bytes (16-bit
address) and 2 data bytes (16-bit data) (see 表 5-4 and 表 5-5).
表 5-4. Write Access
Address Bits
15 to 8
Address Bits
7 to 0
Master
Slave
Data at Addr + 0
N/A
Data at Addr + 1
N/A
BIP-8
N/A
N/A
N/A
The Bit-Interleaved Parity (BIP-8) is calculated using 16-bit address and 16-bit data. If the received BIP-8
does not match with received data, no write is performed. The BIP-8 calculation does not include the I2C
device address.
表 5-5. Read Access
Address Bits
15 to 8
Address Bits
7 to 0
Master
Slave
N/A
N/A
N/A
N/A
N/A
Data at Addr + 0
Data at Addr + 1
BIP-8
For read access, the Bit-Interleaved Parity (BIP-8) is calculated using the received 16-bit address and the
2 transmitted data bytes, and it is transmitted back to the master. The BIP-8 does not include the device
address.
5.7 NFC Type 4B Tag Platform
This device is an NFC Forum Type 4B Tag Platform and ISO/IEC 14443B-compliant transponder that
operates according to the NFC Forum Tag Type-4 specification and supports NDEF (NFC Data Exchange
Format) data structure. Through the RF interface, the user can read and update the contents in the NDEF
memory. The NDEF message in its entirety would only be present on the memory of the host controller.
The RF430CL331H only has a portion of the NDEF message at any one time.
注
This device does not have nonvolatile memory; therefore, the information stored in the NDEF
memory is lost when power is removed.
This device does not support the peer-to-peer mode or the reader/writer mode. All RF communication
between an NFC forum device and this device is in the passive tag mode. The device responds by load
modulation and is not considered an intentional radiator.
This device is intended to be used in applications where the primary reader/writer is, for example, an NFC-
enabled handset. In this case, the host application can be considered the destination device, and the cell
phone or other type of mobile device is treated as the end-point device.
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This device supports ISO/IEC 14443-3, ISO/IEC 14443-4, and NFC Forum commands as described in the
following sections.
The device supports data rates of 106, 212, 424, and 848 kbps.
Even though all data rates up to 848 kbps are supported, the device by default reports only the capability
to support 106 kbps to the PCD. To change this behavior, use the sequence described in 节 5.7.3.
The device always answers ATTRIB commands from the PCD that request higher data rates. The NFC
Forum specifies for NFC-B a maximum data rate of 106 kbps. It is assumed that an NFC-compliant PCD
would not request higher data rates, thus, no interoperability issues are expected.
The NFC Forum Type 4B Tag Platform and ISO/IEC 14443B command and response structure is detailed
in ISO/IEC 14443-3, ISO/IEC 14443-4, and NFC Forum-TS-Digital Protocol. The applicable ISO/IEC 7816-
4 commands are detailed in NFC Forum-TS-Type-4-Tag_2.0.
5.7.1 ISO/IEC 14443-3 Commands
These commands use the character, frame format, and timing that are described in ISO/IEC 14443-3,
clause 7.1. The following commands are used to manage communication:
REQB and WUPB
The REQB and WUPB commands sent by the PCD are used to probe the field for PICCs of Type B. In
addition, WUPB is used to wake up PICCs that are in the HALT state. The number of slots N is
included in the command as a parameter to optimize the anticollision algorithm for a given application.
Slot-MARKER
After a REQB or WUPB command, the PCD may send up to (N – 1) Slot-MARKER commands to
define the start of each timeslot. Slot-MARKER commands can be sent after the end of an ATQB
message received by the PCD to mark the start of the next slot or earlier if no ATQB is received (no
need to wait until the end of a slot, if this slot is known to be empty).
ATTRIB
The ATTRIB command sent by the PCD includes information required to select a single PICC. A PICC
receiving an ATTRIB command with its identifier becomes selected and assigned to a dedicated
channel. After being selected, this PICC only responds to commands defined in ISO/IEC 14443-4 that
include its unique CID.
HLTB
The HLTB command is used to set a PICC in HALT state and stop responding to a REQB.
After answering to this command, the PICC ignores any commands except the WUPB.
5.7.2 NFC Tag Type 4 Commands
Select
Selection of applications or files
Read Binary
Read data from file
Update Binary
Update (erase and write) data to file
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5.7.3 Data Rate Settings
The device supports data rates of 106, 212, 424, and 848 kbps.
The device always answers ATTRIB commands from the PCD that request higher data rates. The NFC
Forum specifies for NFC-B a maximum data rate of 106 kbps. It is assumed that an NFC-compliant PCD
would not request higher data rates, thus, no interoperability issues are expected.
Even though all data rates up to 848 kbps are supported, the device by default reports only the capability
to support 106 kbps to the PCD.
To change this behavior, follow these steps using the I2C serial interface:
1. If you do not want to support all data rates up to 848 kbps, change the Data Rate Capability byte
according to 表 5-7. 表 5-6 summarizes how to write the data rate, and the Data Rate Capability byte is
set by the DATA 0 value in Step 3. Write Access.
2. Do the steps of the selected sequence. It is important to execute this sequence (in 表 5-6) before
setting the Control register.
注
The General Control register (see 节 5.11.1) is set to 0 after the sequence is completed in 表
5-6.
表 5-6. Data Rate Setting Sequence
ADDRESS BITS
15 TO 8
ADDRESS BITS
7 TO 0
ACCESS TYPE
DATA 0
DATA 1
1. Write Access
2. Write Access
3. Write Access
4. Write Access
5. Write Access
0xFF
0xFF
0x2A
0x27
0xFF
0xE0
0xFE
0xBA
0xB8
0xE0
0x4E
0x80
0x00
0x00
0x00
0x00
0x00
(1)
0xF7
0x00
0x00
(1) Data Rate Capability according to 表 5-7. 0xF7: all data rates up to 848 kbps are supported.
表 5-7. Data Rate Capability
DATA RATA CAPABILITY BYTE
DESCRIPTION
B7
0
1
x
B6
0
x
B5
0
x
B4
0
x
B3
0
B2
0
x
B1
0
x
B0
0
x
PICC supports only 106 kbps in both directions (default).
0
Same data rate from PCD to PICC and from PICC to PCD compulsory
PICC to PCD, data rate supported is 212 kbps
PICC to PCD, data rate supported is 424 kbps
PICC to PCD, data rate supported is 848 kbps
PCD to PICC, data rate supported is 212 kbps
PCD to PICC, data rate supported is 424 kbps
PCD to PICC, data rate supported is 848 kbps
x
x
1
x
0
x
x
x
x
x
1
x
0
x
x
x
x
1
x
x
0
x
x
x
x
x
x
0
x
x
1
x
x
x
x
x
0
x
1
x
x
x
x
x
0
1
x
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5.8 NDEF Structure
The NDEF message in its entirety is not stored at any time on the PICC. The host controller writes to the
buffer memory as the NFC Type 4 requests come in.
表 5-8 shows the mandatory structure. This NDEF message would be present on the memory of the host
controller. For more information, refer to the NFC Forum Type 4 Tag Operation Specification (see 节 6.2).
表 5-8. NDEF Application Data
2B - CCLen
(1)
1B - Mapping version
(2)
2B - MLe = 000F9h
2B - MLc = 000F6h
Capability Container
1B - Tag = 04h
Selectable by
File ID = E103h
1B - Len = 06h
NDEF Application
Selectable by Name =
D2760000850101h
The NDEF file
control TLV is
mandatory
2B - File Identifier
2B - Maximum file size
1B - Read access
1B - Write access
NDEF File Ctrl TLV
6B - Val
2B - Len
NDEF File
Selectable by
File ID = xxyyh
Mandatory NDEF
file
xB - Binary NDEF file content
yB - Unused if Len < Maximum file size in File Ctrl TLV
(1) RF430CL331H only supports mapping version up to 2.0.
(2) RF430CL331H specific
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表 5-9. NDEF Application Data (Includes Proprietary Sections)
2B - CCLen
(1)
1B - Mapping version
(2)
2B -MLe = 000F9h
(2)
2B -MLc = 000F6h
1B - Tag = 04h
1B - Len = 06h
The NDEF file
control TLV is
mandatory
2B - File Identifier
2B - Maximum file size
1B - Read access
1B - Write access
NDEF File Ctrl TLV
6B - Val
1B - Tag = 05h
1B - Len = 06h
Capability Container
Selectable by
File ID = E103h
2B - File Identifier
2B - Maximum file size
1B - Read access
1B - Write access
Proprietary File Ctrl
TLV (1)
6B - Val
NDEF Application
Selectable by Name =
D2_7600_0085_0101h
Zero or more
proprietary file
control TLVs
⋮
1B - Tag = 05h
1B - Len = 06h
2B - File Identifier
2B - Maximum file size
1B - Read access
1B - Write access
Proprietary File Ctrl
TLV (N)
6B - Val
2B - Len
NDEF File
Selectable by
File ID = xxyyh
Mandatory NDEF
file
xB - Binary NDEF file content
yB - Unused if Len < Maximum file size in File Ctrl TLV
2B - Len
Proprietary File (1)
Selectable by
File ID = xxyyh
Optional
proprietary file
xB - Binary proprietary file content
yB - Unused if Len < Maximum file size in File Ctrl TLV
⋮
2B - Len
Proprietary File (N)
Selectable by
File ID = xxyyh
Optional
proprietary file
xB - Binary proprietary file content
yB - Unused if Len < Maximum file size in File Ctrl TLV
(1) RF430CL331H only supports mapping version up to 2.0.
(2) RF430CL331H specific
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5.9 Typical Operation
图 5-6 shows typical operation of this device. Generally, on power up or reset, the host controller initializes
this device and then enables the RF. When a PCD approaches the dynamic tag, it starts by performing
the ISO14443-B anticollision sequence. This portion is handled automatically by the RF430CL331H.
Eventually the sequence reaches the NFC Type 4 level. When the PCD issues a file select, Read Binary
or Update Binary commands, the RF430CL331H interrupts the host controller by asserting the INT0 pin to
request the necessary information or act on the information. Each type of interrupt request is detailed in
the following sections.
PCD/Mobile
PICC/Dynamic Tag
Host Controller
Enables RF field
Handled
automatically
ISO/IEC 14443B Layer 3
RF
RF
NDEF tag application
select
Handled
automatically
RF
RF
Yes
Responds based
on existence of
file
Sets up registers for
host controller
Select file?
RF
Interrupt, Then I2C
No
Sets up Layer 4
response
L2/
Deselect
command sent
RF
Turn off RF field
RF
No
Sets up the Layer 4
read or write request
by configuring
Yes
Services the
Layer 4 read or
write request
Read or write
needed?
RF
Interrupt, Then L2/
registers or the buffer
Formats response
into Type 4 format
图 5-6. High-Level Flow
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5.9.1 NDEF or Capability Container Select Procedure
This select procedure does not change between selection of the capability container or an NDEF file.
These two types of selects can be differentiated by the file identifier that the RF430CL331H reports in the
NDEF File Identifier register (see 节 5.11.7).
For the general flow, see 图 5-7.
Dynamic NFC Tag
Reader (PCD)
Host Controller
(PICC)
Configures the
registers to
PCD sends the Select File
request with a file identifier
describe the
request and then
asserts the
INTO
Interrupt
Reads the file ID
from the registers
Does the file
exist?
RF
RF
interrupt
Examines the
response and
converts it to a
Type 4 protocol
format and sends
it to the PCD
Decides whether to
proceed with reading or
writing
Sets the Host
Response register
accordingly
I2C
Yes/No
图 5-7. Select System Flow
The procedure:
1. PCD procedure:
(a) Issues a Capability Container or a NDEF File Select command.
2. RF430CL331H procedure:
(a) Receives the RF packet.
(b) Sets the NDEF File Identifier register (see 节 5.11.7) using the file identifier that was included in
the packet from the PCD.
(c) Sets up the Status register (see 节 5.11.2) and the interrupt registers (see 节 5.11.3) to describe
the file select request.
(d) Ensure that General Type 4 request interrupt is enabled to generate the required interrupt on the
INTO pin.
3. Host controller procedure:
(a) Interrupt is received.
(b) Checks the source of the interrupt by reading the interrupt registers (see 节 5.11.3).
(c) The source of the interrupt is the General Type 4 request.
(d) When there is a General Type 4 request, the Status register (see 节 5.11.2) must be read and the
Type 4 Command field examined to determine what Type 4 command has been received.
(e) The result is a File Select command.
(f) The NDEF File Identifier register (see 节 5.11.7) should be read.
(g) The host controller should, search its available files and determine if the file exists.
(h) The interrupt must be cleared by writing to the Interrupt Flag register (see 节 5.11.3). This step
must be done before setting the Interrupt Serviced field in the Host Response register (see 节
5.11.8).
(i) If a specific Status Word (SW) response is necessary (generally for communicating specific error
conditions) to the Select command:
(i) Set the Custom Status Word Response register (see 节 5.11.13) with the desired status word.
(ii) Set the Use Custom SW Response bit in the Host Response register (see 节 5.11.8).
(j) To complete servicing the Select command interrupt, set the Interrupt Serviced field in the Host
Response register (see 节 5.11.8).
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Servicing of the Select command is complete.
4. RF430CL331H procedure:
(a) If the custom Status Words (SW) feature was not used:
(i) If the host controller indicated that the file existed, the response to the PCD is SW1 = 90h and
SW2 = 00h.
(ii) If the host controller indicated that the file did not exist, the response to the PCD is SW1 = 6Ah
and SW2 = 82h.
(b) If the custom response feature was used, the response to the PCD is what was set in the Custom
Status Word Response register (see 节 5.11.13).
5.9.2 NDEF or Capability Container Read Binary Procedure
This read procedure does not change between when the PCD reads the Capability Container or an NDEF
file. These two types of reads can be differentiated by the file identifier that the RF430CL331H reports in
the NDEF File Identifier register (see 节 5.11.7).
For the general flow, see 图 5-8.
Reader (PCD)
RF430CL331H (PICC)
Host Controller
Is the data
already
available?
Responds with the
data over the
serial bus
ReadBinary command is
sent
No/Interrupt
INTO
RF
If necessary
Yes
PCD processes the data
and possibly repeats the
cycle
Sends the data
using ISO14443-B
protocol
RF
L2/
图 5-8. Read System Flow
The procedure:
1. PCD procedure:
(a) Issues a Capability Container or a NDEF Read Binary command.
2. RF430CL331H procedure:
(a) Receives the RF packet.
(b) Checks its buffer and determines if all of the requested data in the Read Binary command exists
already in the buffer.
(c) If all the data is available in the buffer then (in the case that extra data was written in a previous
read request):
(i) No interrupt is issued to the host controller.
(ii) The data is supplied in the response packet to the PCD automatically.
(iii) The status word response SW1 = 90h and SW2 = 00h is appended to the packet.
(iv) The flow returns to wait for the next Type 4 request.
(d) If no data or only partial data is available, then an interrupt is issued to the host controller.
3. Host controller procedure:
(a) An interrupt is received.
(b) Checks the source of the interrupt by reading the interrupt registers (see 节 5.11.3).
(c) The source of the interrupt is the General Type 4 request.
(d) When there is a General Type 4 request, the Status register (see 节 5.11.2) must be read and the
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Type 4 Command field examined to determine what Type 4 command has been received.
(e) The result is a Read Binary command.
(f) The NDEF File Identifier register (see 节 5.11.7) may be read, but it is not necessary as it is
always the file that the last Select command selected.
(g) Read the Buffer Start register (see 节 5.11.11) to determine where in the buffer of the
RF430CL331H to begin storing the data.
(h) Read the NDEF File Offset register (see 节 5.11.10) to determine at which index in the NDEF or
CC file to begin supplying the data to the RF430CL331H.
(i) Read the NDEF Block Length register (see 节 5.11.9) to determine what block length the PCD is
requesting.
(j) Check if the request is valid:
(i) If it is valid, write the data into the buffer of the RF430CL331H starting at Buffer Start index for
NDEF Block Length bytes.
(ii) If it is not valid, assert the Custom Status Word option in the Host Response register (see 节
5.11.8) and write the custom word in the Custom Status Word Response register (see 节
5.11.13). Only the status word response supplied will be sent out.
(k) If caching is desirable, extra sequential data can be written to the RF430CL331H buffer, up to the
maximum RF430CL331H buffer length (length is 3000 bytes, highest index is 2999).
注
To improve the Read Binary performance of the RF430CL331H , a caching feature may
be used. After writing the requested Read Binary request data into the RF430CL331H
buffer, extra sequential data may be written. If on the next Read Binary request, all of the
requested data is in the buffer, the RF430CL331H automatically responds and services
that request without any intervention of the host controller; that is, no interrupt is issued.
(l) Update the NDEF Block Length register (see 节 5.11.9) with the number of bytes written into the
buffer.
(m) The interrupt must be cleared by writing to the Interrupt Flag register. This step must be done
before setting the Interrupt Serviced field in the Host Response register.
(n) To complete servicing the Read Binary command interrupt, set the Interrupt Serviced field in the
Host Response register.
4. RF430CL331H procedure:
(a) Only the requested data (even if extra was supplied) is included in the response packet to the
PCD. The status words are appended to the response packet per NFC Type 4 specification.
(b) If the command was valid, the status words are SW1 = 90h and SW2 = 00h.
(c) If the custom response feature was used, the response to the PCD is only what was set in the
Custom Status Word Response register.
5.9.2.1 NDEF Read Command Internal Buffer Handling
Entire Buffer Space (not to scale)
N (<255 bytes)
0
1. PCD œ ReadBinary Request
2. Host œ Service Request
3. PCD œ Next ReadBinary
Data Requested
Fill block with data
Data Requested
Previous block cleared
and new data starts at
buffer_start_index of 0
4. Next Request: Cycle repeats
图 5-9. Read Buffer Flow (no extra data)
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In normal read mode, when Read Prefetch functionality has not been enabled, each Read Binary request
that comes in, is passed to the host controller and the internal state machine is in blocking mode until the
data is sent back to the RF430CL331H . The RF430CL331H uses the same memory for each request, it is
no more than the size of the read request packet length.
5.9.2.2 NDEF Read Command Internal Buffer Handling (With Caching)
Entire Buffer Space (not to scale)
0
1. PCD œ ReadBinary Request
(interrupt):
Data Requested
2. Host œ Service Request
More data supplied than required - caching
Automatically Sending
Sent
3. PICC œ Next Request (no interrupt):
Sent
Sent
4. PICC œ Next Request (insufficient data):
Cached
Buffer shifted internally
(then interrupt)
Have
Need
0
L
N
Request Parameters:
buffer_start_index = L
length_requested = N - L
5. Host œ Service Request:
Sending
6. Next Request: Cycle repeats
图 5-10. Read Buffer Flow (with caching)
1. PCD requests a block of data. PICC received the requests, sets up the internal register and asserts the
INTO interrupt.
2. Host controller supplies the request but also adds more data on the file that is continuous with this
request.
3. The next PCD request is fulfilled automatically because the data that is requested is already in the
buffer. The host controller is not interrupted.
4. The next PCD request has insufficient data, so the data that is available is shifted to the beginning of
the buffer and the unavailable data is requested.
5. The full request is transmitted out.
6. The cycle can repeat.
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5.9.3 NDEF or Capability Container Read Procedure (Prefetch Feature)
The read prefetch feature includes the standard read procedure. However, after the requested data is
written into the RF430CL331H buffer, when the RF430CL331H starts to transmit the requested data over
the air, another interrupt is issued to the host controller indicating that extra data can be appended to the
RF430CL331H buffer. The host controller can start adding data to the buffer while the RF430CL331H is
transmitting over RF, because two tasks are happening at once, this increases the throughput of the
system. For optimum operation, the host controller should cease to write extra data before the next
interrupt. If the host controller does not cease to write, latency is introduced into the system, which can
accumulate until requests start to time out. To determine how much is available to write the prefetch data,
the time to send out the packet (that was requested) over RF can be calculated.
To enable read prefetch feature, the Read Prefetch interrupt must be enabled in the Interrupt Enable
register (see 节 5.11.3).
For a general flow, see 图 5-11.
RF430CL331H (PICC)
Host Controller
Reader (PCD)
Is the data
already
available?
Responds with the
data over the data
bus
ReadBinary command is
sent
No/Interrupt
INTO
RF
If necessary
Yes
Starts
transmitting the
data over RF
PCD processes the data
and possibly repeats the
cycle
L2/
Sends the extra
data while the RF
transmission is
ongoing
Then asserts INTO
interrupt
INTO
Interrupt (Second)
Stores it in the
RAM cache (to be
used later if
I2C
necessary)
图 5-11. Read System Flow (Prefetch Feature)
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The procedure:
1. PCD procedure:
(a) Issues a Capability Container or a NDEF Read Binary command.
2. Dynamic Tag/RF430CL331H procedure:
(a) Receives the RF packet.
(b) Checks its buffer and determines if all of the requested data in the Read Binary command exists
already in the buffer.
(c) If all the data is available in the buffer then (in the case that extra data was written in a previous
read request)
(i) No General Type 4 interrupt is issued to the host controller.
(ii) The data is supplied in the response packet to the PCD automatically.
(iii) The status word response SW1 = 90h and SW2 = 00h is appended to the packet.
(iv) The flow now goes to Step 4e.
(d) If no data or only partial data is available, then a General Type 4 interrupt is issued to the host
controller.
3. Host controller procedure:
(a) Interrupt is received.
(b) Checks the source of the interrupt by reading the interrupt registers (see 节 5.11.3).
(c) The source of the interrupt is the General Type 4 request.
(d) When there is a General Type 4 request, the Status register (see 节 5.11.2) must be read and the
Type 4 Command field examined to determine what Type 4 command has been received.
(e) The result is a Read Binary command.
(f) The NDEF File Identifier register (see 节 5.11.7) may be read, but it is not necessary as it is
always the file that the last Select command selected.
(g) Read the Buffer Start register (see 节 5.11.11) to determine where in the buffer of the
RF430CL331H to begin storing the data.
(h) Read the NDEF File Offset register (see 节 5.11.10) to determine at which index in the NDEF or
CC file to begin supplying the data to the RF430CL331H.
(i) Read the NDEF Block Length register (see 节 5.11.9) to determine what block length the PCD is
requesting.
(j) Check if the request is valid:
(i) If it is valid write the data into the buffer of the RF430CL331H starting at Buffer Start index for
NDEF Block Length bytes.
(ii) If it is not valid, assert the Custom Status Word option in the Host Response register (see 节
5.11.8) and write the custom word in the Custom Status Word Response register (see 节
5.11.13). Only the status word response supplied will be sent out.
(k) Write the requested amount of data to the buffer starting at the Buffer Start register index.
注
Read caching (writing data beyond the request in a General Type 4 request interrupt)
should be avoided with the prefetch feature, because caching, at least initially, creates
latency because the system is waiting (blocking) for the General Type 4 request interrupt
to complete. Instead, in prefetch mode, only the requested data should be supplied in the
General Type 4 request interrupt. When the Extra Data interrupt occurs afterwards (in
tandem with the RF transmission), only then as much as possible extra data should be
written to the buffer.
(l) Update the NDEF Block Length register with how much bytes were written into the buffer.
(m) The interrupt must be cleared by writing to the Interrupt Flag register. (This step must be done
before setting the Interrupt Serviced field in the Host Response register.)
(n) To complete servicing the Read Binary command interrupt, set the Interrupt Serviced field in the
Host Response register.
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4. Dynamic Tag RF430CL331H procedure:
(a) Only the requested data (even if extra was supplied) is included in the response packet to the
PCD. The status words are appended to the response packet per NFC Type 4 specification.
(b) If the command was valid, the status words are SW1 = 90h and SW2 = 00h.
(c) If the custom response feature was used, the response to the PCD is what was set in the Custom
Status Word Response register.
(d) RF transmission starts, the Extra Data interrupt is always asserted.
5. The host controller must service the Extra Data interrupt by appending to the buffer extra sequential
data up until the buffer size (3000 bytes).
(a) Checks the source of the interrupt by reading the interrupt registers.
(b) The interrupt is an Extra Data interrupt.
(c) Read the Buffer Start register to determine where in the buffer of the RF430CL331H to begin
storing the data.
注
When the Extra Data interrupt is enabled, the interrupt always occurs when the
RF430CL331H is responding to the Read Binary request. However, this does not mean
that every interrupt service can add to the RF430CL331H buffer (3000 bytes). If the
Buffer Start register read indicates its index is at the end of the buffer, then no more data
can be added. In this case the NDEF Block Length register should be set to 0 indicating
that no data was added to the buffer. On the next Read Binary request, the valid data in
the RF430CL331H buffer is shifted to the beginning to allow more room for extra data to
be appended again.
(d) NDEF File Offset register can be read.
(e) Write sequential extra data to the buffer starting at the Buffer Start register index.
(f) The time limit of writing extra data to the buffer is until the next Read Binary command is
completed to be transmitted to the RF430CL331H. After that point, latency starts to be introduced
into the system as the processing of the new packet is delayed.
(g) Update the NDEF Block Length register with how many bytes were written into the buffer. If none,
set to 0.
(h) The prefetch interrupt must be cleared by writing to the Interrupt Flag register.
(i) Set the Extra Data Send In bit in the Host Response register.
(j) This completes servicing of the Read Prefetch interrupt.
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5.9.3.1 NDEF Read Command With Prefetch Internal Buffer Handling
Entire Buffer Space (not to scale)
0
N (<255 bytes)
1. PCD œ Read Binary Request
2. Host œ Service Request
Block Requested
Filling Block
3. PCD/Host œ Data Being Transmitted (prefetch interrupt): Being Transmitted
Filling Now
Being Transmitted
Sent
4. PCD/Host œ Next Request (only prefetch interrupt):
Sent
Sent
Filling Now
5. PCD/Host œ Next Request (only prefetch interrupt):
6. PCD œ Next Request (General Type 4 Request interrupt)
Buffer shifted internally:
Being Transmitted Filling
(up to limit)
Have
Need
0
L
N
Request Parameters:
buffer_start_index = L
length_requested = N - L
7. Host œ Service Request:
Sending
8. Next: Cycle repeats (to Step 3)
图 5-12. Read Buffer Flow (Prefetch Feature)
The key feature with Prefetch is that while the Read Binary is being transmitted, the next packet can be
sent out by the host controller and be filling the internal RF430CL331H buffer. Each request is stored in
the subsequent buffer memory until the buffer limit is reached. When the buffer limit is reached, the
remaining unsent data is shifted to the beginning of the buffer and what data is needed for the next
request is requested (see Step 6). This command is requested using the General Type 4 request interrupt
(not with a prefetch interrupt) because it does not happen during the time when the RF430CL331H is
sending data over RF.
Read buffer flow procedure (see 图 5-12):
1. PCD requests a block of data.
2. PICC received the requests, sets up the internal register and asserts the INTO interrupt.
3. Host services the interrupt by supplying the data. PICC transmits the data. After starting to transmit the
data, PICC issues a Read Prefetch interrupt. The host supplies the extra data while the RF
communication is ongoing.
4. When the next Read Binary request comes, because the data is already cached, only the Prefetch
interrupt is asserted.
5. This time a Prefetch interrupt is asserted, but only a portion of the data can be written because the
buffer space is running out.
6. Because there is not enough data to service the Read Binary requests, a General Type 4 interrupt is
asserted. The partial data that has been written previously is shifted to the beginning of the buffer and
the only the remaining missing data is requested in the interrupt.
7. The complete data is sent out. The cycle repeats (the Prefetch interrupt is issued again).
If a prefetch interrupt is issued for a file, but there is no more data to send, this interrupt can be canceled
by servicing it by setting the data length sent to 0. Also if data was sent by a prefetch but it was not
needed by the RF430CL331H (due to a different request by the PCD) that data is discarded and the new
request handling initiated.
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5.9.4 NDEF or Capability Container Write Procedure (Blocking)
This write procedure does not change between when the PCD writes the Capability Container or an NDEF
file. These two types of writes can be differentiated by the file identifier that the RF430CL331H reports in
the NDEF File Identifier register (see 节 5.11.7).
For a general flow, see 图 5-13.
RF430CL331H (PICC)
Reader (PCD)
Host Controller
After the RF
transmission is
complete, the PICC
configures the
registers to describe
the request and then
asserts the interrupt
PCD sends the File Write
request
INTO
Interrupt
RF
Reads the data
If necessary
Decides whether to continue
writing more data
Acknowledges the
read over RF
RF
I2C
图 5-13. Write System Flow (Blocking)
The procedure:
1. PCD procedure:
(a) Issues a Capability Container or a NDEF File Write (or Update Binary) command.
2. RF430CL331H procedure:
(a) Receives the RF Update Binary packet.
(b) Sets up the appropriate registers.
(c) Issues the General Type 4 request interrupt.
3. Host controller procedure:
(a) Checks the source of the interrupt by reading the interrupt registers (see 节 5.11.3).
(b) The source of the interrupt is the General Type 4 request.
(c) When there is a General Type 4 request, the Status register (see 节 5.11.2) must be read and the
Type 4 Command field examined to determine what Type 4 command has been received.
(d) The result is an Update Binary command.
(e) The NDEF File Identifier register (see 节 5.11.7) may be read, but it is not necessary as it is
always the file that the last Select command selected.
(f) Read the Buffer Start register (see 节 5.11.11) to determine where in the buffer of the
RF430CL331H to begin reading the stored data. Reading this register is unnecessary as it is
always 0.
(g) Read the NDEF File Offset register (see 节 5.11.10) to determine at which index of the NDEF or
CC file the current data is starting.
(h) Read the NDEF Block Length register (see 节 5.11.9) to determine how much data is being sent
by the PCD in this packet.
(i) Read the data from the buffer of the RF430CL331H starting at index of 0 until the block length
supplied, updating the main file on the host controller.
(j) If a specific Status Word (SW) response is necessary to the Update Binary command:
(i) Set the Custom Status Word Response register (see 节 5.11.13) with the desired status word.
(ii) Set the Use Custom SW Response bit in the Host Response register.
(k) The interrupt must be cleared by writing to the Interrupt Flag register. This step must be done
before setting the Interrupt Serviced field in the Host Response register.
(l) To complete servicing the Update Binary command interrupt, set the Interrupt Serviced field in the
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Host Response register.
4. RF430CL331H procedure:
(a) If the custom SW feature was not used, the response is status words SW1 = 90h and SW2 = 00h.
(b) If the custom response feature was used, the response to the PCD is what was set in the Custom
Status Word Response register.
5.9.4.1 NDEF Write Command (Blocking) Internal Buffer Handling
Entire Buffer Space (not to scale)
0
N (<255 bytes)
1. PCD œ Update Binary command
Block Available
Read This Block
(General Type 4 Request interrupt)
2. Host œ Service Request
3. PCD œ Next Update Binary command
Being Received
Block Available
4. PICC œ General Type 4 Request interrupt
Previous block cleared
and new data starts at
buffer_start_index of 0
图 5-14. Write Buffer Flow (Blocking)
The write with blocking stores the send in data packet until it is read out by the host controller. Once it has
been read out, the next write data packet is stored in the same section of memory. The cycle repeats with
more Update Binary packets.
5.9.5 NDEF or Capability Container Write Procedure (Nonblocking)
This command is different from the blocking operation in that the RF430CL331H automatically responds to
an Update Binary command with a success acknowledgment upon receiving the Update Binary packet.
After the acknowledgment, the PCD starts to send the next Update Binary block. The intent is to increase
throughput by downloading the previous Update Binary packet while the new one is being transmitted into
a separate buffer on the RF430CL331H.
Care must be taken to read out the entire packet before the new one is completely transmitted to the
RF430CL331H. Otherwise, this creates latency that, if not corrected, accumulates to the point where one
Update Binary packet request eventually times out.
To enable write nonblocking mode, set the Automatic ACK On Write field in the General Control register.
For a general flow, see 图 5-15.
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RF430CL331H (PICC)
Host Controller
Reader (PCD)
Stores the packet in the buffer
Reads the PICC
data buffer while
the next RF
transmission is
occurring
PCD sends the File Write
1.) Acknowledges the request
over RF
2.) Issues the interrupt
INTO
Interrupt (Second)
RF
request
If necessary
Decides whether to continue
RF (First)
writing more data
图 5-15. Write System Flow (Nonblocking)
1. PCD procedure:
(a) Issues a Capability Container or a NDEF File Write (or Update Binary) command.
2. RF430CL331H procedure:
(a) Receives the RF Update Binary packet.
(b) Automatically responds with a successful acknowledgment: SW1 = 90h and SW2 = 00h.
(c) Sets up the appropriate registers.
(d) Issues the General Type 4 request interrupt.
(e) Waits for a new Update Binary packet to be transmitted to.
3. Host controller procedure:
(a) Checks the source of the interrupt by reading the interrupt registers (see 节 5.11.3).
(b) The source of the interrupt is the General Type 4 request.
(c) When there is a General Type 4 request, the Status register (see 节 5.11.2) must be read and the
Type 4 Command field examined to determine what Type 4 command has been received.
(d) The result is an Update Binary command.
(e) The NDEF File Identifier register (see 节 5.11.7) may be read, but it is not necessary as it is
always the file that the last Select command selected.
(f) Read the Buffer Start register (see 节 5.11.11) to determine where in the buffer of the
RF430CL331H to begin reading the stored data. Reading this register is unnecessary, as it is
always 0.
(g) Read the NDEF File Offset register (see 节 5.11.10) to determine at which index of the NDEF or
CC file the current data is starting.
(h) Read the NDEF Block Length register (see 节 5.11.9) to determine how much data is being sent
by the PCD in this packet.
(i) Read the data from the buffer of the RF430CL331H, starting at the index of 0, until the block length
supplied, updating the main file on the host controller.
(j) The interrupt must be cleared by writing to the Interrupt Flag register. This step must be done
before setting the Interrupt Serviced field in the Host Response register.
(k) To complete servicing the Update Binary command interrupt, set the Interrupt Serviced field in the
Host Response register.
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5.9.5.1 NDEF Write Procedure (Nonblocking) Internal Buffer Handling
Entire Buffer Space (not to scale)
0
N (<255 bytes)
1. PCD œ UpdateBinary Command
Block Sent
2. PICC œ Automatic Acknowledgment
Block Available
and General Type 4 Interrupt
Reading out this block
Storing in temp buffer
3. Host œ Service Request
Concurrent
4. PCD œ Sending more data
5. Host œ Finishes reading out block
From temp buffer
6. PICC œ Automatic Acknowledgment
and General Type 4 Interrupt
7. Repeats
图 5-16. Write System Flow (Nonblocking)
The main difference in a nonblocking write operation is that when the data packet has been received from
the PCD, the host controller is reading out the packet while the next one is being sent in (see Steps 3 and
4 in 图 5-16). Data is received into a temporary buffer and when the last packet has been read out, the
data in the temporary buffer is copied into the standard buffer so the data can be accessed by the host
controller.
5.10 RF Command Response Timing Limits
Meeting specification timing is an important part of designing a stable and reliable system. There are
various timing parameters that must be considered in this system, and one of the most important is the RF
command response time.
The RF430CL331H negotiates the maximum allowable FWI timing (frame waiting time integer). This
negotiated setting is the maximum of 8 (NFC Digital Protocol Section A.2, NFC-B Technology, FWIMAX),
giving the time of approximately 77 ms. This is the time that the PCD allows to respond to any command.
The RF430CL331H implements an internal timer monitoring this FWI timing specification. The internal
timer defaults to approximately 55 ms instead of 77 ms due to variations in the internal oscillator
frequency. The 55 ms allows meeting the 77-ms specification across all devices reliably.
图 5-17 gives the command response timings. A detailed description follows.
I2C_READY
I2C_SIGNAL
Asserted
INTO
I2C (possible case)
Activity
Activity
55 ms
0 ms œ First time-out time
Second time-out time
2. PICC
prepares
registers and
issues an
interrupt to host
controller
4. PICC formats a
1. Select, Read,
Write Type 4
command sent
to PICC
5. Host controller has
this time to service the
interrupt
S(WTX) request
(see SWTX register)
and sends it over RF
3. Host controller has 55 ms
to service the interrupt
6. After this point,
PCD/Mobile either
sends a NACK
(which will not be
handled) or a
Deselect
command and
cycles the RF field
PICC starts
internal timer
(defaults to
55 ms)
Host controller has not
serviced the interrupt
(Host response register Bit
0 not set)
PCD stops listening and
issues a packet.
This time varies from PCD
to PCD.
图 5-17. Timing Limits
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1. The PCD issues a Type 4 command (Select, Read Binary, or Update Binary).
2. If this command needs host controller response, the RF430CL331H sets up the registers and asserts
INTO.
3. The RF430CL331H starts the internal initial timer of 55 ms.
4. If the host controller does not respond in 55 ms, (that is, the Host Response register Interrupt Serviced
Bit 0 is not set) the RF430CL331H sets the I2C_READY and I2C_SIGNAL pins to low, which.
I2C_SIGNAL is a signal that is asserted when there is an active S(WTX) request ongoing. During this
time the I2C communication does not have to be stopped.
5. After the PICC issues the wait time extension there is another period of time in which the host
controller has time to respond to the initial interrupt request.
6. At this time, the PCD sends out a packet. This point should be avoided, because this will likely mean
the PCD will break off communications..
7. After several milliseconds, the RF430CL331H issues an S(WTX) request to the PCD.
(a) The WTXM field in the Frame Wait Time Extension (see 节 5.11.12) is set with the value in the
SWTX register.
8. Sends the Wait Time Extension request.
9. Sets the I2C_SIGNAL and I2C_READY pins to high indicating that communication can continue.
10. If the host controller does not service the interrupt in a certain period of time (the internal timer
expires, but this does not produce an effect), the PCD issues a R(NACK) command. This and any
other command are not handled by the RF430CL331H; there is no response, because the
RF430CL331H command buffer still has the previous command that it has not serviced. Thus, the
command must be serviced after the first S(WTX) request.
11. If the PCD issues a command after the first S(WTX) command, it is likely to not be serviced, and this
typically results in a Deselect command with a field reset. The communication must be restarted.
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5.11 Registers
注
All 16-bit registers are in little-endian format: the least significant byte with bits 7-0 is at the
lowest address (this address is always even). The most significant byte with bits 15-8 is at
the highest address (this address is always odd).
5.11.1 General Control Register
表 5-10. General Control Register
ADDRESS
0xFFFF
15
14
13
12
11
10
9
8
Automatic
ACK On
Write
Reserved
ADDRESS
0xFFFE
7
6
5
4
3
2
1
0
Standby
Enable
Reserved
BIP-8
INTO Drive
INTO High
Enable INT
Enable RF
SW-Reset
表 5-11. General Control Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
Reserved for future use. Write with 0.
15-9
Reserved
R
0
0
0
0
Enabling this bit causes an automatic acknowledgment to be sent when an
Update Binary command is received. The buffer must be read out immediately
(possibly while a new Update Binary command is being received over RF).
8
7
6
Automatic ACK On Write
Reserved
R/W
R/W
R/W
0b = Manual acknowledgment of Update Binary command
1b = Automatic acknowledgment of Update Binary command
Enables a low-power standby mode. The standby mode is entered if the RF
interface is disabled, the communication watchdog is disabled, and no serial
communication is ongoing.
Standby Enable
0b = Standby mode disabled
1b = Standby mode enabled
Enables BIP-8 communication mode (bit interleaved parity).
If BIP-8 is enabled, a separate running tally is kept of the parity (that is, the
number of ones that occur) for every bit position in the bytes included in the
BIP-8 calculation. The corresponding bit position of the BIP-8 byte is set to 1 if
the parity is currently odd and is set to 0 if the parity is even – resulting in an
overall even parity for each bit position including the BIP-8 byte.
5
BIP-8
R/W
0
All communication when this bit is set must follow the conventions defined in
the BIP-8 communication mode sections in 节 5.6.2.
0b = BIP-8 communication mode disabled
1b = BIP-8 communication mode enabled
Configuration of the interrupt output pin INTO
0b = Pin is Hi-Z if there is no pending interrupt. Application provides an external
pullup resistor if bit 3 (INTO High) = 0. Application provides an external pull-
down resistor if bit 3 (INTO High) = 1.
4
3
INTO Drive
INTO High
R/W
R/W
0
0
1b = Pin is actively driven high or low if there is no pending interrupt. It is driven
high if bit 3 (INTO High) = 0. It is driven low if bit 3 (INTO High) = 1.
Configuration of the interrupt output pin INTO
0b = Interrupts are signaled with an active low
1b = Interrupts are signaled with an active high
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表 5-11. General Control Register Description (continued)
BIT
FIELD
TYPE RESET
DESCRIPTION
Global interrupt output enable
0b = Interrupt output disabled. The INTO pin is Hi-Z.
2
Enable INT
R/W
R/W
0
0
1b = Interrupt output enabled. The INTO pin signals any enabled interrupt
according to the INTO High and INTO Drive bits.
Global enable of RF interface. This bit must be set before the PICC can
respond to any RF commands.
1
0
Enable RF
SW-Reset
0b = RF interface disabled
1b = RF interface enabled
Software reset
0b = Always reads 0.
W
0
1b = Resets the device to default settings and clears memory. The serial
communication is restored after tReady, and the register settings and NDEF
memory must be restored afterward.
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5.11.2 Status Register
表 5-12. Status Register
ADDRESS
0xFFFD
15
7
14
6
13
5
12
11
10
9
1
8
0
Reserved
ADDRESS
0xFFFC
4
3
2
Type 4
Command
MSb
Type 4
Command
LSb
Reserved
Reserved
RF Busy
CRC Active Device Ready
表 5-13. Status Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
Reserved for future use. Write with 0.
15-6
Reserved
R
0
This is set after a NFC Type 4 command is received and only must be serviced
if a General Type 4 request interrupt has been asserted.
Bit 5 + Bit 4
00b = No Type 4 command has been received
01b = File Select Command has been received and must be serviced
10b = Read Binary command has been received and must be serviced
5-4
Type 4 Command
R
0
11b = Update Binary command has been received and must be serviced
Reserved for future use. Write with 0.
3
2
Reserved
RF Busy
R
R
0
0
0b = No RF communication ongoing
1b = RF communication ongoing
0b = No CRC calculation ongoing
1
0
CRC Active
R
R
0
0
1b = CRC calculation ongoing
0b = Device not ready
Device Ready
1b = Device ready for serial communication and control
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5.11.3 Interrupt Registers
The interrupt enable register (see 表 5-14 and 表 5-15) determines which interrupt events are signaled on
the external output pin INTO. Setting any bit high in this register allows the corresponding event to trigger
the interrupt signal. See 表 5-18 for a description of each interrupt.
All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO.
表 5-14. Interrupt Enable Register
ADDRESS
0xFFFB
15
14
13
12
11
10
2
9
8
Read
Prefetch
Reserved
ADDRESS
0xFFFA
7
6
5
4
3
1
0
CRC
Calculation
Completed
RF Field
Removed
General Type BIP-8 Error
4 Request Detected
Generic Error
Reserved
表 5-15. Interrupt Enable Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
Reserved for future use. Write with 0.
15-9
Reserved
R
0
Enable for the Read Prefetch IRQ. All enabled interrupt signals are ORed
together, and the result is signaled on the output pin INTO.
8
Read Prefetch
R/W
R/W
R/W
R/W
R/W
0
0b = IRQ disabled
1b = IRQ enabled
Enable for the Generic Error IRQ. All enabled interrupt signals are ORed
together, and the result is signaled on the output pin INTO.
7
6
5
4
Generic Error
0
0
0
0
0b = IRQ disabled
1b = IRQ enabled
Enable for the RF Field Removed IRQ. All enabled interrupt signals are ORed
together, and the result is signaled on the output pin INTO.
RF Field Removed
General Type 4 Request
BIP-8 Error Detected
0b = IRQ disabled
1b = IRQ enabled
Enable for the General Type 4 Request IRQ. All enabled interrupt signals are
ORed together, and the result is signaled on the output pin INTO.
0b = IRQ disabled
1b = IRQ enabled
Enable for the BIP-8 Error Detected IRQ. All enabled interrupt signals are
ORed together, and the result is signaled on the output pin INTO.
0b = IRQ disabled
1b = IRQ enabled
Enable for the CRC Calculation Completed IRQ. All enabled interrupt signals
are ORed together, and the result is signaled on the output pin INTO.
3
CRC Calculation Completed
Reserved
R/W
R
0
0
0b = IRQ disabled
1b = IRQ enabled
2-0
Reserved for future use. Write with 0.
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The interrupt flag register (see 表 5-16 and 表 5-17) is used to report the status of any interrupts that are
pending. Setting any bit high in this register acknowledges and clears the interrupt associated with the
respective bit. See 表 5-18 for a description of each interrupt.
表 5-16. Interrupt Flag Register
ADDRESS
0xFFF9
15
14
13
12
11
10
2
9
8
Read
Prefetch
Reserved
ADDRESS
0xFFF8
7
6
5
4
3
1
0
CRC
Calculation
Completed
RF Field
Removed
General Type BIP-8 Error
4 Request Detected
Generic Error
Reserved
表 5-17. Interrupt Flag Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
Reserved for future use. Write with 0.
15-9
Reserved
R
0
Flag pending Read Prefetch IRQ.
Read Access:
0b = No pending IRQ
1b = Pending IRQ
Write Access:
8
Read Prefetch
R/W
0
0b = No change
1b = Clear pending IRQ flag
Flag pending Generic Error IRQ.
Read Access:
0b = No pending IRQ
1b = Pending IRQ
Write Access:
7
6
5
Generic Error
R/W
R/W
R/W
0
0
0
0b = No change
1b = Clear pending IRQ flag
Flag pending RF Field Removed IRQ.
Read Access:
0b = No pending IRQ
1b = Pending IRQ
Write Access:
RF Field Removed
0b = No change
1b = Clear pending IRQ flag
Flag pending General Type 4 Request IRQ.
Read Access:
0b = No pending IRQ
1b = Pending IRQ
Write Access:
General Type 4 Request
0b = No change
1b = Clear pending IRQ flag
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表 5-17. Interrupt Flag Register Description (continued)
BIT
FIELD
TYPE RESET
DESCRIPTION
Flag pending BIP-8 Error Detected IRQ.
Read Access:
0b = No pending IRQ
1b = Pending IRQ
Write Access:
4
BIP-8 Error Detected
R/W
0
0b = No change
1b = Clear pending IRQ flag
Flag pending CRC Calculation Completed IRQ.
Read Access:
0b = No pending IRQ
1b = Pending IRQ
Write Access:
3
CRC Calculation Completed
R/W
0
0
0b = No change
1b = Clear pending IRQ flag
2-0
Reserved
R
Reserved for future use. Write with 0.
表 5-18. Interrupts
INTERRUPT
DESCRIPTION
This IRQ occurs when a CRC calculation that is triggered by writing into the CRC registers is completed
and the result can be read from the CRC result register (see 节 5.11.4).
CRC Calculation Completed
BIP-8 Error Detected
This IRQ occurs when a BIP-8 error is detected (only if the BIP-8 communication mode is enabled).
This IRQ occurs if a NFC Type 4 command has been received (Select, Read Binary, Update Binary) and
requires the service of the host controller.
General Type 4 Request
This IRQ occurs when at least NDEF Tag Application Select command has been received and after that
the RF field is removed.
RF Field Removed
Generic Error
This IRQ occurs for any error that makes the device unreliable or nonoperational.
This IRQ occurs immediately after Read Binary request has been serviced (automatically or manually) and
the RF transmission has been started. This allows RF transmission and I2C communication to happen at
the same time.
Read Prefetch
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5.11.4 CRC Registers
Writing the CRC address and the CRC length registers initiates a 16-bit CRC calculation of the specified
address range. The length is always assumed to be even (16-bit aligned). Writing the length register starts
the CRC calculation.
During the CRC calculation, the CRC active bit is set (= 1). When the calculation is complete, the CRC
completion interrupt flag is set and the result of the CRC calculation can be read from the CRC result
register. TI recommends performing a CRC calculation only when the RF interface is disabled (RF Enable
= 0).
表 5-19. CRC Result Register
ADDRESS
0xFFF7
15
7
14
6
13
12
11
10
2
9
1
8
0
CRC CCITT Result (high byte)
ADDRESS
0xFFF6
5
4
3
CRC CCITT Result (low byte)
表 5-20. CRC Result Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
15-0
CRC-CCITT Result
R
0
CRC-CCITT Result
表 5-21. CRC Length Register
ADDRESS
0xFFF5
15
7
14
6
13
12
11
10
2
9
1
8
0
CRC Length (high byte)
ADDRESS
0xFFF4
5
4
3
CRC Length (low byte)
表 5-22. CRC Length Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
CRC Length. Always assumed to be even (Bit 0 = 0). Writing into high byte
starts CRC calculation.
15-0
CRC Length
RW
0
表 5-23. CRC Start Address Register
ADDRESS
0xFFF3
15
7
14
6
13
12
11
10
2
9
1
8
0
CRC Start Address (high byte)
ADDRESS
0xFFF2
5
4
3
CRC Start Address (low byte)
表 5-24. CRC Start Address Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
CRC Start Address. Defines start address within NDEF memory. This address
is always assumed to be even (bit 0 = 0).
15-0
CRC Start Address
RW
0
The CRC is calculated based on the CCITT polynomial initialized with 0xFFFF.
CCITT polynomial: x16 + x12 + x5 + 1
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5.11.5 Communication Watchdog Register
When the communication watchdog is enabled, it expects a write or read access within a specified period;
otherwise, the watchdog resets the device. If the BIP-8 communication mode is enabled, the transfer must
be valid to be accepted as a watchdog reset.
表 5-25. Communication Watchdog Register
ADDRESS
0xFFF1
15
7
14
6
13
12
11
10
9
1
8
Reserved
ADDRESS
0xFFF0
5
4
3
2
0
Reserved
Time-out Period Selection
Enable
表 5-26. Communication Watchdog Register Description
RESE
T
BIT
FIELD
TYPE
DESCRIPTION
15-4 Reserved
R
0
Reserved for future use. Write with 0.
(1)
000b = 2 s ±30%
001b = 32 s ±30%
010b = 8.5 min ±30%
(1)
Time-out Period
Selection
3-1
0
R/W
0
(1)
011b to 111b = Reserved
0b = Communication Watchdog disabled
Enable
R/W
0
1b = Communication Watchdog enabled
(1) This value is based on use of the integrated low-frequency oscillator with a frequency of 256 kHz ±30%.
5.11.6 Version Register
Provides version information about the implemented ROM code.
表 5-27. Version Register
ADDRESS
0xFFEF
15
7
14
6
13
5
12
11
10
2
9
1
8
0
Major Version
ADDRESS
0xFFEE
4
3
Minor Version
表 5-28. Version Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
15-8
7-0
Major Version
Minor Version
R
R
1
0
Software version
Software version
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5.11.7 NDEF File Identifier Register
This register is used by the host controller to determine which file has been selected (or also for Read
Binary and Update Binary commands as needed).
表 5-29. NDEF File Identifier Register
ADDRESS
0xFFED
15
7
14
6
13
12
11
10
2
9
1
8
0
File Identifier Second Byte
ADDRESS
0xFFEC
5
4
3
File Identifier First Byte
表 5-30. NDEF File Identifier Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
This is the file identifier. It is references the second byte of the File ID in the
Select command. (For example this byte for the Capability Container would be
03h).
15-8
7-0
File Identifier Second Byte
File Identifier First Byte
R/W
R/W
0
0
This is the file identifier. It is references the first byte of the File ID in the Select
command. (For example this byte for the Capability Container would be E1h).
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5.11.8 Host Response Register
This register is used, after an interrupt is asserted by the RF430CL331H. It communicates various
responses from the host controller. The actual interrupt flag clearing must happen immediately before
setting the response in this register.
表 5-31. Host Response Register
ADDRESS
0xFFEB
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADDRESS
0xFFEA
7
6
5
4
3
2
1
0
Use Custom
SW
Response
Extra Data
Sent In
Interrupt
Serviced
Reserved
Reserved
Reserved
Reserved
File Exists
表 5-32. Host Response Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
Reserved for future use. Write with 0.
15-4
Reserved
R/W
0
This may only be set if the Read Prefetch interrupt has been asserted. This is
possible only after a Read Binary command. This indicates to the
RF430CL331H that extra data has been written to the buffer during RF data
transmission to a previous Read Binary command. To enable this feature, the
Extra Data Interrupt Enable must be set. This also called Prefetch on Read.
3
Extra Data Sent In
R/W
0
0b = No extra data has been written.
1b = Extra data has been written. Update buffer size.
This sets whether or not a custom SW (status word) should be responded to a
NFC Type 4 command (Select, Read Binary, Update Binary).
2
1
Use Custom SW Response
R/W
R/W
0
0
0b = Default response to the PCD.
1b = Custom response to the PCD. The actual SW response is taken from the
Custom SW Response Register.
This is the response to the interrupt of General Type 4 Request with status of
file select.
File Exists
0b = File named in the NDEF File Identifier Register does not exist.
1b = File named in the NDEF File Identifier Register does exist.
Setting this bit high after an interrupt (this applies only to General Type 4
Requests IRQ) has been asserted by the RF430CL331H indicates that the
interrupt has been completely serviced. The actual interrupt flag clearing must
happen immediately before setting this register.
0
Interrupt Serviced
R/W
0
0b = The interrupt is in the process of being serviced by the host controller
1b = The interrupt has been serviced, RF430CL331H to start processing the
response
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5.11.9 NDEF Block Length Register
This register indicates the block length of the Read Binary or Update Binary commands to the host
controller.
表 5-33. NDEF Block Length Register
ADDRESS
0xFFE9
15
7
14
6
13
12
11
10
2
9
1
8
0
Block Length MSB
ADDRESS
0xFFE8
5
4
3
Block Length LSB
表 5-34. NDEF Block Length Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
Block length most significant byte.
Block length least significant byte.
15-8
7-0
Block Length MSB
Block Length LSB
R/W
R/W
0
0
5.11.10 NDEF File Offset Register
This register indicates the offset of the Read Binary or Update Binary commands to the host controller.
表 5-35. NDEF File Offset Register
ADDRESS
0xFFE7
15
7
14
6
13
12
11
10
2
9
1
8
0
File Offset MSB
ADDRESS
0xFFE6
5
4
3
File Offset LSB
表 5-36. NDEF File Offset Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
15-8
7-0
File Offset MSB
File Offset LSB
R/W
R/W
0
0
File offset most significant byte.
File offset least significant byte.
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5.11.11 Buffer Start Register
This register is written after a Read Binary command by the host controller indicating the index in buffer
memory where the data started to be written. On an Update Binary command, this register indicates
where the RF430CL331H has started to write the packet in its buffer memory.
表 5-37. Buffer Start Register
ADDRESS
0xFFE5
15
7
14
6
13
12
11
10
2
9
1
8
0
Buffer Start MSB
ADDRESS
0xFFE4
5
4
3
Buffer Start LSB
表 5-38. Buffer Start Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
15-8
7-0
Buffer Start MSB
Buffer Start LSB
R/W
R/W
0
0
Buffer start most significant byte.
Buffer start least significant byte.
5.11.12 SWTX Register
When a PCD issues a command, there is a time-out that is negotiated (FWI in the SENSB_RES/ATQB
command). The RF430CL331H has this amount of time to respond to the PCD command. If this time-out
cannot be met by RF430CL331H, the NFC protocol allows a sending a S(WTX) request (refer to Section
13.2.2 of the NFC Digital Protocol). This allows the time-out to be restarted after the PCD S(WTX)
response.
When the internal state machine determines that a wait time extension is necessary, it uses this register
value to populate the INF field of the S(WTX) request (refer to Table 84 of the NFC Digital Protocol). This
custom setting response allows flexibility in negotiating this wait time extension.
表 5-39. SWTX Register
ADDRESS
0xFFDF
15
7
14
6
13
5
12
11
10
2
9
1
8
0
Reserved
ADDRESS
0xFFDE
4
3
SWTX Request
表 5-40. SWTX Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
Reserved for future use. Write with 0.
15-8
7-0
Reserved
SWTX Request
R/W
R/W
0
1
S(WTX) request byte.
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5.11.13 Custom Status Word Response Register
On a NFC Type 4 command (Select, Read Binary, Update Binary), the response contains a status word
(SW). This indicates whether or not the request was successful. By default, the RF430CL331H handles
the SW responses automatically with predefined values. However, if custom responses are needed, for
custom error status word responses, this feature may be used.
When the Use Custom SW Response is set in the Host Response register, the RF430CL331H firmware
uses the SW set here to respond to the command.
表 5-41. Custom Status Word Response Register
ADDRESS
0xFFDB
15
7
14
6
13
12
11
10
9
1
8
0
Custom Status Word Response MSB
ADDRESS
0xFFDA
5
4
3
2
Custom Status Word Response LSB
表 5-42. Custom Status Word Response Register Description
BIT
FIELD
TYPE RESET
DESCRIPTION
Custom Status Word
Response MSB
15-8
7-0
R/W
R/W
0
0
Custom status word 1 (SW1).
Custom status word 2 (SW2).
Custom Status Word
Response LSB
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5.12 Identification
5.12.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings (see 节 7.2.1).
5.12.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings (see 节 7.2.1).
5.12.3 JTAG Identification
This device does not provide JTAG-compliant boundary scan test.
5.12.4 Software Identification
The Version register (see 节 5.11.6) stores the software version number.
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Detailed Description
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RF430CL331H
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ZHCSE57A –SEPTEMBER 2015–REVISED NOVEMBER 2015
6 Applications, Implementation, and Layout
注
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
6.1 Application Diagram
图 6-1 shows a sample application diagram.
VCC
C1
C2
VCC
1
VSS
14
13
12
11
10
9
CCore
Antenna
CTune
ANT1
ANT2
RST
E0
VCORE
SDA
2
3
4
5
6
7
SDA
SCL
SCL
External Reset (optional)
I2C Address Select
I2C Address Select
I2C Address Select
I2C_SIGNAL
I2C_READY
INTO
GPIO Output
GPIO Output
Interrupt Output
E1
E2
8
For recommended capacitance values, see Recommended Operating Conditions.
图 6-1. Application Diagram
6.2 References
1. ISO/IEC 14443-2:2010, Part 2: Radio frequency interface power and signal interface
(http://www.iso.org)
2. ISO/IEC 14443-3:2011, Part 3: Initialization and anticollision (http://www.iso.org)
3. ISO/IEC 14443-4:2008, Part 4: Transmission protocols (http://www.iso.org)
4. NFC Data Exchange Format (NDEF) Technical Specification (http://nfc-forum.org/)
5. NFC Forum Type 4 Tag Operation Specification (http://nfc-forum.org/)
6. NFC Digital Protocol Technical Specification, Section 13.2.2, Frame Wait Time Extension (http://nfc-
forum.org/)
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Applications, Implementation, and Layout
49
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7 器件和文档支持
7.1 器件支持
7.1.1 开发支持
7.1.1.1 入门和下一步
德州仪器 (TI) 提供大量的开发工具，其中包括评估处理器性能、生成代码、开发算法工具、以及完全集成和
调试软件及硬件模块的工具。工具支持文档以电子文档形式提供，包含在 Code Composer Studio™集成开
发环境 (IDE)中。
下列产品为 RF430CL331H 器件的应用开发 提供支持：
软件开发工具：Code Composer Studio 集成开发环境 (IDE)：其中包括编辑器、C/C++/汇编代码生成工
具、调试工具以及其他开发工具。
硬件开发工具：有关
RF430CL331H
平台开发支持工具的完整列表，请访问德州仪器
(TI)
网站
www.ti.com。有关定价和购买信息，请联系最近的 TI 销售办事处或授权分销商。
7.1.2 器件和开发工具命名规则
为了指明产品开发周期所处的阶段，TI 为所有 RF430 MCU 器件和支持工具的产品型号分配了前缀。每个商
业系列成员都具有以下三个前缀中的一个：RF、P 或 X（例如，RFRF430FRL152H）。德州仪器 (TI) 建议
为其支持的工具使用三个可用前缀指示符中的两个：RF 和 X。这些前缀代表了产品开发的发展阶段：即从
工程原型设计（X 表示器件和工具）直到完全合格的生产器件和工具（RF 表示器件和工具）。
器件开发进化流程：
X - 试验器件不一定代表最终器件的电气技术规格
P - 芯片模型符合最终器件的电气技术规格，但是未经完整的质量和可靠性验证
RF - 完全合格的生产器件
支持工具开发发展流程：
X - 还未经德州仪器 (TI) 完整内部质量测试的开发支持产品。
RF – 完全合格的开发支持产品
X 和 P 器件和 X 开发支持工具在供货时附带如下免责条款：
“开发的产品用于内部评估用途。”
RF 器件和 RF 开发支持工具已进行完全特性描述，并且器件的质量和可靠性已经完全论证。TI 的标准保修
证书适用。
预测显示原型器件（X 和 P）的故障率大于标准生产器件。由于这些器件的预计最终使用故障率仍未定义，
德州仪器 (TI) 建议不要将它们用于任何生产系统。只有合格的生产器件将被使用。
TI 器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀包括封装类型（例如，RGE）和温度范围
（例如，T）。图 7-1 提供了读取任一系列产品成员完整器件名称的图例。
50
器件和文档支持
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RF430CL331H
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ZHCSE57A –SEPTEMBER 2015–REVISED NOVEMBER 2015
RF 430 CL
H A I
R -EP
RGE
331
Processor Family
430 MCU Platform
Device Type
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: Revision
Device Designator
Wireless Technology
Processor Family
RF = Embedded RF radio
X = Experimental silicon
P = Prototype device
430 MCU Platform
Device Type
TI’s low-power microcontroller platform
C = Fixed function
L = Low-power series
Device Designator
Various levels of integration within a series
Wireless Technology
Optional: Revision
H = High frequency
A = Device revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
图 7-1. 器件命名规则
7.2 文档支持
7.2.1 相关文档ꢀ
以下文档对 RF430CL331H 应答器进行了介绍。www.ti.com.cn 网站上提供了这些文档的副本。
SLAZ672
RF430CL331H 器件勘误表。 描述了针对此器件的所有芯片修订版本功能技术规格的已知例外
情况。
7.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范和标准且不一定反映 TI 的观点；请见 TI 的使用条款。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区。此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的一般知识的创新和增长。
7.4 商标
Code Composer Studio, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
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器件和文档支持
51
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ZHCSE57A –SEPTEMBER 2015–REVISED NOVEMBER 2015
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7.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
7.6 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
7.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
8 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知
且不对本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。
52
机械、封装和可订购信息
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
RF430CL331HIPWR
RF430CL331HIRGTR
ACTIVE
ACTIVE
TSSOP
VQFN
PW
14
16
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
CL331H
CL331H
RGT
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
RF430CL331HIPWR
RF430CL331HIRGTR
TSSOP
VQFN
PW
14
16
2000
3000
330.0
330.0
12.4
12.4
6.9
3.3
5.6
3.3
1.6
1.1
8.0
8.0
12.0
12.0
Q1
Q2
RGT
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
RF430CL331HIPWR
RF430CL331HIRGTR
TSSOP
VQFN
PW
14
16
2000
3000
338.1
350.0
338.1
350.0
20.6
43.0
RGT
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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