SN54ABT162825WD [TI]
18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 18位缓冲器/驱动器，具有三态输出
| 型号： | SN54ABT162825WD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
SN54ABT162825 . . . WD PACKAGE
SN74ABT162825 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
1OE1
1Y1
1Y2
GND
1Y3
1Y4
1OE2
1A1
1A2
GND
1A3
1A4
1
56
55
54
53
52
51
50
49
48
47
46
45
2
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
3
4
Typical V
(Output Ground Bounce) < 1 V
5
OLP
at V
= 5 V, T = 25°C
6
CC
A
V
V
7
CC
CC
High-Impedance State During Power Up
and Power Down
1Y5
1Y6
1Y7
GND
1Y8
1A5
1A6
1A7
GND
1A8
8
9
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
10
11
12
Flow-Through Architecture Optimizes PCB
Layout
1Y9 13
GND 14
GND 15
2Y1 16
44 1A9
43 GND
42 GND
41 2A1
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
17
18
19
20
21
22
23
24
25
26
27
28
40
39
38
37
36
35
34
33
32
31
30
29
2Y2
GND
2Y3
2Y4
2Y5
2A2
GND
2A3
2A4
2A5
description
The ’ABT162825 are 18-bit buffers and line
drivers designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. These devices
provide true data, and can be used as two 9-bit
buffers or one 18-bit buffer.
V
V
CC
CC
2Y6
2Y7
GND
2Y8
2Y9
2A6
2A7
GND
2A8
2A9
2OE1
2OE2
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all nine affected
outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to
reduce overshoot and undershoot.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
The SN54ABT162825 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT162825 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
FUNCTION TABLE
(each 9-bit buffer)
INPUTS
OUTPUT
Y
OE2
L
A
L
OE1
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
†
logic diagram (positive logic)
logic symbol
1
1
&
1OE1
1OE1
56
EN1
EN2
56
28
29
1OE2
1OE2
&
2OE1
2OE2
55
2
1A1
1Y1
55
54
52
51
49
48
47
45
44
41
40
38
37
36
34
33
31
30
2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
1Y1
3
1
To Eight Other Channels
1Y2
5
1Y3
6
28
29
2OE1
2OE2
1Y4
8
1Y5
9
1Y6
41
16
10
2A1
2Y1
1Y7
1Y8
1Y9
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
2Y9
12
13
16
17
19
20
21
23
24
26
27
To Eight Other Channels
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance, θ (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT162825 SN74ABT162825
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
–12
12
9
–12
12
9
mA
mA
OH
OL
Control inputs
Data inputs
∆t/∆v
∆t/∆V
Input transition rise or fall rate
ns/V
10
10
Power-up ramp rate
200
–55
200
–40
µs/V
°C
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT162825 SN74ABT162825
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –1 mA
= –1 mA
= –3 mA
= –12 mA
= 8 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
V
OH
2.4
2
2.4
2
2.4
2
V
= 4.5 V
= 4.5 V
CC
CC
0.4
0.8
0.8
0.65
0.8
V
V
V
OL
= 12 mA
100
mV
hys
I
I
V
CC
= 0 to 5.5 V, V = V or GND
I CC
±1
±1
±1
µA
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE = X
CC
O
‡
‡
±50
±50
±50
µA
µA
µA
µA
I
OZPU
OZPD
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
±50
10
±50
10
±50
10
I
I
I
V
V
= 2.1 V to 5.5 V,
= 2.7 V, OE ≥ 2 V
CC
O
§
OZH
V
V
= 2.1 V to 5.5 V,
= 0.5 V, OE ≥ 2 V
CC
O
§
–10
–10
–10
OZL
I
I
V
V
V
= 0,
V or V ≤ 4.5 V
±100
50
±100
50
µA
µA
off
CC
CC
CC
I
O
Outputs high
= 5.5 V,
= 5.5 V,
V
= 5.5 V
50
–100
2
CEX
O
O
¶
V
= 2.5 V
–25
–75
–100
2
–25
–25
–100
2
mA
I
O
Outputs high
Outputs low
V
= 5.5 V, I = 0,
or GND
CC
32
32
32
CC
O
I
mA
mA
CC
V = V
I
Outputs
disabled
2
1
2
2
1
V
CC
= 5.5 V,
Outputs enabled
Outputs disabled
1.5
One input at
3.4 V,
Data inputs
Other inputs at
#
∆I
0.05
1.5
1
0.05
1.5
CC
V
CC
or GND
V
CC
= 5.5 V, One input at 3.4 V,
or GND
Control inputs
1.5
Other inputs at V
CC
V = 2.5 V or 0.5 V
C
C
3.5
8
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
†
‡
§
¶
#
All typical values are at V
This parameter is characterized, but not production tested.
= 5 V.
CC
The parameters I
and I
include the input leakage current.
OZL
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162825 SN74ABT162825
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
TYP
2.1
2.8
3.4
3.5
4.1
3.5
MAX
3.6
4.2
6.3
7.3
6.5
5.9
MIN
1
MAX
4.1
5
MIN
1
MAX
3.9
4.7
6.9
6.3
6.6
6.3
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
1.1
1.5
1.6
2.1
1.5
1.1
1.5
1.6
2.1
1.5
1.1
1.5
1.6
2.1
1.5
7.2
6.6
6.8
7.3
OE
OE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162825, SN74ABT162825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS474C – JUNE 1994 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
t
Open
7 V
PLH PHL
t
/t
GND
PLZ PZL
/t
Open
C
= 50 pF
PHZ PZH
L
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
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ABT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48, 0.380 INCH, CERAMIC, FINE PITCH, DFP-48
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