SN65LVDM31DRG4 [TI]
Quad LVDM Transmitter 16-SOIC -40 to 85;
| 型号： | SN65LVDM31DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quad LVDM Transmitter 16-SOIC -40 to 85 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总8页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDM31
www.ti.com
SLLS417C–MARCH 2000–REVISED MAY 2001
HIGH-SPEED DIFFERENTIAL LINE DRIVER
FEATURES
SN65LVDM31D (Marked as LVDM31)
(TOP VIEW)
•
Designed for Signaling Rates
NOTE: The signaling rate is the number of voltage transitions that
can be made per second.
1A
1Y
1Z
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
4A
4Y
4Z
G
Up to 150 Mbps
•
Low-Voltage Differential Signaling With
Typical Output Voltage of 700 mV and a 100-Ω
Load
G
2Z
2Y
3Z
•
•
•
Propagation Delay Time of 2.3 ns, Typical
Single 3.3-V Supply Operation
2A
GND
10 3Y
3A
9
One Driver's Power Dissipation at 75 MHz,
50 mW, Typical
FUNCTIONAL BLOCK DIAGRAM
•
High-Impedance Outputs When Disabled or
With VCC < 1.5 V
4
G
•
•
Bus-Pin ESD Protection Exceeds 12 kV
12
G
Low-Voltage CMOS (LVCMOS) Logic Input
Levels Are 5-V Tolerant
2
1Y
1Z
1
7
1A
2A
3
DESCRIPTION
6
5
2Y
2Z
The SN65LVDM31 incorporates four differential line
drivers that implement the electrical characteristics of
low-voltage differential signaling. This product offers a
low-power alternative to 5-V PECL drivers with similar
signal levels. Any of the four current-mode drivers will
10
11
3Y
3Z
9
3A
4A
deliver
a
minimum differential output voltage
magnitude of 540 mV into a 100-Ω load when
enabled by either an active-low or active-high enable
input.
14
13
4Y
4Z
15
The intended application of this device and signaling
technique is for both point-to-point and multiplexed
baseband data transmission over controlled
impedance media of approximately 100 Ω. The
transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and
distance of data transfer is dependent upon the
attenuation characteristics of the media and the noise
coupling to the environment.
FUNCTION TABLE
INPUT
ENABLES
OUTPUTS
A
H
G
G
X
X
L
Y
H
L
Z
L
H
H
X
X
L
L
H
L
H
H
L
L
L
H
Z
H
H
X
H
X
L
Z
L
The SN65LVDM31 is characterized for operation from
–40°C to 85°C.
Open
Open
H
X
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2001, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDM31
www.ti.com
SLLS417C–MARCH 2000–REVISED MAY 2001
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
50 Ω
G, G or
A Input
50 Ω
Y or Z
10 kΩ
Output
7 V
300 kΩ
7 V
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
(2)
Supply voltage range VCC
–0.5 V to 4 V
–0.5 V to 6 V
–0.5 V to 4 V
Inputs
Input voltage range
Y or Z
Electrostatic discharge(3): Y, Z, and GND
Class 3, A:12 kV, B:600 V
See Dissipation Rating Table
–65°C to 150°C
Continuous power dissipation
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
T
A ≤ 25°C
OPERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D
950 mW
7.6 mW/°C
494 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
MAX UNIT
VCC Supply voltage
3.3
3.6
V
V
VIH
VIL
TA
High-level input voltage
Low-level input voltage
2.0
0.8
85
V
Operating free-air temperature
40
°C
2
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SN65LVDM31
www.ti.com
SLLS417C–MARCH 2000–REVISED MAY 2001
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
RL = 100 Ω,
See Figure 2
See Figure 2
540
270
700
350
860
mV
430
|VOD
|
Differential output voltage magnitude
RL = 50 Ω,
Change in differential output voltage magnitude
between logic states
∆|VOD
|
See Figure 2
–25
1.14
–30
0
1.2
0
25
1.3
30
mV
V
VOC(SS)
∆VOC(SS)
VOC(PP)
Steady-state common-mode output voltage
Change in steady-state common-mode output
voltage between logic states
See Figure 3
mV
mA
Peak-to-peak common-mode output voltage
70
6
100
10
40
0.7
10
10
10
10
±1
±1
Enabled, No load
ICC
Supply current
Enabled, RL = 100 Ω VIN = 0 or VCC
Disabled
35
0.5
3
IIH
IIL
High-level input current
Low-level input current
VIH = 3 V
–10
–10
µA
µA
VIL = 0 V
0
VOY or VOZ = 0 V
VOD = 0 V
7
IOS
Short-circuit output current
mA
7
IOZ
High-impedance state output current
Power-off output current
VO = 0 V or VCC
µA
µA
IO(OFF)
VCC = 1.5 V,
VO = 3.6 V
(1) All typical values are at 25°C and with a 3.3-V supply.
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
1.8
1.8
0.4
0.4
2.3
2.3
0.6
0.6
50
2.9
2.9
1.0
1.0
350
200
1
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
See Figure 4
tf
tsk(p)
tsk(o)
tsk(pp)
tPZH
tPZL
tPHz
tPLZ
Pulse skew (|tPHL– tPLH|)
Channel-to-channel output skew(1)
(2)
Part-to-part skew
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
6
6
6
6
15
See Figure 5
15
15
15
(1) tsk(o) is the maximum delay time difference between drivers on the same device.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
3
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SN65LVDM31
www.ti.com
SLLS417C–MARCH 2000–REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
I
OY
Y
I
I
A
V
OD
I
OZ
(V +V )/2
OY
OZ
V
OY
Z
V
OC
V
I
V
OZ
Figure 1. Driver Voltage and Current Definitions
3.75 kΩ
Y
R
L
V
OD
Input
+
0 V ≤ V
≤ 2.4 V
_
test
Z
3.75 kΩ
Figure 2. VOD Test Circuit
49.9 Ω ± 1%(2 Places)
3 V
0 V
Y
Z
A
A
Input
V
V
OC(SS)
OC(PP)
V
OC
C
= 10 pF
L
V
OC
(2 Places)
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the DUT. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3 V
Input
1.5 V
0 V
Y
Z
Input
V
OD
100 Ω
t
t
PHL
PLH
100%
80%
C
= 10 pF
L
V
OD(H)
(2 Places)
Output
0 V
V
OD(L)
20%
0%
t
f
t
r
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the DUT.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
4
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SN65LVDM31
www.ti.com
SLLS417C–MARCH 2000–REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION (continued)
49.9 Ω ± 1%(2 Places)
Y
0 V or 3 V
Z
G
G
1.2 V
V
OY
V
OZ
Inputs
C
L
= 10 pF
(2 Places)
3 V
1.5 V
0 V
G
G
3 V
1.5 V
0 V
V
≤ 1.4 V
1.25 V
A at 3 V, G at V and Input to G
CC
OY
or
or
V
G at GND and Input to G
OZ
1.2 V
t
t
t
PZH
PHZ
A at 0 V, G at V and Input to G
CC
1.2 V
V
OZ
or
or
1.15 V
≤ 1 V
G at GND and Input to G
V
OY
t
PZL
PLZ
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the DUT.
Figure 5. Enable and Disable Time Circuit and Definitions
5
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SN65LVDM31
www.ti.com
SLLS417C–MARCH 2000–REVISED MAY 2001
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
70
60
50
40
30
20
10
0
V
CC
= 3.6 V
V
CC
= 3 V
V
CC
= 3.3 V
0
50
100
150
200
250
300
f − Frequency − MHz
Figure 6.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
3
2
1
0
3.5
3
V
= 3.3 V
= 25°C,
CC
T
A
Single-Ended
No Load
2.5
2
1.5
1
V
= 3.3 V
= 25°C,
CC
T
A
.5
0
Single-Ended
No Load
0
2
4
6
8
10
12
0
−2
−4
−6
−8
I
− Low-Level Output Current − mA
I
− High-Level Output Current − mA
OL
OH
Figure 7.
Figure 8.
6
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SN65LVDM31
www.ti.com
SLLS417C–MARCH 2000–REVISED MAY 2001
TYPICAL CHARACTERISTICS (continued)
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.75
2.5
2.75
2.5
V
CC
= 3 V
V
CC
= 3 V
V
= 3.3 V
= 3.6 V
CC
V
= 3.3 V
= 3.6 V
CC
2.25
2
2.25
2
V
CC
V
CC
1.75
1.75
−50
−30 −10
10
50
90
−50
−30 −10
10
50
90
30
70
30
70
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 9.
Figure 10.
7
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