SN65LVDM320DGGG4 [TI]
OCTAL LINE TRANSCEIVER, PDSO64, PLASTIC, SOP-64;
| 型号： | SN65LVDM320DGGG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL LINE TRANSCEIVER, PDSO64, PLASTIC, SOP-64 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总31页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDM320
www.ti.com
SLLS462–AUGUST 2001
HIGH-SPEED DIFFERENTIAL 8-BIT REGISTERED TRANSCEIVER
FEATURES
•
Open-Circuit Differential Receiver Fail Safe
Assures a Low-Level Output
•
8-Bit Bidirectional Data Storage Register With
Full Parallel Access
•
•
•
Reset at Power Up
•
Parallel Transfer Rates
12-kV Bus-Pin ESD Protection
(1)
Bus Pins Remain High-Impedance When
Disabled or With VCC Below 1.5 V for
Power-Up/Down Glitch-Free Performance and
Hot Plugging
Parallel data transfer through all channels simultaneously as
defined by TIA/EIA-644 with tr of tf less than 30% of the unit
interval.
– Buffer Mode: Up to 475 Megatransfers
– Flip-Flop Mode: Up to 300 Megatransfers
– Latch Mode: Up to 300 Megatransfers
Operates With a Single 3.3-V Supply
•
5-V Tolerant LVCMOS Inputs
APPLICATIONS
•
•
•
•
•
•
Telecom Switching
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV Across a
50-Ω Load
Printers and Copiers
Audio Mixing Consoles
Automated Test Equipment
•
•
•
Bus and Logic Loopback Capability
Very Low Radiation Emission
Low Skew Performance
– Pulse Skew Less Than 100 ps
– Output Skew Less Than 320 ps
– Part-to-Part Skew Less Than 1 ns
LOGIC DIAGRAM
OEB
OMODE1
OMODE2
LPBK
NODE
CLK/LEAB
D
D
Q
Q
BY
BZ
C
Q
Q
DA
C
IMODE1
IMODE2
CLK/LEBA
Q
Q
D
RA
C
Q
Q
D
C
OEA
LPBK
ENR
One-of-Eight Channels
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001, Texas Instruments Incorporated
SN65LVDM320
www.ti.com
SLLS462–AUGUST 2001
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The SN65LVDM320 is an 8-bit data storage register with differential line drivers and receivers that are electrically
compatible with ANSI EIA/TIA-644 for multipoint architectures with standard-compliant parallel transfer rates of
475 Mbps. The SN65LVDM320 includes transmitter and receiver data registers that remain active regardless of
the state of their associated outputs.
The logic element for data flow in each direction is configured by mode-control inputs. IMODE1 and IMODE2
control data flow in the B-to-A (bus side to digital side) direction when configured as a buffer, a D-type flip-flop, or
a D-type latch. OMODE1 and OMODE2 control data flow in each of the operating modes for the A-to-B (digital
side to bus side) direction. When configured in buffer mode, input data appears at the output port. In the flip-flop
mode, data is stored on the rising edge of the appropriate clock input, CLKAB/LEAB or CLKBA/LEBA. In the
latch mode, this clock pin also serves as an active-high transparent latch enable.
Data flow is further controlled by the A-side loopback (LPBK) input. When LPBK is high, DA input data is looped
back to the RA output. B-side bus data is looped back to the bus in latch mode by means of the IMODE and
OMODE logic states.
The A-side output enable/disable control is provided by OEA. When OEA is low or VCC is less than 2 V, the A
side is in the high-impedance state. When OEA is high, the A side is active (high or low logic levels). The B-side
output enable/disable control is provided by OEB. When OEB is low or VCC is less than 2 V, the B side is in the
high impedance state. When OEB is high, the B side is active (high or low logic levels).
The A-to-B and B-to-A logic elements are active regardless of the state of their associated outputs. New data can
be entered (in latch and flip-flop modes) or previously stored data can be retained while the associated outputs
are in the high-impedance or inactive states. The SN65LVDM320 also includes internally isolated analog (B-side)
and digital (A-side) grounds for enhanced operation.
The SN65LVDM320 is characterized for operation from –40°C to 85°C.
Table 1. Mode Functions(1)
INPUTS
MODE
CLK/LEAB
CLK/LEBA
OEA OEB
ENR
OMODE1
OMODE2
IMODE1
IMODE2
LPBK
X
X
L
L
X
X
X
X
X
X
Isolation
A-to-B buffer mode
(see Figure 1)
X
X
X
X
H
X
X
L
L
L
X
X
X
X
X
X
A-to-B flip-flop mode
(see Figure 2)
↑
X
X
H
H
H
H(B follows A)
L(B latched)
A-to-B latch mode
(see Figure 3)
X
X
H
L
X
X
X
B-to-A buffer mode
(see Figure 4)
X
X
X
H
H
L
L
L
L
X
X
X
X
L
L
L
L
L
B-to-A flip-flop mode(see
Figure 5)
↑
H
H(A follows B)
L(A latched)
B-to-A latch mode
(see Figure 6)
X
H
L
L
X
X
H
L
L
Bus loopback latch mode(see
Figure 7)
X
X
X
X
L
L
L
H
H
H
X
H
X
H
X
H
X
L
DA to RA loopback mode (see
Figures 8 through 10)
H
H
(1) H = high level, L = low level, X = don't care, ↑ = low-to-high
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PIN DESCRIPTIONS
PIN
Description
NAME
NO.
AGND
36, 44, 54, 58, 62 Analog (B-side) ground
1BY-8BY &
1BZ-8BZ
64 & 63, 60 & 59, Differential I/O pair
56 & 55, 52 & 51,
46 & 45, 42 & 41,
38 & 37, 34 & 33
CLK/LEBA
CLK/LEAB
1DA-8DA
18
14
B-side to A-side clock input or latch enable
A-side to B-side clock input or latch enable
1, 3, 7, 9, 21, 25, Single-ended input
29, 31
DGND
5, 11, 15, 19, 23, Digital (A-side) ground
27
ENR
39
50,49
48
Receiver differential data enable
IMODE1IMODE2
B-side to A-side buffer, flip-flop, or latch mode control and bus loopback control (see Table 2)
LPBK
OEA
OEB
A-side loopback enable
47
A-side output enable
40
B-side output enable
OMODE1,OMODE2
RA
13,17
A-side to B-side buffer, flip-flop, or latch mode control and bus loopback control (see Table 3)
2, 4, 8, 10, 22, 26, Single-ended output
30, 32
VCC
6, 12, 16, 20, 24, Supply voltage
28, 35, 43, 53, 57,
61
3
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PIN DESCRIPTIONS
SN65LVDM320DGG
(Marked as LVDM320)
(TOP VIEW)
1DA
1RA
1BY
1BZ
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
2DA
2RA
DGND
VCC
3DA
AGND
VCC
2BY
3
4
5
2BZ
6
AGND
VCC
3BY
7
3RA
4DA
4RA
DGND
VCC
8
9
3BZ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
VCC
4BY
OMODE1
CLK/LEAB
DGND
VCC
OMODE2
CLK/LEBA
DGND
VCC
4BZ
IMODE1
IMODE2
LPBK
OEA
5BY
5BZ
5DA
5RA
DGND
VCC
AGND
VCC
6BY
6BZ
6DA
6RA
DGND
VCC
7DA
OEB
ENR
7BY
7BZ
AGND
VCC
8BY
7RA
8DA
8RA
8BZ
Table 2. IMODE Logic
Table 3. OMODE Logic
MODE FUNCTION
(B SIDE TO A SIDE)
MODE FUNCTION
(A SIDE TO B SIDE)
IMODE1 IMODE2
IMODE1 IMODE2
0
0
1
1
0
1
0
1
Buffer
0
0
1
1
0
1
0
1
Buffer
Flip-Flop
Flip-Flop
Latch
Bus loopback(1)
Latch
Bus loopback(1)
(1) All IMODE and OMODE pins must be high for the differential
bus loopback latch mode.
(1) All IMODE and OMODE pins must be high for the differential
bus loopback latch mode.
4
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MODE FUNCTION DIAGRAMS
OEB (High)
OMODE1 (Low)
OMODE2 (Low)
BY
BZ
DA
Figure 1. A-to-B Buffer Mode
OEB (High)
OMODE1 (Low)
OMODE2 (High)
CLK/LEAB (↑)
D
Q
BY
C
BZ
DA
Figure 2. A-to-B Flip-Flop Mode
OEB (High)
OMODE1 (High)
OMODE2 (Low)
CLK/LEAB
(Low to High)
BY
BZ
D
C
Q
DA
Figure 3. A-to-B Latch Mode
5
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MODE FUNCTION DIAGRAMS (continued)
OEB (Low)
IMODE1 (Low)
IMODE2 (Low)
BY
BZ
RA
OEA (High)
LPBK (Low)
ENR (Low)
One-of-Eight Channels
Figure 4. B-to-A Buffer Mode
OEB (Low)
IMODE1 (Low)
IMODE2 (High)
CLK/LEAB (↑)
BY
BZ
Q
D
C
RA
OEA (High)
LPBK (Low)
ENR (Low)
One-of-Eight Channels
Figure 5. B-to-A Flip-Flop Mode
OEB (Low)
IMODE1 (High)
IMODE2 (Low)
CLK/LEAB
(Low to High)
BY
BZ
RA
Q
D
C
OEA (High)
LPBK (Low)
ENR (Low)
One-of-Eight Channels
Figure 6. B-to-A Latch Mode
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MODE FUNCTION DIAGRAMS (continued)
OEB (Low to Receive,
High to Transmit)
OMODE1 (High)
OMODE2 (High)
BY
BZ
IMODE1 (High)
IMODE2 (High)
CLK/LEBA
Q
Q
D
C
D
C
LPBK (Low)
ENR (Low to Receive,
High to Transmit)
One-of-Eight Channels
Figure 7. Bus Loopback Latch Mode
OEB (Low)
OMODE1 (Low)
OMODE2 (Low)
LPBK
NODE
BY
BZ
DA
IMODE1 (Low)
IMODE2 (Low)
RA
OEA (High)
LPBK (High)
ENR (High)
One-of-Eight Channels
Figure 8. DA to RA Buffer Mode
7
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MODE FUNCTION DIAGRAMS (continued)
OEB (Low)
OMODE1 (Low)
OMODE2 (High)
CLK/LEAB (↑)
LPBK
NODE
D
Q
BY
BZ
C
DA
IMODE1 (Low)
IMODE2 (High)
CLK/LEBA (↑)
Q
D
RA
C
OEA (High)
LPBK (High)
ENR (High)
One-of-Eight Channels
Figure 9. DA to RA Flip-Flop Mode
OEB (Low)
OMODE1 (High)
OMODE2 (Low)
CLK/LEAB (Low to High)
LPBK
NODE
BY
BZ
D
Q
DA
C
IMODE1 (High)
IMODE2 (Low)
CLK/LEBA (Low to High)
RA
Q
Q
D
C
OEA (High)
LPBK (High)
ENR (High)
One-of-Eight Channels
Figure 10. DA to RA Latch Mode
8
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
50 Ω
DA, OEB, or ENR Input
5 Ω
RA Output
7 V
7 V
300 kΩ
V
CC
V
CC
300 kΩ
300 kΩ
10 kΩ
5 Ω
BY or BZ Output
7 V
Z Input
Y Input
7 V
7 V
Table 4. LVDM Receiver Function Table
BUS INPUTS
OUTPUT(1)
VID = VY– VZ
V
ID ≥ 100 mV
H
?
L
L
–100 mV < VID < 100 mV
VID ≤ –100 mV
Open
(1) H = high-level, L = low-level, ? = indeterminate
9
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
(2)
Supply voltage range, VCC
–0.5 V to 4 V
–0.5 V to 6 V
–0.5 V to 4 V
Voltage range (TTL pins)
Voltage range BY and BZ
(3)
Electrostatic discharge
Y, Z, and GND
All pins
Class 3, A: 12 kV, B: 600 V
Class 3, A: 7 kV, B: 500 V
(see Dissipation Rating Table)
-65°C to 150°C
Continuous power dissipation
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with MIL-STD-883E Method 3015.7.
DISSIPATION RATING TABLE
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
TA ≤ 25°C
DGG(2)
DGG(3)
2094 mW
3765 mW
16.7 mW/°C
30.1 mW/°C
1340 mW
2410 mW
1089 mW
1958 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC Supply voltage
3
2
3.3
3.6
V
V
V
V
VIH
VIL
High-level input voltage
Low-level input voltage,
0.8
0.6
|VID
|
Magnitude of differential input voltage
0.1
Ť Ť
V
Ť
IDŤ
V
ID
VIC
Common-mode input voltage
Operating free-air temperature
2.4 –
V
2
2
VCC-0.8
85
TA
-40
°C
SUPPLY CURRENT
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
Driver enabled, receiver enabled, RL = 50 Ω
(DA, OEA, OEB to VCC, ENR to GND)
75
130
3
mA
mA
mA
mA
Driver disabled, receiver disabled
1
60
20
(DA, OEA, OEB to GND, ENR to VCC
)
ICC
Supply current
Driver enabled, receiver disabled, RL = 50 Ω
(DA, OEB, ENR to VCC, OEA to GND)
100
40
Driver disabled, receiver enabled
(DA, OEB, ENR to GND, OEA to VCC
)
10
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RL = 50 Ω,
See Figure 11 and
Figure 12
MIN TYP(1)
MAX UNIT
|VOD
|
Differential output voltage magnitude
247
–50(2)
1.125
–50
330
454
mV
50
Change in differential output voltage magnitude between
logic states
∆|VOD
|
VOC(SS)
Steady-state common-mode B-port output voltage
1.375
50
V
Change in steady-state common-mode B-port output voltage
between logic states
∆VOC(SS)
See Figure 13
mV
VOC(PP)
IOZ
Peak-to-peak common-mode B-port output voltage
RA-port high-impedance output current
DA port high-level input current
50
150
10
VO = 0 V or 3.6 V
VIH = 2 V
–10
µA
µA
µA
mA
mA
µA
IIH
20
IIL
DA port low-level input current
VIL = 0.8 V
10
VOY or VOZ = 0
VOD = 0
–10
–10
–10
10
IOS
Differential short-circuit output current
10
IO(OFF)
VIT+
VIT-
Power-off differential output current
VOD = 2.4 V, VCC = 1.5 V
10
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level RA port output voltage
100
See Figure 16 and Table 5
mV
–100
2.4
VOH
VOL
IOH = –8 mA
IOL = 8 mA
VI = 0 V
V
V
Low-level RA port output voltage
0.4
–35
–10
µA
µA
II
Input current (Y or Z inputs)
VI = 2.4 V
VIY = 0 and VIZ = 100 mV,
VIY = 2.4 V and VIZ = 2.3 V
IID
Differential input current M IIY - IIZM
–10
–20
10
20
µA
II(OFF)
C(INA)
C(INB)
VO(0PX)
Power-off input current (Y or Z inputs)
DA port Input capacitance
VCC 0 V, VI = 2.4 V
µA
pF
VI = 0.4 sin (4E6πt) + 0.5 V
VI = 0.4 sin (4E6πt) + 0.5 V
See Figure 20
5
6
B-port Input capacitance
pF
B-port crosstalk output voltage (zero-to-peak)
0.1
mV
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP MAX UNIT
tPLH
tPHL
tPLH
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
1.4
1.4
2.5
3.3
3.3
4.3
5.2
5.3
6.2
DA (buffer mode), See
Figure 1 and Figure 14
BY, BZ
RA
ns
ns
BY, BZ (buffer mode),
See See Figure 4 and
Figure 17
tPHL
Propagation delay time, high-to-low-level output
2.5
4.3
6.5
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
3
3
5.5
5.5
6.5
6.5
6.5
6.5
8.5
8.7
9.3
9.8
9.5
9.5
DA (latch mode), See
Figure 3 and Figure 14
BY, BZ
RA
ns
ns
ns
ns
ns
4
BY, BZ (latch mode), See
Figure 6
4
3.5
3.5
3.8
3.8
1.8
1.8
CLKAB, See Figure 2
and Figure 22
BY, BZ
RA
6.5 10.5
6.5 10.5
CLKBA, See Figure 5
and Figure 23
3.2
3.2
7
7
DA, See Figure 8 and
Figure 19
RA
11
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DEVICE SWITCHING CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP MAX UNIT
Propagation delay time, high-level-to-high-impedance
output
tPHZ
15
15
15
15
10
10
10
10
26
23
26
23
15
17
15
17
ns
ns
ns
ns
Propagation delay time, low-level-to-high-impedance
output
tPLZ
OEA, See Figure 20
RA
Propagation delay time, high-impedance-to-high-level
output
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
Propagation delay time, high-impedance-to-low-level
output
Propagation delay time, high-level-to-high-impedance
output
Propagation delay time, low-level-to-high-impedance
output
OEB, See Figure 15
BY, BZ
Propagation delay time, high-impedance-to-high-level
output
Propagation delay time, high-impedance-to-low-level
output
tr(B)
Output signal rise time B port
Output signal fall time B port
Output signal rise time A port
Output signal fall time A port
Output skew channel-to-channel
Pulse skew (|tPHL– tPLH|) (A-port)
Pulse skew (|tPHL– tPLH|) (B-port)
Part-to-part skew
470
450
580
630
0.3
0.7
0.7
0.6
See Figure 14
ps
ps
tf(B)
tr(A)
See Figure 17
tf(A)
(1)
tsk(o)
tsk(p)
tsk(p)
ns
ns
ns
ns
(2)
tsk(pp)
(1) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
(2) tsk(pp) is the magnitude of the difference delay times between any specified terminals of two devices when both devices operate with the
same supply voltages, at the same temperature, and have identical packages and test circuits.
TIMING REQUIREMENTS
over recommended operating conditions (see Figure 21) (unless otherwise noted)
MIN
TYP
MAX UNIT
fmax
tSU
CLK/LEAB or CLK/LEBA in flip-flop mode
Setup for flip-flop
300
MHz
ns
0.2
1.0
1.9
1.0
Setup time
Hold time
Setup for latch
ns
Hold time for flip-flop
Hold time for latch
ns
th
ns
12
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PARAMETER MEASUREMENT INFORMATION
V
CC
I
OY
BY
BZ
I
I
V
OY
+ V
C
DA
2
V
OD
I
OZ
ENABLES
OEB
V
OY
H
L
L
V
IA
V
OC
OMODE1
OMODE2
V
OZ
Figure 11. Driver Voltage and Current Definitions
3.75 kΩ
BY
ENABLES
+
DA
OEB
H
L
L
0 V ≤ V
≤ 2.4 V
V
50 Ω
test
Input
_
OD
OMODE1
OMODE2
BZ
3.75 kΩ
Figure 12. VOD Test Circuit
V
OBY
25 Ω ±1% (2 Places)
BY
BZ
V
OBZ
V
OC(SS)
DA
Input
V
OC(PP)
C
L
= 2 pF
V
OC
V
OC
ENABLES
OEB
H
L
L
OMODE1
OMODE2
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of
the device under test. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300
MHz.
Figure 13. Test Circuit and Definitions for the Differential Common-Mode Output Voltage
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PARAMETER MEASUREMENT INFORMATION (continued)
BY
DA
C
L
= 2 pF
V
OD
Input
50 Ω ±1%
BZ
V
CC
V /2
CC
Input
0 V
t
t
PHL
PLH
100%
80%
V
OD(H)
Output
0 V
V
OD(L)
20%
0%
t
f
t
r
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the
device under test.
Figure 14. Test Circuit, Timing, and Voltage Definitions for the DIfferential Output Signal
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PARAMETER MEASUREMENT INFORMATION (continued)
25 Ω ± 1% (2 Places)
BY
C = 2 pF
L
DA
V
OD
+
BZ
1.2 V
–
OEB
Input
V
OBY
V
OBZ
V
OD
= (V
– V
)
OBY
OBZ
V
CC
Input
V /2
CC
0 V
t
t
PHZ
PZH
DA = V
CC
V
OD(H)
Output
Input
50 mV
≡ 0 V
V
V
CC
/2
CC
0 V
t
t
PLZ
PZL
DA = 0 V
≡ 0 V
50 mV
V
OD(L)
Output
Figure 15. A-to-B Enable/Disable Time Test Circuit and Definitions
Y
RA
ENABLES
V
ID
Z
ENR
IMODE1
IMODE2
OEA
L
L
L
H
V
O
V
IC
V
IY
(V + V )/2
IY
IZ
V
IZ
Figure 16. Voltage Definitions
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Table 5. Receiver Minimum and Maximum Fail-Safe Input Threshold Test
Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-MODE
INPUT VOLTAGE
APPLIED VOLTAGES
VIY
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
VIZ
1.15 V
1.25 V
2.3 V
2.4 V
0 V
VID
VIC
100 mV
–100 mV
100 mV
–100 mV
100 mV
–100 mV
600 mV
–600 mV
600 mV
–600 mV
600 mV
–600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0 .3V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
0.6 V
V
IY
1.4 V
1 V
V
V
IZ
RA
0.4 V
V
ID
ID
V
IY
V
IC
= 0 V
V
O
V
IZ
C = 10 pF
L
–0.4 V
t
t
PLH
PHL
V
V
V
OH
V
O
80%
20%
/2
CC
OL
t
f
t
r
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the
device under test.
Figure 17. Timing Test Circuit and Waveforms
V
V
V
IH
RA
DA
V
I
/2
CC
2 V
IL
V
O
t
t
PLH
LPBK
PHL
V
I
C = 10 pF
L
V
OH
V
V
/2
CC
V
O
OL
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the
device under test.
Figure 18. LPBK Timing Test Circuit and Waveforms
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V
IH
RA
DA
V
V
I
V
V
/2
CC
IL
V
O
I
t
t
PLH
PHL
C
= 10 pF
L
V
OH
V
V
/2
CC
V
O
OL
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the
device under test.
Figure 19. DA to RA Timing Test Circuit and Waveforms
500 Ω
BY
RA
BZ
1.2 V
+
V
test
V
O
_
10 pF
OEA
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse
r
f
width = 500 ± 10 ns . C includes instrumentation and fixture capacitance within 0,06 m of the device under test.
L
2.5 V
1 V
V
TEST
BY
V
V
CC
OEA
RA
/2
CC
0 V
t
t
PLZ
PZL
2.5 V
1.4 V
V
OL
V
OL
+ 0.5 V
0 V
1.4 V
V
TEST
BY
V
V
CC
/2
CC
OEA
RA
0 V
t
t
PHZ
PZH
V
V
OH
OH
–0.5 V
1.4 V
0 V
Figure 20. B-to-A Enable/Disable Time Test Circuit and Definitions
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V
I
D Input
V
M
GND
t
h
t
h
t
su
t
su
1/f
max
V
I
CLK/LEAB
or
V
M
CLK/LEBA
Input
GND
t
W
Figure 21. Setup and Hold Time Definition
OEB (High)
OMODE1 (Low)
OMODE2 (High)
D
Q
DA
BY
BZ
C
L
= 2 pF
C
V
OD
50 Ω ±1%
CLK/LEAB (↑)
V
V
CC
/2
CC
DA Input
0 V
t
su
= 0.5 ns
CLK/LEAB
t
t
PHL
PLH
V
OD
Output
~0 V
V
OD
= V – V
OBY OBZ
Figure 22. A-to-B Flip-Flop Mode Timing Circuit
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IMODE1 (Low)
IMODE2 (High)
CLK/LEBA (↑)
Q
D
C
RA Output
10 pF
BY
BZ
V
ID
Input
OEA (High)
LPBK (Low)
ENR (Low)
V
ID
= V – V
BY BZ
V
BY
V
BZ
0.4 V
0 V
V
ID
Input
–0.4 V
t
su
= 0.5 ns
CLK/LEBA
t
t
PHL
PLH
~V
CC
V
OH
RA Output
~V /2
CC
~0 V
Figure 23. B-to-A Flip-Flop Mode Timing Circuit
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APPLICATION INFORMATION
ABSTRACT
This section discusses electrical and operational topics not previously covered in this document, such as error
detection and the device's ability to synchronize clock signals or manage data transfer between systems with
different clock speeds. Basic applications of the analog and digital system diagnostic loopback functions and
timing considerations are also analyzed. The SN65LVDM320 is resistant, although not immune, to the effect of
setup and hold-time violations; therefore, the penalties of a violation are also examined.
INTRODUCTION
The SN65LVDM320 is a versatile, multifunctional device with many applications. Low EMI, low crosstalk, and
high differential-current output makes the SN65LVDM320 ideally suited for sensitive multipoint applications and
low-impedance loads. Balanced differential signaling reduces noise coupling and allows high signaling rates.
Balanced means that the current flowing in each signal line is equal but opposite in direction, resulting in a field
canceling effect. This is one of the keys to the low-noise performance of an LVDS differential bus.
Balanced differential input signals eliminate induced noise with efficient common mode rejection (CMR). Internal
chip design techniques reduce noise generated by inductive and capacitive mutual coupling, thereby increasing
signal integrity. One of the techniques employed to reduce internal noise is the design of separate, dedicated
grounds for the single-ended and differential circuitry incorporated within the device.
APPLICATIONS
The SN65LVDM320 may be used to connect major system blocks, including parallel processors, DRAMs,
fast-cache SRAMs, and complex ASIC gate arrays. It effectively transceives the addresses, data, and control
signals of these integrated-circuit elements to and from system blocks and backplanes.
The SN65LVDM320 not only facilitates extremely-high parallel burst-transfer rates, but in buffer mode, can move
a constant stream of data at 475 Mbps through all of the eight channels simultaneously for a total data
throughput exceeding 5 Gbps (transfer rate).
Deskewing clock signals is a requirement in many complex high-speed circuits, and the SN65LVDM320 performs
this function at synchronous parallel transfers of 300 megatransfers per second (Mxferps) with very-low
channel-to-channel output skew.
The SN65LVDM320 is also ideally suited for connecting system blocks operating at different clock speeds. When
OEA and OEB are low, the system on the A-side of the device may be operated independently of the system on
the B-side.
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APPLICATION INFORMATION (continued)
DIAGNOSTICS AND ERROR DETECTION
OEB (High)
OMODE1 (High)
OMODE2 (Low)
CLK/LEAB
(Low to High)
LPBK
NODE
D
Q
BY
BZ
C
DA
IMODE1 (High)
IMODE2 (Low)
CLK/LEBA
(Low to High)
Q
D
RA
C
OEA (High)
LPBK (High)
ENR (High)
One-of-Eight Channels
Figure 24. Loopback Error Detection
It is not a requirement that the driver be disabled (OEB low) during loopback. The driver may be enabled (OEB
high) while loopback is engaged at any time without damaging the circuit. The loopback configuration in
Figure 24 with the differential driver enabled provides error assessment in which transmitted data is looped back
and compared to the original data by the microprocessor/microcontroller host. This may be implemented in
buffer, flip-flop, or in the latch mode shown in Figure 24, and in accordance with the logic of Table 2 and Table 3.
The SN65LVDM320 has been designed to improve a circuit's fault detection capabilities. 100% of the circuitry of
the SN65LVDM320 may be functionally checked by activating the A-side and B-side loopback modes. With this
functionality, a problem rack, card, circuit block, and even a chip can be located without the burden of
boundary-scan protocols.
Traditionally, testability functions such as read-back, pattern insertion, and functional hardware test control
require additional part count, connector pins, board space, power, and cost. However, the SN65LVDM320
provides full circuit observability and controllability within the package of an 8-bit LVDM transceiver.
METASTABILITY IN LATCHES AND FLIP-FLOPS
Interfacing the asynchronous world to synchronous logic systems can cause problems. Latches and flip-flops, or
basically, registers which are normally considered to have only two stable states (low and high) actually have a
third state, the metastable state. Metastability can occur when the setup or the hold time is violated and the latch
remains balanced in its threshold region. While in this metastable state, system noise can trigger either a high or
low state.
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APPLICATION INFORMATION (continued)
DA
D1
D3
Q
D4
D2
CLK/LEAB
Figure 25. The A-Side to B-Side Signal Path
OEB (High)
OMODE1 (High)
OMODE2 (Low)
BY
BZ
DA
D
C
Q
CLK/LEAB
Figure 26. SN65LVDM320 D-Type latch
The SN65LVDM320 D-type latch circuitry of Figure 26 is shown in Figure 25. When data at pin DA is applied to
D1, data is internally applied to D2. Therefore, when the CLK/LEAB pin is low, the outputs of D1 and D2 are high
and the D3/D4 R-S latch is latched and stable. When CLK/LEAB transitions to high, the latch is transparent to
the data input to DA and Q equals DA.
If data changes during the setup to hold time period, it is possible for the D1 and D2 outputs to be in the
threshold region of D3 and D4. Under these conditions, D3 and D4 could be perfectly balanced in a metastable
condition, allowing system noise to force the latch into a high or low state. This metastable condition can
theoretically last as long as 25 ns and cause a system to crash if care is not taken with the
asynchronous/synchronous interface. Although the SN65LVDM320 is metastable resistant by design, it is not
entirely immune, and the setup and hold times must adhere to those listed in the timing requirements section.
TYPICAL SN65LVDM320 OUTPUT WAVEFORM (THE EYE PATTERN)
Figure 27 displays a receiver's detection window in a typical LVDS output signal. When a receiver's
differential-input voltage level drops, the system noise margin is reduced. Lowering the height enters the input
voltage threshold of a receiver, eventually closing the eye and corrupting the data. Jitter content decreases the
available time for accurate reception, and depending upon the application, may exceed 50% of the bit width
without any problems. To read more about the terms and sources of jitter, see the Jitter Analysis application
report (SLLA075).
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APPLICATION INFORMATION (continued)
Noise Margin
Noise Margin
Receiver Detection
Window
Allowable Jitter
Figure 27. Receiver Detection Window in a Typical LVDS Driver Output
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APPLICATION INFORMATION (continued)
Figure 28. A Receiver Output With All Eight Channels at 630 Megatransfers per Second
The highest signaling rate measurable is 630 Mbps due to the limitations of the test circuit and equipment used
to capture this oscillograph. It was captured while all eight channels were transmitting data in B-to-A buffer mode
from the differential bus to the receiver. The measurement is taken from a receiver output test point across a
1.75-in, 50-Ω characteristic impedance trace of a TI bench evaluation board.
TEST EQUIPMENT
HP 6236B dc power supply provides the required supply voltage of 3.3 V for the LVDM320. A Tektronix
HFS9009 signal generator is employed as a nonreturn-to-zero (NRZ), pseudo-random binary sequence (PRBS)
signal source for the LVDM320 and is adjusted as follows:
•
•
•
•
Pattern: NRZ, PRBS
Differential input high level: 1.6 V
Differential input low level: 0.8 V
Transition time: 800 ps
At high signaling rates, the influence of the equipment used to measure a signal of concern must be minimized.
A Tektronix 794D oscilloscope and Tektronix P6247 differential probes are used in this test. Each probe has a
bandwidth of 1 GHz and the probe capacitance is less than 1 pF.
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TYPICAL CHARACTERISTICS
DRIVER BUFFER MODE
DRIVER BUFFER MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4.0
3.5
3.0
2.5
4.0
3.5
3.0
2.5
V
= 3.3 V
V
= 3.3 V
CC
CC
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
CC
= 3.6 V
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 29.
Figure 30.
DRIVER LATCH MODE
DRIVER LATCH MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
7.0
6.5
6.0
5.5
5.0
4.5
4.0
6.5
6.0
5.5
5.0
4.5
4.0
V
= 3.3 V
CC
V
CC
= 3.0 V
V
CC
= 3.0 V
V
= 3.6 V
CC
V
CC
= 3.6 V
V
CC
= 3.3 V
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T − Free-Air Temperature − °C
A
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
DRIVER FLIP-FLOP MODE
DRIVER FLIP-FLOP MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
7.5
7.0
6.5
6.0
5.5
5.0
4.5
7.5
7.0
6.5
6.0
5.5
5.0
4.5
V
= 3.3 V
CC
V
= 3.3 V
CC
V
CC
= 3.0 V
V
CC
= 3.0 V
V
= 3.6 V
V
= 3.6 V
CC
CC
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 33.
Figure 34.
RECEIVER BUFFER MODE
RECEIVER BUFFER MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5.5
5.0
4.5
4.0
3.5
5.0
4.5
4.0
3.5
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
CC
= 3.6 V
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
RECEIVER LATCH MODE
RECEIVER LATCH MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
7.5
7.0
6.5
6.0
5.5
7.5
7.0
6.5
6.0
5.5
5.0
V
CC
= 3.3 V
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
CC
= 3.6 V
V
CC
= 3.3 V
25
−40
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 37.
Figure 38.
RECEIVER FLIP-FLOP MODE
RECEIVER FLIP-FLOP MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
8.0
7.5
7.0
6.5
6.0
5.5
8.0
7.5
7.0
6.5
6.0
5.5
V
= 3.3 V
CC
V
= 3.3 V
CC
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
= 3.6 V
CC
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 39.
Figure 40.
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TYPICAL CHARACTERISTICS (continued)
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.5
3
V = 3.3 V
CC
T = 25°C
A
V
T
A
= 3.3 V
= 25°C
CC
2.5
2
1.5
1
.5
0
0
2
4
6
8
10
12
0
−2
−4
−6
−8
I
− Low-Level Output Current − mA
OL
I
− High-Level Output Current − mA
OH
Figure 41.
Figure 42.
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
T
= 3.3 V
= 25°C
V
T
= 3.3 V
= 25°C
CC
CC
A
A
3
2
1
0
0
−20
− High-Level Output Current − mA
−40
−60
−80
0
10
I
20
30
40
50
60
70
80
I
− Low-Level Output Current − mA
OH
OL
Figure 43.
Figure 44.
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TYPICAL CHARACTERISTICS (continued)
AVERAGE SUPPLY CURRENT
AVERAGE SUPPLY CURRENT
vs
vs
FREQUENCY
FREQUENCY
150
160
155
150
145
V
CC
= 3.0 V
V
CC
= 3.3 V
148
146
144
142
140
T
A
= 85°C
T
= 85°C
A
T
A
= 25°C
T
A
= 25°C
T
A
= −40°C
T
= −40°C
A
200
250
300
350
400
200
250
300
350
400
f − Frequency − MHz
f − Frequency − MHz
Figure 45.
Figure 46.
AVERAGE SUPPLY CURRENT
vs
FREQUENCY
170
165
160
V
CC
= 3.6 V
T
A
= 85°C
T
= 25°C
A
T
A
= −40°C
155
200
250
300
350
400
f − Frequency − MHz
Figure 47.
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PACKAGE OPTION ADDENDUM
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30-Jul-2009
PACKAGING INFORMATION
Orderable Device
SN65LVDM320DGG
SN65LVDM320DGGG4
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
64
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
DGG
64
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN65LVDM320DGGR
ACTIVE
ACTIVE
TSSOP
TSSOP
DGG
DGG
64
64
TBD
TBD
Call TI
Call TI
Call TI
Call TI
SN65LVDM320DGGRG4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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