SN65MLVD204B_V01 [TI]
SN65MLVD204B Multipoint-LVDS Line Drivers and Receivers (Transceivers) With IEC ESD Protection;
| 型号： | SN65MLVD204B_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN65MLVD204B Multipoint-LVDS Line Drivers and Receivers (Transceivers) With IEC ESD Protection |
| 文件： | 总50页 (文件大小：2364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65MLVD204B
SLLSEN0C – NOVEMBER 2015 – REVISED SEPTEMBER 2020
SN65MLVD204B Multipoint-LVDS Line Drivers and Receivers (Transceivers)
With IEC ESD Protection
receivers which are optimized to operate at signaling
1 Features
rates up to 100 Mbps. This device family has robust
3.3-V drivers and receivers in the standard SOIC and
QFN footprint for demanding industrial applications.
The bus pins are robust to ESD events, with high
levels of protection to human-body model and IEC
contact discharge specifications.
•
Compatible with the M-LVDS Standard TIA/
EIA-899 for Multipoint Data Interchange
Low-Voltage Differential 30-Ω to 55-Ω Line Drivers
and Receivers for Signaling Rates(1) Up to 100
Mbps, Clock Frequencies up to 50 MHz
– Type-2 Receiver Provides an Offset Threshold
to Detect Open-Circuit and Idle-Bus Conditions
Bus I/O Protection
•
The SN65MLVD204B combine a differential driver
and a differential receiver (transceiver), which operate
from a single 3.3-V supply. The transceivers are
optimized to operate at signaling rates up to 100
Mbps.
•
– >±8-kV HBM
– >±8-kV IEC 61000-4-2 Contact Discharge
Controlled Driver Output Voltage Transition Times
for Improved Signal Quality
-1-V to 3.4-V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC
1.5 V
200-Mbps Device Available (SN65MLVD206B) 1
•
•
•
The SN65MLVD204B has enhancements over similar
devices. Improved features include a controlled slew
rate on the driver output to help minimize reflections
from unterminated stubs, resulting in better signal
integrity. The same footprint definition was
maintained, allowing for an easy drop-in replacement
for a system performance upgrade. The devices are
characterized for operation from –40°C to 85°C.
≤
•
•
Improved Alternatives to SN65MLVD204A
The SN65MLVD204B M-LVDS transceivers are part of
TI’s extensive M-LVDS portfolio.
2 Applications
•
Low-Power, High-Speed, and Short-Reach
Alternative to TIA/EIA-485
Device Information (1)
PART NUMBER
SN65MLVD204B
SN65MLVD204B
PACKAGE
BODY SIZE (NOM)
4.90 mm × 3.91 mm
4.0 mm x 4.0 mm
•
Backplane or Cabled Multipoint Data and Clock
Transmission
SOIC (8)
WQFN (16)
•
•
•
Cellular Base Stations
Central Office Switches
Network Switches and Routers
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
3 Description
The SN65MLVD204B device is a multipoint-low-
voltage differential (M-LVDS) line drivers and
SPACER
D
DE
RE
A
B
R
Simplified Schematic, SN65MLVD204B
1
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the
bps of the unit (bits per second).
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
SN65MLVD204B
SLLSEN0C – NOVEMBER 2015 – REVISED SEPTEMBER 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 4
Pin Functions ................................................................... 5
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................7
6.6 Electrical Characteristics – Driver ..............................7
6.7 Electrical Characteristics – Receiver ......................... 8
6.8 Electrical Characteristics – BUS Input and Output .... 8
6.9 Switching Characteristics – Driver ............................. 8
6.10 Switching Characteristics – Receiver .......................9
6.11 Typical Characteristics............................................ 10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Application.................................................... 20
10 Power Supply Recommendations..............................25
11 Layout...........................................................................26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................31
12.1 Receiving Notification of Documentation Updates..31
12.2 Support Resources................................................. 31
12.3 Trademarks.............................................................31
12.4 Electrostatic Discharge Caution..............................31
12.5 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Information.................................................................... 32
13.1 Package Option Addendum....................................33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (November 2015) to Revision A (December 2016)
Page
•
Changed the device status From: Preview To: Production ................................................................................1
Changes from Revision A (December 2016) to Revision B (March 2020)
Page
•
Deleted all references in the text, tables, and figures for devices SN65MLVD200B, SN65MLVD202B, and
SN65MLVD205B ................................................................................................................................................1
Deleted the D 14-Pin Package from the Pin Configuration and Functions ........................................................3
In Bus Input and Output electrical characteristics, changed CA and CB from 5 pF to 12pF................................8
In Bus Input and Output electrical characteristics, changed CAB from 4pF to 7pF............................................. 8
Removed Type1 receiver input threshold test voltage table ............................................................................ 11
Removed pin numbers from Functional Block Diagrams..................................................................................17
Removed Type-1 receiver table in Device Function Table section. ................................................................. 18
•
•
•
•
•
•
Changes from Revision B (March 2020) to Revision C (September 2020)
Page
•
•
•
16-pin WQFN (RUM) package option is in Preview status.................................................................................5
Added 16-pin WQFN (RUM) package option..................................................................................................... 5
Added thermal information for 16-pin WQFN (RUM)..........................................................................................6
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5 Pin Configuration and Functions
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
A
GND
Not to scale
Figure 5-1. D Package 8-Pin SOIC Top View
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Pin Functions
PIN
TYPE
DESCRIPTION
NAME
A
NO.
6
I/O
I/O
Differential I/O
Differential I/O
Driver input
B
7
D
4
Input
Input
Power
NC
DE
GND
NC
R
3
Driver enable pin; High = Enable, Low = Disable
Supply ground
5
—
1
No internal connection
Output
Input
Power
I/O
Receiver output
RE
VCC
Y
2
Receiver enable pin; High = Disable, Low = Enable
Power supply, 3.3 V
8
—
—
Differential I/O
Z
I/O
Differential I/O
R
RE
DE
D
1
2
3
4
12
11
10
9
NC
B
Thermal Pad
A
NC
Not to scale
Figure 5-2. RUM Package 16-Pin WQFN Top View
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Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
R
Output
Input
Input
Input
Power
Power
NC
Receiver output
2
RE
Receiver enable pin; High = Disable, Low = Enable
Driver enable pin; High = Enable, Low = Disable
Driver input
3
DE
4
D
5
GND
Supply ground
6
GND
Supply ground
7
NC
No internal connection
No internal connection
No internal connection
Differential I/O
8
NC
NC
9
NC
NC
10
11
12
13
14
15
16
TP
A
I/O
B
I/O
Differential I/O
NC
NC
No internal connection
Power supply, 3.3 V
VCC
Power
Power
NC
VCC
Power supply, 3.3 V
NC
No internal connection
No internal connection
Thermal pad. Connect to a solid ground plane.
NC
NC
Thermal Pad
Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–1.8
–0.3
–1.8
MAX
UNIT
(2)
Supply voltage range, VCC
4
4
4
4
4
V
V
V
V
V
D, DE, RE
Input voltage range
A, B
R
Output voltage range
A, B
Continuous power dissipation
Storage temperature, Tstg
See the Thermal Information table
–65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±8000
±8000
UNIT
Contact discharge, per IEC 61000-4-2
A, B
A, B
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
V(ESD) Electrostatic discharge all pins
All pins except A
and B
V
±4000
±1500
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins
All pins
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM MAX UNIT
VCC
VIH
VIL
Supply voltage
3.3
3.6
VCC
0.8
V
V
V
V
V
Ω
High-level input voltage
2
Low-level input voltage
0
Voltage at any bus terminal VA or VB
Magnitude of differential input voltage
Differential load resistance
–1.4
3.8
|VID|
RL
VCC
30
50
1/tUI
TA
Signaling rate
100 Mbps
Operating free-air temperature for D package
Operating free-air temperature for RUM package
–40
–40
85
°C
°C
TA
125
6.4 Thermal Information
SN65MLVD204B
RUM
THERMAL METRIC(1)
D (SOIC)
UNIT
(WQFN)
16 PINS
39.0
8 PINS
112.2
56.7
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
34.7
52.8
17.7
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
10.3
0.6
ψJB
52.3
17.7
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SN65MLVD204B
RUM
THERMAL METRIC(1)
D (SOIC)
UNIT
(WQFN)
16 PINS
7.5
8 PINS
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Driver only
REand DE at VCC, RL = 50 Ω, All others open
REat VCC, DE at 0 V, RL = No Load, All others open
REat 0 V, DE at VCC, RL = 50 Ω, All others open
RE at 0 V, DE at 0 V, All others open
13
1
22
4
Both disabled
Both enabled
Receiver only
ICC
Supply current
mA
16
4
24
13
RL = 50 Ω, Input to D is a 50-MHz 50% duty cycle square
wave, DE = high, RE= low, TA = 85°C
PD
Device power dissipation
100
mW
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
6.6 Electrical Characteristics – Driver
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN(1) TYP(2)
MAX UNIT
|VAB
|
Differential output voltage magnitude (3)
480
650
50
mV
mV
V
See Figure 7-2
See Figure 7-3
Change in differential output voltage magnitude
between logic states
Δ|VAB
|
–50
0.8
VOS(SS)
Steady-state common-mode output voltage
1.2
50
Change in steady-state common-mode output
voltage between logic states
ΔVOS(SS)
–50
mV
VOS(PP)
VA(OC)
VB(OC)
VP(H)
VP(L)
IIH
Peak-to-peak common-mode output voltage
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
High-level input current (D, DE)
150
2.4
mV
V
0
0
See Figure 7-7
See Figure 7-5
2.4
V
1.2 VSS
V
–0.2 VSS
V
VIH = 2 V to VCC
VIL = GND to 0.8 V
See Figure 7-4
0
0
10
10
24
µA
µA
mA
IIL
Low-level input current (D, DE)
|IOS
|
Differential short-circuit output current magnitude
(1) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) Measurement equipment accuracy is 10 mV at –40°C
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6.7 Electrical Characteristics – Receiver
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
Positive-going differential input voltage
VIT+
VIT-
Type 2
150
threshold (2)
Negative-going differential input voltage
threshold (2)
See Figure 7-9 and Table 7-1
mV
Type 2
Type 2
50
VHYS
VOH
VOL
IIH
Differential input voltage hysteresis, (VIT+ – VIT–
)
0
High-level output voltage (R)
IOH = –8 mA
2.4
V
Low-level output voltage (R)
IOL = 8 mA
0.4
0
V
High-level input current (RE)
VIH = 2 V to VCC
VIL = GND to 0.8 V
VO = 0 V or 3.6 V
–10
–10
–10
µA
µA
µA
IIL
Low-level input current (RE)
0
IOZ
High-impedance output current (R)
15
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) Measurement equipment accuracy is 10 mV at -40℃
6.8 Electrical Characteristics – BUS Input and Output
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VB = 1.2 V,
VA = 0 V or 2.4 V, VB = 1.2 V
MIN TYP(1) MAX UNIT
VA = 3.8 V,
0
–20
–32
0
32
20
0
Receiver or transceiver with driver
disabled input current
IA
µA
VA = –1.4 V,
VB = 3.8 V,
VB = 1.2 V
VA = 1.2 V
32
20
0
Receiver or transceiver with driver
disabled input current
IB
VB = 0 V or 2.4 V, VA = 1.2 V
–20
–32
µA
µA
µA
VB = –1.4 V,
VA = VB,
VA = 1.2 V
Receiver or transceiver with driver
disabled differential input current (IA – IB)
IAB
1.4 ≤ VA ≤ 3.8 V
–4
4
VA = 3.8 V,
VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
0
–20
–32
0
32
20
0
Receiver or transceiver power-off input
current
IA(OFF)
VA = 0 V or 2.4 V, VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
VA = –1.4 V,
VB = 3.8 V,
VB = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
32
20
0
Receiver or transceiver power-off input
current
IB(OFF)
VB = 0 V or 2.4 V, VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
VB = –1.4 V, VA = 1.2 V, 0 V ≤ VCC ≤ 1.5 V
–20
–32
µA
Receiver input or transceiver power-off
differential input current (IA – IB)
IAB(OFF)
VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V
VA = 0.4 sin (30E6πt) + 0.5 V(2), VB = 1.2 V
VB = 0.4 sin (30E6πt) + 0.5 V(2), VA = 1.2 V
VAB = 0.4 sin (30E6πt)V(2)
–4
4
µA
pF
pF
pF
Transceiver with driver disabled input
capacitance.
CA
12
12
7
Transceiver with driver disabled input
capacitance
CB
Transceiver with driver disabled
differential input capacitance
CAB
CA/B
Transceiver with driver disabled input
capacitance balance, (CA/CB)
0.99
1.01
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
6.9 Switching Characteristics – Driver
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
tpLH
tpHL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
2
2
2.5
2.5
3.5
3.5
ns
ns
See Figure 7-5
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over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
tr
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tpHL – tpLH|)
2
2
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
tf
tsk(p)
30
150
0.9
3
tsk(pp) Part-to-part skew (2)
tjit(per) Period jitter, rms (1 standard deviation)(3)
tjit(pp) Peak-to-peak jitter(3) (6)
50-MHz clock input(4)
2
55
4
100 Mbps 215 –1 PRBS input(5)
150
7
tPHZ
tPLZ
tPZH
tPZL
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
4
7
See Figure 7-6
4
7
4
7
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) Part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same V/T conditions.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) tr = tf = 0.5 ns (10% to 90%), measured over 30K samples.
(5) tr = tf = 0.5 ns (10% to 90%), measured over 100K samples.
(6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
6.10 Switching Characteristics – Receiver
over recommended operating conditions unless otherwise noted
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
TEST CONDITIONS
MIN TYP(1) MAX UNIT
tPLH
tPHL
tr
2
2
6
6
10
10
ns
ns
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
CL = 15 pF, See Figure 7-10
2.3
2.3
750
1
tf
Output signal fall time
tsk(p)
Pulse skew (|tpHL – tpLH|)
Type 2 CL = 15 pF, See Figure 7-10
CL = 15 pF, See Figure 7-10
400
tsk(pp) Part-to-part skew(2)
tjit(per) Period jitter, rms (1 standard deviation)(3)
50-MHz clock input(4)
2
225
6
tjit(pp)
tPHZ
tPLZ
tPZH
tPZL
Peak-to-peak jitter(3) (6)
Type 2 100 Mbps 215 –1 PRBS input(5)
800
10
10
15
15
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
6
See Figure 7-11
10
10
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) Part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same V/T conditions.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) , VID = 400 mVpp , Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30K samples.
(5) , VID = 400 mVpp , Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100K samples.
(6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)
)
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6.11 Typical Characteristics
594
592
590
588
586
584
582
580
578
576
3
3.1
3.2
3.3
VCC (V)
3.4
3.5
3.6
D001
TA = 25°C
Figure 6-1. Differential Output Voltage vs Supply Voltage
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7 Parameter Measurement Information
V
CC
I
A
A
I
I
D
V
AB
I
B
V
A
B
V
I
V
OS
V
B
V
A
+ V
B
2
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. Driver Voltage and Current Definitions
3.32 kΩ
A
+
_
-1 V ≤ V <3.4 V
test
V
AB
49.9 Ω
D
B
3.32 kΩ
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A. All resistors are 1% tolerance.
Figure 7-2. Differential Output Voltage Test Circuit
A
R1
24.9 Ω
≈ 1.3 V
≈ 0.7 V
A
B
C1
1 pF
D
V
V
OS(SS)
OS(PP)
V
OS
B
C3
R2
24.9 Ω
V
OS(SS)
2.5 pF
C2
1 pF
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A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 1 MHz, duty cycle = 50 ±
5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 7-3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
I
OS
A
0 V or V
CC
+
B
V
-
-1 V or 3.4 V
Test
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Figure 7-4. Driver Short-Circuit Test Circuit
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A
C1
1 pF
C3
R1
50 Ω
Output
D
0.5 pF
B
C2
1 pF
V
V
CC
/2
CC
Input
0 V
t
t
pHL
pLH
V
SS
0.9V
SS
V
P(H)
Output
0 V
V
P(L)
0.1V
SS
0 V
SS
t
t
r
f
Copyright © 2016, Texas Instruments Incorporated
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 7-5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A
C1
1 pF
D
C4
0.5 pF
0 V or V
Output
CC
C3
2.5 pF
C2
1 pF
B
R2
24.9 Ω
DE
V
V
CC
/2
CC
DE
0 V
t
t
t
pZH
pHZ
~ 0.6 V
0.1 V
Output With
D at V
0 V
CC
t
pZL
pLZ
Output With
D at 0 V
0 V
-0.1 V
~ -0.6 V
Copyright © 2016, Texas Instruments Incorporated
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 7-6. Driver Enable and Disable Time Circuit and Definitions
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A
B
0 V or V
CC
V , V
A
1.62 kΩ , 1ꢀ
B
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Figure 7-7. Maximum Steady State Output Voltage
V
CC
CC
CLOCK
INPUT
V
/2
0 V
1/f0
Period Jitter
IDEAL
V
V
CC
0 V
OUTPUT
PRBS INPUT
/2
CC
V
A
-V
B
1/f0
0 V
ACTUAL
OUTPUT
Peak to Peak Jitter
0 V
V
A
-V
B
V
A
-V
B
OUTPUT 0 V Diff
-V
t
c(n)
V
t
=
t
c(n)
-1/f0
A
B
jit(per)
t
jit(pp)
Copyright © 2016, Texas Instruments Incorporated
A. All input pulses are supplied by an Agilent 81250 Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 100 Mbps 215–1 PRBS input.
Figure 7-8. Driver Jitter Measurement Waveforms
I
A
A
B
I
O
R
V
ID
V
O
V
CM
V
A
I
B
(V + V )/2
A B
V
B
Copyright © 2016, Texas Instruments Incorporated
Figure 7-9. Receiver Voltage and Current Definitions
Table 7-1. Type-2 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL RESULTING COMMON-
APPLIED VOLTAGES
RECEIVER
OUTPUT(1)
INPUT VOLTAGE
MODE INPUT VOLTAGE
VIA
VIB
VID
VIC
1.200
1.200
3.4
2.400
0.000
3.475
0.000
2.400
3.325
2.400
–2.400
0.150
H
L
H
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Table 7-1. Type-2 Receiver Input Threshold Test Voltages (continued)
RESULTING DIFFERENTIAL RESULTING COMMON-
APPLIED VOLTAGES
RECEIVER
OUTPUT(1)
INPUT VOLTAGE
MODE INPUT VOLTAGE
VIA
VIB
VID
VIC
3.4
–1
3.425
–0.925
–0.975
3.375
–1.075
–1.025
0.050
0.150
0.050
L
H
L
–1
(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)
V
ID
V
A
C
L
V
O
15 pF
V
B
V
1.2 V
1 V
A
V
B
V
ID
0.2 V
0 V
–0.2 V
t
t
pLH
pHL
V
OH
V
O
90%
10%
V
V
/2
CC
OL
t
t
r
f
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 7-10. Receiver Timing Test Circuit and Waveforms
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R
L
499 Ω
B
A
1.2 V
R
+
_
C
L
V
TEST
V
O
Inputs
RE
15 pF
V
CC
V
TEST
1 V
A
V
V
CC
RE
/2
/2
CC
0 V
t
t
pLZ
pZL
V
CC
V
CC
Output
R
V
OL
V
OL
+0.5 V
V
TEST
0 V
1.4 V
A
V
V
CC
RE
/2
CC
0 V
t
t
pHZ
pZH
V
V
V
OH
–0.5 V
OH
V
O
/2
CC
0 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%.
Figure 7-11. Receiver Enable and Disable Time Test Circuit and Waveforms
INPUTS
CLOCK INPUT
V
A
–V
B
V
IC
0.2 V – Type 1 1 V
0.4 V – Type 2
V
A
–V
B
1/f0
Period Jitter
V
OH
IDEAL
OUTPUT
V
A
V /2
CC
PRBS INPUT
V
OL
1/f0
V
B
V
OH
ACTUAL
OUTPUT
Peak-to-Peak Jitter
V
/2
CC
V
OH
V
OL
OUTPUT
V /2
CC
t
c(n)
t
= │t
–1/f0│
V
OL
jit(per)
c(n)
t
jit(pp)
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input.
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D. Peak-to-peak jitter is measured using a 100 Mbps 215-1 PRBS input.
Figure 7-12. Receiver Jitter Measurement Waveforms
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8 Detailed Description
8.1 Overview
The SN65MLVD204B is a multipoint-low-voltage differential (M-LVDS) line drivers and receivers, which are
optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage
differential signaling (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard
compliant LVDS counterparts, with added features to address multipoint applications. The driver output has been
designed to support multipoint buses presenting loads as low as 30 Ω, and incorporates controlled transition
times to allow for stubs off of the backbone transmission line.
The SN65MLVD204B has Type-2 receiver that detect the bus state with as little as 50 mV of differential input
voltage over a common-mode voltage range of –1 V to 3.4 V. Type-2 receivers include an offset threshold to
provide a known output state under open-circuit, idle-bus, and other fault conditions.
8.2 Functional Block Diagram
D
DE
RE
A
R
B
Figure 8-1. SN65MLVD204B Block Diagram
8.3 Feature Description
8.3.1 Power-On-Reset
The SN65MLVD204B device operates and meets all the specified performance requirements for supply voltages
in the range of 3 V to 3.6 V. When the supply voltage drops below 1.5 V (or is turning on and has not yet reached
1.5 V), power-on reset circuitry set the driver output to a high-impedance state.
8.3.2 ESD Protection
The bus terminals of the SN65MLVD204B possess on-chip ESD protection against ±8-kV human body model
(HBM) and ±8-kV IEC61000-4-2 contact discharge. The IEC-ESD test is far more severe than the HBM-ESD
test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD of the IEC model
produce significantly higher discharge currents than the HBM-model.
As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap
testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact
discharge test results.
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RC
RD
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
CS
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
Figure 8-2. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)
8.4 Device Functional Modes
8.4.1 Operation with VCC < 1.5 V
Bus pins will be high impedance under this condition.
8.4.2 Operations with 1.5 V ≤ VCC < 3 V
Operation with supply voltages in the range of 1.5 V ≤ VCC < 3 V is undefined and no specific device
performance is guaranteed in this range.
8.4.3 Operation with 3 V ≤ VCC < 3.6 V
Operation with the supply voltages greater than or equal to 3 V and less than or equal to 3.6 V is normal
operation.
8.4.4 Device Function Tables
Table 8-1. Type-2 Receiver (1)
INPUTS
OUTPUT
VID = VA - VB
RE
R
H
?
VID ≥ 150 mV
L
L
50 mV < VID < 150 mV
VID ≤ 50 mV
L
L
X
X
H
Z
Z
Open
(1) H = high level, L = low level, Z = high impedance, X = Don't care, ? - indeterminate
Table 8-2. Driver (1)
INPUTS
ENABLE
OUTPUTS
D
L
DE
H
A
L
B
H
L
H
H
H
L
Open
X
H
H
Z
Z
Open
L
Z
Z
X
(1) H = high level, L = low level, Z = high impedance, X = Don't care, ? - indeterminate
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8.4.5 Equivalent Input and Output Schematic Diagrams
DRIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
RECEIVER ENABLE
V
CC
V
CC
V
CC
360 kΩ
400 Ω
400 Ω
D or DE
7 V
A or B
RE
7 V
360 kΩ
RECEIVER INPUT
RECEIVER OUTPUT
V
CC
V
CC
100 kΩ
250 kΩ
100 kΩ
250 kΩ
10 Ω
10 Ω
R
A
B
200 kΩ
200 kΩ
7 V
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN65MLVD204B is a multipoint line drivers and receivers. The functionality of these devices is simple, yet
extremely flexible, leading to their use in designs ranging from wireless base stations to desktop computers.
9.2 Typical Application
9.2.1 Multipoint Communications
In a multipoint configuration many transmitters and many receivers can be interconnected on a single
transmission line. The key difference compared to multi-drop is the presence of two or more drivers. Such a
situation creates contention issues that need not be addressed with point-to-point or multidrop systems.
Multipoint operation allows for bidirectional, half-duplex communication over a single balanced media pair. To
support the location of the various drivers throughout the transmission line, double termination of the
transmission line is now necessary.
The major challenge that system designers encounter are the impedance discontinuities that device loading and
device connections (stubs) introduce on the common bus. Matching the impedance of the loaded bus and using
signal drivers with controlled signal edges are the keys to error-free signal transmissions in multipoint topologies.
~
~
100 Ω
~
100 Ω
~
R
R
R
R
D
D
D
D
Figure 9-1. Multipoint Configuration
9.2.2 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETERS
VALUES
3 to 3.6 V
Driver supply voltage
Driver input voltage
0.8 to 3.3 V
DC to 100 Mbps
100 Ω
Driver signaling rate
Interconnect characteristic impedance
Termination resistance (differential)
Number of receiver nodes
Receiver supply voltage
100 Ω
2 to 32
3 to 3.6 V
Receiver input voltage
0 to (VCC – 0.8) V
DC to 100 Mbps
±1 V
Receiver signaling rate
Ground shift between driver and receiver
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9.2.3 Detailed Design Procedure
9.2.3.1 Supply Voltage
The SN65MLVD204B operates from a single supply. The devices can support operation with a supply as low as
3 V and as high as 3.6 V.
9.2.3.2 Supply Bypass Capacitance
Bypass capacitors play a key role in power distribution circuitry. At low frequencies, power supply offers very
low-impedance paths between its terminals. However, as higher frequency currents propagate through power
traces, the source is often incapable of maintaining a low-impedance path to ground. Bypass capacitors are
used to address this shortcoming. Usually, large bypass capacitors (10 μF to 1000 μF) at the board level do a
good job up into the kHz range. Due to their size and length of their leads, large capacitors tend to have large
inductance values at the switching frequencies. To solve this problem, smaller capacitors (in the nF to μF range)
must be installed locally next to the integrated circuit.
Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass
capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes,
a typical capacitor with leads has a lead inductance around 5 nH.
The value of the bypass capacitors used locally with M-LVDS chips can be determined by Equation 1 and
Equation 2, according to High Speed Digital Design – A Handbook of Black Magic by Howard Johnson and
Martin Graham (1993). A conservative rise time of 4 ns and a worst-case change in supply current of 100 mA
covers the whole range of M-LVDS devices offered by Texas Instruments. In this example, the maximum power
supply noise tolerated is 100 mV; however, this figure varies depending on the noise budget available for the
design.
æ
ç
ç
è
ö
÷
÷
ø
DIMaximum Step Change Supply Current
Cchip
=
´ T
Rise Time
DVMaximum Power Supply Noise
(1)
(2)
æ
ç
è
ö
÷
ø
100 mA
100 mV
CMLVDS
=
´ 4ns = 0.004 mF
Figure 9-2 shows a configuration that lowers lead inductance and covers intermediate frequencies between the
board-level capacitor (>10 µF) and the value of capacitance found above (0.004 µF). Place the smallest value of
capacitance as close as possible to the chip.
3.3 V
0.1 µF
0.004 µF
Figure 9-2. Recommended M-LVDS Bypass Capacitor Layout
9.2.3.3 Driver Input Voltage
The input stage accepts LVTTL signals. The driver will operate with a decision threshold of approximately 1.4 V.
9.2.3.4 Driver Output Voltage
The driver outputs a steady state common mode voltage of 1 V with a differential signal of 540 V under nominal
conditions.
9.2.3.5 Termination Resistors
As shown earlier, an M-LVDS communication channel employs a current source driving a transmission line
which is terminated with two resistive loads. These loads serve to convert the transmitted current into a voltage
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at the receiver input. To ensure good signal integrity, the termination resistors should be matched to the
characteristic impedance of the transmission line. The designer should ensure that the termination resistors are
within 10% of the nominal media characteristic impedance. If the transmission line is targeted for 100-Ω
impedance, the termination resistors should be between 90 Ω and 110 Ω. The line termination resistors are
typically placed at the ends of the transmission line.
9.2.3.6 Receiver Input Signal
The M-LVDS receivers herein comply with the M-LVDS standard and correctly determine the bus state. These
devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential voltage
over the common mode range of –1 V to 3.4 V.
9.2.3.7 Receiver Input Threshold (Failsafe)
The MLVDS standard defines a Type-1 and Type-2 receiver. Type-1 receivers have their differential input voltage
thresholds near zero volts. Type-2 receivers have their differential input voltage thresholds offset from 0 V to
detect the absence of a voltage difference. The impact to receiver output by the offset input can be seen in Table
9-2 and Figure 9-3.
Table 9-2. Receiver Input Voltage Threshold Requirements
RECEIVER TYPE
OUTPUT LOW
OUTPUT HIGH
0.05 V ≤ VID ≤ 2.4 V
0.15 V ≤ VID ≤ 2.4 V
Type 1
–2.4 V ≤ VID ≤ –0.05 V
–2.4 V ≤ VID ≤ 0.05 V
Type 2
Type 1
Type 2
200
150
100
50
High
High
0
Low
-50
-100
Low
Transition Regions
Figure 9-3. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region
9.2.3.8 Receiver Output Signal
Receiver outputs comply with LVTTL output voltage standards when the supply voltage is within the range of 3 V
to 3.6 V.
9.2.3.9 Interconnecting Media
The physical communication channel between the driver and the receiver may be any balanced paired metal
conductors meeting the requirements of the M-LVDS standard, the key points which will be included here. This
media may be a twisted pair, twinax, flat ribbon cable, or PCB traces.
The nominal characteristic impedance of the interconnect should be between 100 Ω and 120 Ω with variation no
more than 10% (90 Ω to 132 Ω).
9.2.3.10 PCB Transmission Lines
As per SNLA187, Figure 9-4 depicts several transmission line structures commonly used in printed-circuit boards
(PCBs). Each structure consists of a signal line and a return path with uniform cross-section along its length. A
microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a
ground or power plane. A stripline is a signal trace in the inner layer, with a dielectric layer in between a ground
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plane above and below the signal trace. The dimensions of the structure along with the dielectric material
properties determine the characteristic impedance of the transmission line (also called controlled-impedance
transmission line).
When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 9-4 shows
examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. When excited by
differential signals, the coupled transmission line is referred to as a differential pair. The characteristic
impedance of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is
the differential impedance of the differential pair. In addition to the trace dimensions and dielectric material
properties, the spacing between the two traces determines the mutual coupling and impacts the differential
impedance. When the two lines are immediately adjacent; for example, if S is less than 2 × W, the differential
pair is called a tightly-coupled differential pair. To maintain constant differential impedance along the length, it is
important to keep the trace width and spacing uniform along the length, as well as maintain good symmetry
between the two lines.
Single-Ended Microstrip
Single-Ended Stripline
W
W
T
H
H
T
H
≈
’
≈
∆
«
’
÷
◊
1.9 2 H+ T
87
5.98 H
[
]
60
Z0
=
ln
Z0
=
ln
∆
∆
÷
÷
0.8 W + T
0.8 W + T
er +1.41
[
]
er
«
◊
Edge-Coupled
Edge-Coupled
S
S
H
H
Differential Microstrip
Differential Stripline
s
s
≈
’
÷
≈
’
÷
-0.96 ì
-2.9 ì
H
H
∆
∆
Zdiff = 2 ì Z0 ì 1- 0.48 ì e
Zdiff = 2 ì Z0 ì 1- 0.347 ì e
∆
«
÷
◊
∆
«
÷
◊
Co-Planar Coupled Microstrips
Broad-Side Coupled Striplines
W
W
W
G
S
G
H
S
H
Figure 9-4. Controlled-Impedance Transmission Lines
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9.2.4 Application Curves
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
TA = 25°C
Figure 9-5. Driver Fall Time
Figure 9-6. Driver Rise Time
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10 Power Supply Recommendations
The M-LVDS driver and receivers in this data sheet are designed to operate from a single power supply. Both
drivers and receivers operate with supply voltages in the range of 3 V to 3.6 V. In a typical application, a driver
and a receiver may be on separate boards, or even separate equipment. In these cases, separate supplies
would be used at each location. The expected ground potential difference between the driver power supply and
the receiver power supply would be less than ±1 V. Board level and local device level bypass capacitance should
be used and are covered Supply Bypass Capacitance.
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11 Layout
11.1 Layout Guidelines
11.1.1 Microstrip vs. Stripline Topologies
As per SLLD009, printed-circuit boards usually offer designers two transmission line options: Microstrip and
stripline. Microstrips are traces on the outer layer of a PCB, as shown in Figure 11-1.
Figure 11-1. Microstrip Topology
On the other hand, striplines are traces between two ground planes. Striplines are less prone to emissions and
susceptibility problems because the reference planes effectively shield the embedded traces. However, from the
standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. TI recommends
routing M-LVDS signals on microstrip transmission lines if possible. The PCB traces allow designers to specify
the necessary tolerances for ZO based on the overall noise budget and reflection allowances. Footnotes 12, 23,
and 34 provide formulas for ZO and tPD for differential and single-ended traces. 2 3 4
Figure 11-2. Stripline Topology
11.1.2 Dielectric Type and Board Construction
The speeds at which signals travel across the board dictates the choice of dielectric. FR-4, or equivalent, usually
provides adequate performance for use with M-LVDS signals. If rise or fall times of TTL/CMOS signals are less
than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as Rogers™ 4350
or Nelco N4000-13 is better suited. Once the designer chooses the dielectric, there are several parameters
2
Howard Johnson & Martin Graham.1993. High Speed Digital Design – A Handbook of Black Magic.
Prentice Hall PRT. ISBN number 013395724.
Mark I. Montrose. 1996. Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press. ISBN
3
number 0780311310.
4
Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.
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pertaining to the board construction that can affect performance. The following set of guidelines were developed
experimentally through several designs involving M-LVDS devices:
•
•
•
•
Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz
All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
Solder mask over bare copper with solder hot-air leveling
11.1.3 Recommended Stack Layout
Following the choice of dielectrics and design specifications, you must decide how many levels to use in the
stack. To reduce the TTL/CMOS to M-LVDS crosstalk, it is a good practice to have at least two separate signal
planes as shown in Figure 11-3.
Layer 1: Routed Plane (MLVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Routed Plane (TTL/CMOS Signals)
Figure 11-3. Four-Layer PCB Board
Note
The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and
ground planes tightly coupled, the increased capacitance acts as a bypass for transients.
One of the most common stack configurations is the six-layer board, as shown in Figure 11-4.
Layer 1: Routed Plane (MLVDS Signals)
Layer 2: Ground Plane
Layer 3: Power Plane
Layer 4: Ground Plane
Layer 5: Ground Plane
Layer 4: Routed Plane (TTL Signals)
Figure 11-4. Six-Layer PCB Board
In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one
ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer
board is preferable, because it offers the layout designer more flexibility in varying the distance between signal
layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.
11.1.4 Separation Between Traces
The separation between traces depends on several factors; however, the amount of coupling that can be
tolerated usually dictates the actual separation. Low noise coupling requires close coupling between the
differential pair of an M-LVDS link to benefit from the electromagnetic field cancellation. The traces should be
100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs
should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew
and signal reflection.
In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance
between two traces must be greater than two times the width of a single trace, or three times its width measured
from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The
same rule should be applied to the separation between adjacent M-LVDS differential pairs, whether the traces
are edge-coupled or broad-side-coupled.
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W
MLVDS
Pair
Minimum spacing as
defined by PCB vendor
Differential Traces
S =
W
í 2 W
W
Single-Ended Traces
TTL/CMOS
Trace
Figure 11-5. 3-W Rule for Single-Ended and Differential Traces (Top View)
You should exercise caution when using autorouters, because they do not always account for all factors affecting
crosstalk and signal reflection. For instance, it is best to avoid sharp 90° turns to prevent discontinuities in the
signal path. Using successive 45° turns tends to minimize reflections.
11.1.5 Crosstalk and Ground Bounce Minimization
To reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible
to its originating trace. A ground plane usually achieves this. Because the returning currents always choose the
path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing
crosstalk. Lowering the area of the current loop lowers the potential for crosstalk. Traces kept as short as
possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic
field strength. Discontinuities in the ground plane increase the return path inductance and should be avoided.
11.1.6 Decoupling
Each power or ground lead of a high-speed device should be connected to the PCB through a low inductance
path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally,
via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing a power plane closer
to the top of the board reduces the effective via length and its associated inductance.
V
GND
Via
CC
Via
TOP signal layer + GND fill
1 plane
4 mil
6 mil
V
DD
2 mil
Buried capacitor
>
GND plane
Signal layer
GND plane
Signal layers
V
plane
CC
Signal layer
GND plane
Buried capacitor
>
V
2 plane
DD
4 mil
6 mil
BOTTOM signal layer + GND fill
Typical 12-Layer PCB
Figure 11-6. Low Inductance, High-Capacitance Power Connection
Bypass capacitors should be placed close to VDD pins. They can be placed conveniently near the corners or
underneath the package to minimize the loop area. This extends the useful frequency range of the added
capacitance. Small-physical-size capacitors, such as 0402, 0201, or X7R surface-mount capacitors should be
used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power and ground
plane through vias tangent to the pads of the capacitor as shown in #unique_62/
unique_62_Connect_42_SLLS3734818(a).
An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30
MHz or so, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a
few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03 μF, and 0.1 μF are commonly
used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground
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at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.
Many high-speed devices provide a low-inductance GND connection on the backside of the package. This
center pad must be connected to a ground plane through an array of vias. The via array reduces the effective
inductance to ground and enhances the thermal performance of the small Surface Mount Technology (SMT)
package. Placing vias around the perimeter of the pad connection ensures proper heat spreading and the lowest
possible die temperature. Placing high-performance devices on opposing sides of the PCB using two GND
planes (as shown in Figure 9-4) creates multiple paths for heat transfer. Often thermal PCB issues are the result
of one device adding heat to another, resulting in a very high local temperature. Multiple paths for heat transfer
minimize this possibility. In many cases the GND pad makes the optimal decoupling layout impossible to achieve
due to insufficient pad-to-pad spacing as shown in #unique_62/unique_62_Connect_42_SLLS3734818(b). When
this occurs, placing the decoupling capacitor on the backside of the board keeps the extra inductance to a
minimum. It is important to place the VDD via as close to the device pin as possible while still allowing for
sufficient solder mask coverage. If the via is left open, solder may flow from the pad and into the via barrel. This
will result in a poor solder connection.
V
DD
0402
INœ
IN+
(a)
0402
(b)
11.2 Layout Example
At least two or three times the width of an individual trace should separate single-ended traces and differential
pairs to minimize the potential for crosstalk. Single-ended traces that run in parallel for less than the wavelength
of the rise or fall times usually have negligible crosstalk. Increase the spacing between signal paths for long
parallel runs to reduce crosstalk. Boards with limited real estate can benefit from the staggered trace layout, as
shown in Figure 11-7.
Layer 1
Layer 6
Figure 11-7. Staggered Trace Layout
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This configuration lays out alternating signal traces on different layers; thus, the horizontal separation between
traces can be less than 2 or 3 times the width of individual traces. To ensure continuity in the ground signal path,
TI recommends having an adjacent ground via for every signal via, as shown in Figure 11-8. Note that vias
create additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in
FR4.
Signal Via
Signal Trace
Uninterrupted Ground Plane
Signal Trace
Uninterrupted Ground Plane
Ground Via
Figure 11-8. Ground Via Location (Side View)
Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground
bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create
discontinuities that increase returning current loop areas.
To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and
so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the
same area, as opposed to mixing them together, helps reduce susceptibility issues.
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
Rogers™ is a trademark of Rogers Corporation.
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Option Addendum
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13.1.1 Packaging Information
Status Packag Package
Package
Qty
Lead/Ball MSL Peak Temp
Finish
Orderable Device
SN65MLVD204B
Pins
8
Eco Plan (2)
Op Temp (°C) Device Marking(4) (5)
(1)
(3)
e Type Drawing
ACTIV
E
Green (RoHS
& no Sb/Br)
CU
NIPDAU
Level-1-260C-
UNLIM
SOIC
SOIC
D
75
-40 to 85
-40 to 85
-40 to 125
-40 to 125
MF204B
MF204B
MF204B
MF204B
ACTIV
E
Green (RoHS
& no Sb/Br)
CU
NIPDAU
Level-1-260C-
UNLIM
SN65MLVD204BR
SN65MLVD204BRUM
D
8
2500
250
PREVI
EW
Green (RoHS
& no Sb/Br)
CU
NIPDAU
Level-1-260C-
UNLIM
WQFN
WQFN
RUM
RUM
16
16
SN65MLVD204BRUM PREVI
EW
Green (RoHS
& no Sb/Br)
CU
NIPDAU
Level-1-260C-
UNLIM
3000
R
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using
this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please
check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS
requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where
designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the
die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free
(RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb)
based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
space
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will
appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device
Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI
bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and
accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers
consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to
Customer on an annual basis.
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13.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
SN65MLVD204BDR
SOIC
D
8
2500
3000
330.0
330.0
12.4
12.4
6.4
5.2
2.1
8.0
8.0
12.0
12.0
Q1
Q2
SN65MLVD204BRUMR
WQFN
RUM
16
4.25
4.25
1.15
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
SOIC
Package Drawing Pins
SPQ
2500
3000
Length (mm) Width (mm)
Height (mm)
20.6
SN65MLVD204BDR
SN65MLVD204BRUMR
D
8
340.5
367.0
338.1
367.0
WQFN
RUM
16
35.0
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PSN65MLVD204BRUMR
SN65MLVD204BD
ACTIVE
ACTIVE
WQFN
SOIC
RUM
D
16
8
3000
75
TBD
Call TI
Call TI
-40 to 125
-40 to 85
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
Level-1-260C-UNLIM
MF204B
MF204B
SN65MLVD204BDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 85
SN65MLVD204BRUMR
SN65MLVD204BRUMT
PREVIEW
PREVIEW
WQFN
WQFN
RUM
RUM
16
16
3000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65MLVD204BDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
533.4 186.0 36.0
SN65MLVD204BDR
D
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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