SN74AVC16244_15 [TI]
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS;
| 型号： | SN74AVC16244_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 驱动 输出元件 |
| 文件： | 总11页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢔ ꢌꢍ ꢕ ꢖ ꢊꢀꢍꢄꢍ ꢐ ꢗ ꢎꢍ ꢘꢎ ꢍꢀ
SCES141N − JULY 1998 − REVISED JULY 2004
D
D
Member of the Texas Instruments
Widebus Family
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
I
Supports Partial-Power-Down Mode
off
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
D
Less Than 2-ns Maximum Propagation
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Delay at 2.5-V and 3.3-V V
CC
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I and I of
OH
OL
24 mA at 2.5-V V
CC
description/ordering information
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V vs I and V
vs I
curves to illustrate the output impedance and drive capability of the
OL
OL
OH
OH
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC)
Circuitry Technology and Applications, literature number SCEA009.
3.2
T
= 25°C
T
= 25°C
A
A
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
= 3.3 V
CC
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
= 2.5 V
CC
V
= 1.8 V
CC
V
= 3.3 V
V
= 2.5 V
CC
CC
V
= 1.8 V
CC
−160 −144 −128 −112 −96 −80 −64 −48 −32 −16
− Output Current − mA
0
17
34
51
68
85 102 119 136 153 170
0
I
− Output Current − mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
†
T
PACKAGE
A
MARKING
AVC16244
CVA244
TSSOP − DGG
Tape and reel SN74AVC16244DGGR
Tape and reel SN74AVC16244DGVR
TVSOP − DGV
−40°C to 85°C
VFBGA − GQL
SN74AVC16244GQLR
Tape and reel
CVA244
VFBGA − ZQL (Pb-free)
SN74AVC16244ZQLR
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC and Widebus are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
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ꢔꢌ ꢍ ꢕ ꢖ ꢊꢀꢍꢄꢍ ꢐ ꢗꢎꢍ ꢘ ꢎꢍꢀ
SCES141N − JULY 1998 − REVISED JULY 2004
description/ordering information (continued)
This 16-bit buffer/driver is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V to 3.6-V V
CC
operation.
CC
The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1A1
1A2
GND
1A3
1A4
2
3
4
5
6
7
V
V
CC
CC
8
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
V
CC
CC
4Y1
4Y2
GND
4Y3
4Y4
4A1
4A2
GND
4A3
4A4
3OE
4OE
2
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SCES141N − JULY 1998 − REVISED JULY 2004
GQL OR ZQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Y2
1Y4
2Y2
2Y4
3Y1
3Y3
4Y1
4Y3
4OE
NC
NC
NC
NC
2OE
1A2
1A4
2A2
2A4
3A1
3A3
4A1
4A3
3OE
A
B
C
D
1Y1
1Y3
2Y1
2Y3
3Y2
3Y4
4Y2
4Y4
NC
GND
GND
1A1
1A3
2A1
2A3
3A2
3A4
4A2
4A4
NC
V
CC
V
CC
GND
GND
E
F
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC − No internal connection
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
L
A
L
L
H
Z
L
H
X
H
3
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SCES141N − JULY 1998 − REVISED JULY 2004
logic diagram (positive logic)
1
25
36
1OE
3OE
3A1
47
2
3
5
6
13
14
16
17
1A1
1Y1
1Y2
1Y3
1Y4
3Y1
3Y2
3Y3
3Y4
46
35
33
32
1A2
3A2
3A3
3A4
44
1A3
43
1A4
48
24
30
2OE
4OE
4A1
41
8
9
19
20
22
23
2A1
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
40
29
27
26
2A2
4A2
4A3
4A4
38
11
12
2A3
37
2A4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
Output clamp current, I
OK
O
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
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SCES141N − JULY 1998 − REVISED JULY 2004
recommended operating conditions (see Note 4)
MIN
1.4
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
1.2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2 V
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 1.2 V
0.65 × V
CC
0.65 × V
V
High-level input voltage
V
V
CC
1.7
2
GND
0.35 × V
0.35 × V
0.7
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
CC
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
3.6
V
V
I
Active state
3-state
V
CC
3.6
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
−2
−4
−8
†
I
Static high-level output current
mA
mA
OHS
OLS
−12
2
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
4
†
I
Static low-level output current
8
12
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 1.4 V to 3.6 V
ns/V
T
−40
85
°C
A
†
Dynamic drive capability is equivalent to standard outputs with I
OH
and I
OL
of 24 mA at 2.5-V V . See Figure 1 for V
CC OL
vs I
OL
and V vs I
OH OH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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SCES141N − JULY 1998 − REVISED JULY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
= −100 µA
MIN TYP
V − 0.2
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
1.4 V to 3.6 V
1.4 V
OHS
OHS
OHS
OHS
OHS
OLS
OLS
OLS
OLS
OLS
CC
1.05
= −2 mA,
= −4 mA,
= −8 mA,
= −12 mA,
= 100 µA
= 2 mA,
V
V
V
V
= 0.91 V
= 1.07 V
= 1.7 V
= 2 V
IH
IH
IH
IH
1.65 V
2.3 V
1.2
1.75
2.3
V
V
OH
OL
3 V
1.4 V to 3.6 V
1.4 V
0.2
0.4
0.45
0.55
0.7
2.5
10
V
IL
V
IL
V
IL
V
IL
= 0.49 V
= 0.57 V
= 0.7 V
= 0.8 V
= 4 mA,
1.65 V
2.3 V
V
V
= 8 mA,
= 12 mA,
3 V
I
I
I
I
V = V
CC
or GND
3.6 V
µA
µA
µA
µA
I
I
V or V = 3.6 V
0
off
I
O
V
= V
CC
or GND
3.6 V
10
OZ
CC
O
V = V
or GND,
I = 0
O
3.6 V
40
I
CC
2.5 V
3.5
3.5
6
Control inputs
Data inputs
Outputs
V = V
I
or GND
CC
3.3 V
C
C
pF
pF
i
2.5 V
V = V
or GND
I
CC
3.3 V
6
2.5 V
6.5
6.5
V
O
= V or GND
CC
o
3.3 V
†
Typical values are measured at T = 25°C.
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
0.1 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
V
CC
= 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
A
Y
Y
Y
3.1
7.6
7.2
0.6
1.4
1.7
3.3
0.7
1.3
1.6
2.9
0.6
0.9
1
1.9
0.5
0.7
1
1.7
ns
ns
ns
pd
en
dis
8
6.8
6.2
4
3.5
3.5
OE
OE
7.3
4.3
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
CC
= 2.5 V
V = 3.3 V
CC
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
23
27
33
Power dissipation
capacitance
C
C
= 0,
L
f = 10 MHz
pF
pd
0.1
0.1
0.1
6
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SCES141N − JULY 1998 − REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
Open
R
L
t
t
/t
Open
From Output
Under Test
PLH PHL
GND
t
/t
2 × V
CC
GND
PLZ PZL
/t
PHZ PZH
C
L
R
L
(see Note A)
V
∆
C
L
R
V
CC
L
1.2 V
2 kΩ
2 kΩ
1 kΩ
500 Ω
500 Ω
0.1 V
0.1 V
15 pF
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
15 pF
30 pF
30 pF
30 pF
LOAD CIRCUIT
0.15 V
0.15 V
0.3 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
V
OH
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
S1 at 2 × V
(see Note B)
V
V
CC
OL
∆
V
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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