SN74AXC1T45DBVR [TI]
单位双电源总线收发器 | DBV | 6 | -40 to 125;型号: | SN74AXC1T45DBVR |
厂家: | TEXAS INSTRUMENTS |
描述: | 单位双电源总线收发器 | DBV | 6 | -40 to 125 总线收发器 |
文件: | 总45页 (文件大小:2102K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74AXC1T45
ZHCSHK6D –DECEMBER 2017 –REVISED OCTOBER 2021
具有可配置电压转换的SN74AXC1T45 单比特位双电源总线收发器
1 特性
3 说明
• 在0.65V 至3.6V 范围内进行上行和下行电平转换
SN74AXC1T45 是一款采用两个独立可配置电源轨的
单比特位同相总线收发器。VCCA 和 VCCB 电源电压低
至 0.65V 时,该器件可正常工作。A 端口用于跟踪
VCCA,该端口可支持 0.65V 至 3.6V 范围内的任何电
源电压。B 端口用于跟踪 VCCB,该端口也可支持
0.65V 至3.6V 范围内的任何电源电压。
• 工作温度:–40°C 至+125°C
• 设计采用毛刺信号抑制电路以提高电源定序性能
• 最大静态电流(ICCA + ICCB) 为10µA(最高85°C)
和16µA(最高125°C)
• 从1.8V 转换到3.3V 时,支持高达500Mbps 的转
换速率
DIR 引脚决定信号传播的方向。DIR 引脚配置为高电平
时,信号转换由端口 A 流向端口 B。DIR 配置为低电
平时,则由端口B 流向端口A。DIR 引脚以VCCA 为基
准,这意味着它的逻辑高电平和逻辑低电平阈值跟踪
• VCC 隔离特性:
– 如果任何一个VCC 输入低于100mV,则所有
I/O 输出均禁用且处于高阻抗状态
• Ioff 支持局部断电模式运行
• 闩锁性能超过100mA,符合JESD 78 II 类规范
• ESD 保护性能超过JESD 22 规范要求
V
CCA 电压。
该器件完全符合使用 Ioff 电流的部分断电应用的规范要
求。当器件断电时,Ioff 保护电路可确保不从输入、输
出或偏置到特定电压的组合I/O 获取多余电流,也不向
其提供多余电流。
– 8000V 人体放电模型
– 1000V 充电器件模型
2 应用
VCC 隔离特性可确保当 VCCA 或 VCCB 低于 100mV
时,I/O 端口均禁用其输出并进入高阻态。
• 企业与通信
• 工业
• 个人电子产品
毛刺信号抑制电路使电源轨能以任何顺序打开或关断,
从而提供强大的电源定序性能。
器件信息
器件型号(1)
封装尺寸(标称值)
2.90mm × 1.60mm
2.00mm × 1.25mm
1.60mm × 1.20mm
1.00mm x 1.00mm
1.00mm × 0.80mm
封装
SN74AXC1T45DBV
SN74AXC1T45DCK
SN74AXC1T45DRL
SN74AXC1T45DEA
SN74AXC1T45DTQ
SOT-23 (6)
SC70 (6)
SOT-5X3 (6)
X2SON (6)
X2SON (6)
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
0.7 V
3.3 V
Processor
VCCA
DIR
VCCB
Power Management
Unit
A
B
Control Block
SN74AXC1T45
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SCES882
SN74AXC1T45
ZHCSHK6D –DECEMBER 2017 –REVISED OCTOBER 2021
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Applications.................................................. 21
10 Power Supply Recommendations..............................25
10.1 Power-Up Considerations.......................................25
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Documentation Support.......................................... 26
12.2 接收文档更新通知................................................... 26
12.3 支持资源..................................................................26
12.4 Trademarks.............................................................26
12.5 Electrostatic Discharge Caution..............................26
12.6 术语表..................................................................... 26
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics ...........................................7
6.7 Operating Characteristics: TA = 25°C....................... 14
6.8 Typical Characteristics..............................................15
7 Parameter Measurement Information..........................18
7.1 Load Circuit and Voltage Waveforms........................18
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................20
Information.................................................................... 26
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision C (September 2020) to Revision D (October 2021)
Page
• Updated the Pin Configuration and Functions section to include DRL and DEA packages............................... 3
Changes from Revision B (June 2018) to Revision C (September 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 将所有表更新为最新的3d 表格式.......................................................................................................................1
• Updated ICCA, ICCB, and ICCA + ICCB to reflect updated performance of device..................................................6
Changes from Revision A (April 2018) to Revision B (June 2018)
Page
• 添加了DEA 和DTQ 作为可用封装选项..............................................................................................................1
• 将产品状态从“量产混合”更改为“量产数据”................................................................................................ 1
Changes from Revision * (December 2017) to Revision A (April 2018)
Page
• Added pinout drawing for DEA package ............................................................................................................3
• Added pinout drawing for DTQ package ............................................................................................................3
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5 Pin Configuration and Functions
VCCA
GND
A
1
2
3
6
5
4
VCCB
DIR
B
VCCA
GND
A
1
2
3
6
5
4
VCCB
DIR
B
图5-2. DCK Package
6-Pin SC70
图5-1. DBV Package
6-Pin SOT-23
Top View
Top View
VCCA
GND
A
1
6
5
4
VCCB
DIR
B
1
2
3
6
5
4
VCCA
GND
A
VCCB
DIR
B
2
3
图5-4. DEA Package
6-Pin X2SON
Transparent Top View
图5-3. DRL Package
6-Pin SOT-5X3
Top View
1
6
VCCA
GND
VCCB
DIR
5
2
A
B
3
4
图5-5. DTQ Package
6-Pin X2SON
Transparent Top View
表5-1. Pin Functions
PIN
TYPE
NO.
DESCRIPTION
NAME
Input or output A. This pin is referenced to VCCA. When this pin is configured as an input, do
not leave it floating.
A
3
4
5
I/O
I/O
I
Input or output B. This pin is referenced to VCCB. When this pin is configured as an input, do
not leave it floating.
B
Direction control signal. Set to Logic High for A-to-B level translation. Set to Logic Low for B-
to-A level translation.
DIR
GND
VCCA
VCCB
2
1
6
Ground.
—
—
—
A-port supply voltage. 0.65 V ≤VCCA ≤3.6 V.
B-port supply voltage. 0.65 V ≤VCCB ≤3.6 V.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–50
MAX UNIT
VCCA Supply voltage A
VCCB Supply voltage B
4.2
4.2
V
V
I/O Ports (A Port)
I/O Ports (B Port)
Control Inputs
A Port
4.2
VI
Input Voltage(2)
4.2
V
4.2
4.2
VO
VO
Voltage applied to any output in the high-impedance or power-off state(2)
Voltage applied to any output in the high or low state(2) (3)
V
V
B Port
4.2
A Port
VCCA + 0.2
VCCB + 0.2
B Port
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
Junction Temperature
50 mA
100 mA
150 °C
150 °C
–50
–100
TJ
TSTG Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±8000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
0.65
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
3.6
3.6
V
V
0.65
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCI x 0.70
VCCI x 0.70
VCCI x 0.65
1.6
Data Inputs
2
VIH
High-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCA x 0.70
VCCA x 0.70
VCCA x 0.65
1.6
Control Input (DIR)
Referenced to VCCA
2
VCCI x 0.30
VCCI x 0.30
VCCI x 0.35
0.7
Data Inputs
0.8
VIL
Low-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCA x 0.30
VCCA x 0.30
VCCA x 0.35
0.7
Control Input (DIR)
Referenced to VCCA
0.8
VI
Input voltage (3)
Output voltage
0
0
0
3.6
V
V
Active State
Tri-State
VCCO
VO
3.6
Input transition rate
100 ns/V
125 °C
Δt/Δv
TA
Operating free-air temperature
–40
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74AXC1T45
DBV
(SOT-23)
DCK
(SC70)
DRL
(SOT-5X3)
DEA
(X2SON)
DTQ
(X2SON)
THERMAL METRIC(1)
UNIT
6 PINS
202.2
137.2
80.2
6 PINS
235.3
160.5
76.9
6 PINS
298.9
148.4
165.0
20.7
6 PINS
358.0
201.0
221.8
26.1
6 PINS
327.8
194.9
248.4
24.1
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
64.0
59.7
80.4
77.1
164.9
220.8
247.6
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
UNI
T
PARAMETER
TEST CONDITIONS
VCCA
VCCB
–40°C to 85°C
–40°C to 125°C
MIN TYP(3) MAX
MIN
TYP MAX
VCCO
–0.1
VCCO
–0.1
IOH = -100 µA
0.7 V - 3.6 V
0.7 V - 3.6 V
IOH = -50 µA
IOH = -200 µA
IOH = -500 µA
0.65 V
0.76 V
0.85 V
1.1 V
0.65 V
0.76 V
0.85 V
1.1 V
0.55
0.58
0.65
0.85
1.05
1.2
0.55
0.58
0.65
0.85
1.05
1.2
High-level
output voltage
VOH
VI = VIH
V
IOH = -3 mA
IOH = -6 mA
IOH = -8 mA
IOH = -9 mA
IOH = -12 mA
IOL = 100 µA
IOL = 50 µA
IOL = 200 µA
IOL = 500 µA
IOL = 3 mA
IOL = 6 mA
IOL = 8 mA
IOL = 9 mA
IOL = 12 mA
1.4 V
1.4 V
1.65 V
2.3 V
1.65 V
2.3 V
1.75
2.3
1.75
2.3
3 V
3 V
0.7 V - 3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
0.7 V - 3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
0.1
0.1
0.1
0.1
0.18
0.2
0.18
0.2
Low-level
output voltage
VOL
VI = VIL
0.25
0.35
0.45
0.55
0.7
0.25
0.35
0.45
0.55
0.7
V
1.4 V
1.4 V
1.65 V
2.3 V
1.65 V
2.3 V
3 V
3 V
Control input (DIR): VI =
VCCA or GND
0.65 V- 3.6 V 0.65 V- 3.6 V
0.65 V- 3.6 V 0.65 V- 3.6 V
1
4
1.5
8
–1
–4
–1.5
–8
Input leakage
current
II
µA
A or B Port: Vi = VCCI or
GND
0 V
0 V - 3.6 V
0 V
5
5
8
7.5
7.5
12
–5
–5
–7.5
–7.5
Partial power A or B Port: Vi or Vo = 0 V -
down current 3.6 V
Ioff
µA
µA
0 V - 3.6 V
0.65 V- 3.6 V 0.65 V- 3.6 V
VCCA supply
current
VI = VCCI
or GND
ICCA
IO = 0
0 V
3.6 V
0 V
–2
–8
3.6 V
2
8
2
8
12
8
0.65 V- 3.6 V 0.65 V- 3.6 V
VCCB supply
current
VI = VCCI
or GND
0 V
3.6 V
0 V
ICCB
IO = 0
IO = 0
µA
3.6 V
–2
–8
ICCA
ICCB
+
Combined
supply current or GND
VI = VCCI
0.65 V- 3.6 V 0.65 V- 3.6 V
10
16 µA
pF
Control input
capacitance
CI
VI = 3.3 V or GND
3.3 V
3.3 V
3.3 V
0 V
4.4
5
4.4
5
Data I/O
capacitance,
A Port
VO = 1.65V DC +1 MHz -16
dBm sine wave
CIO
pF
pF
Data I/O
capacitance,
B Port
VO = 1.65V DC +1 MHz -16
dBm sine wave
CIO
0 V
3.3 V
5
5
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All typical data is taken at 25°C.
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6.6 Switching Characteristics
表6-1. Switching Characteristics, VCCA = 0.7 V
B–PORT SUPPLY VOLTAGE (VCCB
1.2 ± 0.1 V 1.5 ± 0.1 V
MAX MAX
)
TEST
CONDITIONS
PARAMETER
FROM
TO
UNIT
0.7 ± 0.05 V
MIN MAX
0.8 ± 0.04 V
MAX
0.9 ± 0.045 V
MAX
1.8 ± 0.15 V
MAX
2.5 ± 0.2 V
MAX
3.3 ± 0.3 V
MAX
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
173
173
173
173
143
143
163
163
389
406
369
395
117
117
154
154
143
143
123
123
331
333
313
339
85
85
51
51
50
50
53
53
65
65
143
143
80
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
A
B
A
A
B
A
B
tpd
tdis
ten
Propagation delay
ns
127
127
143
143
100
100
287
287
281
307
88
83
82
80
B
88
83
82
80
80
143
143
50
143
143
45
143
143
49
143
143
61
143
143
109
109
200
200
339
365
DIR
DIR
DIR
DIR
Disable time
Enable time
ns
ns
50
45
49
61
143
143
247
273
134
134
246
272
137
137
249
275
147
147
261
287
表6-2. Switching Characteristics, VCCA = 0.8 V
B–PORT SUPPLY VOLTAGE (VCCB
1.2 ± 0.1 V 1.5 ± 0.1 V
MAX MAX
)
TEST
CONDITIONS
PARAMETER
FROM
TO
UNIT
0.7 ± 0.05 V
MIN MAX
0.8 ± 0.04 V
MAX
0.9 ± 0.045 V
MAX
1.8 ± 0.15 V
MAX
2.5 ± 0.2 V
MAX
3.3 ± 0.3 V
MAX
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
153
153
117
117
100
100
151
151
321
341
309
317
95
95
64
64
33
33
27
27
26
26
27
27
36
36
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
A
B
A
A
B
A
B
tpd
tdis
ten
Propagation delay
ns
96
78
52
42
41
40
39
B
96
78
52
42
41
40
39
100
100
111
111
261
266
251
259
100
100
88
100
100
38
100
100
32
100
100
30
100
100
30
100
100
38
DIR
DIR
DIR
DIR
Disable time
Enable time
ns
ns
88
38
32
30
30
38
226
229
220
228
96
80
78
76
87
97
80
78
76
87
189
197
183
191
182
190
183
191
192
200
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表6-3. Switching Characteristics, VCCA = 0.9 V
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
CONDITIONS
PARAMETER
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
126
126
85
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
78
78
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
52
52
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
23
23
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
18
18
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
16
16
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
15
15
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
18
18
–40°C to 85°C
A
B
A
A
B
A
B
–40°C to
125°C
Propagation
delay
tpd
ns
64
53
40
28
24
22
21
–40°C to 85°C
B
–40°C to
125°C
85
64
53
40
28
24
22
21
75
75
75
75
75
75
75
75
–40°C to 85°C
DIR
DIR
DIR
DIR
–40°C to
125°C
79
79
79
79
79
79
79
79
tdis Disable time
ns
ns
144
144
282
304
262
269
105
105
223
229
214
221
82
32
25
24
21
23
–40°C to 85°C
–40°C to
125°C
83
36
28
26
21
23
195
199
188
195
77
59
54
48
54
–40°C to 85°C
–40°C to
125°C
81
62
56
49
54
ten Enable time
159
166
154
161
152
159
151
158
154
161
–40°C to 85°C
–40°C to
125°C
表6-4. Switching Characteristics, VCCA = 1.2 V
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
CONDITIONS
PARAMETER
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
0.5
0.5
0.5
0.5
87
87
51
51
0.5
0.5
0.5
0.5
52
52
33
33
0.5
0.5
0.5
0.5
39
39
23
23
0.5
0.5
0.5
0.5
15
15
15
15
0.5
0.5
0.5
0.5
9
10
12
12
0.5
0.5
0.5
0.5
8
9
0.5
0.5
0.5
0.5
7
7
7
8
0.5
0.5
0.5
0.5
7
8
7
7
–40°C to 85°C
A
B
B
A
–40°C to
125°C
Propagation
delay
tpd
ns
10
10
–40°C to 85°C
–40°C to
125°C
Copyright © 2021 Texas Instruments Incorporated
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PARAMETER
表6-4. Switching Characteristics, VCCA = 1.2 V (continued)
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
CONDITIONS
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
29
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
29
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
29
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
29
24
30
45
51
43
49
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
29
18
23
36
41
37
44
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
29
16
21
33
37
36
43
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
29
13
17
26
30
35
41
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
29
13
16
29
32
35
42
–40°C to 85°C
DIR
DIR
DIR
DIR
A
B
A
B
–40°C to
125°C
tdis Disable time
ns
137
137
240
265
115
121
98
74
–40°C to 85°C
–40°C to
125°C
98
78
185
193
80
157
164
67
–40°C to 85°C
–40°C to
125°C
ten Enable time
ns
–40°C to 85°C
–40°C to
125°C
86
73
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表6-5. Switching Characteristics, VCCA = 1.5 V
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
CONDITIONS
PARAMETER
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
83
83
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
42
42
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
28
28
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
12
12
10
10
15
20
22
29
38
44
33
38
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
6
–40°C to 85°C
A
B
A
A
B
A
B
–40°C to
125°C
Propagation
delay
tpd
ns
50
28
18
8
7
5
4
–40°C to 85°C
B
–40°C to
125°C
50
28
18
9
8
6
5
15
15
15
15
20
16
21
30
36
29
35
15
20
14
19
28
33
28
34
15
20
11
15
22
26
26
32
15
20
11
14
24
27
26
32
–40°C to 85°C
DIR
DIR
DIR
DIR
–40°C to
125°C
20
20
20
tdis Disable time
ns
ns
136
136
238
263
104
109
96
72
–40°C to 85°C
–40°C to
125°C
96
76
178
186
63
151
157
49
–40°C to 85°C
–40°C to
125°C
ten Enable time
–40°C to 85°C
–40°C to
125°C
68
54
表6-6. Switching Characteristics, VCCA = 1.8 V
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
CONDITIONS
PARAMETER
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
0.5
0.5
0.5
0.5
81
81
53
53
0.5
0.5
0.5
0.5
41
41
26
26
0.5
0.5
0.5
0.5
24
24
16
16
0.5
0.5
0.5
0.5
10
10
8
0.5
0.5
0.5
0.5
7
8
7
7
0.5
0.5
0.5
0.5
6
7
6
7
0.5
0.5
0.5
0.5
5
5
5
5
0.5
0.5
0.5
0.5
4
5
4
4
–40°C to 85°C
A
B
B
A
–40°C to
125°C
Propagation
delay
tpd
ns
–40°C to 85°C
–40°C to
125°C
9
Copyright © 2021 Texas Instruments Incorporated
10
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SN74AXC1T45
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PARAMETER
表6-6. Switching Characteristics, VCCA = 1.8 V (continued)
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
CONDITIONS
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
18
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
18
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
18
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
18
22
28
35
42
30
34
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
18
15
20
28
33
27
32
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
18
14
18
26
32
26
31
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
18
11
14
21
24
25
29
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
18
11
13
24
26
24
29
–40°C to 85°C
DIR
DIR
DIR
DIR
A
B
A
B
–40°C to
125°C
tdis Disable time
ns
136
136
241
266
101
105
96
72
–40°C to 85°C
–40°C to
125°C
96
75
176
184
61
148
155
44
–40°C to 85°C
–40°C to
125°C
ten Enable time
ns
–40°C to 85°C
–40°C to
125°C
65
48
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表6-7. Switching Characteristics, VCCA = 2.5 V
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
CONDITIONS
PARAMETER
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
80
80
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
40
40
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
22
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
4
–40°C to 85°C
A
B
A
A
B
A
B
–40°C to
125°C
Propagation
delay
tpd
ns
66
27
15
7
5
5
4
3
–40°C to 85°C
B
–40°C to
125°C
66
27
15
7
6
5
5
4
10
10
10
10
13
21
27
33
39
22
26
10
13
14
20
25
31
24
24
10
13
13
17
24
29
20
23
10
13
10
13
19
23
23
23
10
13
10
12
22
25
19
22
–40°C to 85°C
DIR
DIR
DIR
DIR
–40°C to
125°C
13
13
13
tdis Disable time
ns
ns
136
136
254
278
99
95
71
–40°C to 85°C
–40°C to
125°C
95
75
176
185
55
147
153
41
–40°C to 85°C
–40°C to
125°C
ten Enable time
–40°C to 85°C
–40°C to
125°C
98
58
40
表6-8. Switching Characteristics, VCCA = 3.3 V
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
CONDITIONS
PARAMETER
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
0.5
0.5
0.5
0.5
79
79
0.5
0.5
0.5
0.5
39
39
36
36
0.5
0.5
0.5
0.5
22
22
18
18
0.5
0.5
0.5
0.5
7
7
7
8
0.5
0.5
0.5
0.5
4
5
5
6
0.5
0.5
0.5
0.5
4
4
4
5
0.5
0.5
0.5
0.5
3
4
4
4
0.5
0.5
0.5
0.5
3
4
3
4
–40°C to 85°C
A
B
B
A
–40°C to
125°C
Propagation
delay
tpd
ns
144
144
–40°C to 85°C
–40°C to
125°C
Copyright © 2021 Texas Instruments Incorporated
12
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PARAMETER
表6-8. Switching Characteristics, VCCA = 3.3 V (continued)
B–PORT SUPPLY VOLTAGE (VCCB
)
TEST
FROM
TO
UNIT
0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
CONDITIONS
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
12
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
12
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
12
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
12
21
27
33
40
26
27
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
12
14
19
25
31
23
25
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
12
12
17
23
29
23
24
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
12
10
13
19
22
22
24
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
12
10
12
22
24
22
24
–40°C to 85°C
DIR
DIR
DIR
DIR
A
B
A
B
–40°C to
125°C
tdis Disable time
ns
136
136
331
356
98
95
71
–40°C to 85°C
–40°C to
125°C
95
75
185
93
149
156
41
–40°C to 85°C
–40°C to
125°C
ten Enable time
ns
58
–40°C to 85°C
–40°C to
125°C
99
59
42
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MAX UNIT
6.7 Operating Characteristics: TA = 25°C
PARAMETER
TEST CONDITIONS
VCCA
0.7 V
VCCB
0.7 V
MIN
TYP
1.3
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
1.3
1.3
1.3
Power Dissipation Capacitance CL = 0, RL = Open f = 1
pF
pF
pF
pF
per transceiver (A to B)
MHz, tr = tf = 1 ns
1.3
1.4
1.7
2.1
CpdA
9.2
9.4
9.4
9.8
Power Dissipation Capacitance CL = 0, RL = Open f = 1
per transceiver (B to A) MHz, tr = tf = 1 ns
10.1
11.0
14.4
18.6
9.2
9.3
9.4
9.7
Power Dissipation Capacitance CL = 0, RL = Open f = 1
per transceiver (A to B) MHz, tr = tf = 1 ns
10.1
11.0
14.4
18.3
1.3
CpdB
1.3
1.3
1.3
Power Dissipation Capacitance CL = 0, RL = Open f = 1
per transceiver (B to A)
MHz, tr = tf = 1 ns
1.3
1.4
1.7
2.1
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6.8 Typical Characteristics
50
45
40
35
30
25
20
15
45
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
40
35
30
25
20
15
10
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
D016
D001
TA = 25°C VCCA = 0.7 V
TA = 25°C VCCA = 0.8 V
图6-1. Typical Propagation Delay of Low-to-High
图6-2. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
(A to B) vs Load Capacitance
40
30
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
27
24
21
18
15
12
9
35
30
25
20
15
10
5
6
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
D002
D003
TA = 25°C VCCA = 0.9 V
TA = 25°C VCCA = 1.2 V
图6-3. Typical Propagation Delay of Low-to-High
图6-4. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
(A to B) vs Load Capacitance
30
27
CL = 45 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
27
24
21
18
15
12
9
24
21
18
15
12
9
6
6
3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
D004
D005
TA = 25°C VCCA = 1.5 V
TA = 25°C VCCA = 1.8 V
图6-5. Typical Propagation Delay of Low-to-High
图6-6. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
(A to B) vs Load Capacitance
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6.8 Typical Characteristics (continued)
27
27
24
21
18
15
12
9
CL = 45 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
24
21
18
15
12
9
6
6
3
3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
D007
D006
TA = 25°C VCCA = 3.3 V
TA = 25°C VCCA = 2.5 V
图6-7. Typical Propagation Delay of Low-to-High
图6-8. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
(A to B) vs Load Capacitance
50
40
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
45
35
40
35
30
25
20
15
30
25
20
15
10
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
D008
D009
TA = 25°C VCCA = 0.7 V
TA = 25°C VCCA = 0.8 V
图6-9. Typical Propagation Delay of Low-to-High
图6-10. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
(B to A) vs Load Capacitance
36
27.5
CL = 45 pF
CL = 45 pF
33
30
27
24
21
18
15
12
9
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
25
22.5
20
17.5
15
12.5
10
7.5
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
D010
D011
TA = 25°C VCCA = 0.9 V
TA = 25°C VCCA = 1.2 V
图6-11. Typical Propagation Delay of Low-to-High
图6-12. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
(B to A) vs Load Capacitance
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6.8 Typical Characteristics (continued)
30
25
CL = 45 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
27
24
21
18
15
12
9
22.5
20
17.5
15
12.5
10
7.5
5
6
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
D012
D013
TA = 25°C VCCA = 1.5 V
TA = 25°C
VCCA = 1.8 V
图6-13. Typical Propagation Delay of Low-to-High
图6-14. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
(B to A) vs Load Capacitance
30
30
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
27
24
21
18
15
12
9
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
25
20
15
10
5
6
3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
D014
D015
TA = 25°C VCCA = 2.5 V
TA = 25°C VCCA = 3.3 V
图6-15. Typical Propagation Delay of Low-to-High
图6-16. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
(B to A) vs Load Capacitance
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• dv/dt ≤1 ns/V
Measurement Point
2 x VCCO
Open
GND
S1
RL
Output Pin
Under Test
(1)
CL
RL
A. CL includes probe and jig capacitance.
图7-1. Load Circuit
表7-1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
N/A
N/A
N/A
Δt/
Δv
Input transition rise or fall rate
15 pF
15 pF
15 pF
Open
Open
Open
0.65 V –3.6 V
1.1 V –3.6 V
1 MΩ
2 kΩ
20 kΩ
tpd
Propagation (delay) time
0.65 V –0.95
V
15 pF
15 pF
15 pF
2 × VCCO
2 × VCCO
2 × VCCO
0.3 V
0.15 V
0.1 V
3 V –3.6 V
1.65 V –2.7 V
1.1 V –1.6 V
2 kΩ
2 kΩ
2 kΩ
ten, tdis Enable time, disable time
0.65 V –0.95
15 pF
2 × VCCO
0.1 V
20 kΩ
V
15 pF
15 pF
15 pF
GND
GND
GND
0.3 V
0.15 V
0.1 V
3 V –3.6 V
1.65 V –2.7 V
1.1 V –1.6 V
2 kΩ
2 kΩ
2 kΩ
ten, tdis Enable time, disable time
0.65 V –0.95
15 pF
GND
0.1 V
20 kΩ
V
(1)
VCCI
(1)
VCCI
Input A, B
100 kHz
VCCI / 2
VCCI / 2
Input A, B
500 ps/V œ 100 ns/V
0 V
VOH
0 V
VOH
(2)
tpd
tpd
(2)
Output B, A
Ensure Monotonic
Rising and Falling Edge
(2)
VOL
Output B, A
VCCI / 2
VCCI / 2
(2)
VOL
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
图7-3. Input Transition Rise or Fall Rate
图7-2. Propagation Delay
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VCCA
VCCA / 2
DIR
VCCA / 2
GND
(1)
ten
(5)
VCCO
Output A(2)
Output A(3)
VCCO / 2
VOL + VTP
(6)
VOL
tdis
(6)
VOH
VOH - VTP
VCCO / 2
GND
(1)
ten
(5)
VCCO
Output B(2)
Output B(3)
VCCO / 2
VOL + VTP
(6)
VOL
tdis
(6)
VOH
VOH - VTP
VCCO / 2
GND
1. Illustrative purposes only. Enable Time is a calculation as described in the data sheet.
2. Output waveform on the condition that input is driven to a valid Logic Low.
3. Output waveform on the condition that input is driven to a valid Logic High.
4. VCCI is the supply pin associated with the input port
5. VCCO is the supply pin associated with the output port.
6. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
图7-4. Disable and Enable Time
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8 Detailed Description
8.1 Overview
The SN74AXC1T45 is single-bit, dual-supply, noninverting voltage level translation. Pin A and the direction
control pin are support by VCCA and pin B is support by VCCB. The A port can accept I/O voltages ranging from
0.65 V to 3.6 V, and the B port can accept I/O voltages from 0.65 V to 3.6 V. A high logic on the DIR pin allows
data transmission from A to B and a logic low on the DIR pin allows data transmission from B to A.
8.2 Functional Block Diagram
5
DIR
3
A
4
B
V
V
CCB
CCA
8.3 Feature Description
8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 0.65-V to 3.6-V
Power-Supply Range
Both the VCCA and VCCB pins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for
translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).
8.3.2 Support High-Speed Translation
The SN74AXC1T45 device can support high data-rate applications. The translated signal data rate can be up to
500 Mbps when signal is translated from 1.8 V to 3.3 V.
8.3.3 Ioff Supports Partial-Power-Down Mode Operation
The Ioff circuit prevents backflow current by disabling the I/O output circuits when the device is in partial-power-
down mode.
8.4 Device Functional Modes
表8-1 lists the device functions for the DIR input.
表8-1. Function Table
INPUT(1)
OPERATION
DIR
L
B data to A bus
A data to B bus
H
(1) Input circuits of the data I/Os
always are active.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN74AXC1T45 device can be used in level-translation applications for interfacing devices or systems with
one another when they are operating at different interface voltages. The maximum data rate can be up to 500
Mbps when the device translate signal is from 1.8 V to 3.3 V.
9.1.1 Enable Times
Calculate the enable times for the SN74AXC1T45 using the following formulas:
tA_en (DIR to A) = tdis (DIR to B) + tpd (B to A)
tB_en (DIR to B) = tdis (DIR to A) + tpd (A to B)
(1)
(2)
In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is
switched until an output is expected. For example, if the SN74AXC1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled (tdis) before presenting it with an input. After the
B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay (tpd). To avoid bus contention care should be taken to not apply an input signal prior to the
output port being disabled (tdis max).
9.2 Typical Applications
9.2.1 Unidirectional Logic Level-Shifting Application
图9-1 shows an example of the SN74AXC1T45 being used in a unidirectional logic level-shifting application.
V
CC1
V
CC1
V
CC2
V
CC2
1
2
3
6
5
4
SYSTEM-1
SYSTEM-2
图9-1. Unidirectional Logic Level-Shifting Application
表9-1. Unidirectional Level Shifting Function
PIN
1
NAME
VCCA
GND
A
FUNCTION
VCC1
GND
OUT
DESCRIPTION
SYSTEM-1 supply voltage (0.65 V to 3.6 V)
Device GND
2
3
Output level depends on VCC1 voltage.
Input threshold value depends on VCC2 voltage.
GND (low level) determines B-port to A-port direction.
SYSTEM-2 supply voltage (0.65 V to 3.6 V)
4
B
IN
5
DIR
VCCB
DIR
6
VCC2
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9.2.1.1 Design Requirements
For this design example, use the parameters listed in 表9-2.
表9-2. Design Parameters
DESIGN PARAMETERS
Input voltage range
EXAMPLE VALUES
0.65 V to 3.6 V
Output voltage range
0.65 V to 3.6 V
9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AXC1T45 device to determine the input
voltage range. For a valid logic-high, the value must exceed the high-level input voltage (VIH) of the input
port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AXC1T45 device is driving to determine the output
voltage range.
9.2.1.3 Application Curve
图9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V)
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9.2.2 Bidirectional Logic Level-Shifting Application
图 9-3 shows the SN74AXC1T45 being used in a bidirectional logic level-shifting application. Because the
SN74AXC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
V
CC1
V
CC1
V
CC2
V
CC2
Pullup/Pulldown
†
Pullup/Pulldown
†
I/O-1
I/O-2
or Bus Hold
or Bus Hold
1
2
3
6
5
4
DIR CTRL
SYSTEM-1
SYSTEM-2
图9-3. Bidirectional Logic Level-Shifting Application
表9-3 lists the data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.
表9-3. Data Transmission: SYSTEM-1 and SYSTEM-2
STATE DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
2
H
H
Out
In
SYSTEM-1 data to SYSTEM-2.
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-
line state depends on pullup or pulldown resistors.(1)
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
pulldown resistors.(1)
3
4
L
L
Hi-Z
In
Hi-Z
Out
SYSTEM-2 data to SYSTEM-1.
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, essentially, both pullup or both pulldown.
9.2.2.1 Design Requirements
Refer to Design Requirements.
9.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
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9.2.2.3 Application Curve
图9-4. Up Translation at 2.5 MHz (0.7 V to 3.3 V)
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10 Power Supply Recommendations
The SN74AXC1T45 device uses two separate configurable power-supply rails, VCCA and VCCB. The VCCA
power-supply rail accepts any supply voltage from 0.65 V to 3.6 V and the VCCB power-supply rail accepts any
supply voltage from 0.65 V to 3.6 V. The A port and B port are designed to track the VCCA and VCCB supplies
respectively allowing for low-voltage, bidirectional translation between any of the 0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.5 V,
1.8 V, 2.5 V, and 3.3 V voltage nodes.
10.1 Power-Up Considerations
A proper power-up sequence must be followed to avoid excessive supply current, bus contention, oscillations, or
other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect the ground before any supply voltage is applied.
2. Power up the VCCA and VCCB supplies. The VCCA and VCCB supplies can be ramped in any order.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended:
• Bypass capacitors should be used on power supplies.
• Short trace lengths should be used to avoid excessive loading.
• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane
VIA to GND Plane (Inner Layer)
VCCB
VCCA
6
5
4
1
2
3
VCCA
GND
A
VCCB
DIR
B
VCCA
From Controller
To System
图11-1. PCB Layout Example
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ZHCSHK6D –DECEMBER 2017 –REVISED OCTOBER 2021
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Evaluate SN74AXC1T45DRL Using a Generic EVM application report
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
• Texas Instruments, Power Sequencing for the AXC Family of Devices application report
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
26
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Product Folder Links: SN74AXC1T45
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74AXC1T45DBVR
SN74AXC1T45DCKR
SN74AXC1T45DEAR
SN74AXC1T45DRLR
SN74AXC1T45DTQR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DEA
DRL
DTQ
6
6
6
6
6
3000 RoHS & Green
3000 RoHS & Green
5000 RoHS & Green
4000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1GRL
1A3
CR
SN
X2SON
SOT-5X3
X2SON
NIPDAU
NIPDAUAG
NIPDAU
1A1
CW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AXC1T45 :
Automotive : SN74AXC1T45-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AXC1T45DBVR
SN74AXC1T45DCKR
SN74AXC1T45DEAR
SOT-23
SC70
DBV
DCK
DEA
DRL
DTQ
6
6
6
6
6
3000
3000
5000
4000
3000
180.0
178.0
180.0
180.0
180.0
8.4
9.0
9.5
8.4
9.5
3.2
2.4
3.2
2.5
1.4
1.2
4.0
4.0
4.0
4.0
2.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q2
X2SON
1.13
1.98
0.94
1.13
1.78
1.13
0.5
SN74AXC1T45DRLR SOT-5X3
SN74AXC1T45DTQR X2SON
0.69
0.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AXC1T45DBVR
SN74AXC1T45DCKR
SN74AXC1T45DEAR
SN74AXC1T45DRLR
SN74AXC1T45DTQR
SOT-23
SC70
DBV
DCK
DEA
DRL
DTQ
6
6
6
6
6
3000
3000
5000
4000
3000
210.0
180.0
189.0
183.0
189.0
185.0
180.0
185.0
183.0
185.0
35.0
18.0
36.0
20.0
36.0
X2SON
SOT-5X3
X2SON
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DEA0006A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
C
0.4 MAX
SEATING PLANE
0.08 C
0.04
0.00
(0.102) TYP
0.55
SYMM
0.35
0.27
6X
3
4
SYMM
2X
0.7
4X
0.35
6
1
0.20
0.12
6X
PIN 1 ID
45 X 0.075
0.40
0.32
0.1
C B A
C
0.05
4223910/C 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DEA0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
5X (0.31)
(0.36)
1
6X (0.16)
4X (0.35)
6
(R0.05) TYP
SYMM
4
3
SYMM
(0.55)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223910/C 12/2017
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DEA0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
5X (0.31)
(0.36)
1
6X (0.16)
4X (0.35)
6
(R0.05) TYP
SYMM
4
3
SYMM
(0.55)
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE:40X
4223910/C 12/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DTQ0006A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
0.85
0.75
0.40 MAX
(0.1) TYP
C
SEATING PLANE
0.05 C
(0.1)
2X 0.6
0.4
0.05
0.00
(0.027) TYP
3
4
PKG
+0.05
-0.03
0.25
TYP
2
5
(0.08)
0.25
4X
0.17
1
6
PIN 1 ID
(OPTIONAL)
NOTE 5
PKG
0.30
4X
0.22
0.1
0.05
C A B
C
4224056/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
www.ti.com
EXAMPLE BOARD LAYOUT
DTQ0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
0.05 MIN
ALL AROUND
TYP
SOLDER MASK OPEING
TYP
SYMM
4X (0.25)
6
(0.25)
TYP
1
4X (0.4)
SYMM
(0.8)
2
5
(0.2) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
3
4
(0.2)
TYP
(0.027) TYP
(R0.05) TYP
(0.4)
(0.6)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:50X
4224056/A 11/2017
NOTES: (continued)
6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DTQ0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.25)
SYMM
(0.027) TYP
(0.279)
TYP
6
1
4X (0.4)
SYMM
(0.8)
5
2
(0.2) TYP
SOLDER MASK
EDGE, 2X
3
METAL UNDER
SOLDER MASK
TYP
4
(0.2)
TYP
(R0.05) TYP
(0.21)
(0.367)
4X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.07 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:50X
4224056/A 11/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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