SN74AXC2T45 [TI]

具有可配置电压转换的双位双电源总线收发器;


型号：	SN74AXC2T45
厂家：	TEXAS INSTRUMENTS
描述：	具有可配置电压转换的双位双电源总线收发器总线收发器
文件：	总41页 (文件大小：1739K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74AXC2T45

ZHCSKQ4C –AUGUST 2019 –REVISED JUNE 2021

SN74AXC2T45 具有可配置电平转换的2 位转换收发器

SN74AXC2T45 器件旨在实现数据总线间的异步通

信。根据方向控制输入 (DIR) 上的逻辑电平，该器件将

数据从 A 总线传输至 B 总线，或者将数据从 B 总线传

输至 A 总线。SN74AXC2T45 器件旨在使控制引脚

(DIR) 以V_CCA为基准。

1 特性

• 完全可配置的双轨设计可允许各个端口在0.65V 至

3.6V 的电源电压范围内运行

• 工作温度范围为–40°C 至+125°C

• 无干扰电源时序

• 从1.8V 转换到3.3V 时，支持高达380Mbps 的转

换速率

该器件完全符合使用 I_off电流的部分断电应用的规范要

求。当器件断电时，I_off保护电路可确保不从输入、输

出或偏置到特定电压的组合I/O 获取多余电流，也不向

其提供多余电流。

• V_CC隔离特性

– 如果任何一个V_CC输入低于100mV，则所有

I/O 输出均禁用且处于高阻抗状态

• I_off支持局部断电模式运行

V_CC隔离特性可确保当 V_CCA或 V_CCB低于 100mV

时，I/O 端口均禁用其输出并进入高阻抗状态。

• 兼容AVC 系列电平转换器

• 闩锁性能超过100mA，符合JESD 78 II 类规范

• ESD 保护性能超过JESD 22 规范要求

无干扰电源时序使电源轨能以任何顺序打开或关断，从

而提供强大的电源时序性能。

器件信息⁽¹⁾

– 8000V 人体放电模型

– 1000V 充电器件模型

封装尺寸（标称值）

器件型号

封装

SM8 (8)

SN74AXC2T45DCT

2.95mm × 2.80mm

2.30mm x 2.00mm

1.35mm × 0.80mm

2 应用

超薄小外形尺寸

封装(VSSOP)

(8)

SN74AXC2T45DCU

SN74AXC2T45DTM

• 企业与通信

• 工业

• 个人电子产品

• 无线基础设施

• 楼宇自动化

• 销售终端

X2SON (8)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

V_CCA

V_CCB

3 描述

DIR

SN74AXC2T45 是一款使用两个独立可配置电源轨的2

位同相总线收发器。V_CCA和 V_CCB电源电压低至

0.65V 时，该器件可正常工作。A 端口用于跟踪

V_CCA，该端口可支持 0.65V 至 3.6V 范围内的任何电

源电压。B 端口用于跟踪 V_CCB，该端口也可支持

0.65V 至 3.6V 范围内的任何电源电压。此外，

SN74AXC2T45 还与单电源系统兼容。

功能方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCES880

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Table of Contents

7.1 Load Circuit and Voltage Waveforms........................19

8 Detailed Description......................................................21

8.1 Overview...................................................................21

8.2 Functional Block Diagram.........................................21

8.3 Feature Description...................................................21

8.4 Device Functional Modes..........................................22

9 Application and Implementation..................................23

9.1 Application Information............................................. 23

9.2 Typical Application.................................................... 23

10 Power Supply Recommendations..............................25

11 Layout...........................................................................25

11.1 Layout Guidelines................................................... 25

11.2 Layout Example...................................................... 25

12 Device and Documentation Support..........................26

12.1 Documentation Support.......................................... 26

12.2 接收文档更新通知................................................... 26

12.3 支持资源..................................................................26

12.4 Trademarks.............................................................26

12.5 Electrostatic Discharge Caution..............................26

12.6 Glossary..................................................................26

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 描述................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................7

6.6 Switching Characteristics, V_CCA= 0.7 ± 0.05 V.......... 9

6.7 Switching Characteristics, V_CCA= 0.8 ± 0.04 V........ 10

6.8 Switching Characteristics, V_CCA= 0.9 ± 0.045 V...... 11

6.9 Switching Characteristics, V_CCA= 1.2 ± 0.1 V.......... 12

6.10 Switching Characteristics, V_CCA= 1.5 ± 0.1 V........ 13

6.11 Switching Characteristics, V_CCA= 1.8 ± 0.15 V...... 14

6.12 Switching Characteristics, V_CCA= 2.5 ± 0.2 V........ 15

6.13 Switching Characteristics, V_CCA= 3.3 ± 0.3 V........ 16

6.14 Operating Characteristics: T_A= 25°C..................... 17

6.15 Typical Characteristics............................................18

7 Parameter Measurement Information..........................19

Information.................................................................... 26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (January 2020) to Revision C (June 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Updated the Enable Times section...................................................................................................................23

Changes from Revision A (December 2019) to Revision B (January 2020)

Page

• 向数据表添加了DCU 和DCT 封装。.................................................................................................................1

Changes from Revision * (August 2019) to Revision A (December 2019)

Page

• 将“预告信息”更改为“生产数据”.................................................................................................................. 1

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5 Pin Configuration and Functions

V_CCA

V_CCB

V_CCA

V_CCB

GND

DIR

GND

图5-2. DCU Package 8-Pin VSSOP Top View

图5-1. DCT Package 8-Pin SM8 Top View

V_CCB

V_CCA

GND

A2 ³

DIR

图5-3. DTM Package 8-Pin X2SON Transparent Top View

表5-1. Pin Functions

NAME

NO.

DESCRIPTION

DTM, DCU, DCT

Input/output A1. Referenced to V_CCA

Input/output A2. Referenced to V_CCA

Input/output B1. Referenced to V_CCB

Input/output B2. Referenced to V_CCB

DIR

GND

V_CCA

V_CCB

Direction-control in for both ports. Referenced to V_CCA

Ground

A-port power supply voltage. 0.65 V ≤V_CCA≤3.6 V

B-port power supply voltage. 0.65 V ≤V_CCB≤3.6 V

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

–50

MAX UNITS

V_CCASupply voltage A

V_CCBSupply voltage B

4.2

I/O Ports (A Port)

I/O Ports (B Port)

Control Inputs

A Port

4.2

V_I

Input Voltage⁽²⁾

4.2

V_O

Voltage applied to any output in the high-impedance or power-off state⁽²⁾

Voltage applied to any output in the high or low state^{(2) (3)}

B Port

4.2

A Port

V_CCA+ 0.2

V_CCB+ 0.2

B Port

I_IK

I_OK

I_O

Input clamp current

V_I< 0

Output clamp current

V_O< 0

–50

Continuous output current

Continuous current through V_CCor GND

Junction Temperature

50 mA

100 mA

150 °C

–50

–100

T_j

T_stg

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±8000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

Specification JESD22-C101⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

0.65

MAX UNIT

V_CCA

V_CCB

Supply voltage A

Supply voltage B

3.6

0.65

V_CCI× 0.70

V_CCI× 0.65

1.6

V_CCI= 0.65 V –0.75 V

V_CCI= 0.76 V –1 V

V_CCI= 1.1 V –1.95 V

V_CCI= 2.3 V –2.7 V

V_CCI= 3 V –3.6 V

Data Inputs

V_IH

High-level input voltage

V_CCA× 0.70

V_CCA× 0.65

1.6

V_CCA= 0.65 V –0.75 V

V_CCA= 0.76 V –1 V

V_CCA= 1.1 V –1.95 V

V_CCA= 2.3 V –2.7 V

V_CCA= 3 V –3.6 V

V_CCI= 0.65 V –0.75 V

V_CCI= 0.76 V –1 V

V_CCI= 1.1 V –1.95 V

V_CCI= 2.3 V –2.7 V

V_CCI= 3 V –3.6 V

Control Input (DIR), Referenced

to V_CCA

V_CCIx 0.30

V_CCIx 0.35

0.7

Data Inputs

0.8

V_IL

Low-level input voltage

V_CCA× 0.30

V_CCA× 0.35

0.7

V_CCA= 0.65 V –0.75 V

V_CCA= 0.76 V –1 V

V_CCA= 1.1 V –1.95 V

V_CCA= 2.3 V –2.7 V

V_CCA= 3 V –3.6 V

Control Input (DIR), Referenced

to V_CCA

0.8

V_I

Input voltage

3.6

Active State

Tri-State

V_CCO

V_O

Output voltage

3.6

Δt/

Δv⁽²⁾

Input transition rise and fall time

10 ns/V

Δt/

Single channel input transition rise and fall time

Operating free-air temperature

100 ns/V

125 °C

Δv⁽³⁾

T_A

–40

(1) V_CCIis the V_CCassociated with the input port. V_CCOis the V_CCassociated with the output port.

(2) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, SCBA004.

(3) Input transition rate of a single channel while the other channels are at a valid logic state and not switching.

6.4 Thermal Information

SN74AXC2T45

THERMAL METRIC ⁽¹⁾

UNIT

DCT (SM8)

223.5

DCU (VSSOP) DTM (X2SON)

R_θJA

R_θJC(top)

R_θJB

Y_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

242.9

96.2

225.9

131.6

141.3

12.7

°C/W

120.7

138.0

153.3

38.2

47.5

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UNIT

6.4 Thermal Information (continued)

SN74AXC2T45

DCU (VSSOP) DTM (X2SON)

152.5 140.9

THERMAL METRIC ⁽¹⁾

DCT (SM8)

Y_JB

Junction-to-board characterization parameter

136.7

°C/W

(1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) ^{(1) (2) (3)}

Operating free-air temperature (T_A)

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

-40°C to 85°C

-40°C to 125°C

UNIT

MIN

TYP MAX

MIN

TYP MAX

V_CCO

-0.1

V_CCO

-0.1

I_OH= -100 µA

0.7 V –3.6 V 0.7 V –3.6 V

I_OH= -50 µA

I_OH= -200 µA

I_OH= -500 µA

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.55

0.58

0.65

0.85

1.05

1.2

0.55

0.58

0.65

0.85

1.05

1.2

High-level

output voltage

V_OH

V_I= V_IH

I_OH= -3 mA

I_OH= -6 mA

I_OH= -8 mA

I_OH= -9 mA

I_OH= -12 mA

I_OL= 100 µA

I_OL= 50 µA

I_OL= 200 µA

I_OL= 500 µA

I_OL= 3 mA

I_OL= 6 mA

I_OL= 8 mA

I_OL= 9 mA

I_OL= 12 mA

1.75

2.3

1.75

2.3

0.1

0.7 V –3.6 V 0.7 V –3.6 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.18

0.2

0.18

0.2

Low-level

output voltage

V_OL

V_I= V_IL

0.25

0.35

0.45

0.55

0.7

0.25

0.35

0.45

0.55

0.7

Control input (DIR):V_I=

V_CCAor GND

0.65 V –3.6 0.65 V –3.6

-0.5

-4

0.5

-1

-8

µA

Input leakage

current

I_I

Data Inputs (Ax, Bx),V_I=

V_CCIor GND

0.65 V –3.6 0.65 V –3.6

A Port: V_Ior V_O= 0 V –

3.6 V

0 V

-4

0 V –3.6 V

Partial power

down current

I_off

µA

B Port: V_Ior V_O= 0 V –

3.6 V

0 V

-4

0 V –3.6 V

0.65 V –3.6 0.65 V –3.6

V_I=

V_CCAsupply

current

I_CCA

V_CCIor I_O= 0

GND

0 V

3.6 V

0 V

-2

-12

0.65 V –3.6 0.65 V –3.6

V_I=

V_CCBsupply

current

I_CCB

V_CCIor I_O= 0

GND

µA

0 V

3.6 V

0 V

V_I=

I_CCA

I_CCB

Combined

supply current

0.65 V –3.6 0.65 V –3.6

V_CCIor I_O= 0

GND

23 µA

Control Input

(DIR)

Capacitance

C_i

V_I= 3.3 V or GND

3.3 V

3.3

5.4

3.3

5.4

Data I/O

Capacitance

V_O= 1.65 V DC +1 MHz

-16 dBm sine wave

C_io

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

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(3) All typical data is taken at 25°C.

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6.6 Switching Characteristics, V_CCA= 0.7 ± 0.05 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

170

140

143

311

306

0.5

115

149

140

105

311

247

0.5

106

Propagation

delay

t_pd

122

140

107

311

228

DIR

t_disDisable time

311

216

311

186

311

182

311

183

311

194

t_enEnable time

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6.7 Switching Characteristics, V_CCA= 0.8 ± 0.04 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

150

115

0.5

Propagation

delay

t_pd

DIR

t_disDisable time

136

246

243

246

188

246

157

246

128

246

123

246

122

246

123

246

125

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.8 Switching Characteristics, V_CCA= 0.9 ± 0.045 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

122

0.5

Propagation

delay

t_pd

DIR

t_disDisable time

133

211

192

211

146

211

120

211

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.9 Switching Characteristics, V_CCA= 1.2 ± 0.1 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

177

DIR

t_disDisable time

129

177

105

177

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.10 Switching Characteristics, V_CCA= 1.5 ± 0.1 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

172

DIR

t_disDisable time

128

172

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.11 Switching Characteristics, V_CCA= 1.8 ± 0.15 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

171

DIR

t_disDisable time

127

171

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.12 Switching Characteristics, V_CCA= 2.5 ± 0.2 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

182

DIR

t_disDisable time

127

182

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.13 Switching Characteristics, V_CCA= 3.3 ± 0.3 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Condtions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

105

218

DIR

t_disDisable time

128

218

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.14 Operating Characteristics: T_A= 25°C

PARAMETER

TEST CONDITIONS

V_CCA

0.7 V

V_CCB

0.7 V

MIN

TYP

2.2

MAX UNIT

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

2.0

Power Dissipation Capacitance CL = 0, RL = Open f = 1

per transceiver (A to B)

MHz, tr = tf = 1 ns

2.0

2.1

2.5

3.0

C_pdA

10.6

10.7

10.6

10.8

11.1

12.2

15.9

19.6

10.6

10.7

10.6

10.8

11.1

12.2

15.8

19.3

2.2

Power Dissipation Capacitance CL = 0, RL = Open f = 1

per transceiver (B to A) MHz, tr = tf = 1 ns

Power Dissipation Capacitance CL = 0, RL = Open f = 1

per transceiver (A to B) MHz, tr = tf = 1 ns

C_pdB

2.0

Power Dissipation Capacitance CL = 0, RL = Open f = 1

per transceiver (B to A) MHz, tr = tf = 1 ns

2.0

2.1

2.5

3.0

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6.15 Typical Characteristics

3.4

3.2

1.25

1.2

V_CC= 1.8V

V_CC= 2.5V

V_CC= 3.3V

1.15

1.1

1.05

2.8

2.6

2.4

2.2

0.95

0.9

0.85

0.8

0.75

0.7

1.8

1.6

1.4

0.65

0.6

V_CC= 0.7V

V_CC= 1.2V

0.55

0.5

1.5

2.5

I_OH(mA)

3.5

4.5

I_OH(mA)

D001

图6-2. Typical (T_A=25°C) Output High Voltage (V_OH) vs Source

Current (I_OH

图6-1. Typical (T_A=25°C) Output High Voltage (V_OH) vs Source

Current (I_OH

)

700

650

600

550

500

450

400

350

300

250

200

150

100

220

200

180

160

140

120

100

V_CC= 1.8V

V_CC= 2.5V

V_CC= 3.3V

V_CC= 0.7V

V_CC= 1.2V

-50

I_OL(mA)

0.5

1.5

2.5

I_OL(mA)

3.5

4.5

D001

图6-3. Typical (T_A=25°C) Output High Voltage (V_OL) vs Sink

Current (I_OL

图6-4. Typical (T_A=25°C) Output High Voltage (V_OL) vs Sink

Current (I_OL

)

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7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

• f = 1 MHz

• Z_O= 50 Ω

• dv/dt ≤1 ns/V

Measurement Point

2 x V_CCO

Open

GND

R_L

Output Pin

Under Test

(1)

C_L

R_L

A. C_Lincludes probe and jig capacitance.

图7-1. Load Circuit

表7-1. Load Circuit Conditions

Parameter

V_CCO

R_L

C_L

S₁

V_TP

N/A

Δt/

Δv

Input transition rise or fall rate

15 pF

Open

0.65 V –3.6 V

1.1 V –3.6 V

1 MΩ

2 kΩ

20 kΩ

t_pd

Propagation (delay) time

0.65 V –0.95

15 pF

2 × V_CCO

0.3 V

0.15 V

0.1 V

3 V –3.6 V

1.65 V –2.7 V

1.1 V –1.6 V

2 kΩ

t_en, t_disEnable time, disable time

0.65 V –0.95

15 pF

2 × V_CCO

0.1 V

20 kΩ

15 pF

GND

0.3 V

0.15 V

0.1 V

3 V –3.6 V

1.65 V –2.7 V

1.1 V –1.6 V

2 kΩ

t_en, t_disEnable time, disable time

0.65 V –0.95

15 pF

GND

0.1 V

20 kΩ

(1)

V_CCI

(1)

V_CCI

Input A, B

100 kHz

V_CCI/ 2

Input A, B

500 ps/V œ 10 ns/V

0 V

V_OH

0 V

V_OH

(2)

t_pd

(2)

Output B, A

Ensure Monotonic

Rising and Falling Edge

(2)

V_OL

Output B, A

V_CCI/ 2

(2)

V_OL

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁

图7-3. Input Transition Rise or Fall Rate

图7-2. Propagation Delay

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V_CCA

V_CCA/ 2

DIR

V_CCA/ 2

GND

(1)

t_en

(5)

V_CCO

Output A⁽²⁾

Output A⁽³⁾

V_CCO/ 2

V_OL+ V_TP

(6)

V_OL

t_dis

(6)

V_OH

V_OH- V_TP

V_CCO/ 2

GND

(1)

t_en

(5)

V_CCO

Output B⁽²⁾

Output B⁽³⁾

V_CCO/ 2

V_OL+ V_TP

(6)

V_OL

t_dis

(6)

V_OH

V_OH- V_TP

V_CCO/ 2

GND

A. Illustrative purposes only. Enable Time is a calculation as described in the Application Information section.

B. Output waveform on the condition that input is driven to a valid Logic Low.

C. Output waveform on the condition that input is driven to a valid Logic High.

D. V_CCIis the supply pin associated with the input port.

E. V_CCOis the supply pin associated with the output port.

F. V_OHand V_OLare typical output voltage levels with specified R_L, C_L, and S₁.

图7-4. Enable Time And Disable Time

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8 Detailed Description

8.1 Overview

The SN74AXC2T45 is a 2-bit, dual-supply non-inverting bidirectional voltage level translation device. Ax pins

and the DIR pin are referenced to V_CCAlogic levels, and Bx pins are referenced to V_CCBlogic levels. The A port

is able to accept I/O voltages ranging from 0.65 V to 3.6 V, while the B port can accept I/O voltages from 0.65 V

to 3.6 V. A high on DIR enables data transmission from A to B and a low on DIR enables data transmission from

B to A. See Device Functional Modes for a summary of the operation of the control logic.

8.2 Functional Block Diagram

V_CCA

V_CCB

DIR

8.3 Feature Description

8.3.1 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in 节 6.5. The worst case resistance is calculated with the maximum input voltage, given in 节

6.1, and the maximum input leakage current, given in the 节6.5, using Ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in 节 6.3 to avoid excessive

current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger

input should be used to condition the input signal prior to the standard CMOS input.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device

creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. The electrical and thermal limits defined in 节6.1 must be followed at all times.

8.3.3 Partial Power Down (I_off

)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting

current backflow into the device. The maximum leakage into or out of any input or output pin on the device is

specified by I_offin 节6.5.

8.3.4 V_CCIsolation

The inputs and outputs for this device enter a high-impedance state when either supply is <100 mV.

8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum

input voltage value specified in 节6.3.

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8.3.6 Glitch-Free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the

output erroneously transitions to V_CCwhen it should be held low). Glitches of this nature can be misinterpreted

by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device

configuration of the peripheral, or even a false data initialization by the peripheral. For more information

regarding the power up glitch performance of the AXC family of level translators, see the Glitch Free Power

Sequencing With AXC Level Translators application report.

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in 图8-1.

CAUTION

Voltages beyond the values specified in 节 6.1 table can cause damage to the device. The input

negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current

ratings are observed.

V_CCAV_CCB

Device

Input or I/O

configured

as input

Level

Shifter

I/O configured

as output

-I_IK

-I_OK

GND

图8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

Both the V_CCAand V_CCBpins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for

translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).

8.3.9 Supports High-Speed Translation

The SN74AXC2T45 device can support high data-rate applications. The translated signal data rate can be up to

380 Mbps when the signal is translated from 1.8 V to 3.3 V.

8.4 Device Functional Modes

表8-1. Function Table⁽¹⁾

CONTROL INPUT Port Status

OPERATION

DIR

A PORT

Output (Enabled)

Input (Hi-Z)

B PORT

Input (Hi-Z)

Output (Enabled)

B data to A bus

A data to B bus

(1) Input circuits of the data I/O's are always active.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The SN74AXC2T45 device can be used in level-translation applications for interfacing devices or systems

operating at different interface voltages with one another. The SN74AXC2T45 device is ideal for use in

applications where a push-pull driver is connected to the data I/Os. The max data rate can be up to 380 Mbps

when device translates a signal from 1.8 V to 3.3 V.

One example application is shown in 图 9-1, where the SN74AXC2T45 device is used to translate low voltage

error signals from a CPU to a higher voltage signal to properly drive the inputs of a system controller, thus

alerting the system of any CPU errors such as overheating or other catastrophic processor errors.

9.1.1 Enable Times

Calculate the enable times for the SN74AXC2T45 using the following formulas:

t_{A_en}(DIR to A) = t_dis(DIR to B) + t_pd(B to A)

t_{B_en}(DIR to A) = t_dis(DIR to A) + t_pd(A to B)

(1)

(2)

In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is

switched until an output is expected. For example, if the SN74AXC2T45 initially is transmitting from A to B, then

the DIR bit is switched; the B port of the device must be disabled (t_dis) before presenting it with an input. After the

B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified

propagation delay (t_pd). To avoid bus contention care should be taken to not apply an input signal prior to the

output port being disabled (t_dismaximum).

9.2 Typical Application

2.5 V

0.7 V

0.1 µF

System

Controller

CPU

V_CCB

V_CCA

CAT ERR

PROC HOT

GPIO1

SN74AXC2T45

GND

GPIO2

DIR

图9-1. Processor Error Application

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9.2.1 Design Requirements

For this design example, use the parameters listed in 表9-1.

表9-1. Design Parameters

DESIGN PARAMETERS

Input voltage range

EXAMPLE VALUES

0.65 V to 3.6 V

Output voltage range

0.65 V to 3.6 V

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range

– Use the supply voltage of the device that is driving the SN74AXC2T45 device to determine the input

voltage range. For a valid logic-high, the value must exceed the high-level input voltage (V_IH) of the input

port. For a valid logic low the value must be less than the low-level input voltage (V_IL) of the input port.

• Output voltage range

– Use the supply voltage of the device that the SN74AXC2T45 device is driving to determine the output

voltage range.

9.2.3 Application Curve

图9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V)

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing

without any supply sequencing requirements such as ramp order or ramp rate.

This device is designed with various power supply sequencing methods in mind to help prevent unintended

triggering of downstream devices. For more information regarding the power up glitch performance of the AXC

family of level translators, see the Glitch Free Power Sequencing With AXC Level Translators application report

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF

capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF

capacitors in parallel as bypass capacitors.

• Use short trace lengths to avoid excessive loading.

11.2 Layout Example

Legend

Via to V_CCA

Via to V_CCB

Via to GND

Copper Traces

SN74AXC2T45DTM

01005

0.1µF

01005

0.1µF

4 mil

PROC HOT

from CPU

V_CCB

V_CCA

PROC HOT

to Controller

CAT ERR

from CPU

8 mil

GND

CAT ERR

_{to Controller}A2

DIR

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report

• Texas Instruments, Power Sequencing for AXC Family of Devicesapplication report

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

16-Jun-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74AXC2T45DCTR

ACTIVE

SM8

DCT

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

1H6

SN74AXC2T45DCUR

SN74AXC2T45DTMR

ACTIVE

VSSOP

X2SON

DCU

DTM

-40 to 125

22HT

5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM

1FP

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Jun-2021

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AXC2T45 :

Automotive : SN74AXC2T45-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74AXC2T45DCTR

SN74AXC2T45DCUR

SN74AXC2T45DTMR

SM8

DCT

DCU

DTM

3000

5000

177.8

178.0

180.0

178.0

12.4

9.0

9.5

8.4

3.45

2.25

0.93

4.4

1.45

1.05

0.43

4.0

2.0

12.0

8.0

VSSOP

X2SON

3.35

1.49

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74AXC2T45DCTR

SN74AXC2T45DCUR

SN74AXC2T45DTMR

SM8

DCT

DCU

DTM

3000

5000

183.0

180.0

189.0

205.0

183.0

180.0

185.0

200.0

20.0

18.0

36.0

33.0

VSSOP

X2SON

Pack Materials-Page 2

PACKAGE OUTLINE

DCU0008A

VSSOP - 0.9 mm max height

SMALL OUTLINE PACKAGE

3.2

3.0

TYP

0.1 C

PIN 1 INDEX AREA

SEATING

PLANE

6X 0.5

2.1

1.9

1.5

NOTE 3

0.25

0.17

2.4

2.2

0.08

C A B

NOTE 3

SEE DETAIL A

0.9

0.6

0.12

GAGE PLANE

0.1

0.0

0.35

0.20

0 -6

(0.13) TYP

DETAIL A

TYPICAL

4225266/A 09/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-187 variation CA.

www.ti.com

EXAMPLE BOARD LAYOUT

DCU0008A

VSSOP - 0.9 mm max height

SMALL OUTLINE PACKAGE

SEE SOLDER MASK

DETAILS

SYMM

8X (0.85)

(R0.05) TYP

8X (0.3)

SYMM

6X (0.5)

(3.1)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

SOLDER MASK

OPENING

METAL UNDER

METAL

SOLDER MASK

OPENING

SOLDER MASK

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4225266/A 09/2014

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DCU0008A

VSSOP - 0.9 mm max height

SMALL OUTLINE PACKAGE

8X (0.85)

SYMM

(R0.05) TYP

8X (0.3)

SYMM

6X (0.5)

(3.1)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 25X

4225266/A 09/2014

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DCT0008A

SSOP - 1.3 mm max height

SMALL OUTLINE PACKAGE

SEATING PLANE

0.1 C

4.25

3.75

TYP

PIN 1 ID

AREA

6X 0.65

3.15

2.75

1.95

NOTE 3

0.30

0.15

2.9

2.7

NOTE 4

1.3

1.0

0.13

C A B

(0.15) TYP

0.25

SEE DETAIL A

GAGE PLANE

0.1

0.0

0.6

0.2

0 - 8

DETAIL A

TYPICAL

4220784/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DCT0008A

SSOP - 1.3 mm max height

SMALL OUTLINE PACKAGE

8X (1.1)

SYMM

(R0.05)

TYP

8X (0.4)

SYMM

6X (0.65)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4220784/C 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DCT0008A

SSOP - 1.3 mm max height

SMALL OUTLINE PACKAGE

8X (1.1)

SYMM

8X (0.4)

SYMM

6X (0.65)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4220784/C 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DTM0008A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

0.85

0.75

PIN 1 INDEX AREA

1.4

1.3

0.4 MAX

SEATING PLANE

0.05 C

0.04

0.00

SYMM

(0.102) TYP

0.27

0.17

SYMM

0.54

0.5

0.25

0.15

PIN 1 ID

0.27

0.17

0.1

C B A

0.05

4224755/B 10/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad(s) must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DTM0008A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.42)

6X (0.2)

(

0.22)

4X (0.079)

SYMM

(0.27)

(45 ) TYP

(0.5)

4X (0.1)

(R0.05) TYP

SYMM

(0.78)

SEE SOLDER MASK

DETAILS

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:40X

0.0325 MIN

ALL AROUND

0.0325 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL EDGE

SOLDER MASK

DEFINED

(PREFERRED)

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4224755/B 10/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

DTM0008A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.2) TYP

4X (0.42)

(

0.22)

6X (0.2)

(0.411)

4X (0.079)

(0.27)

SYMM

(45 ) TYP

(0.5)

(R0.05) TYP

4X (0.128)

SYMM

EXPOSED

METAL

(0.78)

PINS: 1,3,5,7

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL

SCALE: 40X

4224755/B 10/2022

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74AXC2T45 [TI]

相关型号：

SN74AXC2T45-Q1

SN74AXC2T45-Q1_V01

SN74AXC2T45DCTR

SN74AXC2T45DCUR

SN74AXC2T45DTMR

SN74AXC2T45QDCURQ1

SN74AXC4T245

SN74AXC4T245-Q1

SN74AXC4T245-Q1_V03

SN74AXC4T245-Q1_V04

SN74AXC4T245BQB

SN74AXC4T245BQB-Q1