SN74AXC2T45QDCURQ1 [TI]

SN74AXC2T45-Q1 2-Bit Translating Transceiver with Configurable Level-Shifting;


型号：	SN74AXC2T45QDCURQ1
厂家：	TEXAS INSTRUMENTS
描述：	SN74AXC2T45-Q1 2-Bit Translating Transceiver with Configurable Level-Shifting
文件：	总30页 (文件大小：1471K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74AXC2T45-Q1

SCES928A – APRIL 2021 – REVISED SEPTEMBER 2021

SN74AXC2T45-Q1 2-Bit Translating Transceiver with Configurable Level-Shifting

The SN74AXC2T45-Q1 device is designed for

asynchronous communication between data buses.

1 Features

•

AEC-Q100 automotive qualified

Fully configurable dual-rail design allows each port

to operate with a power supply range from 0.65 V

to 3.6 V

The device transmits data from the A bus to the B

bus or from the B bus to the A bus, depending on

the logic level of the direction-control input (DIR). The

SN74AXC2T45-Q1 device is designed so the control

•

Operating temperature from –40°C to +125°C

Glitch-free power supply sequencing

Up to 380 Mbps support when translating from 1.8

V to 3.3 V

pin (DIR) is referenced to V_CCA.

This device is fully specified for partial-power-down

applications using the I_offcurrent. The I_offprotection

circuitry ensures that no excessive current is drawn

from or to an input, output, or combined I/O that

is biased to a specific voltage while the device is

powered down.

•

V_CCisolation feature

– If either V_CCinput is below 100 mV, all

I/Os outputs are disabled and become high-

impedance

The V_CCisolation feature ensures that if either V_CCA

or V_CCBis less than 100 mV, both I/O ports enter a

high-impedance state by disabling their outputs.

•

I_offsupports partial-power-down mode operation

Compatible with AVC family level shifters

Latch-up performance exceeds 100 mA per JESD

78, Class II

ESD protection exceeds JESD 22

– 8000-V human-body model

Glitch-free power supply sequencing allows either

supply rail to be powered on or off in any order while

providing robust power sequencing performance.

•

– 1000-V charged-device model

Device Information⁽¹⁾

2 Applications

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN74AXC2T45DCU

VSSOP (8)

2.30 mm × 2.00 mm

•

Enterprise and communications

Industrial

Personal electronics

Wireless infrastructure

Building automation

Point-of-sale

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

V_CCA

V_CCB

DIR

3 Description

The SN74AXC2T45-Q1 is a two-bit noninverting bus

transceiver that uses two individually configurable

power-supply rails. The device is operational with both

V_CCAand V_CCBsupplies as low as 0.65 V. The A port

is designed to track V_CCA, which accepts any supply

voltage from 0.65 V to 3.6 V. The B port is designed

to track V_CCB, which also accepts any supply voltage

from 0.65 V to 3.6 V. Additionally the SN74AXC2T45-

Q1 is compatible with a single-supply system.

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74AXC2T45-Q1

SCES928A – APRIL 2021 – REVISED SEPTEMBER 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics, V_CCA= 0.7 ± 0.05 V.......... 7

6.7 Switching Characteristics, V_CCA= 0.8 ± 0.04 V.......... 8

6.8 Switching Characteristics, V_CCA= 0.9 ± 0.045 V........ 9

6.9 Switching Characteristics, V_CCA= 1.2 ± 0.1 V.......... 10

6.10 Switching Characteristics, V_CCA= 1.5 ± 0.1 V........ 11

6.11 Switching Characteristics, V_CCA= 1.8 ± 0.15 V...... 12

6.12 Switching Characteristics, V_CCA= 2.5 ± 0.2 V........ 13

6.13 Switching Characteristics, V_CCA= 3.3 ± 0.3 V........ 14

6.14 Operating Characteristics: T_A= 25°C..................... 15

6.15 Typical Characteristics............................................16

7 Parameter Measurement Information..........................17

7.1 Load Circuit and Voltage Waveforms........................17

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................20

9 Application and Implementation..................................21

9.1 Application Information............................................. 21

9.2 Typical Application.................................................... 21

10 Power Supply Recommendations..............................23

11 Layout...........................................................................23

11.1 Layout Guidelines................................................... 23

11.2 Layout Example...................................................... 23

12 Device and Documentation Support..........................24

12.1 Documentation Support.......................................... 24

12.2 Receiving Notification of Documentation Updates..24

12.3 Support Resources................................................. 24

12.4 Trademarks.............................................................24

12.5 Electrostatic Discharge Caution..............................24

12.6 Glossary..................................................................24

13 Mechanical, Packaging, and Orderable

Information.................................................................... 24

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (April 2021) to Revision A (September 2021)

Page

•

Changed the status of the data sheet from: Advance Information to: Production Data .....................................1

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5 Pin Configuration and Functions

V_CCA

V_CCB

DIR

GND

Figure 5-1. DCU Package 8-Pin VSSOP Top View

Table 5-1. Pin Functions

NAME

NO.

DESCRIPTION

DTM, DCU, DCT

Input/output A1. Referenced to V_CCA

Input/output A2. Referenced to V_CCA

Input/output B1. Referenced to V_CCB

Input/output B2. Referenced to V_CCB

DIR

GND

V_CCA

V_CCB

Direction-control in for both ports. Referenced to V_CCA

Ground

A-port power supply voltage. 0.65 V ≤ V_CCA≤ 3.6 V

B-port power supply voltage. 0.65 V ≤ V_CCB≤ 3.6 V

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX UNITS

V_CCASupply voltage A

V_CCBSupply voltage B

4.2

I/O Ports (A Port)

I/O Ports (B Port)

Control Inputs

A Port

V_I

Input Voltage⁽²⁾

V_O

Voltage applied to any output in the high-impedance or power-off state⁽²⁾

Voltage applied to any output in the high or low state^{(2) (3)}

B Port

A Port

–0.5 V_CCA+ 0.2

–0.5 V_CCB+ 0.2

–50

B Port

I_IK

I_OK

I_O

Input clamp current

V_I< 0

Output clamp current

V_O< 0

–50

Continuous output current

Continuous current through V_CCor GND

Junction Temperature

–50

50 mA

100 mA

150 °C

–100

T_j

T_stg

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6.2 ESD Ratings

VALUE

±8000

±1000

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001

specification.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

0.65

MAX UNIT

V_CCA

V_CCB

Supply voltage A

Supply voltage B

3.6

0.65

V_CCI= 0.65 V – 0.75 V

V_CCI= 0.76 V – 1 V

V_CCI= 1.1 V – 1.95 V

V_CCI= 2.3 V – 2.7 V

V_CCI= 3 V – 3.6 V

V_CCI× 0.70

V_CCI× 0.65

1.6

Data Inputs

V_IH

High-level input voltage

V_CCA= 0.65 V – 0.75 V

V_CCA= 0.76 V – 1 V

V_CCA= 1.1 V – 1.95 V

V_CCA= 2.3 V – 2.7 V

V_CCA= 3 V – 3.6 V

V_CCI= 0.65 V – 0.75 V

V_CCI= 0.76 V – 1 V

V_CCI= 1.1 V – 1.95 V

V_CCI= 2.3 V – 2.7 V

V_CCI= 3 V – 3.6 V

V_CCA× 0.70

V_CCA× 0.65

1.6

Control Input (DIR), Referenced

to V_CCA

V_CCIx 0.30

V_CCIx 0.35

0.7

Data Inputs

0.8

V_IL

Low-level input voltage

V_CCA= 0.65 V – 0.75 V

V_CCA= 0.76 V – 1 V

V_CCA= 1.1 V – 1.95 V

V_CCA= 2.3 V – 2.7 V

V_CCA= 3 V – 3.6 V

V_CCA× 0.30

V_CCA× 0.35

0.7

Control Input (DIR), Referenced

to V_CCA

0.8

V_I

Input voltage

3.6

Active State

Tri-State

V_CCO

V_O

Output voltage

3.6

Δt/Δv⁽²⁾Input transition rise and fall time

10 ns/V

100 ns/V

125 °C

Δt/Δv⁽³⁾Single channel input transition rise and fall time

T_A

Operating free-air temperature

–40

(1) V_CCIis the V_CCassociated with the input port. V_CCOis the V_CCassociated with the output port.

(2) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, SCBA004.

(3) Input transition rate of a single channel while the other channels are at a valid logic state and not switching.

6.4 Thermal Information

SN74AXC2T45-Q1

THERMAL METRIC ⁽¹⁾

UNIT

DCT (SM8)

223.5

DCU (VSSOP) DTM (X2SON)

R_θJA

R_θJC(top)

R_θJB

Y_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

242.9

96.2

225.9

131.6

141.3

12.7

°C/W

120.7

138.0

153.3

38.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

47.5

Y_JB

136.7

152.5

140.9

(1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) ^{(1) (2) (3)}

Operating free-air temperature (T_A)

-40°C to 85°C -40°C to 125°C

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

UNIT

MIN

TYP MAX

MIN

TYP MAX

V_CCO

-0.1

V_CCO

-0.1

I_OH= -100 µA

0.7 V – 3.6 V 0.7 V – 3.6 V

I_OH= -50 µA

I_OH= -200 µA

I_OH= -500 µA

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.55

0.58

0.65

0.85

1.05

1.2

0.55

0.58

0.65

0.85

1.05

1.2

High-level

output voltage

V_OH

V_I= V_IH

I_OH= -3 mA

I_OH= -6 mA

I_OH= -8 mA

I_OH= -9 mA

1.75

2.3

1.75

2.3

I_OH= -12 mA

I_OL= 100 µA

I_OL= 50 µA

0.7 V – 3.6 V 0.7 V – 3.6 V

0.1

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

0.65 V

0.76 V

0.85 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

I_OL= 200 µA

I_OL= 500 µA

V_I= V_ILI_OL= 3 mA

I_OL= 6 mA

0.18

0.2

0.18

0.2

0.25

0.35

0.45

0.55

0.7

Low-level

output voltage

V_OL

0.25

0.35

0.45

0.55

0.7

I_OL= 8 mA

I_OL= 9 mA

I_OL= 12 mA

Control input (DIR):V_I=

V_CCAor GND

0.65 V – 3.6 V 0.65 V – 3.6 V

-0.5

-4

0.5

-1

-8

µA

Input leakage

current

I_I

Data Inputs (Ax, Bx),V_I=

V_CCIor GND

A Port: V_Ior V_O= 0 V –

3.6 V

0 V

0 V – 3.6 V

0 V

-4

Partial power

down current

I_off

µA

B Port: V_Ior V_O= 0 V –

3.6 V

0 V – 3.6 V

-4

0.65 V – 3.6 V 0.65 V – 3.6 V

V_I=

V_CCAsupply

current

I_CCA

V_CCIor I_O= 0

GND

0 V

3.6 V

0 V

-2

-12

µA

3.6 V

0.65 V – 3.6 V 0.65 V – 3.6 V

V_I=

V_CCBsupply

current

I_CCB

V_CCIor I_O= 0

GND

0 V

3.6 V

0 V

3.6 V

V_I=

I_CCA

I_CCB

Combined

supply current

V_CCIor I_O= 0

GND

0.65 V – 3.6 V 0.65 V – 3.6 V

23 µA

Control Input

(DIR)

Capacitance

C_i

V_I= 3.3 V or GND

3.3 V

3.3

5.4

3.3

5.4

Data I/O

Capacitance

V_O= 1.65 V DC +1 MHz

-16 dBm sine wave

C_io

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) All typical data is taken at 25°C.

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6.6 Switching Characteristics, V_CCA= 0.7 ± 0.05 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

170

140

143

311

306

0.5

115

149

140

105

311

247

0.5

106

Propagation

delay

t_pd

122

140

107

311

228

DIR

t_disDisable time

311

216

311

186

311

182

311

183

311

194

t_enEnable time

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6.7 Switching Characteristics, V_CCA= 0.8 ± 0.04 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

150

115

0.5

Propagation

delay

t_pd

DIR

t_disDisable time

136

246

243

246

188

246

157

246

128

246

123

246

122

246

123

246

125

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.8 Switching Characteristics, V_CCA= 0.9 ± 0.045 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

122

0.5

Propagation

delay

t_pd

DIR

t_disDisable time

133

211

192

211

146

211

120

211

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.9 Switching Characteristics, V_CCA= 1.2 ± 0.1 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

177

DIR

t_disDisable time

129

177

105

177

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.10 Switching Characteristics, V_CCA= 1.5 ± 0.1 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

172

DIR

t_disDisable time

128

172

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.11 Switching Characteristics, V_CCA= 1.8 ± 0.15 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

171

DIR

t_disDisable time

127

171

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.12 Switching Characteristics, V_CCA= 2.5 ± 0.2 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

182

DIR

t_disDisable time

127

182

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.13 Switching Characteristics, V_CCA= 3.3 ± 0.3 V

See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Condtions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

0.5

Propagation

delay

t_pd

105

218

DIR

t_disDisable time

128

218

t_en

Enable time

(1)

(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.

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6.14 Operating Characteristics: T_A= 25°C

PARAMETER

TEST CONDITIONS

V_CCA

0.7 V

V_CCB

0.7 V

MIN

TYP

2.2

MAX UNIT

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

2.0

Power Dissipation Capacitance CL = 0, RL = Open f = 1

per transceiver (A to B)

MHz, tr = tf = 1 ns

2.0

2.1

2.5

3.0

C_pdA

10.6

10.7

10.6

10.8

11.1

12.2

15.9

19.6

10.6

10.7

10.6

10.8

11.1

12.2

15.8

19.3

2.2

Power Dissipation Capacitance CL = 0, RL = Open f = 1

per transceiver (B to A) MHz, tr = tf = 1 ns

Power Dissipation Capacitance CL = 0, RL = Open f = 1

per transceiver (A to B) MHz, tr = tf = 1 ns

C_pdB

2.0

Power Dissipation Capacitance CL = 0, RL = Open f = 1

per transceiver (B to A) MHz, tr = tf = 1 ns

2.0

2.1

2.5

3.0

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6.15 Typical Characteristics

3.4

3.2

1.25

1.2

V_CC= 1.8V

V_CC= 2.5V

V_CC= 3.3V

1.15

1.1

1.05

2.8

2.6

2.4

2.2

0.95

0.9

0.85

0.8

0.75

0.7

1.8

1.6

1.4

0.65

0.6

V_CC= 0.7V

V_CC= 1.2V

0.55

0.5

1.5

2.5

I_OH(mA)

3.5

4.5

I_OH(mA)

D001

Figure 6-2. Typical (T_A=25°C) Output High Voltage (V_OH) vs

Source Current (I_OH

Figure 6-1. Typical (T_A=25°C) Output High Voltage (V_OH) vs

Source Current (I_OH

)

700

650

600

550

500

450

400

350

300

250

200

150

100

220

200

180

160

140

120

100

V_CC= 1.8V

V_CC= 2.5V

V_CC= 3.3V

V_CC= 0.7V

V_CC= 1.2V

-50

I_OL(mA)

0.5

1.5

2.5

I_OL(mA)

3.5

4.5

D001

Figure 6-3. Typical (T_A=25°C) Output High Voltage (V_OL) vs Sink Figure 6-4. Typical (T_A=25°C) Output High Voltage (V_OL) vs Sink

Current (I_OLCurrent (I_OL

)

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7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

•

f = 1 MHz

Z_O= 50 Ω

dv/dt ≤ 1 ns/V

Measurement Point

2 x V_CCO

Open

R_L

Output Pin

Under Test

GND

(1)

C_L

R_L

A. C_Lincludes probe and jig capacitance.

Figure 7-1. Load Circuit

Table 7-1. Load Circuit Conditions

Parameter

V_CCO

R_L

C_L

S₁

V_TP

N/A

Δt/Δv Input transition rise or fall rate

0.65 V – 3.6 V

1.1 V – 3.6 V

1 MΩ

2 kΩ

15 pF

Open

t_pd

Propagation (delay) time

0.65 V – 0.95

20 kΩ

15 pF

Open

N/A

3 V – 3.6 V

1.65 V – 2.7 V

1.1 V – 1.6 V

2 kΩ

15 pF

2 × V_CCO

0.3 V

0.15 V

0.1 V

t_en, t_disEnable time, disable time

0.65 V – 0.95

20 kΩ

15 pF

2 × V_CCO

0.1 V

3 V – 3.6 V

1.65 V – 2.7 V

1.1 V – 1.6 V

2 kΩ

15 pF

GND

0.3 V

0.15 V

0.1 V

t_en, t_disEnable time, disable time

0.65 V – 0.95

20 kΩ

15 pF

GND

0.1 V

(1)

V_CCI

(1)

V_CCI

Input A, B

100 kHz

V_CCI/ 2

Input A, B

500 ps/V œ 10 ns/V

0 V

V_OH

0 V

V_OH

(2)

t_pd

(2)

Output B, A

Ensure Monotonic

Rising and Falling Edge

(2)

V_OL

Output B, A

V_CCI/ 2

(2)

V_OL

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁

Figure 7-3. Input Transition Rise or Fall Rate

Figure 7-2. Propagation Delay

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V_CCA

V_CCA/ 2

DIR

V_CCA/ 2

GND

(1)

t_en

(5)

V_CCO

Output A⁽²⁾

Output A⁽³⁾

V_CCO/ 2

V_OL+ V_TP

(6)

V_OL

t_dis

(6)

V_OH

V_OH- V_TP

V_CCO/ 2

GND

(1)

t_en

(5)

V_CCO

Output B⁽²⁾

Output B⁽³⁾

V_CCO/ 2

V_OL+ V_TP

(6)

V_OL

t_dis

(6)

V_OH

V_OH- V_TP

V_CCO/ 2

GND

A. Illustrative purposes only. Enable Time is a calculation as described in the Application Information section.

B. Output waveform on the condition that input is driven to a valid Logic Low.

C. Output waveform on the condition that input is driven to a valid Logic High.

D. V_CCIis the supply pin associated with the input port.

E. V_CCOis the supply pin associated with the output port.

F. V_OHand V_OLare typical output voltage levels with specified R_L, C_L, and S₁.

Figure 7-4. Enable Time And Disable Time

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8 Detailed Description

8.1 Overview

The SN74AXC2T45-Q1 is a 2-bit, dual-supply non-inverting bidirectional voltage level translation device. Ax pins

and the DIR pin are referenced to V_CCAlogic levels, and Bx pins are referenced to V_CCBlogic levels. The A port

is able to accept I/O voltages ranging from 0.65 V to 3.6 V, while the B port can accept I/O voltages from 0.65 V

to 3.6 V. A high on DIR enables data transmission from A to B and a low on DIR enables data transmission from

B to A. See Section 8.4 for a summary of the operation of the control logic.

8.2 Functional Block Diagram

V_CCA

V_CCB

DIR

8.3 Feature Description

8.3.1 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in Section 6.5. The worst case resistance is calculated with the maximum input voltage, given

in Section 6.1, and the maximum input leakage current, given in the Section 6.5, using Ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Section 6.3 to avoid excessive

current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger

input should be used to condition the input signal prior to the standard CMOS input.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device

creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. The electrical and thermal limits defined in Section 6.1 must be followed at all times.

8.3.3 Partial Power Down (I_off)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting

current backflow into the device. The maximum leakage into or out of any input or output pin on the device is

specified by I_offin Section 6.5.

8.3.4 V_CCIsolation

The inputs and outputs for this device enter a high-impedance state when either supply is <100 mV.

8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum

input voltage value specified in Section 6.3.

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8.3.6 Glitch-Free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is,

where the output erroneously transitions to V_CCwhen it should be held low). Glitches of this nature can be

misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral,

a false device configuration of the peripheral, or even a false data initialization by the peripheral. For more

information regarding the power up glitch performance of the AXC family of level translators, see the Glitch Free

Power Sequencing With AXC Level Translators application report.

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in Figure 8-1.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to

the device. The input negative voltage and output voltage ratings may be exceeded if the input and

output clamp-current ratings are observed.

V_CCAV_CCB

Device

Input or I/O

configured

as input

Level

Shifter

I/O configured

as output

-I_IK

-I_OK

GND

Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

Both the V_CCAand V_CCBpins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for

translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).

8.3.9 Supports High-Speed Translation

The SN74AXC2T45-Q1 device can support high data-rate applications. The translated signal data rate can be

up to 380 Mbps when the signal is translated from 1.8 V to 3.3 V.

8.4 Device Functional Modes

Table 8-1. Function Table⁽¹⁾

CONTROL INPUT Port Status

OPERATION

DIR

A PORT

Output (Enabled)

Input (Hi-Z)

B PORT

Input (Hi-Z)

Output (Enabled)

B data to A bus

A data to B bus

(1) Input circuits of the data I/O's are always active.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The SN74AXC2T45-Q1 device can be used in level-translation applications for interfacing devices or systems

operating at different interface voltages with one another. The SN74AXC2T45-Q1 device is ideal for use in

applications where a push-pull driver is connected to the data I/Os. The maximum data rate can be up to 380

Mbps when device translates a signal from 1.8 V to 3.3 V.

Figure 9-1 shows one example application where the SN74AXC2T45-Q1 device is used to translate low voltage

error signals from a CPU to a higher voltage signal to properly drive the inputs of a system controller, thus

alerting the system of any CPU errors such as overheating or other catastrophic processor errors.

9.1.1 Enable Times

Calculate the enable times for the SN74AXC2T45-Q1 using the following formulas:

t_{A_en}(DIR to A) = t_dis(DIR to B) + t_pd(B to A)

t_{B_en}(DIR to A) = t_dis(DIR to A) + t_pd(A to B)

(1)

(2)

In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is

switched until an output is expected. For example, if the SN74AXC2T45-Q1 initially is transmitting from A to B,

then the DIR bit is switched; the B port of the device must be disabled (t_dis) before presenting it with an input.

After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the

specified propagation delay (t_pd). To avoid bus contention care should be taken to not apply an input signal prior

to the output port being disabled (t_dismaximum).

9.2 Typical Application

2.5 V

0.7 V

0.1 µF

System

Controller

CPU

V_CCB

V_CCA

CAT ERR

PROC HOT

GPIO1

SN74AXC2T45

GND

GPIO2

DIR

Figure 9-1. Processor Error Application

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9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1.

Table 9-1. Design Parameters

DESIGN PARAMETERS

Input voltage range

EXAMPLE VALUES

0.65 V to 3.6 V

Output voltage range

0.65 V to 3.6 V

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

•

Input voltage range

– Use the supply voltage of the device that is driving the SN74AXC2T45-Q1 device to determine the input

voltage range. For a valid logic-high, the value must exceed the high-level input voltage (V_IH) of the input

port. For a valid logic low the value must be less than the low-level input voltage (V_IL) of the input port.

Output voltage range

•

– Use the supply voltage of the device that the SN74AXC2T45-Q1 device is driving to determine the output

voltage range.

9.2.3 Application Curve

Figure 9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V)

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing

without any supply sequencing requirements such as ramp order or ramp rate.

This device is designed with various power supply sequencing methods in mind to help prevent unintended

triggering of downstream devices. For more information regarding the power up glitch performance of the AXC

family of level translators, see the Glitch Free Power Sequencing With AXC Level Translators application report.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

•

Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1

µF capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF

capacitors in parallel as bypass capacitors.

•

Use short trace lengths to avoid excessive loading.

11.2 Layout Example

Legend

Via to V_CCA

Via to V_CCB

Via to GND

Copper Traces

SN74AXC2T45DCU

0402

0.1µF

0402

0.1µF

V_CCA

V_CCB

PROC HOT

to Co ntroller

PROC HOT

fro m CPU

CATERR

to Co ntroller

CATERR

fro m CPU

GND

DIR

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

•

Texas Instruments, Implications of Slow or Floating CMOS Inputs application report

Texas Instruments, Power Sequencing for AXC Family of Devices application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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7-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PCAXC2T45QDCURQ1

ACTIVE

VSSOP

DCU

3000

TBD

Call TI

-40 to 125

SN74AXC2T45QDCURQ1

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

2FZT

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

OTHER QUALIFIED VERSIONS OF SN74AXC2T45-Q1 :

Catalog : SN74AXC2T45

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74AXC2T45QDCURQ1 VSSOP

DCU

3000

178.0

9.0

2.25

3.35

1.05

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSSOP DCU

SPQ

Length (mm) Width (mm) Height (mm)

180.0 180.0 18.0

SN74AXC2T45QDCURQ1

3000

Pack Materials-Page 2

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