SN74AXCH2T45DCUR [TI]
具有总线保持电流的 2 位 0.65V 至 3.6V AXC 双电源总线收发器 | DCU | 8 | -40 to 125;
| 型号： | SN74AXCH2T45DCUR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有总线保持电流的 2 位 0.65V 至 3.6V AXC 双电源总线收发器 | DCU | 8 | -40 to 125 总线收发器 |
| 文件： | 总41页 (文件大小：938K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN74AXCH2T45
SCES881 –FEBRUARY 2020
SN74AXCH2T45 2-Bit Bus Transceiver with Configurable Level-Shifting
and Bus-Hold Inputs
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not
recommended. If a supply is present for VCCA or
VCCB, the bus-hold circuitry always remains active
on the A or B inputs respectively, independent of the
state of the direction control pin.
1 Features
1
•
Fully configurable dual-rail design allows each
port to operate with a power supply range from
0.65 V to 3.6 V
•
•
•
Operating temperature from –40°C to +125°C
Glitch-free power supply sequencing
This device is fully specified for partial-power-down
applications using the Ioff current. The Ioff protection
circuitry ensures that no excessive current is drawn
from or to an input, output, or combined I/O that is
biased to a specific voltage while the device is
powered down.
Up to 380 Mbps support when translating from 1.8
V to 3.3 V
•
VCC isolation feature
–
If either VCC input is below 100 mV, all I/O
outputs are disabled and become high
impedance
The VCC isolation feature ensures that if either VCCA
or VCCB is less than 100 mV, both I/O ports enter a
high-impedance state by disabling their outputs.
•
•
•
Ioff supports partial-power-down mode operation
Compatible with AVC family level shifters
Latch-up performance exceeds 100 mA per JESD
78, Class II
Glitch-free power supply sequencing allows either
supply rail to be powered on or off in any order while
providing robust power sequencing performance.
•
ESD protection exceeds JESD 22
–
–
8000-V human-body model (HBM)
1000-V charged-device model (CDM)
Device Information(1)
PART NUMBER
SN74AXCH2T45DCU
SN74AXCH2T45DTM
PACKAGE
VSSOP (8)
X2SON (8)
BODY SIZE (NOM)
2.30 mm × 2.00 mm
1.35 mm x 0.80 mm
2 Applications
•
•
•
•
•
•
Enterprise and communications
Industrial
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Personal electronics
Wireless infrastructure
Building automation
Point of sale
Logic Diagram (Positive Logic)
VCCA
VCCB
DIR
A1
3 Description
The SN74AXCH2T45 is a two-bit non-inverting bus
transceiver that uses two individually configurable
power-supply rails. The device is operational with
both VCCA and VCCB supplies as low as 0.65 V. The A
port is designed to track VCCA, which accepts any
supply voltage from 0.65 V to 3.6 V. The B port is
designed to track VCCB, which also accepts any
supply voltage from 0.65 V to 3.6 V. Additionally the
SN74AXCH2T45 is compatible with a single-supply
system.
Bus-Hold
B1
B2
Bus-Hold
Bus-Hold
A2
Bus-Hold
Note: Bus-hold circuits are only present for data inputs, not control inputs
The SN74AXCH2T45 device is designed for
asynchronous communication between data buses.
The device transmits data from the A bus to the B
bus or from the B bus to the A bus, depending on the
logic level of the direction-control input (DIR). The
SN74AXCH2T45 device is designed so the control
pin (DIR) is referenced to VCCA
.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AXCH2T45
SCES881 –FEBRUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
8
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 19
8.4 Bus-Hold Data Inputs.............................................. 21
8.5 Device Functional Modes........................................ 21
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics, VCCA = 0.7 ± 0.05 V........ 8
6.7 Switching Characteristics, VCCA = 0.8 ± 0.045 V...... 9
6.8 Switching Characteristics, VCCA = 0.9 ± 0.04 V...... 10
6.9 Switching Characteristics, VCCA = 1.2 ± 0.1 V........ 11
6.10 Switching Characteristics, VCCA = 1.5 ± 0.1 V...... 12
6.11 Switching Characteristics, VCCA = 1.8 ± 0.15 V.... 13
6.12 Switching Characteristics, VCCA = 2.5 ± 0.2 V...... 14
6.13 Switching Characteristics, VCCA = 3.3 ± 0.3 V...... 15
6.14 Operating Characteristics: TA = 25°C ................... 16
Parameter Measurement Information ................ 17
7.1 Load Circuit and Voltage Waveforms ..................... 17
9
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 26
12.1 Related Documentation ....................................... 26
12.2 Receiving Notification of Documentation Updates 26
12.3 Support Resources ............................................... 26
12.4 Trademarks........................................................... 26
12.5 Electrostatic Discharge Caution............................ 26
12.6 Glossary................................................................ 26
13 Mechanical, Packaging, and Orderable
7
Information ........................................................... 27
4 Revision History
DATE
REVISION
NOTES
February 2020
*
Advance Information release.
2
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SCES881 –FEBRUARY 2020
5 Pin Configuration and Functions
DCU Package
8-Pin VSSOP
Top View
VCCA
A1
1
VCCB
B1
8
7
6
5
2
3
4
A2
B2
DIR
GND
DTM Package
8-Pin X2SON
Transparent Top View
7
6
5
1
B1
VCCA
VCCB
8
2
A1
B2
4
GND
A2
3
DIR
Pin Functions
PIN
NAME
NO.
DESCRIPTION
DCU, DTM
VCCA
A1
1
2
3
4
5
6
7
8
A-port power supply voltage. 0.65 V ≤ VCCA ≤ 3.6 V
Input/output A1. Referenced to VCCA
Input/output A2. Referenced to VCCA
Ground
.
A2
.
GND
DIR
B2
Direction Pin for both ports. Referenced to VCCA
Input/output B2. Referenced to VCCB
.
.
B1
Input/output B1. Referenced to VCCB
VCCB
B-port power supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V
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SCES881 –FEBRUARY 2020
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
MIN
MAX
S
V
V
VCCA Supply voltage A
VCCB Supply voltage B
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
4.2
4.2
4.2
4.2
4.2
4.2
4.2
I/O Ports (A Port)
I/O Ports (B Port)
Control Inputs
A Port
VI
Input Voltage(2)
V
VO
VO
Voltage applied to any output in the high-impedance or power-off state(2)
Voltage applied to any output in the high or low state(2)(3)
V
V
B Port
A Port
–0.5 VCCA + 0.2
–0.5 VCCB + 0.2
–50
B Port
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
Junction Temperature
–50
50 mA
–100
100 mA
Tj
150
150
°C
°C
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±8000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCES881 –FEBRUARY 2020
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
0.65
0.65
3.6
3.6
V
V
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCI x 0.70
VCCI x 0.70
VCCI x 0.65
1.6
Data Inputs
2
VIH
High-level input voltage
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCA x 0.70
VCCA x 0.70
VCCA x 0.65
1.6
Control Input (DIR), Referenced
to VCCA
2
VCCI x 0.30
VCCI x 0.30
VCCI x 0.35
0.7
Data Inputs
0.8
VIL
Low-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCA x 0.30
VCCA x 0.30
VCCA x 0.35
0.7
Control Input (DIR), Referenced
to VCCA
0.8
(3)
VI
Input voltage
0
0
0
3.6
V
V
Active State
Tri-State
VCCO
VO
Output voltage
3.6
Δt/Δv(2) Input transition rise and fall time
10 ns/V
125 °C
TA Operating free-air temperature
–40
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74AXCH2T45
THERMAL METRIC
DCU (VSSOP)
8 PINS
242.9
DTM (X2SON)
8 PINS
225.9
UNIT
RθJA
RθJC(top)
RθJB
YJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
96.2
131.6
153.3
141.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
38.2
12.7
YJB
152.5
140.9
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
(1) (2)
Operating free-air temperature (TA)
-40°C to 85°C -40°C to 125°C
MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
UNIT
VCCO
– 0.1
VCCO
– 0.1
IOH = -100 µA
0.7 V - 3.6 V 0.7 V - 3.6 V
IOH = -50 µA
IOH = -200 µA
IOH = -500 µA
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.55
0.58
0.65
0.85
1.05
1.2
0.55
0.58
0.65
0.85
1.05
1.2
High-level
output
voltage
VOH
VI = VIH
V
IOH = -3 mA
IOH = -6 mA
IOH = -8 mA
IOH = -9 mA
IOH = -12 mA
IOL = 100 µA
IOL = 50 µA
IOL = 200 µA
IOL = 500 µA
VI = VIL IOL = 3 mA
IOL = 6 mA
1.75
2.3
1.75
2.3
0.7 V - 3.6 V 0.7 V - 3.6 V
0.1
0.1
0.1
0.1
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.18
0.2
0.18
0.2
0.25
0.35
0.45
0.55
0.7
Low-level
output
voltage
VOL
0.25
0.35
0.45
0.55
0.7
V
IOL = 8 mA
IOL = 9 mA
IOL = 12 mA
VI = 0.20 V
VI = 0.23 V
VI = 0.26 V
VI = 0.39 V
VI = 0.49 V
VI = 0.58 V
VI = 0.7 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4
8
4
7
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
10
10
Bus-hold low
sustaining
current (Port
A or Port B)
20
20
IBHL
40
30
55
45
90
80
VI = 0.8 V
145
–4
135
–4
VI = 0.20 V
VI = 0.23 V
VI = 0.26 V
VI = 0.39 V
VI = 0.49 V
VI = 0.58 V
VI = 0.7 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
–8
–7
–10
–20
–40
–55
–90
–145
40
–10
–20
–30
–45
–80
–135
40
Bus-hold
high
sustaining
current (Port
A or Port B)
IBHH
VI = 0.8 V
0.75 V
0.84 V
0.95 V
1.3 V
1.6 V
1.95 V
2.7 V
3.6 V
0.75 V
0.84 V
0.95 V
1.3 V
1.6 V
1.95 V
2.7 V
3.6 V
50
50
65
65
Bus-hold low
overdrive
current (Port
A or Port B)
105
150
250
410
600
105
150
250
410
600
IBHLO
VI = 0 to VCC
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
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SCES881 –FEBRUARY 2020
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
-40°C to 85°C -40°C to 125°C
PARAMETER
TEST CONDITIONS
VCCA
VCCB
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
0.75 V
0.75 V
–40
–50
–40
–50
µA
µA
µA
µA
µA
µA
µA
µA
0.84 V
0.95 V
1.3 V
0.84 V
0.95 V
1.3 V
–65
–65
Bus-hold
high
–105
–150
–250
–410
–600
–105
–150
–250
–410
–600
IBHHO overdrive
current (Port
A or Port B)
VI = 0 to VCC
1.6 V
1.6 V
1.95 V
2.7 V
1.95 V
2.7 V
3.6 V
3.6 V
Control input (DIR):VI =
VCCA or GND
0.65 V- 3.6 V 0.65 V- 3.6 V
0.65 V- 3.6 V 0.65 V- 3.6 V
–0.5
–4
0.5
4
–1
–8
1
8
µA
µA
Input leakage
current
II
Data Inputs (Ax, Bx),VI =
VCCI or GND
A Port: VI or VO = 0 V -
3.6 V
0 V
0 V - 3.6 V
0 V
–8
8
–12
–12
12
Partial power
Ioff
µA
µA
down current
B Port: VI or VO = 0 V -
3.6 V
0 V - 3.6 V
–8
8
8
12
14
0.65 V- 3.6 V 0.65 V- 3.6 V
VI =
VCCI or IO = 0
GND
VCCA supply
current
ICCA
0 V
3.6 V
0 V
–2
–2
–12
–12
3.6 V
4
8
4
8
14
8
0.65 V- 3.6 V 0.65 V- 3.6 V
VI =
VCCI or IO = 0
GND
VCCB supply
current
ICCB
0 V
3.6 V
0 V
µA
µA
3.6 V
Combined
supply
current
VI =
VCCI or IO = 0
GND
ICCA
ICCB
+
0.65 V- 3.6 V 0.65 V- 3.6 V
16
23
Control Input
(DIR)
Capacitance
Ci
VI = 3.3 V or GND
3.3 V
3.3 V
3.3 V
3.3 V
3.1
7.2
3.1
7.2
pF
pF
Data I/O
VO = 1.65V DC +1 MHz
Cio
Capacitance -16 dBm sine wave
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6.6 Switching Characteristics, VCCA = 0.7 ± 0.05 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
177
177
177
177
147
147
151
151
326
326
320
320
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
117
117
155
155
147
147
110
110
326
326
257
257
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
86
86
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
51
51
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
51
51
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
57
57
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
72
72
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
108
108
82
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
129
129
147
147
87
89
85
83
82
89
85
83
82
82
147
147
41
147
147
38
147
147
42
147
147
56
147
147
108
108
326
326
233
233
DIR
DIR
DIR
DIR
tdis Disable time
ns
ns
87
41
38
42
56
326
326
223
223
326
326
194
194
326
326
190
190
326
326
192
192
326
326
200
200
ten Enable time
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6.7 Switching Characteristics, VCCA = 0.8 ± 0.045 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
155
155
117
117
101
101
143
143
256
256
255
255
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
96
96
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
64
64
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
34
34
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
28
28
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
27
27
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
29
29
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
34
34
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
96
78
52
42
41
40
40
96
78
52
42
41
40
40
101
101
103
103
256
256
196
196
101
101
79
101
101
33
101
101
27
101
101
26
101
101
28
101
101
35
DIR
DIR
DIR
DIR
tdis Disable time
ns
ns
79
33
27
26
28
35
256
256
163
163
256
256
134
134
256
256
128
128
256
256
127
127
256
256
128
128
256
256
132
132
ten
Enable time
(1)
(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.
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6.8 Switching Characteristics, VCCA = 0.9 ± 0.04 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
129
129
86
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
78
78
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
53
53
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
24
24
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
18
18
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
17
17
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
15
15
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
17
17
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
64
53
39
28
24
22
22
86
64
53
39
28
24
22
22
75
75
75
75
75
75
75
75
DIR
DIR
DIR
DIR
75
75
75
75
75
75
75
75
tdis Disable time
ns
ns
141
141
219
219
202
202
99
75
30
23
22
20
22
99
75
31
24
22
20
23
219
219
152
152
219
219
125
125
219
219
97
219
219
92
219
219
90
219
219
89
219
219
90
ten
Enable time
(1)
97
92
90
89
90
(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.
10
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SCES881 –FEBRUARY 2020
6.9 Switching Characteristics, VCCA = 1.2 ± 0.1 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
89
89
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
52
52
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
39
39
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
15
15
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
11
11
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
10
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
51
34
24
15
12
10
8
8
51
34
24
15
12
10
8
8
26
26
26
26
26
26
26
27
15
16
185
185
35
35
26
27
15
16
185
185
35
35
DIR
DIR
DIR
DIR
27
27
27
27
27
27
tdis Disable time
ns
ns
136
136
185
185
111
111
95
71
27
20
18
95
72
28
21
19
185
185
73
185
185
60
185
185
40
185
185
38
185
185
35
ten
Enable time
(1)
73
60
41
38
36
(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.
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SCES881 –FEBRUARY 2020
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6.10 Switching Characteristics, VCCA = 1.5 ± 0.1 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
85
85
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
42
42
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
28
28
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
12
12
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
51
28
18
11
9
8
6
5
51
28
18
11
9
8
6
5
18
18
18
18
18
19
19
20
180
180
27
28
18
19
17
18
180
180
26
27
18
19
13
14
180
180
24
25
18
19
13
14
180
180
23
25
DIR
DIR
DIR
DIR
19
19
19
19
tdis Disable time
ns
ns
135
135
180
180
98
94
70
26
94
71
27
180
180
55
180
180
42
180
180
30
ten
Enable time
(1)
98
55
42
31
(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.
12
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SCES881 –FEBRUARY 2020
6.11 Switching Characteristics, VCCA = 1.8 ± 0.15 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
84
84
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
41
41
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
24
24
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
10
10
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
56
27
16
8
7
5
5
56
27
16
10
16
17
25
26
178
178
26
27
8
7
6
5
16
16
16
16
17
18
19
178
178
23
24
16
17
16
17
178
178
22
23
16
17
12
13
178
178
21
22
16
17
12
13
178
178
20
22
DIR
DIR
DIR
DIR
17
17
17
tdis Disable time
ns
ns
134
134
180
180
94
93
70
93
71
178
178
52
178
178
36
ten
Enable time
(1)
94
52
36
(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.
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SCES881 –FEBRUARY 2020
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6.12 Switching Characteristics, VCCA = 2.5 ± 0.2 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
82
82
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
40
40
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
22
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
72
29
15
8
6
6
5
4
72
29
15
8
6
6
5
4
11
11
11
11
12
25
26
183
183
18
19
11
12
18
19
183
183
17
18
11
12
15
16
183
183
16
17
11
12
12
13
183
183
16
17
11
12
11
12
183
183
15
16
DIR
DIR
DIR
DIR
12
12
12
tdis Disable time
ns
ns
135
135
188
188
90
93
70
93
70
183
183
47
183
183
29
ten
Enable time
(1)
90
47
29
(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.
14
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SCES881 –FEBRUARY 2020
6.13 Switching Characteristics, VCCA = 3.3 ± 0.3 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Condtions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
82
82
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
40
40
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
22
22
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
4
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
106
106
10
34
17
8
6
5
5
4
34
17
8
6
5
5
4
10
10
10
11
25
26
222
222
17
18
10
11
17
19
222
222
15
16
10
11
15
16
222
222
15
16
10
11
11
12
222
222
14
15
10
11
11
11
222
222
14
15
DIR
DIR
DIR
DIR
11
11
11
tdis Disable time
ns
ns
135
135
222
222
90
93
70
93
70
222
222
46
222
222
28
ten
Enable time
(1)
90
46
28
(1) The enable time is a calculated value, derived using the formula shown in the Enable Times section.
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6.14 Operating Characteristics: TA = 25°C
PARAMETER
TEST CONDITIONS
VCCA
0.7 V
VCCB
0.7 V
MIN
TYP
2.3
MAX UNIT
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
2.1
2.1
2
Power Dissipation Capacitance CL = 0, RL = Open f = 1
pF
pF
pF
pF
per transceiver (A to B)
MHz, tr = tf = 1 ns
2
2.1
2.7
3.4
CpdA
11.2
11.1
11.1
11.2
11.5
12.7
16.5
20.3
11.4
11.2
11.2
11.3
11.6
12.7
16.7
20.5
2.2
Power Dissipation Capacitance CL = 0, RL = Open f = 1
per transceiver (B to A) MHz, tr = tf = 1 ns
Power Dissipation Capacitance CL = 0, RL = Open f = 1
per transceiver (A to B) MHz, tr = tf = 1 ns
CpdB
2.1
2.1
2.1
Power Dissipation Capacitance CL = 0, RL = Open f = 1
per transceiver (B to A)
MHz, tr = tf = 1 ns
2.2
2.3
2.7
3.6
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
•
•
•
f = 1 MHz
ZO = 50 Ω
dv/dt ≤ 1 ns/V
Measurement Point
2 x VCCO
Open
S1
RL
Output Pin
Under Test
GND
(1)
CL
RL
(1) CL includes probe and jig capacitance.
Figure 1. Load Circuit
Table 1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
N/A
N/A
Δt/Δv Input transition rise or fall rate
0.65 V – 3.6 V
1.1 V – 3.6 V
1 MΩ
2 kΩ
15 pF
15 pF
Open
Open
tpd Propagation (delay) time
0.65 V – 0.95
V
20 kΩ
15 pF
Open
N/A
3 V – 3.6 V
1.65 V – 2.7 V
1.1 V – 1.6 V
2 kΩ
2 kΩ
2 kΩ
15 pF
15 pF
15 pF
2 × VCCO
2 × VCCO
2 × VCCO
0.3 V
0.15 V
0.1 V
ten, tdis Enable time, disable time
0.65 V – 0.95
V
20 kΩ
15 pF
2 × VCCO
0.1 V
3 V – 3.6 V
1.65 V – 2.7 V
1.1 V – 1.6 V
2 kΩ
2 kΩ
2 kΩ
15 pF
15 pF
15 pF
GND
GND
GND
0.3 V
0.15 V
0.1 V
ten, tdis Enable time, disable time
0.65 V – 0.95
V
20 kΩ
15 pF
GND
0.1 V
(1)
VCCI
(1)
VCCI
Input A, B
100 kHz
VCCI / 2
VCCI / 2
Input A, B
500 ps/V œ 10 ns/V
0 V
VOH
0 V
VOH
(2)
tpd
tpd
(2)
Output B, A
Ensure Monotonic
Rising and Falling Edge
(2)
VOL
Output B, A
VCCI / 2
VCCI / 2
(2)
VOL
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur with
specified RL, CL, and S1
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur with
specified RL, CL, and S1
Figure 3. Input Transition Rise or Fall Rate
Figure 2. Propagation Delay
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VCCA
GND
VCCA / 2
DIR
VCCA / 2
(1)
ten
(5)
VCCO
Output A(2)
Output A(3)
VCCO / 2
VOL + VTP
(6)
VOL
tdis
(6)
VOH
VOH - VTP
VCCO / 2
GND
(1)
ten
(5)
VCCO
Output B(2)
Output B(3)
VCCO / 2
VOL + VTP
(6)
VOL
tdis
(6)
VOH
VOH - VTP
VCCO / 2
GND
(1) Illustrative purposes only. Enable Time is a calculation as described in the Application Information section.
(2) Output waveform on the condition that input is driven to a valid Logic Low.
(3) Output waveform on the condition that input is driven to a valid Logic High.
(4) VCCI is the supply pin associated with the input port.
(5) VCCO is the supply pin associated with the output port.
(6) VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 4. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN74AXCH2T45 is a 2-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins
and the DIR pin are referenced to VCCA logic levels, and Bx pins are referenced to VCCB logic levels. The A port
is able to accept I/O voltages ranging from 0.65 V to 3.6 V, while the B port can accept I/O voltages from 0.65 V
to 3.6 V. A high on DIR enables data transmission from A to B and a low on DIR enables data transmission from
B to A. See Device Functional Modes for a summary of the operation of the control logic.
8.2 Functional Block Diagram
VCCA
VCCB
DIR
A1
Bus-Hold
B1
B2
Bus-Hold
Bus-Hold
A2
Bus-Hold
Note: Bus-hold circuits are only present for data inputs, not control inputs
8.3 Feature Description
8.3.1 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff
)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the .
8.3.4 VCC Isolation
The inputs and outputs for this device enter a high-impedance state when either supply is <100mV.
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Feature Description (continued)
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Glitch-free Power Supply Sequencing
Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the
output erroneously transitions to VCC when it should be held low). Glitches of this nature can be misinterpreted
by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device
configuration of the peripheral, or even a false data initialization by the peripheral. For more information
regarding the power up glitch performance of the AXC family of level translators, see the Glitch Free Power
Sequencing With AXC Level Translators application report
8.3.7 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in Figure 5.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
Figure 5. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.8 Fully Configurable Dual-Rail Design
Both the VCCA and VCCB pins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for
translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).
8.3.9 Supports High-Speed Translation
The SN74AXCH2T45 device can support high data-rate applications. The translated signal data rate can be up
to 380 Mbps when the signal is translated from 1.8 V to 3.3 V.
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8.4 Bus-Hold Data Inputs
Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of
these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low
state. After data has been sent through a channel, the latch then maintains the previous state on the input if the
line is left floating. It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as
it may cause undefined inputs to occur which leads to excessive current consumption.
Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs
application report explains the problems associated with leaving CMOS inputs floating.
These latches remain active at all times, independent of all control signals such as direction control or output
enable.
The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.
Input
Logic
Output
Bus-Hold Latch
Figure 6. Simplified Schematic For Device With Bus-Hold Data Inputs
8.5 Device Functional Modes
Table 2. Function Table
(Each 2-Bit Section)(1)
CONTROL INPUT
Port Status
A PORT B PORT
OPERATION
DIR
L
Output (Enabled)
Input (Hi-Z)
Input (Hi-Z)
B data to A bus
A data to B bus
H
Output (Enabled)
(1) Input circuits of the data I/Os are always active.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AXCH2T45 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74AXCH2T45 device is ideal for use in
applications where a push-pull driver is connected to the data I/Os. The max data rate can be up to 380 Mbps
when device translates a signal from 1.8 V to 3.3 V.
One example application is shown in Figure 7, where the SN74AXCH2T45 device is used to translate low
voltage error signals from a CPU to a higher voltage signal to properly drive the inputs of a system controller,
thus alerting the system of any CPU errors such as overheating or other catastrophic processor errors.
9.1.1 Enable Times
Calculate the enable times for the SN74AXCH2T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
(1)
(2)
(3)
(4)
In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is
switched until an output is expected. For example, if the SN74AXCH2T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
9.2 Typical Application
2.5 V
0.7 V
0.1 µF
0.1 µF
System
Controller
CPU
VCCB
VCCA
CAT ERR
GPIO1
B1
A1
A2
SN74AXCH2T45
GND
PROC HOT
GPIO2
B2
DIR
Figure 7. Processor Error Application
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
DESIGN PARAMETERS
Input voltage range
EXAMPLE VALUES
0.65 V to 3.6 V
0.65 V to 3.6 V
Output voltage range
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
Input voltage range
–
Use the supply voltage of the device that is driving the SN74AXCH2T45 device to determine the input
voltage range. For a valid logic-high, the value must exceed the high-level input voltage (VIH) of the input
port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
•
Output voltage range
–
Use the supply voltage of the device that the SN74AXCH2T45 device is driving to determine the output
voltage range.
9.2.3 Application Curve
Figure 8. Up Translation at 2.5 MHz (0.7 V to 3.3 V)
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10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices. For more information regarding the power up glitch performance of the AXC
family of level translators, see the Glitch Free Power Sequencing With AXC Level Translators application report
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
•
Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF
capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF
capacitors in parallel as bypass capacitors.
•
Use short trace lengths to avoid excessive loading.
11.2 Layout Example
Legend
Via to VCCA
Via to VCCB
A
B
G
Via to GND
Copper Traces
SN74AXCH2T45DTM
01005
0.1µF
G
01005
0.1µF
4 mil
PROC HOT
from CPU
7
1
A
B1
VCCB
8
VCCA
B
PROC HOT
to Controller
CAT ERR
from CPU
2
6
5
A1
B2
8 mil
G
4
GND
CAT ERR
to Controller A2
G
3
DIR
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Layout Example (continued)
Legend
Via to VCCA
Via to VCCB
A
B
G
Via to GND
Copper Traces
SN74AXCH2T45DCU
0402
0.1µF
0402
0.1µF
G
G
A
B
VCCA
1
2
3
4
VCCB
8
7
6
5
PROC HOT
to Controller
PROC HOT
from CPU
A1
A2
B1
CAT ERR
to Controller
CAT ERR
from CPU
B2
GND
DIR
G
G
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12 Device and Documentation Support
12.1 Related Documentation
For related documentation see the following:
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
Texas Instruments, Power Sequencing for AXC Family of Devices application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DTM0008A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
1.4
1.3
C
0.4 MAX
SEATING PLANE
0.05 C
0.04
0.00
SYMM
(0.102) TYP
5
3
0.27
0.17
2X
4
2X
1
SYMM
0.54
2
1
6
7
4X
8
0.5
0.25
0.15
6X
PIN 1 ID
0.27
0.17
6X
0.1
C B A
C
0.05
4224755/A 01/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad(s) must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DTM0008A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.42)
6X (0.2)
(
0.22)
1
7
8
(0.27)
SYMM
(45 X 0.75)
(0.5)
4
5
3
(45 X 0.1)
(R0.05) TYP
SYMM
(0.78)
SEE SOLDER MASK
DETAILS
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.0325 MIN
ALL AROUND
0.0325 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL EDGE
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224755/A 01/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
DTM0008A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.2) TYP
4X (0.42)
(
0.22)
7
6X (0.2)
(0.411)
1
8
(0.27)
SYMM
(0.5)
4
5
3
EXPOSED
METAL
SYMM
(R0.05) TYP
(0.78)
PINS: 1,3,5,7
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4224755/A 01/2019
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74AXCH2T45DCUR
SN74AXCH2T45DTMR
ACTIVE
ACTIVE
VSSOP
X2SON
DCU
DTM
8
8
3000 RoHS & Green
5000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
22IT
1GE
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AXCH2T45DCUR VSSOP
SN74AXCH2T45DTMR X2SON
DCU
DTM
8
8
3000
5000
178.0
178.0
9.0
8.4
2.25
0.93
3.35
1.49
1.05
0.43
4.0
2.0
8.0
8.0
Q3
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AXCH2T45DCUR
SN74AXCH2T45DTMR
VSSOP
X2SON
DCU
DTM
8
8
3000
5000
180.0
205.0
180.0
200.0
18.0
33.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCU0008A
VSSOP - 0.9 mm max height
S
C
A
L
E
6
.
0
0
0
SMALL OUTLINE PACKAGE
3.2
3.0
TYP
C
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.5
8
1
2X
2.1
1.9
1.5
NOTE 3
4
5
0.25
0.17
8X
2.4
2.2
B
0.08
C A B
NOTE 3
SEE DETAIL A
0.9
0.6
0.12
GAGE PLANE
0.1
0.0
0.35
0.20
0 -6
(0.13) TYP
A
30
DETAIL A
TYPICAL
4225266/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.
www.ti.com
EXAMPLE BOARD LAYOUT
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
SEE SOLDER MASK
DETAILS
SYMM
8X (0.85)
(R0.05) TYP
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(3.1)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
OPENING
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225266/A 09/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
8X (0.85)
SYMM
(R0.05) TYP
8
1
8X (0.3)
SYMM
6X (0.5)
4
5
(3.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 25X
4225266/A 09/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DTM0008A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
1.4
1.3
C
0.4 MAX
SEATING PLANE
0.05 C
0.04
0.00
SYMM
(0.102) TYP
5
3
0.27
0.17
2X
4
2X
1
SYMM
0.54
2
1
6
7
4X
8
0.5
0.25
0.15
6X
PIN 1 ID
0.27
0.17
6X
0.1
C B A
C
0.05
4224755/B 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad(s) must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DTM0008A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.42)
6X (0.2)
(
0.22)
1
7
8
4X (0.079)
SYMM
(0.27)
(45 ) TYP
(0.5)
4
5
3
4X (0.1)
(R0.05) TYP
SYMM
(0.78)
SEE SOLDER MASK
DETAILS
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.0325 MIN
ALL AROUND
0.0325 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL EDGE
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224755/B 10/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DTM0008A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.2) TYP
4X (0.42)
(
0.22)
7
6X (0.2)
(0.411)
1
8
4X (0.079)
(0.27)
SYMM
(45 ) TYP
(0.5)
4
5
3
(R0.05) TYP
4X (0.128)
SYMM
EXPOSED
METAL
(0.78)
PINS: 1,3,5,7
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4224755/B 10/2022
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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