SN74FB2033KRCR [TI]
8-BIT TTL/BTL REGISTERED TRANSCEIVER; 8位TTL / BTL寄存收发器
| 型号： | SN74FB2033KRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT TTL/BTL REGISTERED TRANSCEIVER |
| 文件： | 总14页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
Compatible With IEEE Std 1194.1-1991
(BTL)
High-Impedance State During Power Up
and Power Down
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
Open-Collector B-Port Outputs Sink
100 mA
TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination
BIAS V
Pin Minimizes Signal Distortion
CC
During Live Insertion/Withdrawal
RC PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
AO2
AI3
AO3
AI4
GND
B2
2
3
GND
B3
GND
B4
GND
B5
GND
B6
4
5
6
AO4
LOOPBACK
AI5
7
8
9
AO5
AI6
AO6
AI7
10
11
12
13
GND
B7
GND
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
description
TheSN74FB2033Kisan8-bittransceiverfeaturingasplitinput(AI)andoutput(AO)busontheTTL-levelA port.
The common I/O, open-collector B port operates at backplane transceiver logic (BTL) signal levels. The
SN74FB2033K is specifically designed to be compatible with IEEE Std 1194.1-1991.
The logic element for data flow in each direction is configured by two mode inputs (IMODE1 and IMODE0 for
B-to-A, OMODE1 and OMODE0 for A-to-B) as a buffer, a D-type flip-flop, or a D-type latch. When configured
in the buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on
the rising edge of the appropriate clock input (CLKAB/LEAB or CLKBA/LEBA). In the latch mode, the clock
inputs serve as active-high transparent latch enables.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
description (continued)
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element (before inversion) is the B-to-A input.
The AO port-enable/-disable control is provided by OEA. When OEA is low or when V
AO port is in the high-impedance state. When OEA is high, the AO port is active (high or low logic levels).
is less than 2.5 V, the
CC
TheBportiscontrolledbyOEBandOEB. IfOEBislow, orOEBishigh, orwhenV islessthan2.5 V, theB port
CC
is inactive. If OEB is high and OEB is low, the B port is active.
BG V
and BG GND are the bias-generator reference inputs.
CC
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO port) or inactive (B port) states.
Output clamps are provided on the BTL outputs to reduce switching noise. One clamp reduces inductive ringing
effectsonV
duringalow-to-hightransition. TheotherclampsoutringingbelowtheBTLV voltage of 0.75 V.
OH
OL
Both of these clamps are active only during ac switching and do not affect the BTL outputs during steady-state
conditions.
BIAS V
establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when V
is not connected.
CC
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
0°C to 70°C QFP – RC Tube
SN74FB2033KRC
FB2033K
†
Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
Function Tables
FUNCTION
INPUTS
OEB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK
FUNCTION/MODE
OEA
L
OEB
L
X
H
L
X
X
L
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
Isolation
L
X
H
H
H
L
X
AI to B, buffer mode
AI to B, flip-flop mode
AI to B, latch mode
X
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
X
H
X
H
X
H
X
H
X
H
L
B to AO, buffer mode
B to AO, flip-flop mode
X
L
L
L
L
L
H
H
X
X
L
L
X
L
L
L
H
H
L
L
B to AO, latch mode
AI to AO, buffer mode
X
L
L
H
H
H
H
H
H
L
X
L
L
L
L
H
H
X
X
X
AI to AO, flip-flop mode
X
L
L
H
H
X
AI to AO, latch mode
AI to B, B to AO
X
H
ENABLE/DISABLE
INPUTS
OUTPUTS
OEA
L
OEB
X
OEB
X
AO
B
Hi Z
H
X
X
Active
X
L
L
Inactive (H)
Inactive (H)
Active
X
L
H
X
H
L
X
H
H
Inactive (H)
BUFFER
INPUT
OUTPUT
L
H
L
H
LATCH
INPUTS
CLK/LE DATA
OUTPUT
H
H
L
L
H
X
H
L
Q
0
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
Function Tables (Continued)
LOOPBACK
†
Q
LOOPBACK
L
B port
‡
H
Point P
†
‡
Q is the input to the B-to-A
logic element.
P is the output of the A-to-B
logic element (see functional
block diagram).
SELECT
INPUTS
SELECTED-LOGIC
ELEMENT
MODE1
MODE0
L
L
L
H
X
Buffer
Flip-flop
Latch
H
FLIP-FLOP
INPUTS
CLK/LE DATA
OUTPUT
L
↑
↑
X
L
Q
0
H
H
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
functional block diagram
23
OEB
24
OEB
21
OMODE1
20
OMODE0
47
CLKAB/LEAB
Transceiver
1D
C1
40
50
B1
AI1
P
1D
C1
46
IMODE1
45
IMODE0
19
CLKBA/LEBA
1D
C1
51
Q
AO1
1D
C1
43
OEA
One of Eight Channels
7
LOOPBACK
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Voltage range applied to any B output in the disabled or power-off state, V . . . . . . . . . . . . . . –0.5 V to 3.5 V
Voltage range applied to any output in the high state, V : A port . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
O
CC
Input voltage range, V : Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V
Input clamp current, I : Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA
IK
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Current applied to any single output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN NOM
MAX
5.25
5.5
UNIT
V
V
, BG V
Supply voltage
Supply voltage
4.75
4.5
5
5
CC
BIAS V
CC
V
CC
B port
1.62
2
2.3
V
High-level input voltage
V
IH
Except B port
B port
0.75
1.47
0.8
–3
V
IL
Low-level input voltage
High-level output current
Low-level output current
V
Except B port
AO port
I
I
mA
mA
OH
AO port
24
OL
B port
100
10
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
Except B port
ns/V
T
A
0
70
°C
NOTE 2: To ensure proper device operation, all unused inputs must be terminated as follows: A and control inputs to V (5 V) or GND, and
CC
B inputs to GND only. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
B port
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
–0.5
UNIT
V
V
V
= 4.75 V,
CC
CC
CC
I
V
IK
V
Except B port
= 4.75 V,
I = –40 mA
I
= 4.75 V to 5.25 V,
I
I
I
I
I
I
I
= –10 µA
= –3 mA
= –32 mA
= 20 mA
= 55 mA
= 100 mA
= 4 mA
V
–1.1
OH
OH
OH
OL
OL
OL
OL
CC
V
OH
AO port
2.5
2
2.85
0.33
3.4
V
V
V
CC
V
CC
V
CC
= 4.75 V
= 4.75 V
= 4.75 V
0.5
0.8
1.1
AO port
B port
V
OL
0.75
0.5
I
I
Except B port
Except B port
V
V
V
V
V
V
V
V
V
V
V
V
= 0,
V = 5.25 V
100
50
µA
µA
I
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
= 5.25 V,
V = 2.7 V
I
IH
IL
‡
B port
= 0 to 5.25 V,
= 5.25 V,
V = 2.1 V
I
100
–50
Except B port
V = 0.5 V
I
I
µA
‡
B port
B port
= 5.25 V,
V = 0.75 V
I
–100
100
50
I
I
I
I
I
I
I
= 0 to 5.25 V,
= 2.1 V to 5.25 V,
= 2.1 V to 5.25 V,
= 0 to 2.1 V,
= 2.1 V to 0,
= 5.25 V,
V
O
V
O
V
O
V
O
V
O
V
O
= 2.1 V
µA
µA
µA
µA
µA
mA
mA
pF
OH
AO port
= 2.7 V
OZH
OZL
AO port
= 0.5 V
–50
50
A port
= 0.5 V to 2.7 V
= 0.5 V to 2.7 V
= 0
OZPU
OZPD
A port
–50
–150
70
§
AO port
–40
–80
45
5
OS
All outputs on
AI port and control inputs
AO port
= 5.25 V,
I
O
= 0
CC
C
C
V = 0.5 V or 2.5 V
I
i
V
V
V
= 0.5 V or 2.5 V
= 0 to 4.75 V
5
pF
o
O
6
6
B port
CC
CC
pF
C
io
per IEEE Std 1194.1-1991
= 4.75 V to 5.25 V
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
= 5 V, TA = 25°C
CC
IH IL
live-insertion characteristics over recommended operating free-air temperature range (see Note 3)
PARAMETER
TEST CONDITIONS
MIN
MAX
1.2
10
UNIT
mA
µA
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0 to 4.75 V,
= 4.75 V to 5.25 V,
= 0,
V
V
= 0 to 2 V,
= 0 to 2 V,
BIAS V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
B
CC
I
(BIAS V )
CC
CC
BIAS V
B
CC
V
B port
B port
BIAS V
CC
= 5 V
1.62
2.1
V
O
= 0,
V
B
= 1 V,
V (BIAS V ) = 4.75 V to 5.25 V
CC
–1
I
I
O
= 0 to 5.25 V,
= 0 to 2.2 V,
OEB = 0 to 0.8 V
OEB = 0 to 5 V
100
100
µA
NOTE 3: Power-up sequence is GND, BIAS V , V
CC CC
.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
150
0
3.3
2.7
0.7
150
MHz
ns
clock
Pulse duration, CLKAB/LEAB or CLKBA/LEBA
Setup time, data before CLKAB/LEAB or CLKBA/LEBA↑
Hold time, data after CLKAB/LEAB or CLKBA/LEBA↑
3.3
2.7
0.7
w
ns
su
h
ns
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
V
T
= 5 V,
= 25°C
CC
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
150
2.8
2.5
3.1
3.1
2.8
2.6
2.2
2.5
2.7
2.4
2.5
2.5
1.6
2.3
1.7
1.2
5.2
3.8
1.7
1.8
2.9
3
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
150
2.8
2.5
2.2
2.6
2.8
2.6
2.2
2.5
2.7
2.4
2.5
2.5
1.6
2.3
1.7
1.2
3.7
3.4
1.7
1.8
2.9
3
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
r
5.1
4.2
4.3
4.2
5.1
4.2
4.3
4.2
5.1
4.2
4.8
4.3
3.6
4.3
4
6.8
5.7
5.1
5.1
6.8
5.7
6
8.1
6.1
6.6
6
AI (through mode)
B
AO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B (through mode)
AI (transparent)
8.1
6.1
6.6
6
B
AO
B (transparent)
OEB
5.6
6.8
5.7
6.4
5.9
5.1
5.7
5.5
4.4
7.8
7.1
5.5
5.1
8.4
7.5
5.8
5.7
7.3
6.3
5.6
5.7
3.8
3.8
4.8
3.8
8.3
6.1
7.7
6.4
5.6
6
B
OEB
OEA
B
AO
5.9
4.7
9.9
7.7
5.9
5.5
10
8.3
6.4
5.9
8.2
6.4
6.1
5.9
4
OEA
CLKAB/LEAB
CLKBA/LEBA
OMODE
AO
2.9
6.5
5.4
3.8
3.6
6.6
5.7
4.1
4.2
5.2
4.8
3.9
4.3
2.5
2.5
3.4
2.5
B
AO
B
1.4
1.9
2
1.4
1.9
2
IMODE
AO
LOOPBACK
AI
AO
AO
2.6
1.7
2.2
1.8
1.7
2.5
1.5
2.6
1.7
2.2
1.7
1.5
2
Rise time, 1.3 V to 1.8 V, B port
Fall time, 1.8 V to 1.3 V, B port
Rise time, 10% to 90%, AO
Fall time, 90% to 10%, AO
4
f
5
r
ns
ns
1
5
f
1
B-port input pulse rejection
output-voltage characteristics
PARAMETER
TEST CONDITIONS
See Figure 1
MIN
MAX
UNIT
V
OHP
V
OHV
V
OLV
Peak output voltage during turnoff of 100 mA into 40 nH
Minimum output voltage during turnoff of 100 mA into 40 nH
Minimum output voltage during high-to-low switch
B port
3
V
V
V
B port
B port
See Figure 1
1.62
0.3
I
= –50 mA
OL
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
2.1 V
9 Ω
40 nH
From Output
Under Test
30 pF
Figure 1. Load Circuit for V
and V
OHV
OHP
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
2.1 V
9 Ω
7 V
Open
TEST
S1
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
t
/t
Open
7 V
PLH PHL
/t
t
PLZ PZL
/t
C
= 50 pF
C = 30 pF
L
(see Note A)
L
t
Open
PHZ PZH
500 Ω
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
3 V
0 V
t
w
Timing Input
1.5 V
3 V
Input
1.5 V
1.5 V
0 V
t
t
h
su
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
0 V
Data Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
1.5 V
1.5 V
3 V
0 V
t
t
PLZ
PZL
Input
1.5 V
1.5 V
Output
Waveform 1
S1 at 7 V
3.5 V
1.5 V
V
V
+ 0.3 V
t
t
PLH
OL
PHL
(see Note B)
V
OL
OH
V
V
OH
t
t
PHZ
PZH
Output
1.55 V
1.55 V
Output
Waveform 2
S1 at Open
(see Note B)
OL
V
– 0.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A TO B)
1.5 V
OH
≈ 0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES (A PORT)
2.1 V
1 V
Input
1.55 V
1.55 V
t
t
PLH
PHL
V
OHP
2.1 V
1 V
V
V
OHV
OH
Output
1.5 V
1.5 V
V
OLV
VOLTAGE WAVEFORMS
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B TO A)
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns,
O
r
t ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
f
O
r
f
Figure 2. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
QFP
QFP
Drawing
SN74FB2033KRC
SN74FB2033KRCR
ACTIVE
ACTIVE
RC
52
52
96
TBD
TBD
CU SNPB
CU SNPB
Level-2-240C-1YR
Level-2-240C-1YR
RC
500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MQFP003 – OCTOBER 1994
RC (S-PQFP-G52)
PLASTIC QUAD FLATPACK
0,38
0,22
M
0,13
0,65
39
27
40
26
52
14
0,16 NOM
1
13
7,80 TYP
10,20
SQ
9,80
Gage Plane
13,45
SQ
12,95
0,25
0,05 MIN
0°–7°
2,20
1,80
1,03
0,73
Seating Plane
0,10
2,45 MAX
4040151/ B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
1
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