SN74SSTL16847DGGR [TI]
SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64;
| 型号： | SN74SSTL16847DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64 输出元件 |
| 文件： | 总6页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MAY 1998
DGG PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Supports SSTL_3 Signal Inputs and
Outputs
Y1
Y2
GND
Y3
A1
A2
GND
A3
A4
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
Flow-Through Architecture Optimizes PCB
Layout
3
4
Meets SSTL_3 Class I and Class II
Specifications
Y4
5
V
V
6
DDQ
Y5
CC
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
A5
A6
GND
A7
A8
7
Y6
GND
Y7
8
9
Latch-Up Performance Exceeds 250 mA Per
JESD 17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Y8
V
V
DDQ
Y9
CC
Packaged in Plastic Thin Shrink
Small-Outline Package
A9
Y10
GND
OE
A10
GND
NC
description
This 20-bit buffer is designed for 3-V to 3.6-V V
operation and SSTL_3 input levels.
CC
V
NC
REF
GND
GND
A11
A12
Y11
Y12
Data flow from A to Y is controlled by the
output-enable (OE). When OE is high, the outputs
are in the high-impedance state.
V
V
DDQ
Y13
CC
A13
A14
GND
A15
A16
To ensure the high-impedance state during power
up or power down, OE should be tied to V
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
Y14
GND
Y15
CC
Y16
V
V
DDQ
Y17
CC
The SN74SSTL16847 is characterized for
operation from 0°C to 70°C.
A17
A18
GND
A19
A20
Y18
GND
Y19
Y20
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MAY 1998
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
H
X
Z
logic diagram (positive logic)
16
OE
64
1
A1
Y1
To 19 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
DDQ
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V , V
Package thermal impedance,
Storage temperature range, T
O
DDQ
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
(see Note 3): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
CC DDQ
JA
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current will flow only when the output is in the high state and V > V
.
DDQ
O
3. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MAY 1998
recommended operating conditions (see Note 4)
MIN
NOM
MAX
3.6
UNIT
V
V
V
V
V
V
V
V
V
V
Supply voltage
V
CC
DDQ
REF
TT
I
DDQ
3
Output supply voltage
3.6
V
Reference voltage (V
Termination voltage
Input voltage
= 0.45 × V
)
DDQ
1.3
1.5
1.7
V
REF
V
–50mV
0
V
V
+50mV
V
REF
REF
REF
V
V
CC
AC high-level input voltage
AC low-level input voltage
All inputs
All inputs
All inputs
All inputs
V
+400mV
REF
V
IH
V
REF
–400mV
V
IL
DC high-level input voltage
DC low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
+200mV
REF
V
IH
V
REF
–200mV
–20
20
V
IL
I
OH
OL
mA
I
T
A
0
70
C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
IK
I = –18 mA
I
3 V
–1.2
V
I
I
I
I
I
I
= –100 µA
= –16 mA
= –20 mA
= 100 µA
= 16 mA
3 V to 3.6 V
V
–0.2
OH
OH
OH
OL
OL
OL
CC
2.2
2.1
V
V
V
OH
3 V
3 V to 3.6 V
3 V
0.2
0.5
V
OL
= 20 mA
0.55
±5
V = 2.1 V or 0.9 V,
V
= 1.3 V or 1.7 V
µA
µA
µA
mA
Data inputs, OE
I
REF
I
I
3.6 V
V
REF
V
= 1.3 V or 1.7 V
±150
±10
90
REF
= 0.9 V or 2.1 V
O
I
I
V
3.6 V
3.6 V
OZ
V = 2.1 V or 0.9 V,
I
O
= 0
CC
I
Control inputs
A port
2
2.5
3.5
C
V = 2.1 V or 0.9 V
3.3 V
3.3 V
pF
pF
i
I
C
Y port
V
O
= 2.1 V or 0.9 V
o
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MAY 1998
switching characteristics over recommended operating free-air temperature range,
Class I, V
= V = V
X 0.45 and C = 10 pF (unless otherwise noted) (see Figure 1)
REF
TT
DDQ L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
t
t
t
A
Y
Y
Y
1.5
1.5
1.6
3
4
ns
ns
ns
pd
en
dis
OE
OE
4.9
switching characteristics over recommended operating free-air temperature range,
Class II, V = V = V X 0.45 and C = 30 pF (unless otherwise noted) (see Figure 1)
REF
TT
DDQ
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
t
t
t
A
Y
Y
Y
1.5
1.5
1.5
3
4.1
4.8
ns
ns
ns
pd
en
dis
OE
OE
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16847
20-BIT SSTL_3 INTERFACE BUFFER
WITH 3-STATE OUTPUTS
SCBS709A – OCTOBER 1997 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
V
TT
25 Ω = SSTL_3 Class II
50 Ω = SSTL_3 Class I
Test
Point
25 Ω
C
= 10 pF or 30 pF
(see Note A)
L
LOAD CIRCUIT
‡
V
V
IH
Timing
Input
t
w
†
V
REF
§
‡
§
IL
V
IH
†
†
Input
V
REF
V
REF
t
t
h
su
V
IL
‡
V
V
IH
Data
Input
†
†
V
REF
V
REF
VOLTAGE WAVEFORMS
PULSE DURATION
§
IL
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
‡
V
IH
Output
Control
†
†
V
REF
V
REF
§
V
IL
t
PZL
‡
V
IH
t
PLZ
†
†
Input
Output
Waveform 1
(see Note B)
V
V
REF
REF
V
V
TT
§
§
§
V
IL
V
IL
V
IL
t
PLH
OL
t
PHL
t
PHZ
t
PZH
V
V
OH
Output
Waveform 2
(see Note B)
V
V
OH
†
†
Output
V
REF
V
REF
‡
‡
V
IH
V
IH
OL
TT
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
†
‡
§
V
V
V
= 0.45 V
REF
IH
IL
DDQ
= V
+400mV (AC voltage levels)
REF
–400mV (AC voltage levels)
= V
REF
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1.25 ns/V,
O
r
t ≤ 1.25 ns/V.
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
H.
V
= V
and t
and t
= V
X 0.45
TT
REF
DDQ
t
t
t
are the same as t
are the same as t
are the same as t .
pd
.
dis
en
PLZ
PZL
PLH
PHZ
PZH
.
and t
PHL
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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