SN75DP149RSBT [TI]
工作温度为 0°C 至 70°C 的 3.4Gbps DP++ 1.1 至 HDMI 1.4b 重定时器 | RSB | 40 | 0 to 70;型号: | SN75DP149RSBT |
厂家: | TEXAS INSTRUMENTS |
描述: | 工作温度为 0°C 至 70°C 的 3.4Gbps DP++ 1.1 至 HDMI 1.4b 重定时器 | RSB | 40 | 0 to 70 |
文件: | 总57页 (文件大小:3227K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
SNx5DP149 3.4-Gbps DP++ 到 HDMI 重定时器
1 特性
3 说明
1
•
DisplayPort™支持高达 3.4Gbps 数据速率的物理层
SNx5DP149 器件是一款双模[1] DisplayPort 转最小化
输入端口到 TMDS 物理层输出端口
支持 DisplayPort 双模标准版本 1.1
支持 HDMI1.4b 变送器电气参数
传输差分信号 (TMDS) 重定时器,支持数字视频接口
(DVI) 1.0 以及高清多媒体接口 (HDMI) 1.4b 输出信
号。SNx5DP149 器件通过 DDC 链路支持双模标准版
本 1.1 的 1 类和 2 类应用。SNx5DP149 器件的每条
数据信道支持的数据速率高达 3.4Gbps,可支持超高
清 (4K × 2K/30Hz) 8 位彩色高分辨率视频和 1080p 16
位色深的彩色 HDTV (1920 × 1080/60Hz)。
•
•
•
集成了 TMDS 电平转换器和时钟和数据恢复
(CDR) 功能
•
•
•
自适应接收器均衡器和可编程固定均衡器
可选去加重功能
低功耗典型值
SNx5DP149 器件在数据速率低于 1Gbps 时可自动配
置为转接驱动器,在超过该速率后可自动配置为重定时
器。此特性可通过 I2C[4] 编程来关闭。
–
–
390mW(3.4Gbps 重定时器)
10mW(关断状态)
•
•
•
•
•
集成了 DVI 和 HDMI 标识识别双模 DP 2 类功能
有源 I2C[4] 缓冲器
为确保信号完整性,SNx5DP149 器件实现了多种 功
能。SNx5DP149 接收器支持自适应和固定均衡,以便
消除电路板走线或电缆因带宽受限而引起的码间串扰
(ISI) 抖动或损耗。用作重定时器时,内置的时钟和数
据恢复 (CDR) 功能可清除输入端高频和视频源的随机
抖动。发送器提供多种 功能 不仅有利于达到合规要
求,还能够减少系统设计问题,例如去加重功能可补偿
驱动长电缆或高损耗电路板走线时的衰减。
主信道输入交换
I2C[4] 和引脚设置可编程
工业温度范围:
–40°C 至 85°C (SN65DP149)
•
•
扩展商业温度范围:
0°C 至 85°C (SN75DP149)
40 引脚、0.4mm 间距、5mm × 5mm WQFN 封装
SNx5DP149 器件还包含使用 Vsadj 引脚外部电阻实现
的 TMDS 输出幅值调节功能、源端选择功能和输出转
换率控制功能。器件的运行和配置可通过引脚设置或
I2C[4] 编程。
2 应用
•
•
•
•
•
•
•
•
个人计算机
下一代适配器软件狗
台式计算机
笔记本电脑
扩展基座
SNx5DP149 器件实现了多种方法来进行电源管理和有
功功率降低。
器件信息(1)
HDTV
器件型号
SN65DP149
SN75DP149
封装
封装尺寸(标称值)
独立显卡
WQFN (40)
5.00mm x 5.00mm
平板电脑
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
DP149 母板应用结构
DP149 软件狗应用结构
GPU
DP1x9
GPU
Dongle
DP++
HDMI
Monitor
Dual Mode DisplayPort
HDMI/DVI
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEL2
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
目录
9.1 Overview ................................................................. 22
9.2 Functional Block Diagram ....................................... 22
9.3 Feature Description................................................. 23
9.4 Device Functional Modes........................................ 28
9.5 Register Maps......................................................... 30
10 Application and Implementation........................ 38
10.1 Application Information.......................................... 38
10.2 Typical Application ................................................ 42
10.3 System Example ................................................... 44
11 Power Supply Recommendations ..................... 45
11.1 Power Management.............................................. 45
12 Layout................................................................... 45
12.1 Layout Guidelines ................................................. 45
12.2 Layout Example .................................................... 47
12.3 Thermal Considerations........................................ 47
13 器件和文档支持 ..................................................... 47
13.1 相关链接................................................................ 47
13.2 文档支持................................................................ 48
13.3 接收文档更新通知 ................................................. 48
13.4 社区资源................................................................ 48
13.5 商标....................................................................... 48
13.6 静电放电警告......................................................... 48
13.7 Glossary................................................................ 48
14 机械、封装和可订购信息....................................... 48
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 8
7.5 Power Supply Electrical Characteristics ................... 9
7.6 Differential Input Electrical Characteristics ............. 10
7.7 HDMI and DVI TMDS Output Electrical
Characteristics ......................................................... 11
7.8 DDC, and I2C Electrical Characteristics.................. 12
7.9 HPD Electrical Characteristics ................................ 12
7.10 HDMI and DVI Main Link Switching
Characteristics ......................................................... 13
7.11 HPD Switching Characteristics ............................. 13
7.12 DDC and I2C Switching Characteristics................ 14
7.13 Typical Characteristics.......................................... 15
Parameter Measurement Information ................ 15
Detailed Description ............................................ 22
8
9
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision B (April 2016) to Revision C
Page
•
•
Recommended Operating Conditions, Changed the CONTROL PINS section ..................................................................... 8
Changed the DDC, and I2C Electrical Characteristics table................................................................................................. 12
Changes from Revision A (December 2015) to Revision B
Page
•
•
•
•
•
Added "Low-level input voltage at OE" to VIL in the Recommended Operating Conditions table.......................................... 8
Added OE to VIH "High-level input voltage" in the Recommended Operating Conditions table ............................................ 8
Changed 图 21 .................................................................................................................................................................... 23
Deleted the VDD_ramp and VCC_ramp MIN values in 表 1 ............................................................................................... 24
Changed text "through the I2C interface" To: "through the I2C access on the DDC interface" in DDC Functional
Description............................................................................................................................................................................ 29
•
•
•
Changed the HDMI and DVI value for 1Ah 表 3 ................................................................................................................. 30
Added Note to 11–400-kbps in 表 7 .................................................................................................................................... 34
Changed the note in the DEV_FUNC_MODE section of 表 7.............................................................................................. 34
2
版权 © 2015–2016, Texas Instruments Incorporated
SN65DP149, SN75DP149
www.ti.com.cn
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
Changes from Original (September 2015) to Revision A
Page
•
•
•
Added new table note for VIL, VIM, and VIH ............................................................................................................................ 8
Changed VSADJ Resistor Value from 7.06k to 6.5K ............................................................................................................ 9
Removed AUX column ........................................................................................................................................................ 45
版权 © 2015–2016, Texas Instruments Incorporated
3
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
5 说明 (续)
SNx5DP149 接收器采用40 引脚 RSB 封装,支持空间受限的 应用;。
SN65DP149 器件的特性适用于 –40°C 至 85°C 的工业运行温度范围。
SN75DP149 器件的特性适用于 0°C 至 85°C 的扩展商业运行温度范围。
6 Pin Configuration and Functions
RSB Package
40-Pin WQFN
Top View
39
38
37
36
35
34
33
32
31
40
30
29
28
27
26
25
OUT_D2p
OUT_D2n
HPD_SNK
OUT_D1p
IN_D2p
IN_D2n
1
2
3
4
5
6
7
8
HPD_SRC
IN_D1p
IN_D1n
OUT_D1n
OUT_D0p
OUT_D0n
IN_D0p
IN_D0n
I2C_EN/PIN
IN_CLKp
Db5
HDMI_SEL/A1
OUT_CLKp
OUT_CLKn
9
IN_CLKn
Pin Functions
PIN
SIGNAL NAME
(1)
I/O
DESCRIPTION
NO.
MAIN LINK INPUT PINS (FAIL SAFE)
IN_D2p
IN_D2n
1
2
I
I
I
Channel 2 differential input
Channel 1 differential input
Channel 0 differential input
IN_D1p
IN_D1n
4
5
IN_D0p
IN_D0n
6
7
(1) (H) Logic high (pin strapped to VCC through 65-kΩ resistor); (L) logic low (pin strapped to GND through 65-kΩ resistor); (for mid-level,
no connect)
4
Copyright © 2015–2016, Texas Instruments Incorporated
SN65DP149, SN75DP149
www.ti.com.cn
SIGNAL NAME
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
Pin Functions (continued)
PIN
(1)
I/O
DESCRIPTION
NO.
IN_CLKp
IN_CLKn
9
10
I
Clock differential input
Copyright © 2015–2016, Texas Instruments Incorporated
5
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
Pin Functions (continued)
PIN
SIGNAL NAME
MAIN LINK OUTPUT PINS (FAIL SAFE)
(1)
I/O
DESCRIPTION
NO.
OUT_D2n
OUT_D2p
29
30
O
O
O
O
TMDS data 2 differential output
TMDS data 1 differential output
TMDS data 0 differential output
TMDS data clock differential output
OUT_D1n
OUT_D1p
26
27
OUT_D0n
OUT_D0p
24
25
OUT_CLKn
OUT_CLKp
21
22
HOT PLUG DETECT PINS
HPD_SRC
3
O
Hot plug detect output
HPD_SNK
28
I (Failsafe) Hot plug detect input
DDC DATA PINS
SDA_SRC
SCL_SRC
39
38
I/O
(Failsafe)
Source side TMDS port bidirectional DDC data line
SDA_SNK
SCL_SNK
33
32
I/O
(Failsafe)
Sink side TMDS port bidirectional DDC data lines
CONTROL PINS
Operation enable/reset pin
OE = L: Power-down mode
OE = H: Normal operation
OE
36
34
16
I
Internal weak pullup: Resets device when transitions from H to L
Slew rate control when I2C_EN/PIN = Low. SLEW_CTL = H, fastest data rate (default)
SLEW_CTL = L, 5-ps slow
I
3
SLEW_CTL
PRE_SEL
SLEW_CTL = No Connect, 10-ps slow
level (1)
When I2C_EN/PIN = High Slew rate is controlled through I2C[4]
PRE_SEL = L: - 2-dB de-emphasis
PRE_SEL = No Connect: 0-dB
I
3
PRE_SEL = H: Reserved
level (1)
Note: (3 level for pin strap programming, but 2 level when I2C[4] address)
Input Receive Equalization pin strap when I2C_EN/PIN = Low
EQ_SEL = L: Fixed EQ at 7.5-dB
I
3
EQ_SEL = No Connect: Adaptive EQ
EQ_SEL = H: Fixed at 14-dB
When I2C_EN/PIN = High
EQ_SEL/A0
17
level (1)
Address bit 1
Note: (3 level for pin strap programming but 2 level when I2C[4] address)
I2C_EN/PIN = High; puts device into I2C control mode
I2C_EN/PIN = Low; puts device into pin strap mode
I2C clock signal
I2C_EN/PIN
SCL_CTL
8
I
I
13
Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be
changed by I2C
I2C data signal
SDA_CTL
Vsadj
14
18
I/0
I
Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be
changed by I2C
TMDS-compliant voltage swing control nominal resistor to GND
HDMI_SEL when I2C_EN/PIN = Low
HDMI_SEL = High: Device configured for DVI
HDMI_SEL = Low: Device configured for HDMI (Adaptor ID block is readable through I2C
When I2C_EN/PIN = High
HDMI_SEL/A1
23
I
Address bit 2
Note: Weak internal pull down
SUPPLY AND GROUND PINS
VCC
11, 37
P
P
3.3-V power supply
1.1-V power supply
12, 19, 20, 31,
40
VDD
6
Copyright © 2015–2016, Texas Instruments Incorporated
SN65DP149, SN75DP149
www.ti.com.cn
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
Pin Functions (continued)
PIN
(1)
I/O
DESCRIPTION
SIGNAL NAME
NO.
15, 35,
Thermal Pad
GND
—
Ground
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)(2)
MIN
–0.3
–0.3
MAX
4
UNIT
VCC
Supply voltage(3)
VDD
V
V
V
V
1.4
1.56
4
Main link input (IN_Dx AC-coupled mode)
TMDS outputs ( OUT_Dx)
–0.3
–0.3
–0.3
Voltage
HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, HDMI_SEL/A1, EQ_SEL/A0,
I2C_EN/PIN, SLEW_CTL, SDA_SRC, SCL_SRC
4
6
V
V
HPD_SNK, SDA_SNK, SCL_SNK
Continuous power dissipation
Storage temperature, Tstg
See Thermal Information
–65 150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2015–2016, Texas Instruments Incorporated
7
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
GENERAL PARAMETERS
VCC
3
3.3
1.1
3.6
1.27
93.5
85
Supply voltage
VDD
V
1.00
TCASE
Case temperature for RSB package
SN75DP149
SN65DP149
°C
°C
0
TA
Operating free-air temperature
–40
85
MAIN LINK DIFFERENTIAL PINS
VID_PP
Peak-to-peak input differential voltage
75
0
1200
2
mv
V
VIC
Input common mode voltage
AC coupling capacitance
Data rate
CAC
75
100
6.5
200
5
nF
dR
0.25
Gbps
kΩ
Vsadj
TMDS-compliant swing voltage bias resistor
CONTROL PINS
VI-DC
DC input voltage
–0.3
3.6
0.8
0.3
1.4
V
V
Low-level input voltage at OE
(1)
VIL
Low-level input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, SWAP/POL
No connect input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, SWAP/POL
High-level input voltage at SLEW_CTL, OE(2) , PRE_SEL, EQ_SEL/A0, SWAP/POL
Low-level output voltage
(1)
VIM
1
1.2
V
V
(1)
VIH
2.6
VOL
VOH
IIH
0.4
V
High-level output voltage
2.4
–30
–10
–50
V
High-level input current
30
10
µA
µA
mA
µA
kΩ
IIL
Low-level input current
IOS
Short circuit output current
50
IOZ
High impedance output current
10
ROEPU
Pullup resistance on OE pin
150
250
(1) These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the
internal bias to the proper voltage level which will not match the values shown here.
(2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup
resistor will set OE pin properly, but may have a different value than shown due to internal biasing.
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
SNx5DP149
THERMAL METRIC(1)
RSB (WQFN)
UNIT
40 PINS
37.3
9.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-board thermal resistance (High-K board(2)
)
Junction-to-case (top) thermal resistance (High-K board(2)
Junction-to-case (bottom) thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJB
RθJC(top)
RθJC(bot)
ψJT
)
23.1
3.2
0.3
ψJB
Junction-to-case (bottom) thermal resistance
3.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Test conditions for ΨJB and ΨJT are clarified in TI document Semiconductor and IC Package Thermal Metrics.
8
Copyright © 2015–2016, Texas Instruments Incorporated
SN65DP149, SN75DP149
www.ti.com.cn
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
7.5 Power Supply Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
OE = H, HDMI_SEL = L, VCC = 3.3/3.6-V, VDD
=
1.1/1.27-V, VSadj = 6.5-kΩ
IN_Dx: VID_PP = 1200-mV, 3.4-Gbps TMDS pattern
AUX: VI = 3.3-V
Device power dissipation
(retimer mode)
PD1
390
510
mW
I2C_EN/PIN = L, PRE_SEL= H, IN_EQ_CTL= H,
SDA_CTL/CLK_CTL = 0-V
OE = H, HDMI_SEL = L, VCC = 3.3/3.6-V, VDD
=
1.1/1.27-V, VSadj = 6.5-kΩ
IN_Dx: VID_PP = 1200-mV, 3.4-Gbps TMDS pattern
AUX: VI = 3.3-V
I2C_EN/PIN = L, PRE_SEL= H, IN_EQ_CTL= H,
SDA_CTL/CLK_CTL = 0-V
Device power dissipation
(redriver mode)
PD2
225
5
350
15
mW
mW
mA
Device power with shut down
OE = L
OE = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, VSadj =
7.06 kΩ
PSD1
OE = H, HDMI_SEL = L, VCC = 3.3/3.6-V, VDD
=
1.1/1.27-V, VSadj = 6.5-kΩ
IN_Dx: VID_PP = 1200-mV, 3.4-Gbps TMDS pattern
AUX: VI = 3.3-V, 100-kHz PRBS
VDD Supply current (TMDS 3.4-
Gpbs retimer mode)
IDD1
250
300
I2C_EN/PIN = L, PRE_SEL = H, IN_EQ_CTL = H,
SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H
OE = H, HDMI_SEL = L, VCC = 3.3/3.6-V, VDD
=
1.1/1.27-V, VSadj = 6.5-kΩ
IN_Dx: VID_PP = 1200-mV, 3.4-Gbps TMDS pattern
AUX: VI = 3.3-V, 100-kHz PRBS
I2C_EN/PIN = L, PRE_SEL = H, IN_EQ_CTL = H,
SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H
VCC Supply current (TMDS 3.4-
Gpbs retimer mode)
ICC1
IDD2
ICC2
35
170
8
50
200
20
mA
mA
mA
OE = H, HDMI_SEL = L, VCC = 3.3/3.6-V, VDD
=
1.1/1.27-V, VSadj = 6.5-kΩ
IN_Dx: VID_PP = 1200-mV, 3.4-Gbps TMDS pattern
AUX: VI = 3.3-V, 100-kHz PRBS
I2C_EN/PIN = L, PRE_SEL = H, IN_EQ_CTL = H,
SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H
VDD Supply current (TMDS 3.4-
Gpbs redriver mode)
OE = H, HDMI_SEL = L, VCC = 3.3/3.6-V, VDD
=
1.1/1.27-V, VSadj = 6.5-kΩ
IN_Dx: VID_PP = 1200-mV, 3.4-Gbps TMDS pattern
AUX: VI = 3.3-V, 100-kHz PRBS
VCC Supply current (TMDS 3.4-
Gpbs redriver mode)
I2C_EN/PIN = L, PRE_SEL = H, IN_EQ_CTL = H,
SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H
OE = L, VCC = 3.3/3.6-V, VDD = 1.1/1.27-V, VSadj =
6.5-kΩ
ISD1
ISD1
VDD Shutdown current
VCC Shutdown current
3
2
10.5
5
mA
mA
OE = L, VCC = 3.3/3.6-V, VDD = 1.1/1.27-V, VSadj =
6.5-kΩ
(1) The typical rating is simulated at 3.3-V VCC and 1.1-V VDD and at 27°C temperature unless otherwise noted
Copyright © 2015–2016, Texas Instruments Incorporated
9
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
7.6 Differential Input Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.25
25
TYP
MAX UNIT
DR_RX_DATA Ddata lanes data rate
3.4 Gbps
DR_RX_CLK
tRX_DUTY
tCLK_JIT
Clock lanes clock rate
Input clock duty circle
Input clock jitter tolerance
Input data jitter tolerance
340
60%
0.3
MHz
40%
50%
Tbit
ps
tDATA_JIT
Test the TTP2, see 图 10
150
Test at TTP2 when DR = 1.6-Gbps, see 图
10
TRX_INTRA
TRX_INTER
EQH(D)
Input intra-pair skew tolerance
Input inter-pair skew tolerance
112
ps
ns
dB
1.8
Fixed EQ gain for data lane
IN_D(0,1,2)n/p
EQ_SEL/A0 = H; Fixed EQ gain,
test at 3.4-Gbps
14
Fixed EQ gain for data lane
IN_D(0,1,2)n/p
EQ_SEL/A0 = L; Fixed EQ gain,
test at 3.4-Gbps
EQL(D)
EQZ(D)
7.5
dB
dB
Adaptive EQ gain for data lane
IN_D(0,1,2)n/p
EQ_SEL/A0 = Z; adaptive EQ
EQ_SEL/A0 = H,L,NC
2
14
EQ(c)
EQ gain for clock lane IN_CLKn/p
Input differential termination impedance
Input termination voltage
3
100
0.7
RINT
80
75
120
Ω
VITERM
VID_PP
OE = H
V
Input differential voltage (peak to peak)
Tested at TTP2, check 图 10
1200 mVPP
10
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7.7 HDMI and DVI TMDS Output Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC + 10
Data rate ≤ 1.65 Gbps; PRE_SEL =
NC; SLEW_CTL = H; OE = H; DR =
750 Mbps, VSadj = 7.06 kΩ
VCC – 10
VOH
Single-ended high level output voltage
mV
1.65 Gbps < Data rate ≤ 3.4 Gbps;
PRE_SEL = NC; SLEW_CTL = H;
OE = H; DR = 2.97 Gbps, VSadj =
7.06 kΩ
VCC – 200
VCC – 600
VCC – 700
VCC + 10
VCC – 400
VCC – 400
Data rate ≤ 1.65 Gbps; PRE_SEL =
NC; SLEW_CTL = H; OE = H; DR =
750 Mbps, VSadj = 6.5 kΩ
VOL
Single-ended low level output voltage
mV
1.65-Gbps < Data rate ≤ 3.4-Gbps;
PRE_SEL = NC; SLEW_CTL = H;
OE = H; DR = 2.97-Gbps, VSadj =
6.5 kΩ
PRE_SEL = NC; SLEW_CTL = H;
OE = H; DR = 270-Mbs/2.97 VSadj =
6.5 kΩ
Single-ended output voltage swing on
data lane
VSWING_DA
400
400
500
600
600
mV
mV
Data rate ≤ 3.4-Gbps; PRE_SEL =
NC; SLEW_CTL = H; OE = H; VSadj
= 6.5 kΩ
Single-ended output voltage swing on
clock lane
VSWING_CLK
500
20
Change in single-end output voltage
swing per 100 Ω ΔVsadj
ΔVSWING
ΔVOCM(SS)
VOD(PP)
mV
mV
mV
mV
Change in steady state output common
mode voltage between logic levels
–5
800
600
5
1200
1050
Output differential voltage before pre-
emphasis
Vsadj = 7.06 kΩ; PRE_SEL = Z, See
图 8
Vsadj = 7.06 kΩ; PRE_SEL = L, See
图 9
VOD(SS)
Steady-state output differential voltage
VCC = 0 V; VDD = 0-V; output pulled
to 3.3 V through 50-Ω resistors
ILEAK
IOS
Failsafe condition leakage current
Short circuit current limit
45
50
µA
mA
Ω
Main link output shorted to GND
Source termination resistance for HDMI
2.0
RTERM
75
150
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7.8 DDC, and I2C Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL/SDA_SNK DC input voltage
–0.3
5.6
V
VI-DC
SCL/SDA_CTL, SCL/SDA_SRC DC input
voltage
–0.3
3.6
V
V
SCL/SDA_SNK, SCL/SDA_SRC Low level
input voltage
0.3 xVCC
0.3 x VCC
VIL
SCL/SDA_CTL Low level input voltage
SCL/SDA_SNK high level input voltage
SCL/SDA_SRC high level input voltage
SCL/SDA_CTL high level input voltage
V
V
V
V
V
V
3
0.7 x VCC
0.7 x VCC
VIH
I0 = 3 mA and VCC > 2-V
I0 = 3 mA and VCC < 2-V
0.4
SCL/SDA_CTL, SCL/SDA_SRC low-level
output voltage
VOL
0.2 x VCC
SCL clock frequency fast I2C mode for
local I2C control
fSCL
400
400
kHz
pF
Total capacitive load for each bus line
(DDC and local I2C pins)
Cbus
7.9 HPD Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Failsafe condition leakage current
HPD_SNK
2.1
VIL
HPD_SNK
0.8
3.6
0.1
40
V
VOH
VOL
ILEAK
IOH = –50 µA; HPD_SRC
IOL = 500 µA; HPD_SRC
VCC = 0 V; VDD = 0 V; HPD_SNK = 5 V
2.4
0
V
V
μA
Device powered; VIH = 5 V;
IH_HPD includes RpdHPD resistor current
IH_HPD
High-level input current
40
μA
Device powered; VIL = 0.8 V;
IL_HPD includes RpdHPD resistor current
IL_HPD
Low-level input current
30
RpdHPD
HPD input termination to GND
VCC = 0 V
150
190
220
kΩ
12
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7.10 HDMI and DVI Main Link Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
REDRIVER MODE
DR
Data rate (Automatic Mode)
250
250
250
250
1000 Mbps
3400 Mbps
DR
Data rate (full redriver mode)
tPLH
tPHL
Propagation delay time (low to high)
Propagation delay time (high to low)
600
800
ps
ps
SLEW_CTL = H; PRE_SEL = NC; OE =
H; DR = 2.97 Gbps
tT1
75
75
Transition time (rise and fall time);
measured at 20% and 80% levels for data
lanes. TMDS clock meets tT3 for all three
times.
SLEW_CTL = L; PRE_SEL = NC; OE =
H; DR = 2.97 Gbps
tT2
ps
ps
SLEW_CTL = NC; PRE_SEL = NC; OE
= H; DR = 2.97 Gbps; CLK 297MHz
tT3
100
SLEW_CTL = NC; PRE_SEL = NC; OE
= H; DR = 2.97 Gbps;
tSK1(T)
tSK2(T)
Intra-pair output skew
Inter-pair output skew
40
SLEW_CTL = NC; PRE_SEL = NC; OE
= H; DR = 2.97 Gbps;
100
DR = 2.97 Gbps, HDMI_SEL/A1 = NC,
EQ_SEL/A0 = NC; PRE_SEL = NC;
SLEW_CTL = H OE = H.
tJITD1
Total output data jitter
Total output clock jitter
0.2
Tbit
Tbit
See 图 10 at TTP3
tJITC1
CLK = 297 MHz
0.25
RETIMER MODE
dR
dR
Data rate (Full retimer mode)
Data rate (Automatic mode)
0.25
1.0
3.4 Gbps
3.4 Gbps
Measured with input signal applied from
0 to 200 mVpp
dXVR
Automatic redriver to retimer crossover
.75
1.0
1.25 Gbps
MHz
fCROSSOVER
PLLBW
Crossover frequency hysteresis
Data retimer PLL bandwidth
250
.4
Default loop bandwidth setting
1
MHz
Input clock frequency detection and retimer
acquisition time
tACQ
IJT1
tT1
180
μs
Input clock jitter tolerance
Tested when data rate > 1.0 Gbps
0.3
Tbit
SLEW_CTL = H; PRE_SEL = NC; OE =
H; DR = 3.4 Gbps
75
75
Transition time (rise and fall time);
measured at 20% and 80% levels for data
lanes. TMDS clock meets tT3 for all three
times.
SLEW_CTL = L; PRE_SEL = NC; OE =
H; DR = 3.4 Gbps
tT2
tT3
ps
SLEW_CTL = NC; PRE_SEL = NC; OE
= H; DR = 3.4 Gbps; CLK = 297 MHz
100
tDCD
OUT_CLK ± duty cycle
Inter-pair output skew
Total output clock jitter
40%
50%
60%
0.2
tSK_INTER
tSK_INTRA
tJITC1(1.4b)
Tch
Tbit
Tbit
Default setting for internal inter-pair skew
adjust, HDMI_SEL/A1 = NC
0.15
0.25
CLK = 297 MHz
7.11 HPD Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See 图 13; not valid during switching time
See 图 14
MIN
TYP
MAX UNIT
Propagation delay from HPD_SNK to
HPD_SRC; rising edge and falling edge
tPD(HPD)
tT(HPD)
40
2
120
ns
HPD logical disconnected timeout
ms
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7.12 DDC and I2C Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Vcc = 3.3-V
MIN
TYP
MAX
UNIT
ns
tr
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Pulse duration, SCL high
300
300
tf
ns
tHIGH
tLOW
tSU1
0.6
1.3
100
0.6
0.6
0.6
1.3
μs
Pulse duration, SCL low
μs
Setup time, SDA to SCL
ns
tST, STA
tHD,STA
tST,STO
t(BUF)
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Bus free time between stop and start condition.
μs
μs
μs
μs
Source-to-sink: 100-kbps pattern;
tPLH1
tPHL1
tPLH2
tPHL2
Propagation delay time, low-to-high-level output Cb(Sink) = 400-pF(1)
;
360
230
250
200
ns
ns
ns
ns
See 图 17
Propagation delay time, high-to-low-level output
Sink to Source: 100-kbps pattern;
Propagation delay time, low-to-high-level output Cb(Source) = 100-pF(1)
See 图 18
;
Propagation delay time, high-to-low-level output
(1) Cb = total capacitance of one bus line in pF.
14
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7.13 Typical Characteristics
200
180
160
140
120
100
80
300
270
240
210
180
150
120
90
1.1 V
3.3 V
1.1 V
3.3 V
60
40
60
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Data Rate (Gbps)
Data Rate (Gbps)
D001
D002
图 1. Current vs Data Rate in Retimer Mode
图 2. Current vs Data Rate in Redriver Mode
1600
VOD No Term
VOD 150 to 300 W
1400
1200
1000
800
600
400
200
0
4
4.5
5
5.5
6
6.5
7
7.5
8
Vsadj (kW)
D003
图 3. VOD vs Vsadj
8 Parameter Measurement Information
ëÇ9wa
3.3ë
ꢀ0Q
ꢀ0Q
ꢀ0Q
7ꢀ-200nC
7ꢀ-200nC
ꢀ0Q
0.ꢀ pC
5+
5-
ò
ù
weceiver
5river
ëL5
ë5+
ëò
ëL5 = ë5+ - ë5-
ëh5 = ëò - ëù
ë5-
ëù
ëL/a = (ë5+ + ë5-
)
ëh/ = (ëò + ëù)
2
2
图 4. TMDS Main Link Test Circuit
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Parameter Measurement Information (接下页)
2.2 V
VTERM
VID
1.8 V
VID+
VID(pp)
0 V
VIDœ
tPHL
80%
tPLH
80%
VOD(pp)
VOD
0 V
20%
tf
20%
tr
图 5. Input and Output Timing Measurements
tSK1(T)
tSK1(T)
TMDS_OUTxp
TMDS_OUTxn
50%
tSK2(T)
TMDS_OUTyp
TMDS_OUTyn
图 6. HDMI and DVI Sink TMDS Output Skew Measurements
VOC
ûVOC(SS)
图 7. TMDS Main Link Common Mode Measurements
16
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Parameter Measurement Information (接下页)
ëh5(tt)
tw9_{9[=ù
ësadj = 7.06YQ
图 8. Output Differential Waveform 0 dB De-Emphasis
tw9_{9[ = ù
ësadj = 7.06 lQ
tw9_{9[ = [
ësadj = 7.06 lQ
1sꢀ biꢀ
2nd ꢀo ꢁ biꢀ
ëh5({{)
ëh5(tt)
图 9. PRE_SEL = L for –2-dB De-Emphasis
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Parameter Measurement Information (接下页)
Avcc(4)
RT
(5)
RT
SMA
SMA
SMA
SMA
w9C
/able
9v
Data +
Data -
Coax
Coax
Coax
Coax
RX
+EQ
OUT
Parallel(6)
BERT
Jitter Test
Instrument(2,3)
FR4 PCB trace(1)
AC coupling Caps
&
Device
FR4 PCB trace
AVcc
RT
[No Pre-
emphasis]
RT
SMA
SMA
w9C
/able
9v
SMA
SMA
Coax
Coax
Coax
Coax
Clk+
Clk-
RX
+EQ
OUT
Jitter Test
Instrument(2,3)
TTP4_EQ
TTP4
TTP1
TTP2
TTP3
(1) The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling cap, connector and another
1-2” of FR4. Trace width – 4 mils. 100-Ω differential impedance.
(2) All jitter is measured at a BER of 10-9.
(3) Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1.
(4) AVCC = 3.3-V
(5) RT = 50-Ω
(6) The input signal from parallel bit error rate tester (BERT) does not have any pre-emphasis. Refer to Recommended
Operating Conditions.
图 10. TMDS Output Jitter Measurement
690
90
0
œ90
œ690
Absolute Time
75 ps
75 ps
75 ps
75 ps
Normalized Time: Tbit
TMDS data eye mask at connector for clock frequency over 165 MHz.
图 11. Input Eye Mask at TTP2
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Parameter Measurement Information (接下页)
It5_{bY
It5_{w/
190Kꢀ
100Kꢀ
图 12. HPD Test Circuit
HPD_SNK
VCC
50%
0 V
tPD(HPD)
HPD_SRC
VCC
50%
0 V
图 13. HPD Timing Diagram Number 1
HPD_SNK
Vcc
50%
0ë
It5 [ogical 5isconnecꢀ
Çimeouꢀ
HPD_SRC
ꢀÇ(It5)
Vcc
0ë
Logically
Disconnected
Device Logically
Connected
图 14. HPD Logic Disconnect Timeout
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Parameter Measurement Information (接下页)
tI5,{Ç!
tf
tr
SCL
SDA
t{Ç,{Çh
t(.ÜC)
START
STOP
图 15. Start and Stop Condition Timing
tILDI
t[hí
SCL
t{Ç,{Ç!
SDA
t
{Ü1
图 16. SCL and SDA Timing
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Parameter Measurement Information (接下页)
SDA_SRC/
SCL_SRC
INPUT
½ Vcc
tꢀ[I1
tꢀI[1
80%
20%
SDA_SNK/
SCL_SNK
OUTPUT
½ Vcc
tf
tr
图 17. DDC Propagation Delay – Source to Sink
SDA_SNK/
SCL_SNK
INPUT
½ Vcc
tꢀI[2
tꢀ[I2
80%
20%
SDA_SRC/
SCL_SRC
OUTPUT
½ Vcc
tf
图 18. DDC Propagation Delay – Sink to Source
tr
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9 Detailed Description
9.1 Overview
The SNx5DP149 device is a Dual Mode[1] DisplayPort retiming level shifter that supports data rates up to 3.4-
Gbps for HDMI1.4b. The device takes in AC coupled HDMI/DVI signals and level shifts them to TMDS signals
while compensating for loss and jitter through its receiver equalizer and retiming functions. The SNx5DP149 in
default configuration should meet most system needs but also provides features that allow the system
implementer flexibility in design. Programming can be accomplished through I2C[4] or pin strapping.
9.2 Functional Block Diagram
Iꢃ5_{w/
Iꢃ5_{bY
ë{!5W
1ꢆ0YQ
ë.L!{
ꢁ0Q
ꢁ0Q
Lb_/[Yp
Lb_/[Yn
hÜÇ_/[Yp
hÜÇ_/[Yn
Çꢄ5{
9v
5ata wegisters
{í!ꢃ
ë.L!{
ꢃ[[
ꢃ[[ /ontrol
{9w59{
ꢁ0Q
ꢁ0Q
Lb_5ꢀ2:0]p
Lb_5ꢀ2:0]n
hÜÇ_5ꢀ2:0]p
hÜÇ_5ꢀ2:0]n
9v
Çꢄ5{
Ç9wꢄ_{9[
{[9í_{9[
ꢃw9_{9[
9naꢅle
/ontrol .lock, L2/ wegisters
L2/_9bꢂꢃLb
9v_/Ç[
9v_{9[
9v_{9[ꢂ!0
I5ꢄL_{9[
!0
I5ꢄL_{9[ꢂ!1
ꢃw9_{9[
h9
!1
[ocal L2/
/ontrol
{[9í_/Ç[
{5!_/Ç[
{/[_/Ç[
{5!_{w/
{/[_{w/
{5!_{bY
{/[_{bY
Db5
!/ÇLë9 55/ .[h/Y
1ꢇ1ë
3ꢇ3ë
ë55
ëw9D
ë//
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ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
9.3 Feature Description
9.3.1 Reset Implementation
When OE is de-asserted, control signal inputs are ignored; the Dual Mode[1] DisplayPort inputs and outputs are
high impedance. It is critical to transition the OE input from a low level to a high level after the VCC supply has
reached the minimum recommended operating voltage. Achieve this transition by a control signal to the OE
input, or by an external capacitor connected between OE and GND. To ensure that the SNx5DP149 device is
properly reset, the OE pin must be de-asserted for at least 100-μs before being asserted. When OE is toggled in
this manner the device is reset. This requires the device to be reprogrammed if it was originally programmed
through I2C for configuration. When implementing the external capacitor, the size of the external capacitor
depends on the power-up ramp of the VCC supply, where a slower ramp-up results in a larger value external
capacitor. Refer to the latest reference schematic for SNx5DP149; consider approximately 200-nF capacitor as a
reasonable first estimate for the size of the external capacitor. Both OE implementations are shown in 图 19 and
图 20.
SPACE
Dth
h9
h9
ww{Ç = 200 YΩ
/
/
图 19. External Capacitor Controlled OE
9.3.2 Operation Timing
图 20. OE Input from Active Controller
SNx5DP149 starts to operate after the OE signal goes high (see 图 21, 图 22, and 表 1). Keeping OE low until
VDD and VCC become stable avoids any timing requirements as shown in 图 21.
t
d2
h9
t
d1
ë// ꢀ ë55
ë55 ꢀ ë//
图 21. Power-Up Timing for SNx5DP149
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Feature Description (接下页)
td3
/5w !ctive
td4
wetimer mode
h9 5e-assert or
Iꢀ5_{bY 5e-assert or
图 22. CDR Timing for SNx5DP149
表 1. SNx5DP149 Operation Timing
MIN
0
MAX
UNIT
µs
td1
VDD/VCC stable before VCC/VDD
200
td2
VDD and VCC stable before OE deassertion
CDR active operation after retimer mode initial
CDR turn off time after retimer mode de-assert
VDD supply ramp-up requirements
100
µs
td3
15
120
100
100
ms
ns
td4
VDD_ramp
VCC_ramp
ms
ms
VCC supply ramp-up requirements
9.3.3 Input Lane Swap and Polarity Working
The SNx5DP149 device incorporates the swap function, which can set the input lanes in swap mode. The IN_D2
routes to the OUT_CLK position. The IN_D1 swaps with IN_D0. The swap function only changes the input pins;
EQ setup follows new mapping. The user needs to control the register 0x09h bit 7 for SWAP enable. Lane swap
is operational in both redriver and retimer mode.
表 2. Lane Swap(1)
NORMAL OPERATION
IN_D2 → OUT_D2
IN_D1 → OUT_D1
IN_D0 → OUT_D0
IN_CLK → OUT_CLK
SWAP = L OR CSR 0x09h BIT 7 IS 1’b1
IN_D2 → OUT_CLK
IN_D1 → OUT_D0
IN_D2 → OUT_D1
IN_CLK → OUT_D2
(1) The output lanes never change. Only the input lanes change. See and 图 23.
24
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ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
Lb_ꢂ2p
Lb_ꢂ2n
1
2
30
29
28
27
26
Lb_ꢂ2p
1
2
30
29
28
27
26
hÜÇ_ꢂ2p
hÜÇ_ꢂ2n
Itꢂ_{bY
hÜÇ_ꢂ2p
hÜÇ_ꢂ2n
Itꢂ_{bY
ꢂ!Ç! [!bꢀ2
/[h/Y [!bꢀ
Lb_ꢂ2n
Itꢂ_{w/
Itꢂ_{w/
3
3
Lb_ꢂ1p
Lb_ꢂ1n
4
Lb_ꢂ1p
4
hÜÇ_ꢂ1p
hÜÇ_ꢂ1p
ꢂ!Ç! [!bꢀ1
ꢂ!Ç! [!bꢀ0
ꢂ!Ç! [!bꢀ1
Lb_ꢂ1n
5
5
hÜÇ_ꢂ1n
hÜÇ_ꢂ0p
hÜÇ_ꢂ1n
hÜÇ_ꢂ0p
Lb_ꢂ0p
25
24
Lb_ꢂ0p
6
25
24
6
ꢂ!Ç! [!bꢀ0
Lb_ꢂ0n
L2/_ꢀbꢁDtLh
Lb_/[Yp
7
Lb_ꢂ0n
7
hÜÇ_ꢂ0n
hÜÇ_ꢂ0n
23
22
21
L2/_ꢀbꢁDtLh
23
22
21
8
8
IꢂaL_{ꢀ[
hÜÇ_/[Yp
hÜÇ_/[Yn
IꢂaL_{ꢀ[
hÜÇ_/[Yp
hÜÇ_/[Yn
Lb_/[Yp
9
9
ꢂ!Ç! [!bꢀ2
/[h/Y [!bꢀ
Lb_/[Yn
Lb_/[Yn
10
10
40-tin w{.
Ln {ꢀap íorking
40-tin w{.
Ln bormal íorking
图 23. SNx5DP149 Swap Function for 40 Pins
The SNx5DP149 can also change the polarity of the input signals. Use Register 0x9h bit 6 to swap polarity using
I2C. Polarity swap only works for retimer mode. When the device is in automatic redriver to retimer mode this
only works when device is in retimer stage. If set and data rate falls below 1.0-Gbps in this mode the polarity
function will be lost.
9.3.4 Main Link Inputs
Standard Dual Mode[1] DisplayPort terminations are integrated on all inputs with expected AC coupling
capacitors on board prior to input pins. External terminations are not required. Each input data channel contains
an adaptive or fixed equalizer to compensate for cable or board losses. The voltage at the input pins must be
limited below the absolute maximum ratings. The input pins have incorporated failsafe circuits. The input pins
can be polarity changed through the local I2C register.
9.3.5 Main Link Inputs Debug Tools
There are two methods for debugging a system making sure the inputs to the SNx5DP149 are valid. A TMDS
error checker is implemented that will increment an error counter per data lane. This allows the system
implementer to determine how the link between the source and SNx5DP149 is performing on all three data
lanes. See CSR Bit Field Definitions – RX PATTERN VERIFIER CONTROL/STATUS register in 表 10.
If a high error count is evident, the SNx5DP149 has the ability to provide the general eye quality. A tool is
available that uses the I2C[4] link to download data that can be plotted for an eye diagram. This is available per
data lane.
9.3.6 Receiver Equalizer
Equalizers are used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board
traces or cables. The SNx5DP149 device supports both fixed receiver equalizer (redriver and retimer mode) and
adaptive receive equalizer (retimer mode) by setting the EQ_SEL/A0 pin or through I2C using reg0Ah[5]. When
the EQ_SEL/A0 pin is high, the EQ gain is fixed to 14-dB. The EQ gain will be 7.5-dB if the EQ_SEL/A0 pin is
set low. The SNx5DP149 device operates in adaptive equalizer mode when EQ_SEL/A0 left floating. Using
adaptive equalization the gain will be automatically adjusted based on the data rate to compensate for variable
trace or cable loss. Using the local I2C[4] control, reg0Dh[5:1], the fixed EQ gain can be selected for both data
and clock.
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图 24. Adaptive EQ Gain Curve
9.3.7 Termination Impedance Control
For HDMI1.4b[2] when data rate over 2 Gbps, the output performance could be better if the termination value
between 150 to 300-Ω which was allowed. For compliance this may not be the best solution so be prepared to
utilize no termination. The SNx5DP149 supports two different source termination impedances for HDMI1.4b[2] .
This can be adjusted by I2C[4]; reg0Bh[4:3] TX_TERM_CTL.
9.3.8 TMDS Outputs
An 1% precision resistor, 6.5-kΩ, is recommended to be connected from Vsadj pin to ground to allow the
differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10-
mA current sink capability when no source term is enabled, which provides a typical 500-mV voltage drop across
a 50-Ω termination resistor. As compliance testing is system dependant this resistor value can be adjusted.
!ë//
ëcc
ùo=wÇ
ùo=wÇ
Ça5{ 5wLë9w
Ça5{ w9/9Lë9w
图 25. TMDS Driver and Termination Circuit
Referring to 图 25, if both VCC (device supply) and AVCC (sink termination supply) are powered, the TMDS
output signals are high impedance when OE = low. The normal operating condition is that both supplies are
active. A total of 33-mW of power is consumed by the terminations independent of the OE logical selection.
When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the power
source of the device is off and the power source to termination is on, the IO(off) (output leakage current)
specification ensures the leakage current is limited 45-μA or less.
The clock and data lanes VOD can be changed through I2C[4] (see VSWING_CLK and VSWING_DATA in 表 8
for details). shows the different output voltage based on different Vsadj resistor values.
26
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9.3.8.1 Pre-Emphasis/De-Emphasis
The SNx5DP149 provides De-emphasis as a way to compensate for the ISI loss between the TMDS outputs and
the receiver it is driving. There are two methods to implement this function. When in pin strapping mode the
PRE_SEL pin controls this. The PRE_SEL pin provides –2-dB, or 0-dB de-emphasis, which allows output signal
pre-conditioning to offset interconnect losses from the SNx5DP149 device outputs to a TMDS receiver. TI
recommends setting PRE_SEL at 0 dB while connecting to a receiver through a short PCB route. When pulled to
ground with a 65-kΩ resistor –2-dB can be realized, see 图 9. When using I2C, Reg0Ch[1:0] is used to make
these adjustments.
As there are times true pre-emphasis may be the best solution there are two ways to accomplish this. If pin
strapping is being use the best method is to reduce the Vsadj resistor value increasing the VOD and then pulling
the PRE_SEL pin to ground using the 65-kΩ resistor, see 图 26. If using I2C this can be accomplished using two
methods. First is similar to pin strapping by adjusting the Vsadj resistor value and then implementing –2-dB de-
emphasis. Second method is to set Reg0Ch[7:5] = 011 and the set Reg0Ch[1:0] = 01 which accomplishes the
same pre-emphasis setting. See 图 27.
tw9_{9[ = ù
ësadj = 7.06YQ
tw9_{9[ = [
ësadj = 4.5YQ
1sꢁ biꢁ
ëh5(tt) = 1400mëpp
2nd ꢁo ꢂ biꢁ
ëh5({{) = 11ꢀ0mëpp
图 26. Pre-Emphasis Using Pin Strapping Method
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tw9_{9[ = ù
ësadj = 7.06YQ
ësadj = 7.06YQ
L2/ weg0/hꢀ7:5] = 011
weg0/ꢀ1:0] = 01
1sꢀ biꢀ
2nd ꢀo ꢁ biꢀ
ëh5(tt) = 1200mëpp
ëh5({{) = 1020mëpp
图 27. Pre-Emphasis Using I2C Method
9.4 Device Functional Modes
9.4.1 Retimer Mode
Clock and data recovery circuits (CDR) are used to track, sample and retime the equalized data bit streams. The
CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to the
TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1-MHz, will be transferred to the TMDS outputs.
Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce
the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock
above approximately 100-MHz when jitter cleaning is needed for robust operation. The retimer operates at about
1.0 to 3.4-Gbps DR supporting HDMI1.4b[3]. At pixel clock frequency below about 100 MHz, the SNx5DP149
automatically bypasses the internal retimer and operates as a redriver. When the video source changes
resolution, the internal retimer starts the acquisition process to determine the input clock frequency and acquire
lock to the new data bit streams. During the clock frequency detection period and the retimer acquisition period
(that last approximately 7-ms), the TMDS drivers can be kept active (default) or programmed to be disabled to
avoid sending invalid clock or data to the downstream receiver.
9.4.2 Redriver Mode
The SNx5DP149 also has a redriver mode that can be enabled through I2C[4]; at offset address 0Ah bits 1:0
DEV_FUNC_MODE. When in this mode, the CDR and PLL are shut off, thus reducing power. Jitter performance
is degraded as the device will now only compensate for ISI loss in the link. In redriver mode HDMI1.4b[3]
compliance is not guaranteed as skew compensation and retiming functions are disabled. Excessive random or
phase jitter will not be compensated.
28
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Device Functional Modes (接下页)
9.4.3 DDC Functional Description
The SNx5DP149 solves sink- or source-level issues by implementing a master/slave control mode for the DDC
bus. When the SNx5DP149 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it will
transfer the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK
detects the feedback from the downstream device, the SNx5DP149 will pull up or pull down the SDA_SRC bus
and deliver the signal to the source.
The DDC link defaults to 100 kbps, but can be set to various values including 400 kbps by setting the correct
value to address 22h (see 表 3) through the I2C access on the DDC interface. The DDC lines are 5-V tolerant.
The HPD_SRC goes to high impedance when VCC is under low power conditions, < 1.5-V.
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9.5 Register Maps
9.5.1 DP-HDMI Adaptor ID Buffer
The SNx5DP149 device includes the DP-HDMI adapter ID buffer for HDMI/DVI adaptor recognition, defined by
the VESA DisplayPort Dual-Mode Standard Version 1.1, accessible by standard I2C[4] protocols through the
DDC interface when the HDMI_SEL/A1 pin is low. The DP-HDMI adapter buffer and extended DDC register for
Type 2 capability is accessed at target addresses 80h (Write) and 81h (Read).
The DP-HDMI adapter buffer contains a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII
characters, as shown in 表 3, and supports the WRITE command procedures (accessed at target address 80h)
to select the subaddress, as recommended in the VESA DisplayPort Interoperability Guideline Adaptor Checklist
Version 1.0 section 2.3.
表 3. SNx5DP149 DP-HDMI Adaptor ID Buffer and Extended DDC
Read or
Read/Write
Address
Description
Value HDMI
Value DVI
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
44h
50h
2Dh
48h
44h
4Dh
49h
20h
41h
44h
41h
50h
54h
4Fh
52h
04h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
HDMI ID code
Read only
Video Adaptor Identifier
Bit 2:0 ADAPTOR_REVISION
0
0
0
0
0
10h
Read only
Bit 3 Reserved: but 0 for type 2
Bits 7:4 1010 = Dual mode defined by dual mode[1]
standard
1010
11h
12h
13h
14h
15h
16h
17h
18h
19h
IEE_OUI first two hex digits
IEE_OUI second two hex digits
IEE_OUI third two hex digits
08h
00h
28h
44h
50h
31h
34h
39h
00h
02h
00h
02h
00h
00h
08h
00h
28h
44h
50h
31h
34h
39h
00h
02h
00h
02h
00h
00h
Read only
Read only
Read only
Device ID
Read only
Hardware revision
1Ah
Bits 7:4 major revision
Read only
Bits 3:0 minor revision
1Bh
1Ch
Firmware or software major revision
Firmware or software minor revision
Read only
Read only
30
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Register Maps (接下页)
表 3. SNx5DP149 DP-HDMI Adaptor ID Buffer and Extended DDC (接下页)
Read or
Read/Write
Address
Description
Value HDMI
Value DVI
Max TMDS clock rate
Default value is 88h in HDMI column
Note: Value determined by taking clock rate and dividing by
2.5 and converting to HEX. For HDMI2.0 extend as if the
clock rate extended instead of its actual method, clock 1/10
DR and not 1/40 DR.
1Dh
1Eh
88h
42h
Read only
Read only
If I2C_DR_CTL = 0 the value is 0Fh → If
DDC_AUX_DR_SEL = 0 the value is 0Fh
If I2C_DR_CTL = 1 the value is 1Fh → If
DDC_AUX_DR_SEL = 1 then value is 1Fh
If I2C_DR_CTL = 0 the value is 0Fh
If I2C_DR_CTL = 1 the value is 1Fh
0Fh
0Fh
1Fh
20h
Reserved
00h
00h
00h
00h
Write/Read
Write/Read
TMDS_OE
Bit 0: 0 = TMDS_ENABLED (default)
Bit 0: 1 = TMDS_DISABLED
Bits 7:1 Reserved
HDMI Pin Control
Bit 0 = CEC_EN
Enables connection between the HDMI CEC pin connected
to the sink and the
CONFIG2 pin to the upstream device + 27-kΩ pullup.
0 = CEC_ DISABLED (default)
1 = CEC_ ENABLED
21h
00h
00h
Write/Read
Bits 7:1 = RESERVED
Writing a bit pattern to this register that is not defined above
may result in an unpredictable I2C speed selection, but the
adaptor must continue to otherwise work normally. Only
applicable when using I2C-over-AUX transport
01h = 1-Kbps
02h = 5-Kbps
04h = 10-Kbps
22h
08h = 100-kbps
08h
08h
Write/Read
10h = 400-Kbps (RSVD in Dual Mode STND)
On read, the dual-mode cable adaptor returns a value to
indicate the speed currently in use. The default I2C speed
prior to software writing to this register is 100-Kbps.
Illegal write value shall write register default (08h). This
register sets the DDC output DR whether I2C-over-AUX or
straight DDC
23h-FFh Reserved
00h
00h
Read
9.5.2 Local I2C Interface Overview
The SCL_CTL and SDA_CTL pins are used for I2C clock and I2C data respectively. The SNx5DP149 I2C
interface conforms to the 2-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000),
and supports the fast mode transfer up to 400 kbps.
The device address byte is the first byte received following the start condition from the master device. The 7-bit
device address for the SNx5DP149 device decides by the combination of EQ_SEL/A0 and HDMI_SEL/A1. 表 4
clarifies the SNx5DP149 device target address.
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表 4. I2C Device Address Description
SNx5DP149 I2C Device Address
A1/A0
ADD
7 (MSB)
6
0
0
0
0
5
1
1
1
1
4
1
1
1
1
3
1
1
1
0
2
1
0
0
1
1
0
1
0
1
0 (W/R)
0/1
00
01
10
11
1
1
1
1
BC/BD
BA/BB
B8/B9
B6/B7
0/1
0/1
0/1
9.5.3 I2C Control Behavior
Follow this procedure to write to the SNx5DP149 device I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP149 device
7-bit address and a zero-value W/R bit to indicate a write cycle.
2. The SNx5DP149 device acknowledges the address cycle by combination of A0 and A1.
3. The master presents the subaddress (I2C register within SNx5DP149 device) to be written, consisting of one
byte of data, MSB-first.
4. The SNx5DP149 device acknowledges the subaddress cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The SNx5DP149 device acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the SNx5DP149.
8. The master terminates the write operation by generating a stop condition (P).
Follow this procedure to read the SNx5DP149 I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP149 7-bit
address and a zero-value W/R bit to indicate a write cycle.
2. The SNx5DP149 device acknowledges the address cycle by combination of A0 and A1.
3. The master presents the subaddress (I2C register within SNx5DP159 device) to be read, consisting of one
byte of data, MSB-first.
4. The SNx5DP149 device acknowledges the subaddress cycle.
5. The master initiates a read operation by generating a start condition (S), followed by the SNx5DP149 7-bit
address and a one-value W/R bit to indicate a read cycle.
6. The SNx5DP159 device acknowledges the address cycle.
7. The SNx5DP149 device transmit the contents of the memory registers MSB-first starting at the written
subaddress.
8. The SNx5DP149 device will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the
master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
9. If an ACK is received, the SNx5DP149 device transmits the next byte of data.
10. The master terminates the read operation by generating a stop condition (P).
注
No sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation.
Refer to 表 6 for the SNx5DP149 device local I2C register descriptions. Reads from reserved fields return 0s and
writes are ignored.
32
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9.5.4 I2C Control and Status Registers
Reads from reserved fields return 0, and writes to read-only reserved registers are ignored. Writes to reserved
registers, which are marked with ‘W’, produce unexpected behavior. All addresses not defined by this
specification are considered reserved. Reads from these addresses return 0 and writes will be ignored.
9.5.4.1 Bit Access Tag Conventions
A table of bit descriptions is typically included for each register description that indicates the bit field name, field
description, and the field access tags. The field access tags are described in 表 5.
表 5. Field Access Tags
ACCESS TAG
NAME
Read
Write
Set
DESCRIPTION
R
W
S
The field is read by software
The field is written by software
The field is set by a write of one. Writes of 0 to the field have no effect
C
Clear
The field is cleared by a write of 1. Writes of 0 to the field have no
effect
U
Update
Hardware may autonomously update this field
Not accessible or not applicable
NA
No access
9.5.4.2 CSR Bit Field Definitions
9.5.4.2.1 ID Registers
表 6. ID Registers
ADDRESS
BIT
DESCRIPTION
ACCESS
DEVICE_ID
00h:07h
7:0
R
These fields return a string of ASCII characters “DP149” followed by three space characters.
Address 0x00 – 0x07 = {0x44”D”, 0x50”P”, 0x31”1”, 0x34”4”, 0x39”9”, 0x20, 0x20, 0x20}
REV _ID. This field identifies the device revision.
0000001 – DP149 revision 1
08h
7:0
R
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9.5.4.2.2 Misc Control
表 7. Misc Control
ADDRESS
BIT
DEFAULT DESCRIPTION
ACCESS
SWAP_EN: This field enables swapping the input main link lanes
0 – Disable (default)
1 – Enable
7
1’b0
RWU
Note: field is loaded from SWAP/POL pin; Writes ignored when I2C_EN/PIN = 0
LANE_POLARITY: swaps the input data and clock lanes polarity.
0 – Disabled: No polarity swap
6
1’b0
1 – Swaps the input data and clock lane polarity
RWU
Note: field is loaded from SWAP/POL pin; Writes ignored when I2C_EN/PIN = 0. This
feature is only valid when in retimer mode.
5:4
3
2'b00
1’b0
Reserved
R
PD_EN
09h
0 – Normal working (default)
RW
1 – Forced power-down by I2C, lowest power state
HPD_AUTO_PWRDWN_DISABLE
0 – Automatically enters power down mode based on HPD_SNK (default)
1 – Will not automatically enter power mode based upon HPD_SNK
2
1’b0
RW
RW
I2C_DR_CTL. I2C data rate supported for configuring device
00 – 5-kbps
01 – 10-kbps
10 – 100-kbps (default)
1:0
2’b10
11 – 400-kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be set before enabling 400
Kbps mode)
Application Mode Selection
0 – Source (default) - Set the adaptive EQ mid point to between 6.5-dB and 7.5-dB
1 – Sink - Sets the adaptive EQ starting point to between 12-dB and 13-dB
7
6
1’b0
1’b0
RW
RW
HPDSNK_GATE_EN: This field sets the functional relationship between HPD_SNK and
HPD_SRC.
0 – HPD_SNK passed through to the HPD_SRC (default)
1 – HPD_SNK will not pass through to the HPD_SRC.
EQ_ADA_EN: this field enables the equalizer working state.
0 – Fixed EQ
1 – Adaptive EQ (default)
5
1’b1
RWU
Writes are ignored when I2C_EN/PIN = 0
EQ_EN: this field enables the receiver equalizer.
0 – EQ disabled
1 – EQ enable (default)
4
3
1’b1
1’b0
RW
RW
0Ah
Reserved
APPLY_RXTX_CHANGES , Self clearing write-only bit. Writing a 1 to this bit will apply new
slew, tx_term, twpst1, eqen, eqadapten, swing, eqftc, eqlev settings to the clock and data
2
1’b0
lanes. Writes to the respective registers do not take immediate effect. This bit does not need
to be written if I2C configuration occurs while OE or hpd_sink are low, I2C power down is
active.
W
DEV_FUNC_MODE: This field selects the device working function mode.
00 – Redriver mode across full range 250 Mbps to 3.4-Gbps
01 - Automatic redriver to retimer crossover at 1.0 Gbps (default)
10 - Reserved
1:0
2’b01
RW
11 - Retimer mode across full range 250 Mbps to 3.4-Gbps
When changing crossover point, need to toggle PD_EN or toggle external HPD_SNK.
34
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Mode Selection Definition: This bit lets the receiver know where the device is located in a system for the
purpose of centering the AEQ point. The SNx5DP149 is targeting the source application, so the default value is
0, which will center the EQ at 6.5 to 7.5-dB , see 表 9. If the SNx5DP149 is in a dock or sink application, the
value should be changed to a value of 1, which will center the EQ at 12 to 13-dB .
9.5.4.2.3 HDMI Control
表 8. HDMI Control
ADDRESS BIT
DEFAULT DESCRIPTION
ACCESS
SLEW_CTL. Slew rate control.2’00 is fastest and 2’b11 is slowest
Writes ignored when I2C_EN/PIN = 0
7:6
2’b00
RWU
HDMI_SEL: Contro; Writes ignored when I2C_EN/PIN = 0l
0 – HDMI (default)
1 – DVI
5
1’b0
RWU
RWU
TX_TERM_CTL: Controls termination for HDMI TX
00 – No termination
01 – 150 to 300-Ω
0Bh
4:3
2’b00
10 – Reserved
11 - Reserved
2
1
0
1’b0
1’b0
1’b0
Reserved
. Reserved
Reserved
R
R
R
VSWING_DATA: Data output swing control
000 – Vsadj set
001 – Increase by 7%
010 – Increase by 14%
011 – Increase by 21%
100 – Decrease by 30%
101 – Decrease by 21%
110 – Decrease by 14%
111 – Decrease by 7%
7:5
3’b000
RW
VSWING_CLK: Clock Output Swing Control
000 – Vsadj set
001 – Increase by 7%
0Ch
010 – Increase by 14%
011 – Increase by 21%
4:2
3’b000
100 – Decrease by 30%
RW
101 – Decrease by 21%
110 – Decrease by 14%
111 – Decrease by 7%
Note: Default is set by DR, which means standard based swing values but this allows for
the swing to be overridden by selecting one of these values
HDMI_TWPST1. HDMI de-emphasis FIR post-cursor-1 signed tap weight.
00 – No de-emphasis
01 – 2-dB de-emphasis
10 – Reserved
1:0
2’b00
RWU
11 – Reserved
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35
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
9.5.4.2.4 Equalization Control Register
表 9. Equalization Control Register
ADDRESS
BIT
DEFAULT
DESCRIPTION
ACCESS
7:6
2’b00
Reserved
RW
Data Lane EQ – Sets fixed EQ values
HDMI1.4b[2]
000 – 0-dB
001 – 4.5-dB
010 – 6.5-dB
011 – 8.5-dB
100 – 10.5-dB
101 – 12-dB
110 – 14-dB
111 – 16.5-dB
5:3
1’b000
RW
0Dh
Clock Lane EQ - Sets fixed EQ values
HDMI1.4b[2]
00 – 0-dB
01 – 1.5-dB
10 – 3-dB
2:1
0
1’b00
1’b0
RW
RW
11 – RSVD
Reserved
9.5.4.2.5 EyeScan Control Register
表 10. EyeScan Control Register
ADDRESS
BITS
DEFAULT
DESCRIPTION
ACCESS
PV_SYNC[3:0]. Pattern timing pulse. This field is updated for 8UI once
every cycle of the PRBS generator. 1 bit per lane.
7:4
4’b0000
R
PV_LD[3:0]. Load pattern-verifier controls into RX lanes. When asserted
high, the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are
enabled into the corresponding RX lane. These values are then latched
and held when PV_LD[n] is subsequently de-asserted low. 1 bit per lane.
0Eh
3:0
4’b0000
RWU
7:4
3:0
4’b0000
4’b0000
PV_FAIL[3:0]. Pattern verification mismatch detected. 1 bit per lane.
PV_TIP[3:0]. Pattern search/training in progress. 1 bit per lane.
RU
RU
0Fh
PV_CP20. Customer pattern length 20 or 16 bits.
7
6
1’b0
1’b0
0 – 16 bits
1 – 20 bits
RW
R
Reserved
PV_LEN[2:0]. PRBS pattern length
000 – PRBS7
001 – PRBS11
010 – PRBS23
5:3
3’b000
3’b000
011 – PRBS31
100 – PRBS15
101 – PRBS15
110 – PRBS20
RW
10h
111 – PRBS20
PV_SEL[24:0]. Pattern select control
000 – Disabled
001 – PRBS
010 – Clock
2:0
RW
011 – Custom
1xx – Timing only mode with sync pulse spacing defined by PV_LEN
11h
12h
7:0
7:0
7:4
3:0
‘h00
‘h00
PV_CP[7:0]. Custom pattern data.
PV_CP[15:8]. Custom pattern data.
Reserved
RW
RW
R
4’b0000
4’b0000
13h
PV_CP[19:16]. Custom pattern data. Used when PV_CP20 = 1’b1.
RW
36
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SN65DP149, SN75DP149
www.ti.com.cn
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
表 10. EyeScan Control Register (接下页)
ADDRESS
BITS
7:3
DEFAULT
5’b00000
3’b000
DESCRIPTION
ACCESS
Reserved
R
14h
2:0
PV_THR[2:0]. Pattern-verifier retain threshold.
RW
DESKEW_CMPLT: Indicates TMDS lane deskew has completed when
high
7
1'b0
R
6:5
4
2’b00
1’b0
Reserved
R
15h
BERT_CLR. Clear BERT counter (on rising edge).
TST_INTQ_CLR. Clear latched interrupt flag.
TST_SEL[2:0]. Test interrupt source select.
RSU
RSU
RW
3
1’b0
2:0
3’b000
PV_DP_EN[3:0]. Enabled datapath verified based on DP_TST_SEL, 1 bit
per lane.
7:4
3
4’b0000
1’b0
RW
R
Reserved
DP_TST_SEL[2:0] Selects pattern reported by BERT_CNT[11:0],
TST_INT[0] and TST_INTQ[0]. PV_DP_EN is non-zero
000 – TMDS disparity or data errors
001 – FIFO errors
16h
010 – FIFO overflow errors
011 – FIFO underflow errors
100 – TMDS deskew status
2:0
3'b000
RW
101 – Reserved
110 – Reserved
111 – Reserved
7:4
3:0
7:0
7:4
3:0
7:0
7:4
3:0
7:0
7:4
3:0
7:0
7:4
3:0
4’b0000
4’b0000
‘h00
TST_INTQ[3:0]. Latched interrupt flag. 1 bit per lane
TST_INT[3:0]. Test interrupt flag. 1 bit per lane.
BERT_CNT[7:0]. BERT error count. Lane 0
Reserved
RU
RU
RU
R
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
4’b0000
4’b0000
‘h00
BERT_CNT[11:8]. BERT error count. Lane 0
BERT_CNT[19:12]. BERT error count. Lane 1
Reserved
RU
RU
R
4’b0000
4’b0000
‘h00
BERT_CNT[23:20]. BERT error count. Lane 1
BERT_CNT[31:24]. BERT error count. Lane 2
Reserved
RU
RU
R
4’b0000
4’b0000
‘h00
BERT_CNT[35:32]. BERT error count. Lane 2
BERT_CNT[19:12]. BERT error count. Lane 3
Reserved
RU
RU
R
4’b0000
‘h00
BERT_CNT[23:20]. BERT error count. Lane 3
RU
Power Down Status Bit
7
1'b0
0 – Normal Operation
R
1 – Device in Power Down Mode
20h
Standby Status Bit
6
1'b0
0 – Normal Operation
1 – Device in Standby Mode
R
R
5:0
6'b000000
Reserved
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SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Use Case of SNx5DP149
SNx5DP149 can be used on the motherboard and dongle applications. The following use case diagrams show
the connection of DDC between source side and sink side. The control pin pull up and pull down resistors are
shown from reference. If a high is needed only use the pull up. If a low is needed only use the pull down. If mid
level is to be selected do not use either resistors and leave the pin floating/No connect. The 6.5-KΩ Vsadj
resistor value shown is explained further in the compliance section.
图 28 shows the original connection of SNx5DP149 on motherboard through the DDC channel. The DDC DR
default is 100-kHz and is capable to adjust to 400-kHz.
38
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www.ti.com.cn
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
Application Information (接下页)
I5ꢀL/5ëL
weceptacle
40-tin
1
30
2ꢃ
27
26
2ꢂ
24
22
21
0.1uC
0.1uC
0.1uC
0.1uC
0.1uC
0.1uC
0.1uC
0.1uC
1
2
2
Çꢀ5{_52p
ꢀ[0p
ꢀ[0n
ꢀ[1p
ꢀ[1n
ꢀ[2p
ꢀ[2n
ꢀ[3p
ꢀ[3n
Lb_52p
Lb_52n
Lb_51p
Lb_51n
Lb_50p
Lb_50n
Lb_ꢁ[Yp
Lb_ꢁ[Yn
It5_{wꢁ
hÜÇ_52p
hÜÇ_52n
hÜÇ_51p
hÜÇ_51n
hÜÇ_50p
hÜÇ_50n
Db51
3
4
ꢂ
Çꢀ5{_52n
Çꢀ5{_51p
Db52
Db53
Db54
Db5ꢂ
Db56
8
4
11
14
17
6
ꢂ
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Çꢀ5{_50p
Çꢀ5{_50n
Çꢀ5{_ꢁ[Yp
Çꢀ5{_ꢁ[Yn
ꢁ9ꢁ
7
6
ꢃ
7
10
12
ꢃ
hÜÇ_ꢁ[Yp
hÜÇ_ꢁ[Yn
10
3
ꢂë
13
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ꢁ9ꢁ
20
21
22
23
2YQ
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55ꢁ_{ꢁ[ ꢁ!{9_Db52
55ꢁ_{5! ꢁ!{9_Db53
3.3ë
2YQ
32
33
28
1ꢂ
16
1ꢃ
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{5!_{bY
It5_{bY
2YQ
2YQ
2YQ
38
3ꢃ
55ꢁ_{ꢁ[
55ꢁ_{5!
{ꢁ[_{wꢁ
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ëꢁꢁ
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100YQ
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65lQ
65lQ
2YQ
13
14
{ꢁ[_ꢁÇ[
{5!_ꢁÇ[
L2ꢁ_{ꢁ[
L2ꢁ_{5!
10uC
0.1uC 0.1uC
8
L2ꢁ_9b/tLb
tw9_{9[
16
17
23
hptional
36
18
9v_{9[/!0
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34
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65lQ
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Db5
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11
37
12
20
1ꢃ
31 40
ëꢁꢁ
ë55
Copyright © 2016, Texas Instruments Incorporated
图 28. Implementation for Motherboard
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39
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
Application Information (接下页)
shows the SNx5DP149 in the dongle application. It uses the unified structure on DisplayPort connector.
10.1.2 DDC Pullup Resistors
注
This section is for information only and subject to change depending upon system
implementation.
40
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SN65DP149, SN75DP149
www.ti.com.cn
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
Application Information (接下页)
The pullup resistor value is determined by two requirements:
1. The maximum sink current of the I2C buffer:
The maximum sink current is 3-mA or slightly higher for an I2C driver supporting standard-mode I2C[4]
operation.
VCC
=
Rup(min)
Isink
(1)
2. The maximum transition time on the bus:
The maximum transition time, T, of an I2C bus is set by an RC time constant, where R is the pullup resistor
value, and C is the total load capacitance. The parameter, k, can be calculated from 公式 3 by solving for t,
the times at which certain voltage thresholds are reached. Different input threshold combinations introduce
different values of t. 表 11 summarizes the possible values of k under different threshold combinations.
T = k ´RC
(2)
-t
æ
ö
÷
RC
ç
V(t) = VCC´ 1- e
ç
÷
è
ø
(3)
表 11. Value k Upon Different Input Threshold Voltages
Vth–\Vth+
0.7 VCC
1.0986
1.0415
0.9808
0.9163
0.8473
0.65 VCC
0.9445
0.8873
0.8267
0.7621
0.6931
0.6 VCC
0.8109
0.7538
0.6931
0.6286
0.5596
0.55 VCC
0.6931
0.6360
0.5754
0.5108
0.4418
0.5 VCC
0.5878
0.5306
0.4700
0.4055
0.3365
0.45 VCC
0.4925
0.4353
0.3747
0.3102
0.2412
0.4 VCC
0.4055
0.3483
0.2877
0.2231
0.1542
0.35 VCC
0.3254
0.2683
0.2076
0.1431
0.0741
0.3 VCC
0.2513
0.1942
0.1335
0.0690
0.1 VCC
0.15 VCC
0.2 VCC
0.25 VCC
0.3 VCC
From 公式 1, Rup(min) = 5.5-V / 3-mA = 1.83-kΩ to operate the bus under a 5-V pullup voltage and provide less
than 3-mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is
allowed, Rup(min) can be as low as 1.375-kΩ.
If DDC is working at a standard mode of 100-Kbps, the maximum transition time, T, is fixed, 1 μs, and using the
k values from 表 11, the recommended maximum total resistance of the pullup resistors on an I2C bus can be
calculated for different system setups. If DDC is working in a fast mode of 400-kbps, the transition time should be
set at 300 ns, according to I2C[4] specification.
To support the maximum load capacitance specified in the HDMI specification, Ccable(max) = 700-pF, Csource = 50-
pF, Ci = 50-pF, and R(max) can be calculated as shown in 表 12.
表 12. Pullup Resistor Upon Different Threshold Voltages and 800-pF Loads
Vth–\Vth+
0.1 VCC
0.15 VCC
0.2 VCC
0.25 VCC
0.3 VCC
0.7 VCC
1.14
1.2
0.65 VCC
1.32
0.6 VCC
1.54
1.66
1.8
0.55 VCC
1.8
0.5 VCC
2.13
0.45 VCC
2.54
0.4 VCC
3.08
3.59
4.35
5.6
0.35 VCC
3.84
0.3 VCC
4.97
6.44
9.36
18.12
—
UNIT
kΩ
1.41
1.97
2.36
2.87
4.66
kΩ
1.27
1.36
1.48
1.51
2.17
2.66
3.34
6.02
kΩ
1.64
1.99
2.23
2.45
3.08
4.03
8.74
kΩ
1.8
2.83
3.72
5.18
8.11
16.87
kΩ
To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support
a maximum 800-pF load capacitance for a standard-mode I2C bus.
版权 © 2015–2016, Texas Instruments Incorporated
41
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
10.2 Typical Application
I5ꢀL/5ëL
weceptacle
40-tin
1
3
30
2ꢃ
27
26
2ꢂ
24
22
21
0.1uC
0.1uC
0.1uC
0.1uC
0.1uC
0.1uC
0.1uC
0.1uC
1
2
2
Çꢀ5{_52p
ꢀ[0p
ꢀ[0n
ꢀ[1p
ꢀ[1n
ꢀ[2p
ꢀ[2n
ꢀ[3p
ꢀ[3n
Lb_52p
Lb_52n
Lb_51p
Lb_51n
Lb_50p
Lb_50n
Lb_ꢁ[Yp
Lb_ꢁ[Yn
It5_{wꢁ
hÜÇ_52p
hÜÇ_52n
hÜÇ_51p
hÜÇ_51n
hÜÇ_50p
hÜÇ_50n
Db51
ꢂ
Çꢀ5{_52n
Çꢀ5{_51p
Db52
Db53
Db54
Db5ꢂ
Db56
8
4
4
11
14
17
6
ꢂ
Çꢀ5{_51n
Çꢀ5{_50p
Çꢀ5{_50n
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Çꢀ5{_ꢁ[Yn
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6
ꢃ
7
10
12
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hÜÇ_ꢁ[Yn
10
3
ꢂë
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21
22
23
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33
28
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11
37
12
20
1ꢃ
31 40
ëꢁꢁ
ë55
Copyright © 2016, Texas Instruments Incorporated
图 29. Implementation for Motherboard Schematic
10.2.1 Design Requirements
The SNx5DP149 can be designed into many types of applications. All applications have certain requirements for
the system to work properly. Two voltage rails are required to support the lowest possible power consumption.
The OE pin must have a 0.1-µF capacitor to ground. This pin can be driven by a processor but the pin needs to
change states after voltage rails have stabilized. Configure the device by using I2C. Pin strapping is provided as
I2C is not available in all cases. Because sources may have different naming conventions, confirm the link
between the source and the SNx5DP149 is correctly mapped. A swap function is provided for the input pins in
case signaling is reversed between the source and the device. For the control pins the values provided below are
when they are being controlled by a micro-controller. If this is not the case then using the 65-kΩ for a pull up for
high, pulled down for low, and left floating for mid level.
42
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ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
表 13. Design Parameters
DESIGN PARAMETER
VALUE
VCC
3.3 V
1.1 V
VDD
Main link input voltage
Control pin Low
Control pin Mid
Control pin High
Vsadj resistor
VID = 75 mVpp to 1.2 Vpp
65-kΩ pulled to GND
No Connect
65-kΩ pulled to 3.3-V
7.06-kΩ
Main link AC decoupling capacitor 75 to 200 nF, recommend 100 nF
10.2.2 Detailed Design Procedure
The SNx5DP149 is a signal conditioner that provides AC coupling to DC coupling level shifting, to support Dual
Mode DisplayPort-capable GPUs or GPUs with AC-coupled drive capability to support HDMI or DVI connectors
and compliance. Signal conditioning is accomplished using receive equalization, retiming, and output driver
configurability. The transmitter drives 2 to 3 inches of board trace and connector.
Designing in the SNx5DP149 requires the following:
•
•
Determine the loss profile between the GPU and the HDMI/DVI connector.
Based upon the loss profile and signal swing, determine the optimal location for the SNx5DP149, to pass
electrical compliance.
•
•
•
Use the typical application drawings in Use Case of SNx5DP149 for information on using the AC coupling
capacitors and control pin resistors.
The DP149 has a receiver adaptive equalizer by default but can also be configured for fixed value
equalization using the EQ_SEL control pin.
Set the VOD, pre-emphasis, termination, and edge rate levels to support compliance by using the appropriate
Vsadj resistor value and by setting the PRE_SEL and SLEW_CTL control pins.
•
•
The thermal pad must be connected to ground.
See the schematics in Application Information on recommended decouple capacitors from VCC pins to
ground.
10.2.3 Application Curves
图 30. 4k2k30 TX Compliance Eye
图 31. 1080p TX Compliance Eye
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SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
10.3 System Example
10.3.1 Compliance Testing
Compliance testing is very system design specific. Properly designing the system and configuring the
SNx5DP149 can help pass transmitter compliance for the system. The following information is the starting point
to help prepare for compliance test. As each system is different there are many features in the DP149 to help
tune the circuit. These include VOD adjust by changing the Vsadj resistor value or using I2C. Other knobs to turn
are pre/de-emphasis and slew rate control. Passing HDMI1.4b compliance is easier to accomplish when using
I2C as this provides more fine tuning capability.
For the SNx5DP149RSB:
Pin Strapping
HDMI1.4b
Vsadj Resistor = 6.5 kΩ
PRE_SEL = L for –2 dB
SLEW_CTL = NC
I2C
HDMI1.4b
Vsadj Resistor = 6.5 kΩ
VSWING_DATA & VSWING_CLK to -7% = Reg0Ch[7:2] = 111111
PRE_SEL = Reg0Ch[1:0] = 00: (Labeled HDMI_TWPST)
TX_TERM_CTL: Reg0Bh[4:3]
•
•
<2 Gbps = 00 for no termination (This may be best value for all HDMI1.4b)
>2 Gbps and < 3.4 Gbps = 01 for 150 to 300 Ω
SLEW_CTL = Reg0Bh[7:6] = 10
44
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SN65DP149, SN75DP149
www.ti.com.cn
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
11 Power Supply Recommendations
11.1 Power Management
To minimize the power consumption of customer application, SNx5DP149 uses dual power supply. VCC is 3.3-V
with 10% range to support the I/O voltage. The VDD is 1.00-V to 1.27-V range to supply the internal digital control
circuit. SNx5DP149 operates in two different working states. See 表 15 for conditions for each mode. When OE
is deasserted and then reasserted the device will rest to its default configurations. If different configurations were
programmed using I2C then the device will have to be reprogrammed.
•
Power-down mode:
OE = Low puts the device into its lowest power state by shutting down all function blocks
–
–
When OE is re-asserted the transitions from L → H will create a reset and if the device is programmed
through I2C it will have to be reprogrammed.
–
–
OE = High, HPD_SNK = Low
Writing a 1 to register 09h[3]
•
•
•
Normal operation: Working in redriver or retimer
When HPD asserts, the device CDR and output will enable based on the signal detector circuit result
HPD_SRC = HPD_SNK in all conditions. The HPD channel operational when VCC over 3-V.
表 14. Control Logic and Mode of Operation
INPUTS(1)
HPD_SNK
STATUS
MODE
SDA_CTL
SCL_CTL
OUT_Dx
OUT_CLK
AUX_SRC±
(48 PIN ONLY)
Mode of
Operation
OE
L
HPD_SRC
IN_Dx
High-Z
High-Z
DDC
Power-down
mode
H
L
X
X
H
L
Disabled
High-Z
High-Z
Disabled
Disabled
Disable
Disable
Power-down
mode
H
Active
Active
Power-down
mode when a one
is written to 09h[3]
H
H
X
H
High-Z
High-Z
Disabled
Disable
H
H
H
H
Redriver
Retimer
H
H
RX active
RX active
Active
Active
TX active
TX active
Active
Active
Active
Active
Normal operation
Normal operation
(1) L = LOW, H = HIGH
TMDS output termination control impacts the operating power.
表 15. Control Logic and Mode of Operation
INPUTS(1)
HPD_SNK
STATUS
MODE
SDA_CTL
SCL_CTL
OUT_Dx
OUT_CLK
OE
Mode of Operation
HPD_SRC
IN_Dx
DDC
H
L
L
X
X
H
L
High-Z
High-Z
Disabled
Active
High-Z
Disabled
Disabled
Power-down mode
Power-down mode
H
High-Z
Power-down mode
when a one is written
to 09h[3]
H
H
X
H
High-Z
Active
High-Z
Disabled
H
H
H
H
Redriver
Retimer
H
H
RX active
RX active
Active
Active
TX active
TX active
Active
Active
Normal operation
Normal operation
(1) L = LOW, H = HIGH
TMDS output termination control impacts the operating power.
12 Layout
12.1 Layout Guidelines
TI recommends to use at a minimum a four layer stack up to accomplish a low-EMI PCB design. TI recommends
six layers because the SNx5DP149 is a two voltage rail device.
•
Routing the high-speed input DisplayPort traces and TMDS output traces on the top layer avoids the use of
vias (and their discontinuities) and allows for clean interconnects from the HDMI connectors to the repeater
版权 © 2015–2016, Texas Instruments Incorporated
45
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
Layout Guidelines (接下页)
inputs and from the repeater output to the subsequent receiver circuit. It is important to match the electrical
length of these high speed traces to minimize both inter-pair and intra-pair skew.
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
•
•
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
•
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
•
The control pin pullup and pulldown resistors are shown in application section for reference. If a high is
needed only use the pull up. If a low is needed only use the pull down. If mid level is to be selected do not
use either resistors and leave the pin floating/No connect.
Layer 1: TMDS signal layer
Layer 1: TMDS signal layer
5 to 10 mils
Layer 2: Ground
Layer 3: VCC
Layer 2: Ground plane
20 to 40 mils
Layer 4: VDD
Layer 3: Power plane
Layer 5: Ground
5 to 10 mils
Layer 6: Control signal layer
Layer 4: Control signal layer
图 32. Recommended 4- or 6-Layer Stack for a Receiver PCB Design
46
版权 © 2015–2016, Texas Instruments Incorporated
SN65DP149, SN75DP149
www.ti.com.cn
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
12.2 Layout Example
图 33. Layout Example for the DP149RSB
12.3 Thermal Considerations
On a high-K board: TI recommends to solder the PowerPAD™ onto the thermal land. A thermal land is the area
of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the SNx5DP149 device can
operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.
On a low-K board: For the device to operate across the temperature range on a low-K board, a 1-oz Cu trace
connecting the GND pins to the thermal land must be used. A simulation shows RθJA = 100.84°C/W allowing 545-
mW power dissipation at 70°C ambient temperature.
A general PCB design guide for PowerPAD packages is provided in PowerPAD Thermally Enhanced Package,
SLMA002.
13 器件和文档支持
13.1 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的
快速链接。
版权 © 2015–2016, Texas Instruments Incorporated
47
SN65DP149, SN75DP149
ZHCSEG3C –SEPTEMBER 2015–REVISED JULY 2016
www.ti.com.cn
相关链接 (接下页)
表 16. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
SN65DP149
SN75DP149
请单击此处
请单击此处
13.2 文档支持
13.2.1 相关文档
本节标识的文档均在本数据表中引用。为简化文本,数据表中的大多数参考文献均使用方括号 [文档标签] 标识的文
本,而不使用完整的文档标题。
(1) [双模] VESA DisplayPort 双模标准版本 1.1,2013 年 2 月 8 日
(2) [HDMI1.4b] 高清多媒体接口规范版本 1.4b,2011 年 10 月
(3) [HDMI2.0] 高清多媒体接口规范版本 2.0a,2015 年 3 月
(4) [I2C] I2C 总线规范版本 2.1,2000 年 1 月
(5) [HDMI1.4b CTS] 高清多媒体接口 CTS 版本 1.4b,2011 年 10 月
(6) [HDMI2.0 CTS] 高清多媒体接口 CTS 版本 2.0k,2015 年 6 月
13.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册,即可收到任意产品
信息更改每周摘要。有关更改的详细信息,请查看任意已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
PowerPAD, E2E are trademarks of Texas Instruments.
DisplayPort is a trademark of VESA.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时,我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本,请参见左侧的导航栏。
48
版权 © 2015–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65DP149RSBR
SN65DP149RSBT
SN75DP149RSBR
SN75DP149RSBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RSB
RSB
RSB
RSB
40
40
40
40
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
0 to 70
DP149
NIPDAU
NIPDAU
NIPDAU
DP149
75DP149
75DP149
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65DP149RSBR
SN65DP149RSBT
SN75DP149RSBR
SN75DP149RSBT
WQFN
WQFN
WQFN
WQFN
RSB
RSB
RSB
RSB
40
40
40
40
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65DP149RSBR
SN65DP149RSBT
SN75DP149RSBR
SN75DP149RSBT
WQFN
WQFN
WQFN
WQFN
RSB
RSB
RSB
RSB
40
40
40
40
3000
250
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RSB0040E
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.6
(0.2) TYP
EXPOSED
11
20
THERMAL PAD
36X 0.4
10
21
2X
41
SYMM
3.6
3.15 0.1
1
30
0.25
0.15
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.5
0.3
0.05
40X
4219096/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSB0040E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.15)
SYMM
40
31
40X (0.6)
40X (0.2)
1
30
36X (0.4)
41
SYMM
(4.8)
(1.325)
(
0.2) TYP
VIA
10
21
(R0.05)
TYP
11
20
(1.325)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219096/A 11/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSB0040E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.785)
4X ( 1.37)
40
31
40X (0.6)
1
30
40X (0.2)
36X (0.4)
SYMM
(0.785)
(4.8)
41
(R0.05) TYP
10
21
METAL
TYP
20
11
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 41
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219096/A 11/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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