SN75LVDS83CZQLR [TI]
FLATLINK⢠TRANSMITTER; FlatLinkâ ?? ¢变送器
| 型号： | SN75LVDS83CZQLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FLATLINK⢠TRANSMITTER |
| 文件： | 总26页 (文件大小：854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75LVDS83C
www.ti.com
SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
FLATLINK™ TRANSMITTER
Check for Samples: SN75LVDS83C
1
FEATURES
2
•
LVDS Display Serdes Interfaces Directly to
•
28 Data Channels Plus Clock In Low-Voltage
LCD Display Panels with Integrated LVDS
TTL to 4 Data Channels Plus Clock Out
Low-Voltage Differential
•
•
Package: 4.5mm x 7mm BGA
•
•
Consumes Less Than 1mW When Disabled
1.8V up to 3.3V Tolerant Data Inputs to
Connect Directly to Low-Power, Low-Voltage
Application and Graphic Processors
Selectable Rising or Falling Clock Edge
Triggered Inputs
•
Transfer Rate up to 85Mpps (Mega Pixel Per
Second); Pixel Clock Frequency Range 10MHz
to 85MHz
•
•
ESD: 5kV HBM
Support Spread Spectrum Clocking (SSC)
•
•
Suited for Display Resolutions Ranging From
HVGA up to HD With Low EMI
APPLICATIONS
•
•
•
LCD Display Panel Driver
UMPC and Netbook PC
Digital Picture Frame
Operates From a Single 3.3V Supply and
148mW (typical) at 75MHz
DESCRIPTION
The SN75LVDS83C FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock
synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS
receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The
frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and
serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.
The frequency of CLKOUT is the same as the input clock, CLKIN.
Application
processor
SN75LVDS83C
FlatLinkTM Transmitter
(e.g. OMAPTM
)
BGA Package: 4.5 x 7mm
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
SN75LVDS83C
SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The SN75LVDS83C requires no external components and little or no control. The data bus appears the same at
the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The
only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a
low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the
clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all
internal registers to a low-level.
The SN75LVDS83C is characterized for operation over ambient air temperatures of -10°C to 70°C.
ORDERING INFORMATION(1)
PART NUMBER
PART MARKING
PACKAGE
SN75LVDS83CZQLR
LVDS83C in BGA package
56-pin ZQL LARGE Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or
refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
UNIT
MIN
-0.5
-0.5
-0.5
MAX
Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC(2)
Voltage range at any output terminal
Voltage range at any input terminal
Continuous power dissipation
4
V
V
V
VCC + 0.5
IOVCC + 0.5
See the Thermal Information Table
Storage temperature, Ts
–65
150
5
°C
kV
V
Human Body Model (HBM)(3) all pins
ESD rating Charged Device Model (CDM)(4) all pins
Machine Model (MM)(5) all pins
500
150
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) All voltages are with respect to the GND terminals.
(3) In accordance with JEDEC Standard 22, Test Method A114-A.
(4) In accordance with JEDEC Standard 22, Test Method C101.
(5) In accordance with JEDEC Standard 22, Test Method A115-A.
2
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SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
2.8
NOM
MAX
3.6
3.6
3.6
3.6
0.1
UNIT
Supply voltage, VCC
3.3
3.3
LVDS output Supply voltage, LVDSVCC
PLL analog supply voltage, PLLVCC
IO input reference supply voltage, IOVCC
Power supply noise on any VCC terminal
2.8
2.8
3.3
V
1.62
1.8 / 2.5 / 3.3
IOVCC = 1.8V
IOVCC = 2.5V
IOVCC = 3.3V
IOVCC = 1.8V
IOVCC = 2.5V
IOVCC = 3.3V
IOVCC/2 + 0.3V
IOVCC/2 + 0.4V
IOVCC/2 + 0.5V
High-level input voltage, VIH
Low-level input voltage, VIL
V
V
IOVCC/2 - 0.3V
IOVCC/2 - 0.4V
IOVCC/2 - 0.5V
132
Differential load impedance, ZL
90
Ω
Operating free-air temperature, TA
-10
70
C
THERMAL INFORMATION
SN75LVDS83C
THERMAL METRIC(1)
UNIT
ZQL (56 PINS)
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
67.1
25.2
31.0
0.8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
30.3
n/a
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
TIMING REQUIREMENTS
PARAMETER
MIN
MAX
100
8%
UNIT
Input clock period, tc
Input clock modulation
11.76
ns
with modulation frequency 30kHz
with modulation frequency 50kHz
6%
High-level input clock pulse width duration, tw
Input signal transition time, tt
0.4 tc
0.6 tc
3
ns
ns
ns
ns
Data set up time, D0 through D27 before CLKIN (See Figure 3)
Data hold time, D0 through D27 after CLKIN
2
0.8
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ZQL PACKAGE
(TOP VIEW)
6
5
4
3
2
1
K
J
D8
D9
D7
GND
VCC
D12
GND
D15
D18
GND
D21
D23
D5
D6
D4
D3
D2
D0
D1
D27
Y0M
Y1M
H
G
F
D11
D13
D14
D16
D17
D19
D20
D22
D10
GND
GND
Y0P
Y1P
IOVCC
GND LVDSVCC
E
D
C
B
A
Y2P
CLKP
Y3P
Y2M
CLKM
Y3M
CLKSEL GND
IOVCC GND
D25
D24
SHTDN PLLVCC GND
D26
CLKIN
GND
ZQL PIN LIST
Ball #
A1
A4
B1
B4
C1
C4
D1
D4
E1
E4
F1
Signal
GND
Ball #
A2
A5
B2
B5
C2
C5
D2
D5
E2
E5
F2
Signal
CLKIN
D23
Ball #
A3
A6
B3
B6
C3
C6
D3
D6
E3
E6
F3
Signal
D26
D24
D22
GND
PLLVCC
D21
SHTDN
D25
D20
Y3M
Y3P
GND
IOVCC
CLKM
CLKSEL
Y2M
GND
CLKP
D18
D19
GND
D17
Y2P
ball not populated
ball not populated
LVDSVCC
ball not populated
Y1M
D15
D16
GND
GND
Y1P
ball not populated
F4
F5
F6
D14
GND
D13
GND
D11
D3
G1
G4
H1
H4
J1
G2
G5
H2
H5
J2
G3
G6
H3
H6
J3
IOVCC
Y0M
D12
Y0P
D10
VCC
D0
D27
J4
D6
J5
GND
D2
J6
D9
K1
K4
D1
K2
K5
K3
K6
D4
D5
D7
D8
4
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PIN
SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
PIN FUNCTIONS
I/O
DESCRIPTION
Y0P, Y0M, Y1P,
Y1M, Y2P, Y2M
Differential LVDS data outputs.
Outputs are high-impedance when SHTDN is pulled low (de-asserted)
Differential LVDS Data outputs.
Y3P, Y3M
LVDS Out
Output is high-impedance when SHTDN is pulled low (de-asserted).
Note: if the application only requires 18-bit color, this output can be left open.
Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
CLKP, CLKM
Data inputs; supports 1.8V to 3.3V input voltage selectable by VDD supply. To connect a graphic
source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily
intuitive).
For input bit assignment see Figure 11 to Figure 14 for details.
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23,
and D27 to GND.
D0 – D27
CMOS IN with
pulldn
CLKIN
Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and
high (assert) for normal operation.
SHTDN
Selects between rising edge input clock trigger (CLKSEL = VIH and falling edge input clock trigger
(CLKSEL = VIL).
CLKSEL
VCC
3.3V digital supply voltage
IOVCC
PLLVCC
LVDSVCC
GND
I/O supply reference voltage (1.8V up to 3.3V matching the GPU data output signal swing)
Power Supply(1) 3.3V PLL analog supply
3.3V LVDS output analog supply
Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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FUNCTIONAL BLOCK DIAGRAM
Parallel-Load 7-bit
Shift Register
D0, D1, D2, D3,
D4, D6, D7
7
7
7
7
Y0P
Y0M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
Shift Register
D8, D9, D12, D13,
D14, D15, D18
Y1P
Y1M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
ShiftRegister
D19, D20, D21, D22,
D24, D25, D26
Y2P
Y2M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
Shift Register
D27, D5, D10, D11,
D16, D17, D23
Y3P
Y3M
A,B,...G
SHIFT/LOAD
>CLK
Control Logic
SHTDN
7X Clock/PLL
7XCLK
CLKOUTP
CLKOUTM
>CLK
CLKIN
CLKINH
CLKSEL
RISING/FALLING EDGE
6
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SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
Dn
CLKIN
or
CLKIN
CLKOUT
Previous cycle
Next
Current cycle
Y0
Y1
Y2
Y3
D7+1
D0-1
D7
D18
D26
D23
D6
D15
D25
D17
D4
D14
D24
D16
D3
D13
D22
D11
D2
D12
D21
D10
D1
D9
D0
D8
D8-1
D19-1
D27-1
D18+1
D26+1
D23+1
D20
D5
D19
D27
Figure 1. Typical SN75LVDS83C Load and Shift Sequences
LVDSVCC
IOVCC
5W
YnP or
YnM
D or
SHTDN
50W
10kW
7V
7V
300kW
Figure 2. Equivalent Input and Output Schematic Diagrams
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
V
VT
Input voltage threshold
IOVCC/2
Differential steady-state output voltage
magnitude
mV
|VOD
|
250
450
35
RL = 100Ω, See Figure 4
Change in the steady-state differential
output voltage magnitude between
opposite binary states
Δ|VOD
|
1
mV
Steady-state common-mode output
voltage
VOC(SS)
VOC(PP)
1.125
1.375
35
V
See Figure 4
tR/F (Dx, CLKin) = 1ns
Peak-to-peak common-mode output
voltage
mV
IIH
IIL
High-level input current
Low-level input current
VIH = IOVCC
VIL = 0 V
25
±10
±24
±12
±20
μA
μA
VOY = 0 V
mA
mA
μA
IOS
Short-circuit output current
VOD = 0 V
IOZ
High-impedance state output current
VO = 0 V to VCC
IOVCC = 1.8V
IOVCC = 3.3V
200
100
Input pull-down integrated resistor on all
inputs (Dx, CLKSEL, SHTDN, CLKIN)
Rpdn
kΩ
μA
disabled, all inputs at GND;
SHTDN = VIL
IQ
Quiescent current (average)
2
100
SHTDN = VIH, RL = 100Ω (5 places),
grayscale pattern (Figure 5)
VCC = 3.3V, fCLK = 75MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
I(IOVCC) with IOVCC = 1.8V
SHTDN = VIH, RL = 100Ω (5 places),
44.9
0.1
mA
ICC
Supply current (average)
worst-case pattern (Figure 6),
VCC = 3.3V, fCLK = 75MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
55.1
0.5
2
mA
pF
I(IOVCC) with IOVCC = 1.8V
CI
Input capacitance
(1) All typical values are at VCC = 3.3V, TA = 25°C.
8
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SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
Delay time, CLKOUT↑ after Yn valid
(serial bit position 0, equal D1, D9,
D20, D5)
t0
t1
t2
t3
t4
t5
-0.15
0
0.15
7 tc + 0.15
7 tc + 0.15
7 tc + 0.15
7 tc + 0.15
7 tc + 0.15
7 tc + 0.15
ns
ns
ns
ns
ns
ns
Delay time, CLKOUT↑ after Yn valid
(serial bit position 1, equal D0, D8,
D19, D27)
1
2
3
4
5
6
1
2
3
4
5
6
/
/
/
/
/
/
7 tc - 0.15
7 tc - 0.15
7 tc - 0.15
7 tc - 0.15
7 tc - 0.15
7 tc - 0.15
/
/
/
/
/
/
Delay time, CLKOUT↑ after Yn valid
(serial bit position 2, equal D7, D18,
D26. D23)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 3; equal D6, D15,
D25, D17)
See Figure 7, tC = 13.3ns,
|Input clock jitter| < 25ps
(2)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 4, equal D4, D14,
D24, D16)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 5, equal D3, D13,
D22, D11)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 6, equal D2, D12,
D21, D10)
t6
ns
ns
tc(o)
Output clock period
tc
tC = 13.3ns; clean reference clock, see
Figure 8
±26
(3)
Δtc(o)
Output clock cycle-to-cycle jitter
ps
tC = 13.3ns with 0.05UI added noise
modulated at 3MHz, see Figure 8
±44
4
tw
High-level output clock pulse duration
/
7 tc
ns
ps
Differential output voltage transition
time (tr or tf)
tr/f
See Figure 4
200
250
800
15
Enable time, SHTDN↑ to phase lock
(Yn valid)
ten
f(clk) = 85MHz, See Figure 9
f(clk) = 85MHz, See Figure 10
µs
Disable time, SHTDN↓ to off-state
(CLKOUT high-impedance)
tdis
13
ns
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed
over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
PARAMETER MEASUREMENT INFORMATION
tsu
thold
Dn
CLKIN
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.
CLKSEL = 0V.
Figure 3. Set Up and Hold Time Definition
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PARAMETER MEASUREMENT INFORMATION (continued)
49.9W ꢀ1 ꢁ( ꢂPLCS
Yꢂ
V
OD
V
YM
OL
ꢀ001
801
V
ODꢁHS
0V
V
ODꢁPS
(01
01
t
t
r
f
V
OLꢁꢂꢂS
V
V
OLꢁCCS
OLꢁCCS
0V
Figure 4. Test Load and Voltage Definitions for LVDS Outputs.
CLKIN
D0,8,16
D1,9,17
D2,10,18
D3,11,19
D4-7,12-15,20-23
D24-27
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 5. 16 Grayscale Test Pattern
10
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PARAMETER MEASUREMENT INFORMATION (continued)
T
CLKIN
EVEN Dn
ODD Dn
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 6. Worst-Case Power Test Pattern
t7
CLKIN
CLKOUT
t6
t5
t4
t3
t2
t1
t0
Yn
VOD(H)
0.00V
VOD(L)
~2.5V
1.40V
~0.5V
CLKOUT
or Yn
CLKIN
t7
t0-6
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 7. SN75LVDS83C Timing Definitions
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PARAMETER MEASUREMENT INFORMATION (continued)
Device
Under
Test
+
Reference
VCO
+
Modulation
v(t) = A sin(2 pf
t)
mod
HP8656B Signal
Generator,
0.1 MHz-990 MHz
HP8665A Synthesized
Signal Generator,
0.1 MHz-4200 MHz
Device Under
Test
DTS2070C
Digital
TimeScope
Input
RF Output
CLKIN
CLKOUT
RF Output
Modulation Input
Figure 8. Output Clock Jitter Test Set Up
CLKIN
Dn
ten
SHTDN
Yn
Invalid
Valid
Figure 9. Enable Time Waveforms
CLKIN
tdis
SHTDN
CLKOUT
Figure 10. Disable Time Waveforms
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APPLICATION INFORMATION
This section describes the power up sequence, provides information on device connectivity to various GPU and
LCD display panels, and offers a pcb routing example.
Power Up Sequence
The SN75LVDS83C does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to
GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while
all other device blocks are still powered down.
It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device
will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true
input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output
stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still
lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (SN75LVDS83C SHTDN input initially low):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Enable video source output; start sending black video data.
4. Toggle LVDS83C shutdown to SHTDN = VIH.
5. Send >1ms of black video data; this allows the LVDS83C to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (SN75LVDS83C SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set SN75LVDS83C input SHTDN = GND; wait for 250ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
Signal Connectivity
While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the
industry has aligned over the years on a certain data format (bit order). Figure 11 through Figure 14 show how
each signal should be connected from the graphic source through the SN75LVDS83C input, output and LVDS
LCD panel input. Detailed notes are provided with each figure.
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SN75LVDS83C
SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
www.ti.com
24-bpc GPU
SN75LVDS83C
FORMAT1 FORMAT2 (See Note A)
R0(LSB)
R1
R2
D0
D1
D27
D5
D2
D3
D4
D6
D27
D5
D7
D8
D0
D1
D2
D3
R3
R4
R5
R6
Y0M
Y0P
100
100
to column
driver
D4
R7(MSB)
G0(LSB)
G1
D6
Y1M
Y1P
D10
D11
D7
FPC
Cable
LVDS
timing
Controller
G2
G3
D9
Y2M
Y2P
100
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
D8
G4
D9
(8bpc, 24bpp)
G5
G6
D12
D13
D14
D16
D17
D15
D18
D19
D20
D21
D22
D24
D25
D26
D23
Y3M
Y3P
100
to row driver
G7(LSB)
B0(LSB)
B1
CLKOUTM
CLKOUTP
100
B2
B3
B4
B5
24-bpp LCD Display
B6
B7(MSB)
HSYNC
VSYNC
ENABLE
RSVD (Note C)
CLK
CLKIN CLKIN
4.8k
3.3V
C2
3.3V
C3
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note B)
Main Board
Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each
color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of
each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by
checking the LCD display data sheet.
•
Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the
dominate data format for LCD panels.
•
Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
Note D. RSVD must be driven to a valid logic level. All unused SN75LVDS83C inputs must be tied to a valid logic
level.
Figure 11. 24-Bit Color Host to 24-bit LCD Panel Application
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SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
18-bpp GPU
SN75LVDS83C
R0(LSB)
R1
R2
D0
D1
D2
R3
R4
D3
D4
D6
Y0M
Y0P
100
R5(MSB)
to column
driver
D27
D5
D7
D8
Y1M
Y1P
100
G0(LSB)
G1
G2
FPC
Cable
D9
Y2M
Y2P
LVDS
timing
Controller
100
G3
G4
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
(6-bpc, 18-bpp)
G5(MSB)
CLKOUTM
CLKOUTP
100
to row driver
B0(LSB)
B1
B2
B3
B4
B5(MSB)
18-bpp LCD Display
Y3M
Y3P
(See Note A)
HSYNC
VSYNC
ENABLE
RSVD
CLK
3.3V
C2
3.3V
C3
4.8k
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note B)
Main Board
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 12. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
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SN75LVDS83C
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12-bpp GPU
SN75LVDS83C
(See Note B)
R2 or VCC
R3 or GND
R0
D0
D1
D2
R1
R2
D3
D4
D6
Y0M
Y0P
100
100
R3(MSB)
to column
driver
D27
D5
D7
D8
Y1M
Y1P
(See Note B)
G2 or VCC
G3 or GND
G0
FPC
Cable
D9
Y2M
Y2P
LVDS
timing
Controller
100
G1
G2
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
(6-bpc, 18-bpp)
G3(MSB)
CLKOUTM
CLKOUTP
100
to row driver
(See Note B)
B2 or VCC
B3 or GND
B0
B1
B2
18-bpp LCD Display
B3(MSB)
Y3M
Y3P
(See Note A)
HSYNC
VSYNC
ENABLE
RSVD
CLK
4.8k
3.3V
C2
3.3V
C3
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 N.C.
Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of
the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic
range, connect D1, D8, and D18 to GND.
R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color
space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect
D0, D7, and D15 to VCC.
Note C.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 13. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application
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Product Folder Link(s): SN75LVDS83C
SN75LVDS83C
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SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
24-bpp GPU
SN75LVDS83C
R0 and R1: NC
(See Note B)
R2
D0
R3
R4
D1
D2
R5
R6
D3
D4
D6
Y0M
Y0P
100
R7(MSB)
to column
driver
D27
D5
D7
D8
G0 and G1: NC
(See Note B)
Y1M
Y1P
100
G2
G3
FPC
Cable
G4
G5
G6
D9
Y2M
Y2P
LVDS
timing
Controller
100
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
(6-bpc, 18-bpp)
G7(MSB)
CLKOUTM
CLKOUTP
100
to row driver
B0 and B1: NC
(See Note B)
B2
B3
B4
B5
B6
B7(MSB)
18-bpp LCD Display
B0 and B1: NC
(See Note B)
Y3M
Y3P
(See Note A)
HSYNC
VSYNC
ENABLE
RSVD
CLK
4.8k
3.3V
C2
3.3V
C3
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 NC.
Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down
to18-bit per pixel.
NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 14. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
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www.ti.com
Typical Application Schematic
Figure 15 represents the schematic drawing of the SN75LVDS83C evaluation module.
J1
U1H
J2
sma_surface
C3
GND1
C5
GND2
D3
GND3
F5
J3
GND4
sma_surface
G3
H3
U1A
GND5
D1
GND6
CLKM
J5
D2
GND7
CLKP
A1
J4
PLLGND
sma_surface
B1
H2
LVDSGND1
LVDSGND2
Y0P
Y0M
F2
H1
G2
J5
sma_surface
Y1P
SN75LVDS83CZQL
G1
Y1M
E1
Y2P
E2
J6
sma_surface
Y2M
IOVCC
C2
C1
Y3P
R4
R5
R6
R7
R8
R9
R10
4.7k
Y3M
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
J7
sma_surface
JMP1
SN75LVDS83CZQL
U1B
J2
K1
K2
J3
K3
J4
K5
D0
D1
D2
D3
D4
D6
D7
D0
D1
D2
D3
D4
D6
D7
1
2
J8
sma_surface
J9
sma_surface
14
Header 7x2
SN75LVDS83CZQL
J10
sma_surface
IOVCC
R11
4.7k
R12
4.7k
R13
4.7k
R14
4.7k
R15
4.7k
R16
4.7k
R17
4.7k
sma_surface
JMP2
U1C
K6
D8
D8
J6
D9
1
2
D9
IOVCC
IOVCC
G5
D12
D13
D14
D15
D18
D12
G6
D13
F6
D14
E5
D15
D5
D18
14
R1
R2
Header 7x2
4.7k
SN75LVDS83CZQL
IOVCC
R18
4.7k
R19
4.7k
R20
4.7k
R21
4.7k
R22
4.7k
R23
4.7k
R24
4.7k
JMP6
U1G
JMP3
B3
SHTDN
U1D
SHTDN
1
3
2
4
D4
CLKSEL
C6
D19
D19
D20
D21
D22
D24
D25
D26
CLKSEL
1
2
B6
D20
Header 2x2
B5
D21
A6
D22
SN75LVDS83CZQL
A4
D24
B4
D25
A3
D26
14
U1J
E3
NC1
E4
Header 7x2
NC2
F3
NC3
SN75LVDS83CZQL
F4
NC4
IOVCC
SN75LVDS83CZQL
R25
4.7k
R26
4.7k
R27
4.7k
R28
4.7k
R29
4.7k
R30
4.7k
R31
4.7k
JMP4
U1E
K4
D5
D5
VCC
IOVCC
1
2
H4
D10
H6
D10
D11
D16
D17
D23
D27
U1I
D11
E6
D16
G4
VCC
B2
D6
PLLVCC
F1
LVDSVCC
D17
A5
D23
J1
D27
14
H5
IOVCC1
C4
IOVCC2
Header 7x2
SN75LVDS83CZQL
SN75LVDS83CZQL
VCC
VCC
VCC
IOVCC
C31
1uF
C32
0.1uF
C33
0.01uF
C34
1uF
C35
0.1uF
C36
0.01uF
C40
1uF
C41
C42
C37
1uF
C38
C39
0.1uF
0.01uF
0.1uF
0.01uF
PLACE UNDER LVDS83C
(bottom pcb side)
Figure 15. Schematic Example (SN75LVDS83C Evaluation Board)
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SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
PCB Routing
Figure 16 and Figure 17 show a possible breakout of the data input and output signals from the BGA package.
R1
R2
R3
R4
R5
R6
R7
R8
G0
G1
D8
D7
D5
D6
D4
D3
D2
D0
D1
G2
D9
GND
VCC
D12
GND
D15
D27
Y0M
Y1M
D11
D10
GND
GND
Y0P
Y1P
G3
G4
D13
D14
D16
IOVCC
G5
G6
G7
B0
LVDSGND LVDSVCC
Y2P
CLKP
Y3P
Y2M
CLKM
Y3M
B1
B2
D17
D19
D20
D22
D18 CLKSEL GND
GND
D21
D23
IOVCC GND
B3
B4
D25
D24
SHTDN PLLVCC LVDS GND
+PLLGND
B5
B6
D26 CLKIN PLLGND
B7
HS
VS
EN
CLK
Figure 16. 24-Bit Color Routing (See Figure 11 for the Schematic)
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www.ti.com
G1
G0
R5 R4 R3 R2
R1
R0
D8
D7
D5
D6
D4
D3
D2
D0
D1
To GND
G2
D9
GND
VCC
D12
GND
D15
D18
GND
D21
D27
Y0M
Y1M
D11
D13
D14
D16
D10
GND
Y0P
Y1P
G3
G4
IOVCC GND
G5
B0
LVDS GND LVDS VCC
To GND
B1
Y2P
CLKP
Y3P
Y2M
CLKM
Y3M
D17
D19
D20
CLKSEL GND
IOVCC GND
B2
remains
unconnected
B3
B4
B5
D25
SHTDN PLLVCC LVDSGND
+PLLGND
CLKIN
D22
D23 D24
D26
PLLGND
HS VS EN
CLK
Figure 17. 18-Bit Color Routing (See Figure 12, Figure 13, and Figure 14 for the Schematic)
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SLLSE66A –OCTOBER 2010–REVISED SEPTEMBER 2011
REVISION HISTORY
Changes from Original (May 2009) to Revision A
Page
•
Multiply changes throughout the data sheet ......................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Feb-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN75LVDS83CZQLR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Green (RoHS
& no Sb/Br)
SNAGCU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75LVDS83CZQLR
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 28.6
SN75LVDS83CZQLR
BGA MICROSTAR
JUNIOR
ZQL
56
1000
Pack Materials-Page 2
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