SN75LVPE4410RNQT [TI]
4 通道 16Gbps 线性转接驱动器 | RNQ | 40 | 0 to 70;
| 型号： | SN75LVPE4410RNQT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4 通道 16Gbps 线性转接驱动器 | RNQ | 40 | 0 to 70 驱动 驱动器 |
| 文件： | 总31页 (文件大小：1606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN75LVPE4410
SNLS666 –JANUARY 2020
SN75LVPE4410 Quad-Channel PCI Express 4.0 Linear Redriver
1 Features
3 Description
The SN75LVPE4410 is a four channel low-power
high-performance linear repeater/redriver designed to
support PCI Express (PCIe) Generation 1.0, 2.0, 3.0
and 4.0.
1
•
Quad-channel linear equalizer supporting PCIe
1.0/2.0/3.0/4.0 up to 16 Gbps interfaces
•
CTLE boosts up to 18 dB at 8 GHz helps to
extend channel reach
The SN75LVPE4410 receivers deploy continuous
time linear equalizers (CTLE) to provide
•
•
Automatic receiver detection for PCIe use cases
a
Protocol agnostic linear redriver allows seamless
support for PCIe link training
programmable high-frequency boost. The equalizer
can open an input eye that is completely closed due
to inter-symbol interference (ISI) induced by an
interconnect medium, such as PCB traces. The CTLE
receiver is followed by a linear output driver. The
linear datapaths of SN75LVPE4410 preserve transmit
preset signal characteristics. The linear redriver
becomes part of the passive channel that as a whole
get link trained for best transmit and receive
equalization settings. This transparency in the link
training protocol result in best electrical link and
lowest possible latency. The programmable
equalization of the device along with its linear
datapaths maximizes the flexibility of physical
placement within the interconnect channel and
improves overall channel performance.
•
•
Ultra-low latency of 70 ps (typical)
Low additive random jitter of 60 fs (typical) with
PRBS data
•
•
Single 3.3-V supply
Low active power of 124 mW/channel (typical) -
no heat sink required
•
•
Pin-strap or SMBus programming
Support for x2, x4, x8, x16 PCIe bus width with
one or multiple SN75LVPE4410
•
•
Commercial temperature range of 0ºC to 70ºC
4.0 mm × 6.0 mm, 40 pin WQFN package
The programmable settings can be applied easily
through software (SMBus or I2C) or by using pin
control.
2 Applications
•
•
•
Desktop PC/motherboard
Notebook PC
Device Information(1)
Data storage
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN75LVPE4410
WQFN (40)
4.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
PCIe Endpoint
SN75LVPE4410
4-Channel
CPU
PCIe Gen4 Redriver
Connector
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75LVPE4410
SNLS666 –JANUARY 2020
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ................................................ 15
Power Supply Recommendations...................... 21
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 DC Electrical Characteristics .................................... 6
6.6 High Speed Electrical Characteristics....................... 6
6.7 SMBUS/I2C Timing Charateristics ............................ 8
6.8 Typical Characteristics.............................................. 9
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1 Documentation Support ....................................... 23
11.2 Receiving Notification of Documentation Updates 23
11.3 Support Resources ............................................... 23
11.4 Trademarks........................................................... 23
11.5 Electrostatic Discharge Caution............................ 23
11.6 Glossary................................................................ 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
January 2020
*
Initial release.
2
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SNLS666 –JANUARY 2020
5 Pin Configuration and Functions
RNQ Package
40-Pin WQFN
Top View
NC
1
28
27
26
25
24
23
22
21
NC
NC
EN_SMB
SCL
2
3
RX_DET
PWDN2
RSVD3
VOD
SDA
GAIN
4
5
6
7
8
Thermal
Pad
EQ1_ADDR1
EQ0_ADDR0
RSVD1
RSVD2
PWDN1
Not to scale
Pin Functions
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
RSVD1
EN_SMB
8
—
RESERVED. Can be left unconnected or pulled up to VDD with 4.7k resistor.
Four-level control input used to select SMBus/I2C or Pin control.
L0: Pin mode
2
I, 4-level
L1: RESERVED
L2: RESERVED
L3: I2C or SMBus Slave Mode
EQ0_ADDR0
EQ1_ADDR1
7
6
I, 4-level
I, 4-level
The 4-Level Control Input pins of SN75LVPE4410 is defined according to Table 4.
In I2C or SMBus Mode (EN_SMB =L3), the pins are used to set the I2C or SMBus address
of the device. The pin state is read on power up and decoded according to Table 5.
In Pin mode (EN_SMB = L0), the pins are decoded at power up to control the CTLE boost
setting according to Table 1.
GAIN
GND
Sets DC gain of CTLE at power up.
L0: Reserved
L1: Reserved
L2: 0 dB (recommended)
L3: 3.5 dB
5
I, 4-level
EP is the Exposed Pad at the bottom of the WQFN package. It is used as the GND return for
the device. The EP should be connected to ground plane(s) through low resistance path. A
via array provides a low impedance path to GND, and also improves thermal dissipation.
EP
P
NC
1, 14, 15,
27, 28
No connect
—
PWDN1
Two-level logic controlling the operating state of the redriver.
High: Power down for channels 0 and 1
Low: Power up, normal operation for channels 0 and 1.
I, 3.3 V
LVCMOS
21
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SNLS666 –JANUARY 2020
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Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NO.
PWDN2
Two-level logic controlling the operating state of the redriver.
High: Power down for channels 2 and 3
Low: Power up, normal operation for channels 2 and 3.
I, 3.3 V
LVCMOS
25
RSVD2
RSVD3
RX_DET
22
24
—
—
RESERVED. The pin must be pulled high to VDD with external 4.7k resistor.
Reserved use for TI. The pin must be left floating (NC).
The RX_DET pin controls the receiver detect function. Depending on the input level, a 50 Ω
or >50 kΩ termination to the power rail is enabled. See Table 3 for details.
26
30
29
33
32
37
36
40
39
I, 4-level
RX0N
RX0P
RX1N
RX1P
RX2N
RX2P
RX3N
RX3P
SCL
Inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects
RXP to RXN. Channel 0.
I
I
I
I
I
I
I
I
Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor
connects RXP to RXN. Channel 0.
Inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects
RXP to RXN. Channel 1.
Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor
connects RXP to RXN. Channel 1.
Inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects
RXP to RXN. Channel 2.
Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor
connects RXP to RXN. Channel 2.
Inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects
RXP to RXN. Channel 3.
Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor
connects RXP to RXN. Channel 3.
I/O, 3.3 V
LVCMOS,
open drain
SMBus / I2C clock input / open-drain output. External 1 kΩ to 5 kΩ pullup resistor is required
3
4
as per SMBus / I2C interface standard. This pin is 3.3 V tolerant.
SDA
I/O, 3.3 V
LVCMOS,
open drain
SMBus / I2C data input / open-drain clock output. External 1 kΩ to 5 kΩ pullup resistor is
required as per SMBus interface standard. This pin is 3.3 V tolerant.
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
VDD
Inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for
RX detection at power up. Channel 0.
19
20
16
17
12
13
9
O
O
O
O
O
O
O
O
Non-inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used
for RX detection at power up. Channel 0.
Inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for
RX detection at power up. Channel 1.
Non-inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used
for RX detection at power up. Channel 1.
Inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for
RX detection at power up. Channel 2.
Non-inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used
for RX detection at power up. Channel 2.
Inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for
RX detection at power up. Channel 3.
Non-inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used
for RX detection at power up. Channel 3.
10
Power supply pins. VDD = 3.3 V ±10%. The VDD pins on this device should be connected
through a low-resistance path to the board VDD plane. Typical supply decoupling consists of
a 0.1 µF capacitor per VDD pin and one 1.0 µF bulk capacitor per device.
31, 34, 35,
38
P
I, 4-level
P
VOD
Sets TX VOD setting at power up.
L0: –6 dB
L1: –3.5 dB
L2: 0 dB (recommended)
L3: –1.5 dB
23
VREG
Internal voltage regulator output. Must add decoupling caps of 0.1 µF near each pin. The
regulator is only for internal use. Do not use to power any external components. Do not route
the signal beyond the decoupling capacitors on board.
11, 18
4
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SNLS666 –JANUARY 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.0
UNIT
V
VDDABSMAX
VIOCMOS,ABSMAX
VIO4LVL,ABSMAX
VIOHS-RX,ABSMAX
VIOHS-TX,ABSMAX
TJ,ABSMAX
Supply Voltage (VDD)
3.3 V LVCMOS and Open Drain I/O voltage
4-level Input I/O voltage
4.0
V
2.75
3.2
V
High-speed I/O voltage (RXnP, RXnN)
High-speed I/O voltage (TXnP, TXnN)
Junction temperature
V
2.75
150
150
V
°C
°C
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
DC plus AC power should not
exceed these limits
VDD
NVDD
Supply voltage, VDD to GND
Supply noise tolerance
3.0
3.3
3.6
V
Supply noise, DC to <50 Hz,
sinusoidal1
250
20
mVpp
mVpp
mVpp
Supply noise, 50 Hz to 10 MHz,
sinusoidal1
Supply noise, >10 MHz,
sinusoidal1
10
TRampVDD
TA
VDD supply ramp time
From 0 V to 3.0 V
0.150
0
100
70
ms
C
Operating ambient temperature
Minimum pulse width required for
PWLVCMOS the device to detect a valid signal PWDN1/2
on LVCMOS inputs
200
μs
SMBus SDA and SCL Open
Drain Termination Voltage
Supply voltage for open drain
pull-up resistor
VDDSMBUS
3.6
V
SMBus clock (SCL) frequency in
SMBus slave mode
FSMBus
10
400
kHz
Source differential launch
amplitude
VIDLAUNCH
DR
800
1
1200
16
mVpp
Gbps
Data rate
SN75LVPE4410
6.4 Thermal Information
THERMAL METRIC(1)
UNIT
RNQ, 40 Pins
31.1
RθJA-High
Junction-to-ambient thermal resistance
℃/W
℃/W
K
RθJC(top)
Junction-to-case (top) thermal resistance
21.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
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UNIT
Thermal Information (continued)
THERMAL METRIC(1)
RNQ, 40 Pins
RθJB
ψJT
Junction-to-board thermal resistance
12.1
0.3
℃/W
℃/W
℃/W
℃/W
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
12.1
4.1
RθJC(bot)
6.5 DC Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
Device current consumption when all
four channels are active
All four channels enabled with VOD =
L2, PWDN1,2 = L
IACTIVE
150
85
200
112
33
mA
mA
Device current consumption when two Two channels enabled with VOD = L2,
channels are active PWDN1 or PWDN2 = L
IACTIVE-HALF
ISTBY
Device current consumption in standby All four channels disabled, PWDN1,2
power mode
22
mA
V
= H
VREG
Control IO
VIH
Internal regulator output
2.5
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
SDA, SCL, PWDN1, PWDN2 pins
SDA, SCL, PWDN1, PWDN2 pins
Rpull-up = 100 kΩ (SDA, SCL pins)
IOL = –4 mA (SDA, SCL pins)
2.1
2
V
V
V
V
VIL
1.08
VOH
VOL
0.4
10
VInput = VDD, (SCL, SDA, PWDN1,
PWDN2 pins)
IIH
Input high leakage current
µA
VInput = 0 V, (SCL, SDA, PWDN1,
PWDN2 pins)
IIL
Input low leakage current
Input capacitance
-10
µA
pF
CIN-CTRL
1.5
4 Level IOs (EQ0_ADDR0, EQ1_ADDR1, EN_SMB, RX_DET, VOD, GAIN pins)
IIH_4L
Input high leakage current, 4 level IOs VIN = 2.5V
Input low leakage current, , 4 level IOs VIN = GND
10
µA
µA
IIL_4L
-150
Receiver
ZRX-DC
Rx DC Single-Ended Impedance
Rx DC Differential Impedance
50
Ω
Ω
ZRX-DIFF-DC
Transmitter
100
Impedance of Tx during active
signaling, VID,diff = 1Vpp
ZTX-DIFF-DC
VTX-DC-CM
ITX-SHORT
DC Differential Tx Impedance
Tx DC common mode Voltage
Tx Short Circuit Current
120
90
Ω
V
0.75
Total current the Tx can supply when
shorted to GND
mA
6.6 High Speed Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver
50 MHz to 1.25 GHz
-22
-19
-17
-14
dB
dB
dB
dB
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
Input differential return loss with
minimal channel in TI evaluation board
RLRX-DIFF
Input differential return loss with
minimal channel in TI evaluation board
RLRX-DIFF
8.0 GHz to 12.5 GHz
-13
dB
6
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High Speed Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
50 MHz to 2.5 GHz
MIN
TYP
-18
MAX
UNIT
dB
Input common-mode return loss with
minimal channel in TI evaluation board
RLRX-CM
RLRX-CM
2.5 GHz to 8.0 GHz
-13
dB
Input common-mode return loss with
minimal channel in TI evaluation board
8.0 GHz to 12.5 GHz
-10
-45
3.0
dB
dB
dB
Minimum pair-to-pair isolation
(SDD21) between two adjacent
receiver pairs from 10 MHz to 8 GHz.
XTRX
GAIN
Receive-side pair-to-pair isolation
CTLE block DC gain
Ratio at GAIN = L3 and GAIN = L2,
with low freq CK
Transmitter
VODL0-L2
VODL1-L2
VODL3-L2
Ratio of VOD gain L0 to L2
Ratio of VOD gain L1 to L2
Ration of VOD gain L3 to L2
GAIN = L2, with low freq CK
GAIN = L2, with low freq CK
GAIN = L2, with low freq CK
-6
-3.5
-1.5
dB
dB
dB
Measured with lowest EQ, VOD = L2;
PRBS-7, 16 Gbps, over at least
106 bits using a bandpass-Pass Filter
from 30 Khz - 500 Mhz
Tx AC Peak-to-Peak Common Mode
Voltage
VTX-AC-CM-PP
50
mVpp
mV
VTX-CM-DC = |VOUTn+ + VOUTn–|/2,
Measured by taking the absolute
difference of VTX-CM-DC during PCIe
state L0 and Electrical Idle
VTX-CM-DC-
ACTIVE-IDLE-
DELTA
Absolute Delta of DC Common Mode
Voltage during L0 and Electrical Idle
0
0
0
100
Measured by taking the absolute
difference of VOUTn+ and VOUTn– during
Electrical Idle, Measured with a band-
pass filter consisting of two first-order
filters. The High-Pass and Low-
Pass –3 dB bandwidths are 10 kHz
and 1.25 GHz, respectively - zero at
input
VTX-IDLE-DIFF- AC Electrical Idle Differential Output
10
mV
mV
Voltage
AC-p
Measured while Tx is sensing whether
a low-impedance Receiver is present.
No load is connected to the driver
output
VTX-RCV-
DETECT
Amount of Voltage change allowed
during Receiver Detection
600
50 MHz to 1.25 GHz
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
50 MHz to 2.5 GHz
-22
-20
-18
-15
-13
dB
dB
dB
dB
dB
Output differential return loss with
minimal channel in TI evaluation board
RLTX-DIFF
Output Common-mode return loss
with minimal channel in TI evaluation
board
RLTX-CM
2.5 GHz to 8.0 GHz
-11
dB
Minimum pair-to-pair isolation
(SDD21) between two adjacent
transmitter pairs from 10 MHz to 8
GHz.
XTTX
Transmit-side pair-to-pair isolation
-45
dB
Device Datapath
Input-to-output latency (propagation
Measured by observing propagation
delay during either Low-to-High or
High-to-Low transition
TPLHD/PHLD
70
18
90
20
ps
ps
delay) through a channel
Measured between any two lanes
within a single transmitter
LTX-SKEW
Lane-to-Lane Output Skew
Measured with maximum CTLE setting
and maximum BW setting (EQ1 = L3,
EQ0 = L3). Boost is defined as the
gain at 8 GHz relative to 100 MHz.
EQGAIN8G
High-frequency EQ boost @ 8 GHz
Maximum DC gain variation
dB
dB
DCGAINVAR,
max
VOD=L2, GAIN=L2, min EQ setting
-2.1
1.1
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High Speed Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EQGAINVAR,
max
VOD=L2, GAIN=L2, max EQ setting,
at 8 Ghz
Maximum EQ boost variation
The maximum DC input amplitude for
-2.9
3.5
dB
VOD = L2. Minimal input channel and
minimum EQ using 128T pattern at 2.5
Gbps.
LINEARITYD which the repeater remains linear,
C
800
750
mVpp
mVpp
defined as ≤1 dB compression of
Vout/Vin.
The maximum DC input amplitude for
VOD = L2. Minimal input channel and
minimum EQ using 1T pattern at 16
Gbps.
LINEARITYA which the repeater remains linear,
C
defined as ≤1 dB compression of
Vout/Vin.
6.7 SMBUS/I2C Timing Charateristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Slave Mode
TSDA-HD
TSDA-SU
TSDA-R
Data hold time
0
ns
ns
ns
ns
Data setup time
100
SDA rise time, read operation
SDA fall time, read operation
Pull-up resistor = 1 kΩ, Cb = 50 pF
Pull-up resistor = 1 kΩ, Cb = 50 pF
120
10
TSDA-F
8
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6.8 Typical Characteristics
Figure 1. Typical EQ Boost vs Frequency for 8 (Out of
Available 16) EQ Indices
Figure 2. EQ Boost vs Frequency with EQ Index 15
(Maximum Setting) for Different Supply Voltage and
Temperature Settings
Figure 3. Typical Input (RX) Differential Return Loss vs
Frequency in TI Evaluation Board with ~2 dB input and ~2
dB output loss
Figure 4. Typical Input (RX) Common Mode Return Loss vs
Frequency in TI Evaluation Board with ~2 dB Input and ~2
dB Output Loss
Figure 5. Typical Output (TX) Differential Return Loss vs
Frequency in TI Evaluation Board with ~2 dB Input and ~2
dB Output Loss
Figure 6. Typical Output (TX) Common Mode Return Loss vs
Frequency in TI Evaluation Board with ~2 dB Input and ~2
dB Output Loss
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Typical Characteristics (continued)
Figure 7. SN75LVPE4410 Typical Jitter Characteristics in TI Evaluation Board. Left - Input to the Device, Right - Output of the
Device with Jitter Decomposition Shown.
10
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7 Detailed Description
7.1 Overview
The SN75LVPE4410 is a four-channel multi-rate linear repeater with integrated signal conditioning. The four
channels operate independently from one another. Each channel includes a continuous-time linear equalizer
(CTLE) and a linear output driver, which together compensate for a lossy transmission channel between the
source transmitter and the final receiver. The linearity of the data path is specifically designed to preserve any
transmit equalization while keeping receiver equalization effective.
The SN75LVPE4410 can be configured two different ways:
Pin Mode – device control configuration is done solely by strap pins. Pin mode is expected to be good
enough for many system implementation needs.
SMBus/I2C Slave Mode - provides most flexibility. Requires a SMBus/I2C master device to configure
SN75LVPE4410 through writing to its slave address.
7.2 Functional Block Diagram
One Channel of Four
Term
Term
RXnP
RXnN
TXnP
TXnN
Linear
Driver
CTLE
Receiver
Detect
Shared Digital
EQ1_ADDR1
EQ0_ADDR0
Power-
On Reset
Always-On
10MHz
Shared Digital Core
SCL
SDA
EN_SMB
PWDN
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7.3 Feature Description
7.3.1 Linear Equalization
The SN75LVPE4410 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency
boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the
passive channel. Table 1 shows available equalization boost through EQ0_ADDR0 and EQ1_ADDR1 control
pins, when in Pin Control mode (EN_SMB = L0).
Table 1. Equalization Control Settings
EQUALIZATION SETTING
TYPICAL EQ BOOST
INDEX
EQ1_ADDR1
EQ0_ADDR0
@ 4 GHz
–0.3
0.4
@ 8 GHz
–0.8
1.3
0
1
L0
L0
L0
L0
L1
L1
L1
L1
L2
L2
L2
L2
L3
L3
L3
L3
L0
L1
L2
L3
L0
L1
L2
L3
L0
L1
L2
L3
L0
L1
L2
L3
2
3.3
5.7
3
3.8
7.1
4
4.9
8.4
5
5.2
9.1
6
5.4
9.8
7
6.5
10.7
11.3
12.6
13.6
14.4
15.0
15.9
16.5
17.8
8
6.7
9
7.7
10
11
12
13
14
15
8.7
9.1
9.4
10.3
10.6
11.8
The equalization of the device can also be set by writing to SMBus/I2C registers in slave mode. Refer to the
SN75LVPE4410 Programming Guide (SNLU270) for details.
7.3.2 DC Gain
The VOD or GAIN pins can be used to set the overall data-path DC (low frequency) gain of the SN75LVPE4410
as outlined in the Pin Configuration and Functions section.
Table 2 shows how DC gain of the overall data-paths can be set using GAIN and VOD pins, when in Pin Control
mode (EN_SMB = L0).
Table 2. DC Gain Settings
Desired DC Gain (dB)
GAIN
L3
VOD
L2
+3.5
0
L2
L2
-1.5
-3.5
-6
L2
L3
L2
L1
L2
L0
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It is advised that the DC gain and equalization of the SN75LVPE4410 are set such that the signal swing at DC
and high frequency does not exceed the DC and AC linearity ranges of the devices, respectively. For most PCIe
systems the default DC gain setting 0 dB (GAIN and VOD pins floating) would be sufficient. However a DC
attenuation can utilized to be able to apply extra equalization when needed and keeping the data-path linear.
7.3.3 Receiver Detect State Machine
The SN75LVPE4410 deploys an RX detect state machine that governs the RX detection cycle as defined in the
PCI express specifications. At power up, after a manually triggered event through PWDN1 and PWDN2 pins (in
pin mode), or writing to the relevant I2C / SMBus register, the redriver determines whether or not a valid PCI
express termination is present at the far end of the link. The RX_DET pin of SN75LVPE4410 provides additional
flexibility for system designers to appropriately set the device in desired mode according to Table 3.
If all four channels of SN75LVPE4410 are used for same PCI express link, the PRWDN1 and PWDN2 pin can be
shorted and driven together.
Table 3. Receiver Detect State Machine Settings
PWDN1 and PWDN2
RXDET
COMMENTS
PCI Express RX detection state machine is
enabled. RX detection is asserted after 2x valid
detections.
L
L0
Pre Detect: Hi-Z, Post Detect: 50 Ω.
PCI Express RX detection state machine is
enabled. RX detection is asserted after 3x valid
detections.
L
L
L1
Pre Detect: Hi-Z, Post Detect: 50 Ω.
PCI Express RX detection state machine is
enabled. RX detection is asserted after 1x valid
detection.
L2 (Float)
Pre Detect: Hi-Z, Post Detect: 50 Ω.
PCI Express RX detection state machine is
disabled.
Recommended for non PCI Express interface use
case where the SN75LVPE4410 is used as buffer
with equalization.
L
L3
X
Always 50 Ω.
H
Manual reset, input is high impedance.
7.4 Device Functional Modes
7.4.1 Active PCIe Mode
The device is in normal operation with PCIe state machine enabled by RX_DET = L0/L1/L2. In this mode
PWDN1/PWDN2 pins are driven low in a system (for example by PCIe connector "PRSNT" signal). In this mode,
the SN75LVPE4410 redrivers and equalizes PCIe RX or TX signals to provide better signal integrity.
7.4.2 Active Buffer Mode
The device is in normal operation with PCIe state machine disabled by RX_DET = L3. This mode is
recommended for non-PCIe use cases. In this mode the device is working as a buffer to provide linear
equalization to improve signal integrity.
7.4.3 Standby Mode
The device is in standby mode invoked by PWDN1/PWDN2 = H. In this mode, the device is in standby mode
conserving power.
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7.5 Programming
7.5.1 Control and Configuration Interface
7.5.1.1 Pin Mode
The SN75LVPE4410 can be fully configured through GPIO/Pin-strap pins. In this mode the device uses 2-level
and 4-level pins for device control and signal integrity optimum settings. The Pin Configuration and Functions
section defines the control pins.
7.5.1.1.1 Four-Level Control Inputs
The SN75LVPE4410 has six (GAIN, VOD, EQ1_ADDR1, EQ0_ADDR0, EN_SMB, and RX_DET) 4-level inputs
pins that are used to control the configuration of the device. These 4-level inputs use a resistor divider to help set
the four valid levels and provide a wider range of control settings. External resistors must be of 10% tolerance or
better.
Table 4. 4-Level Control Pin Settings
LEVEL
L0
SETTING
1 kΩ to GND
13 kΩ to GND
F (Float)
L1
L2
L3
59 kΩ to GND
7.5.1.2 SMBUS/I2C Register Control Interface
If EN_SMB = L3 (SMBus / I2C control mode), the SN75LVPE4410 is configured through a standard I2C or
SMBus interface that may operate up to 400 kHz. The slave address of the SN75LVPE4410 is determined by the
pin strap settings on the EQ1_ADDR1 and EQ0_ADDR0 pins. The device can be configured for best signal
integrity and power settings in the system using the I2C or SMBus interface. The sixteen possible slave
addresses (8-bit) for the SN75LVPE4410 are shown in Table 5.
Table 5. SMBUS/I2C Slave Address Settings
EQ1_ADDR1 PIN LEVEL
EQ0_ADDR0 PIN LEVEL
8-BIT WRITE ADDRESS (HEX)
7-BIT ADDRESS (HEX)
L0
L0
L0
L0
L1
L1
L1
L1
L2
L2
L2
L2
L3
L3
L3
L3
L0
L1
L2
L3
L0
L1
L2
L3
L0
L1
L2
L3
L0
L1
L2
L3
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The SN75LVPE4410 is a high-speed linear repeater which extends the reach of differential channels impaired by
loss from transmission media like PCBs and cables. It can be deployed in a variety of different systems. The
following sections outline typical applications and their associated design considerations.
8.2 Typical Applications
The SN75LVPE4410 is a PCI Express linear redriver that can also be configured as interface agnostic redriver
by disabling its RX detect feature. The device can be used in wide range of interfaces including:
•
•
•
PCI Express
SATA
SAS
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Typical Applications (continued)
The SN75LVPE4410 is a protocol agnostic 4-channel linear redriver with PCI Express receiver-detect capability.
Its protocol agnostic nature allows it to be used in PCI Express x2, x4, x8, and x16 applications. Figure 8 shows
how a number of SN75LVPE4410 devices can be used to obtain signal conditioning for PCI Express buses of
varying widths. Note all four channels of the SN75LVPE4410 flow in same direction. Therefore, if the device is
used for x2 configuration, careful layout consideration is needed. In x2 configuration, the two-channel grouping
can be used for PCIe receiver detect. PWDN1 pin puts channels 1 and 2, and PWDN2 pin puts channels 3 and 4
into standby.
CPU/
Root
Complex
SN75LVPE4410
SN75LVPE4410
CPU/
Root
X2 PCIe
Complex
SN75LVPE4410
SN75LVPE4410
Two X2 PCIe
SN75LVPE4410
SN75LVPE4410
CPU/
Root
Complex
SN75LVPE4410
SN75LVPE4410
X4 PCIe
SN75LVPE4410
SN75LVPE4410
SN75LVPE4410
SN75LVPE4410
SN75LVPE4410
CPU/
Root
Complex
SN75LVPE4410
SN75LVPE4410
SN75LVPE4410
SN75LVPE4410
CPU/
Root
Complex
X8 PCIe
X16 PCIe
Figure 8. PCI Express x2, x4, x8, and x16 Use Cases Using SN75LVPE4410
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Typical Applications (continued)
8.2.1 PCIe x4 Lane Configuration
The SN75LVPE4410 can be used in server or motherboard applications to boost transmit and receive signals to
increase the reach of the host or root complex processor to PCI Express slots/connectors. The following design
recommendations can be used in any lane configuration. Figure 9 shows a simplified schematic for x4
configuration.
SN75LVPE4410
TX Repeater
RX0P
RX0N
TX0P
TX0N
.
.
.
.
.
.
.
.
.
.
.
.
RX3P
RX3N
TX3P
TX3N
GPIO mode
EN_SMB
Optional pin strap
control for best
signal integrity
VOD
GAIN
1 kΩ
GND
Pin strap to fine
tune EQ gain
settings
EQ0_ADDR0
EQ1_ADDR1
SDA
SDC
RX_DET
System level
power control
PWDN1,2
VREG
GND
0.1ꢀF
(2x)
3.3V
Minimum
recommended
decoupling
VDD
0.1ꢀF
(4x)
1ꢀF
Host/Root
complex side
Connector/
Socket Side
SN75LVPE4410
RX Repeater
TX0P
TX0N
RX0P
RX0N
.
.
.
.
.
.
.
.
.
.
.
.
TX3P
TX3N
RX3P
RX3N
GPIO mode
EN_SMB
Optional pin strap
control for best
signal integrity
VOD
GAIN
1 kΩ
GND
Pin strap to fine
tune EQ gain
settings
EQ0_ADDR0
EQ1_ADDR1
SDA
SDC
RX_DET
System level
power control
PWDN1,2
VREG
GND
0.1ꢀF
(2x)
3.3V
Minimum
recommended
decoupling
VDD
0.1ꢀF
(4x)
1ꢀF
Figure 9. Simplified Schematic for PCIe x4 Lane Configuration
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Typical Applications (continued)
8.2.1.1 Design Requirements
As with any high-speed design, there are many factors which influence the overall performance. The following list
indicates critical areas for consideration during design.
•
Use 85 Ω impedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N
traces should be done on the single-ended segments of the differential pair.
•
•
•
Use a uniform trace width and trace spacing for differential pairs.
Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
AC-coupling capacitors of 220 nF are recommended, set the maximum body size to 0402, and add a cutout
void on the GND plane below the landing pad of the capacitor to reduce parasitic capacitance to GND.
•
•
Back-drill connector vias and signal vias to minimize stub length.
Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
In PCIe Gen 4.0 and Gen 3.0 applications, the specification requires Rx-Tx link training to establish and optimize
signal conditioning settings at 16 Gbps and 8 Gbps, respectively. In link training, the Rx partner requests a series
of FIR – pre-shoot and de-emphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-
levels (6 dB to 12 dB) of CTLE followed by a single tap DFE. The link training would pre-condition the signal, with
an equalized link between the root-complex and endpoint.
Note that there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications. The
SN75LVPE4410 is placed in between the Tx and Rx. It helps extend the PCB trace reach distance by boosting
the attenuated signals with its equalization, which allows the user to recover the signal by the downstream Rx
more easily.
For operation in Gen 4.0 and Gen 3.0 links, the SN75LVPE4410 transmit outputs are designed to pass the Tx
Preset signaling onto the Rx for the PCIe Gen 4.0 or Gen 3.0 link to train and optimize the equalization settings.
The suggested setting for the SN75LVPE4410 are VOD = 0 dB and DC GAIN = 0 dB. Adjustments to the EQ
setting should be performed based on the channel loss to optimize the eye opening in the Rx partner. The
available EQ gain settings are provided in Table 1.
The Tx equalization presets or CTLE and DFE coefficients in the Rx can also be adjusted to further improve the
eye opening.
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Typical Applications (continued)
Figure 10 shows as an example for SN75LVPE4410 Typical Connection Schematic.
3.3 V (filtered)
3.3 V (filtered)
VDD
VDD
3.3 V
VDD
10µF
1µF
0.1µF
0.1µF
0.1µF
0.1µF
VDD
0.1µF
0.1µF
VREG
VREG
C9
C1
TX0P
TX0N
TX1P
RX0P
RX0N
RX1P
C10
C11
C2
C3
C12
C13
C4
C5
TX1N
TX2P
RX1N
RX2P
High-speed
inputs
High-speed
outputs
C14
C15
C16
C6
C7
C8
TX2N
TX3P
TX3N
RX2N
RX3P
RX3N
3.3 V
3.3 V
4.7k
4.7k
4.7k
RSVD2
PWDN1
SDA
SCL
I2C
Control
PWDN2
RSVD1
RSVD3
NC (x5)
DAP
EN_SMB
RX_DET
R1
R2
VOD
R3
GAIN
R4
EQ0_ADDR0
EQ1_ADDR1
R5
R6
NOTES:
C1 œ C16 = 220 nF (10 V / X7R / 0402)
R1 (see EN_SMB Resistor Values Table)
R2 (see RX_DET Resistor Values Table)
R3 (see VOD Resistor Values Table)
R4 (see GAIN Resistor Values Table)
R5, R6 (see EQ Control or I2C Slave Address Settings Table)
R3
Figure 10. SN75LVPE4410 Typical Connection Schematic
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Typical Applications (continued)
8.2.1.3 Application Curves
The SN75LVPE4410 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-
compliant TX and RX are equipped with signal-conditioning functions and can handle channel losses of up to 28
dB at 8 GHz. With the SN75LVPE4410, the total channel loss between a PCIe root complex and an end point
can be up to 45 dB at 8 GHz.
Figure 11 shows an electric link that models a single channel of a PCIe link and eye diagrams measured at
different locations along the link. The source that models a PCIe TX sends a 16 Gbps PRBS-15 signal with P7
presets. After a transmission channel with –30 dB at 8-GHz insertion loss, the eye diagram is fully closed. The
SN75LVPE4410 with its CTLE set to the maximum (18 dB boost) together with the source TX equalization
compensates for the losses of the pre-channel (TL1) and opens the eye at the output of the SN75LVPE4410.
The post-channel (TL2) losses mandate the use of PCIe RX equalization functions such as CTLE and DFE that
are normally available in PCIe compliant receivers.
RX CTLE: 12 dB
PCIe Root
Complex
SN75LVPE4410
PCIe
End Point
TL1
-30 dB @ 8 GHz
TL2
-15 dB @ 8 GHz
Pre-Cursor: 3.5 dB
Post-Cursor: -6 dB
RX EQ Boost: 18 dB
Figure 11. PCIe Gen 4.0 Link Reach Extension Using SN75LVPE4410
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9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the operating conditions outlined in the Recommended
Operating Conditions for DC voltage, AC noise, and start-up ramp time.
2. The SN75LVPE4410 does not require any special power supply filtering, such as ferrite beads, provided that
the recommended operating conditions are met. Only standard supply decoupling is required. Typical supply
decoupling consists of a 0.1 µF capacitor per VDD pin, one 1.0 µF bulk capacitor per device, and one 10 µF
bulk capacitor per power bus that delivers power to one or more SN75LVPE4410 devices. The local
decoupling (0.1 µF) capacitors must be connected as close to the VDD pins as possible and with minimal
path to the SN75LVPE4410 ground pad.
10 Layout
10.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing the decoupling
capacitors directly underneath the device is recommended if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and
impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, take
care to minimize the via stub, either by transitioning through most/all layers or by back drilling.
4. GND relief can be used (but is not required) beneath the high-speed differential signal pads to improve signal
integrity by counteracting the pad capacitance.
5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to
the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board.
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10.2 Layout Example
Top Layer
Use ac-coupling
capacitors with 0201
package
Ensure high-speed
trace length is
matched with ≤ 5 mils
intra-pair; pair-pair
skew is less critical
Route high-speed
traces as differential
coupled microstrips
(S=2W*) with tight
impedance control
( 10%)
Avoid acute angles
when routing high-
speed traces
Bottom Layer
Use recommended
package footprint and
ground via placement
Place decoupling
capacitors close to
VDD and VREG pins;
minimize ground
loops
Ensure pair-pair gap
is > 5W* for minimal
pair-pair coupling
Add ground pours for
additional isolation
Follow connector
manufacturer
guidelines
*W is a trace width. S is a
gap between adjacent
traces.
Figure 12. SN75LVPE4410 Layout Example - Sub-Section of a PCIe Riser Card With CEM Connectors
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, DS160PR410 Programming Guide (SNLU255)
Texas Instruments, Understanding EEPROM Programming for DS160PR410 PCI-Express Gen-4 Redriver
(SNLA320)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN75LVPE4410RNQR
SN75LVPE4410RNQT
ACTIVE
ACTIVE
WQFN
WQFN
RNQ
RNQ
40
40
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
PX410
PX410
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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3-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75LVPE4410RNQR
SN75LVPE4410RNQT
WQFN
WQFN
RNQ
RNQ
40
40
3000
250
330.0
180.0
12.4
12.4
4.3
4.3
6.3
6.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN75LVPE4410RNQR
SN75LVPE4410RNQT
WQFN
WQFN
RNQ
RNQ
40
40
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
4.7±0.1
2X 4.4
(0.2) TYP
9
20
EXPOSED
THERMAL PAD
36X 0.4
8
21
2X
2.8
2.7±0.1
1
28
0.25
40X
0.15
29
40
PIN 1 ID
0.1
C A
B
0.5
0.3
(OPTIONAL)
40X
0.05
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
4X
(1.1)
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
(5.8)
(
0.2) TYP
VIA
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
6X
(0.695)
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
20
6X (1.3)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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