TAS5614LA_15 [TI]
150-W Stereo and 300-W Mono PurePath HD Digital-Input Class-D Power Stage;
| 型号： | TAS5614LA_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 150-W Stereo and 300-W Mono PurePath HD Digital-Input Class-D Power Stage |
| 文件： | 总31页 (文件大小：941K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5614LA
www.ti.com
SLAS846 –MAY 2012
150-W Stereo / 300-W Mono PurePath™ HD Digital-Input Class-D Power Stage
Check for Samples: TAS5614LA
1
FEATURES
DESCRIPTION
The TAS5614LA is a feature optimized class-D power
amplifier based on the TAS5614LA.
234
•
PurePath™ HD Integrated Feedback Provides:
–
–
–
0.03% THD at 1 W into 4 Ω
>65 dB PSRR (No Input Signal)
>105 dB (A weighted) SNR
The TAS5614LA uses large MOSFETs for improved
power efficiency and a novel gate drive scheme for
reduced losses in idle and at low output signals
leading to reduced heat sink size.
•
•
Pre-Clipping Output for Control of a Class-G
Power Supply
The unique pre clipping output signal can be used to
control a Class-G power supply. This combined with
the low idle loss and high power efficiency of the
TAS5614LA leads to industry leading levels of
efficiency ensuring a super “green” system.
Reduced Heat Sink Size due to use of 60mΩ
Output MOSFET with >90% Efficiency at Full
Output Power
•
•
Output Power at 10%THD+N
The TAS5614LA uses constant voltage gain. The
internally matched gain resistors ensure a high Power
Supply Rejection Ratio giving an output voltage only
dependent on the audio input voltage and free from
any power supply artifacts.
–
–
150 W / 4 Ω BTL Stereo Configuration
300 W / 2 Ω in PBTL Mono Configuration
Output Power at 1%THD+N
–
–
125 W / 4 Ω BTL Stereo Configuration
65 W / 8 Ω BTL Stereo Configuration
The high integration of the TAS5614LA makes the
amplifier easy to use and using TI’s reference
schematics and PCB layouts leads to fast design in
time. The TAS5614LA is available in the space
saving surface mount 44-pin HTSSOP package.
PowerPAD™ PurePath™ HD
•
•
Click and Pop Free Startup
Error Reporting Self-protected Design with
UVP, Over Temperature, and Short Circuit
Protection
•
•
EMI Compliant when used with Recommended
System Design
44-Pin HTSSOP (DDV) Package for Reduced
Board Size
PurePath HDTM
TAS5614LA
TASxxxx
Digital Audio
Processor
DIGITAL
AUDIO
INPUT
APPLICATIONS
+12V
18V-36V
•
•
•
•
Blu-ray™/DVD Receivers
High Power Sound Bars
PurePath HDTM
+3.3V
REG.
Class G Power Supply
Ref design
Powered Subwoofer and Active Speakers
Mini Combo Systems
105VAC
240VAC
→
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
PowerPAD, PurePath are trademarks of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disk Association (BDA).
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TAS5614LA
SLAS846 –MAY 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5614LA is available in a thermally enhanced package:
44-Pin HTSSOP package (DDV)
•
The package contains a PowerPAD™ that is located on the top side of the device for convenient thermal
coupling to the heat sink.
44 PIN
DDV PACKAGE
(TOP VIEW)
GVDD_AB
VDD
BST_A
BST_B
GND
OC_ADJ
RESET
INPUT_A
INPUT_B
C_START
GND
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
DVDD
GND
GND
GND
GND
GND
GND
AVDD
OUT_C
PVDD_CD
PVDD_CD
INPUT_C
INPUT_D
FAULT
OTW
PVDD_CD
OUT_D
CLIP
M1
OUT_D
GND
GND
M2
M3
BST_C
BST_D
GVDD_CD
2
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SLAS846 –MAY 2012
PIN FUNCTIONS
DESCRIPTION
PIN NAME
AVDD
PINOUT DDV-44
I/O/P(1)
13
44
43
24
23
18
7
P
P
P
P
P
O
O
P
O
Internal voltage regulator, analog section
Bootstrap pin, A-side
BST_A
BST_B
BST_C
BST_D
CLIP
Bootstrap pin, B-side
Bootstrap pin, C-side
Bootstrap pin, D-side
Clipping warning; open drain; active low
Startup ramp
C_START
DVDD
8
Internal voltage regulator, digital section
Shutdown signal, open drain; active low
FAULT
16
9, 10, 11, 12, 25,
26, 33, 34, 41, 42
GND
P
Ground
GVDD_AB
GVDD_CD
INPUT_A
INPUT_B
INPUT_C
INPUT_D
M1
1
P
P
I
Gate-drive voltage supply; AB-side
Gate-drive voltage supply; CD-side
PWM Input signal for half-bridge A
PWM Input signal for half-bridge B
PWM Input signal for half-bridge C
PWM Input signal for half-bridge D
Mode selection 1 (LSB)
22
5
6
I
14
I
15
I
19
I
M2
20
I
Mode selection 2
M3
21
I
Mode selection 3 (MSB)
OC_ADJ
OTW
3
O
O
O
O
O
O
P
P
I
Over-Current threshold programming pin
Over-temperature warning; open drain; active low
Output, half-bridge A
17
39, 40
35
OUT_A
OUT_B
OUT_C
OUT_D
PVDD_AB
PVDD_CD
RESET
VDD
Output, half-bridge B
32
Output, half-bridge C
27, 28
36, 37, 38
29, 30, 31
4
Output, half-bridge D
PVDD supply for half-bridge A and B
PVDD supply for half-bridge C and D
Device reset Input; active low
Input power supply
2
P
P
PowerPAD™
Ground, connect to grounded heat sink
(1) I = Input, O = Output, P = Power
Table 1. ORDERING INFORMATION(1)
TA
PACKAGE
DESCRIPTION
TAS5614LADDV
TAS5614LADDVR
0°C–70°C
44 pin HTSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5614LA
–0.3 to 13.2
–0.3 to 50
–0.3 to 62.5
–0.3 to 4.2
–0.3 to 8.5
–0.3 to 4.2
–0.3 to 4.2
9
UNIT
V
VDD to GND, GVDD_X(2) to GND
PVDD_X(2) to GND(3), OUT_X to GND(3), BST_X to GVDD_X(2)(3)
BST_X to GND(3)(4)
V
V
DVDD to GND
V
AVDD to GND
V
OC_ADJ, M1, M2, M3, C_START, INPUT_X to GND
RESET, FAULT, OTW, CLIP, to GND
Maximum continuous sink current (FAULT, OTW, CLIP)
Maximum operating junction temperature range, TJ
Storage temperature, Tstg
V
V
mA
°C
°C
°C
kV
V
0 to 150
–40 to 150
260
Lead temperature
Human body model(4) (all pins)
Charged device model(4) (all pins)
±2
Electrostatic discharge
±500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) GVDD_X and PVDD_X represents a full bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD, PVDD_X is
PVDD_AB or PVDD_CD
(3) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
(4) Maximum BST_X to GND voltage is the sum of maximum PVDD to GND and GVDD to GND voltages minus a diode drop.
THERMAL INFORMATION
TAS5614LA
THERMAL METRIC(1)
UNITS
DDV (44-PIN)
θJH
Junction-to-heat sink thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
2.3
0.8
2.1
0.8
2.1
n/a
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil
thickness.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP MAX UNIT
PVDD_X
GVDD_X
VDD
Full-bridge supply
DC supply voltage
DC supply voltage
DC supply voltage
12
36
38
V
V
V
Supply for logic regulators and gate-drive
circuitry
10.8
12 13.2
Digital regulator supply voltage
BTL
10.8
3.0
1.5
1.5
12 13.2
4.0
Output filter: L = 10 µH, 1 µF.
Output AD modulation,
switching frequency > 350 kHz.
RL
Load impedance
SE
3.0
Ω
PBTL
2.0
Minimum inductance at overcurrent limit,
including inductor tolerance, temperature
and possible inductor saturation
LOUTPUT
Output filter inductance
PWM frame rate
5
μH
FPWM
352
384 500 kHz
CPVDD
PVDD close decoupling capacitors
0.44
1
100
1
μF
nF
μF
BTL and PBTL configuration
C_START
Startup ramp capacitor
SE and 1xBTL+2xSE configuration
4
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RECOMMENDED OPERATING CONDITIONS (continued)
MIN
24
47
0
TYP MAX UNIT
ROC
Over-current programming resistor
Over-current programming resistor
Junction temperature
Resistor tolerance = 5%
Resistor tolerance = 5%
33
68
kΩ
kΩ
°C
ROC_LATCHED
TJ
62
125
MODE SELECTION PINS
MODE PINS
PWM Input(1)
Output Configuration
Input A
Input B
Input C
Input D
MODE
M3
0
M2
0
M1
0
2N + 1
1N + 1(2)
2N + 1
2 x BTL
2 x BTL
PWMa
PWMa
PWMa
PWMa
PWMa
PWMa
PWMa
PWMa
PWMb
Unused
PWMb
Unused
PWMb
Unused
PWMb
PWMb
PWMc
PWMc
PWMc
PWMc
0
PWMd
Unused
PWMd
PWMd
0
AD Mode
AD Mode
BD Mode
AD Mode
AD Mode
AD Mode
BD Mode
AD Mode
0
0
1
0
1
0
2 x BTL
0
1
1
1N + 1(2)
1 x BTL + 2 x SE
1 x PBTL
1
0
0
2N + 1
1
0
0
1N + 1(2)
2N + 1
1 x PBTL
0
1
1
0
0
1 x PBTL
4 x SE(3)
1
0
1
0
1
1N + 1
PWMc
PWMd
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.
(3) The 4xSE mode can be used as 1xBTL + 2xSE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for
improved DC offset accuracy
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TYPICAL SYSTEM BLOCK DIAGRAM
Capacitors for
System
microcontroller
External
Filtering
&
/AMP RESET
I2C
Startup/Stop
TASxxxx
PWM Modulator
*NOTE1
/RESET
BST_A
BST_B
VALID
Bootstrap
Capacitors
2nd Order
L-C Output
Filter for
each
PWM_A
PWM_B
INPUT_A
INPUT_B
OUT_A
OUT_B
Left-
Input
H-Bridge 1
Output
H-Bridge 1
Channel
Output
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
2nd Order
L-C Output
Filter for
each
PWM_C
PWM_D
INPUT_C
INPUT_D
OUT_C
OUT_D
Right-
Channel
Output
Input
H-Bridge 2
Output
H-Bridge 2
H-Bridge
M1
BST_C
BST_D
Hardwire
Mode
M2
M3
Bootstrap
Capacitors
Control
Hardwire
PVDD
GND
PVDD
Power Supply
Decoupling
GVDD, VDD,
& VREG
Power Supply
36V
Over-
Current
Limit
SYSTEM
Power
Supplies
Decoupling
GND
12V
GVDD (12V)/VDD (12V)
VAC
(1) Logic AND is inside or outside the micro processor.
6
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SLAS846 –MAY 2012
FUNCTIONAL BLOCK DIAGRAM
/CLIP
/OTW
/FAULT
BST_X
GVDD_X
AVDD
UVP
DVDD
/RESET
MODE1-3
POWER-UP
RESET
AVDD
VDD
AVDD
DVDD
TEMP
SENSE
CB3C OVER-
LOAD
DVDD
PROTECTION
STARTUP
CONTROL
C_START
BST_A
PVDD_AB
OUT_A
GND
PWM
RECEIVER
INPUT_A
PWM &
TIMING
+
-
ANALOG
GATE-DRIVE
LOOP FILTER
CONTROL
GVDD_AB
BST_B
PVDD_AB
OUT_B
GND
PWM
RECEIVER
INPUT_B
INPUT_C
INPUT_D
PWM &
TIMING
+
-
ANALOG
LOOP FILTER
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
CONTROL
BST_C
PVDD_CD
OUT_C
GND
PWM
PWM &
TIMING
CONTROL
+
-
RECEIVER
ANALOG
LOOP FILTER
GVDD_CD
BST_D
PVDD_CD
OUT_D
GND
PWM
PWM &
TIMING
+
-
RECEIVER
ANALOG
LOOP FILTER
CONTROL
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AUDIO SPECIFICATION STEREO (BTL)
Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and
a TAS5614LA power stage with PCB and system configurations in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 36V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM
10 μH, CDEM = 1 µF, unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
RL = 4 Ω, 10% THD+N
MIN
TYP MAX UNIT
150
125
0.03
180
10
PO
Power output per channel
W
RL = 4 Ω, 1% THD+N
THD+N
Vn
Total harmonic distortion + noise
Output integrated noise
Output offset voltage
Signal-to-noise ratio(1)
Dynamic range
1 W, 1 kHz signal
%
μV
mV
dB
dB
A-weighted, AES17 measuring filter
No signal
VOS
20
SNR
DNR
A-weighted, AES17 measuring filter
A-weighted, –60 dBFS (rel 1% THD+N)
105
105
Power dissipation due to Idle losses
(IPVDD_X)
Pidle
PO = 0, channels switching(2)
1.6
W
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
AUDIO SPECIFICATION 4 CHANNELS (SE)
Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and
a TAS5614LA power stage with PCB and system configurations in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 36V, GVDD_X = 12V, RL = 4Ω, fS = 384 kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM
10μH, CDEM = 1µF, CDCB = 470µF, unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
RL = 3 Ω, 10% THD+N
MIN
TYP MAX UNIT
50
PO
Power output per channel
W
RL = 3 Ω, 1% THD+N
42
THD+N
Vn
Total harmonic distortion + noise
Output integrated noise
Signal-to-noise ratio(1)
Dynamic range
1 W, 1 kHz signal
0.025
180
%
A-weighted, AES17 measuring filter
A-weighted, AES17 measuring filter
A-weighted, –60 dBFS (rel 1% THD+N)
μV
dB
dB
SNR
DNR
102
102
Power dissipation due to Idle losses
(IPVDD_X)
Pidle
PO = 0, channels switching(2)
1.6
W
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
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AUDIO SPECIFICATION MONO (PBTL)
Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and
a TAS5614LA power stage with PCB and system configurations in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 36V, GVDD_X = 12V, RL = 4Ω, fS = 384kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM
10μH, CDEM = 1μF, unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
RL = 2 Ω, 10%, THD+N
MIN
TYP MAX UNIT
300
200
RL = 3 Ω, 10% THD+N
RL = 4 Ω, 10% THD+N
RL = 2 Ω, 1% THD+N
160
PO
Power output per channel
W
250
RL = 3 Ω, 1% THD+N
160
130
RL = 4 Ω, 1% THD+N
THD+N
Vn
Total harmonic distortion + noise
Output integrated noise
Output offset voltage
Signal to noise ratio(1)
Dynamic range
1 W, 1 kHz signal
0.025
180
10
%
μV
mV
dB
dB
A-weighted, AES17 measuring filter
No signal
VOS
20
SNR
DNR
A-weighted, AES17 measuring filter
A-weighted, –60 dBFS (rel 1% THD)
105
105
Power dissipation due to idle losses
(IPVDD_X)
Pidle
PO = 0, All channels switching(2)
1.6
W
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as a
DVDD
VDD = 12 V
3.0
3.3
7.8
3.6
V
V
reference node
Voltage regulator, only used as a
reference node
AVDD
VDD = 12 V
Operating, 50% duty cycle
Idle, reset mode
20
20
IVDD
VDD supply current
mA
mA
50% duty cycle
9
IGVDD_X
Gate-supply current per full-bridge
Reset mode
2
50% duty cycle without load
RESET low
23
IPVDD_X
Full-bridge idle current
1.9
0.35
mA
VDD and GVDD_X at 0V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side
RDS(on), LS
60
60
100
100
mΩ
mΩ
(LS)
TJ = 25°C, excludes metalization resistance,
GVDD = 12 V
Drain-to-source resistance, high side
(HS)
RDS(on), HS
I/O PROTECTION
Vuvp,GVDD
8.5
0.7
8.5
0.7
8.5
0.7
125
V
V
Undervoltage protection limit, GVDD_X
Undervoltage protection limit, VDD
(1)
Vuvp,GVDD, hyst
Vuvp,VDD
V
(1)
Vuvp,VDD, hyst
V
Vuvp,PVDD
V
Undervoltage protection limit, PVDD_X
Overtemperature warning
(1)
Vuvp,PVDD,hyst
OTW(1)
V
115
145
135
165
°C
Temperature drop needed below OTW
temperature for OTW to be inactive
after OTW event.
(1)
OTWhyst
25
°C
°C
OTE(1)
Overtemperature error
155
(1) Specified by design.
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
OTE-OTWdifferential
OTE-OTW differential
30
°C
A device reset is needed to clear
FAULT after an OTE event
(1)
OTEHYST
25
2.6
15
°C
ms
A
OLPC
IOC
Overload protection counter
Overcurrent limit protection
fPWM = 384 kHz
Resistor – programmable, nominal peak current in
1Ω load, ROC = 24 kΩ
Resistor – programmable, nominal peak current in
1Ω load, ROC = 62 kΩ
IOC_LATCHED
IOCT
Overcurrent limit protection, latched
Overcurrent response time
15
150
3
A
Time from application of short condition to Hi-Z of
affected half bridge
ns
Internal pulldown resistor at output of
each half bridge
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
IPD
mA
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
1.9
V
V
INPUT_X, M1, M2, M3, RESET
VIL
Low level input voltage
Input leakage current
0.8
LEAKAGE
100
μA
OTW / SHUTDOWN (FAULT)
Internal pullup resistance, OTW, CLIP,
FAULT to DVDD
RINT_PU
20
3
26
33
kΩ
VOH
High level output voltage
Low level output voltage
Device fanout OTW, FAULT, CLIP
Internal pullup resistor
IO = 4mA
3.3
200
30
3.6
V
VOL
500
mV
FANOUT
No external pullup
devices
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
Measurement conditions are: 1kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20Hz to 20kHz BW (AES17 low pass filter), unless otherwise noted.
OUTPUT POWER vs SUPPLY VOLTAGE
TOTAL HARMONIC+NOISE vs
OUTPUT POWER, 1kHz
vs
DISTORTION + NOISE = 10%
10
200
180
160
140
120
100
80
4Ω
8Ω
4Ω
8Ω
1
0.1
60
40
20
0.01
TC = 75°C
THD+N at 10%
TC = 75°C
100 200
0.005
0
0.02
0.1
1
10
10
15
20
25
30
35 40
PVDD − Supply Voltage − V
PO − Output Power − W
G001
G003
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
OUTPUT POWER vs SUPPLY VOLTAGE, vs
DISTORTION + NOISE = 1%
vs FREQUENCY, 4Ω
10
1
160
140
120
100
80
1 W
10 W
100 W
4Ω
8Ω
0.1
60
0.01
0.001
40
20
TC = 75°C
10k 20k
TC = 75°C
35 40
0
20
100
1k
10
15
20
25
30
Frequency − Hz
PVDD − Supply Voltage − V
G002
G004
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
Measurement conditions are: 1kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20Hz to 20kHz BW (AES17 low pass filter), unless otherwise noted.
SYSTEM EFFICIENCY vs
OUTPUT POWER
SYSTEM POWER LOSS vs
OUTPUT POWER
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
4Ω
8Ω
4Ω
8Ω
TC = 75°C
400
TC = 75°C
400
0
0
0
100
200
300
0
100
200
300
2 Channel Output Power − W
2 Channel Output Power − W
G005
G006
Figure 5.
Figure 6.
OUTPUT POWER vs
TEMPERATURE
NOISE AMPLITUDE vs
FREQUENCY
200
180
160
140
120
100
80
0
−10
−20
−30
−40
−50
−60
−70
−80
TC = 75°C
VREF = 22.5 V
Sample Rate = 48kHz
FFT Size = 16384
4Ω
−90
−100
−110
−120
−130
−140
−150
−160
−170
−180
−190
−200
60
40
20
4Ω
8Ω
THD+N at 10%
0
−10
0
10 20 30 40 50 60 70 80 90 100 110
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
f − Frequency − Hz
TC − Case Temperature −°C
G007
G008
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS, SE CONFIGURATION
Measurement conditions are: 1kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24kΩ, TC = 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, CDCB = 470 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise
noted.
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
OUTPUT POWER vs
SUPPLY VOLTAGE
10
100
80
60
40
20
0
2Ω
3Ω
4Ω
2Ω
3Ω
4Ω
1
0.1
0.01
TC = 75°C
THD+N at 10%
TC = 75°C
100
0.005
0.02
0.1
1
10
10
15
20
25
30
35
40
PVDD − Supply Voltage − V
PO − Output Power − W
G009
G010
Figure 9.
Figure 10.
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
Measurement conditions are: 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24kΩ, TC = 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
OUTPUT POWER vs
SUPPLY VOLTAGE
10
400
350
300
250
200
150
100
50
2Ω
3Ω
4Ω
2Ω
3Ω
4Ω
1
0.1
0.01
TC = 75°C
TC = 75°C
100 400
THD+N at 10%
0.005
0
0.02
0.1
1
10
10
15
20
25
30
35
40
PVDD − Supply Voltage − V
PO − Output Power − W
G011
G012
Figure 11.
Figure 12.
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5614LA needs only a 12V supply in addition to the (typical) 36 V power-
stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and
output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
bootstrap pins (BST_X) and each full-bridge has separate power stage supply (PVDD_X) and gate supply
(GVDD_X) pins. Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although
supplied from the same 12 V source, it is highly recommended to separate GVDD_AB, GVDD_CD, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X
connection is decoupled with minimum 2x 220 nF ceramic capacitors placed as close as possible to each supply
pin. It is recommended to follow the PCB layout of the TAS5614LA reference design. For additional information
on recommended power supply and required components, see the application diagrams in this data sheet.
The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36 V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the TAS5614LA is fully protected against
erroneous power-stage turn on due to parasitic gate charging when power supplies are applied. Thus, voltage-
supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating
Conditions table of this data sheet).
Boot Strap Supply
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300kHz to 400 kHz, it is recommended to use 33 nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5614LA does not require a power-up sequence. The outputs of the H-bridges remain in a high-
impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not
specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows
an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge
output.
Powering Down
The TAS5614LA does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
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STARTUP AND SHUTDOWN RAMP SEQUENCE
The integrated startup and stop sequence ensures a click and pop free startup and shutdown sequence of the
amplifier. The startup sequence uses a voltage ramp with a duration set by the CSTART capacitor. The
sequence uses the input PWM signals to generate output PWM signals, hence input idle PWM should be present
during both startup and shut down ramping sequences.
VDD, GVDD_X and PVDD_X power supplies must be turned on and with settled outputs before starting
the startup ramp by setting RESET high.
During startup and shutdown ramp the input PWM signals should be in muted condition with the PWM processor
noise shaper activity turned off (50% duty cycle).
The duration of the startup and shutdown ramp is 100 ms + X ms, where X is the CSTART capacitor value in nF.
It is recommended to use 100nF CSTART in BTL and PBTL mode and 1 µF in SE mode configuration. This
results in ramp times of 200 ms and 1.1s respectively. The longer ramp time in SE configuration allows charge
and discharge of the output AC coupling capacitor without audible artifacts.
STARTUP/SHUTDOWN RAMP
Ramp Start
Ramp End
Ramp Start
Ramp End
3.3V
0V
/RESET
INPUT_X
OUT_X
3.3V
Hi-Z
0V
INPUT_X IS SWITCHING (MUTE)
NOISE SHAPER OFF
INPUT_X IS SWITCHING (MUTE)
NOISE SHAPER OFF
(UNMUTED)
(UNMUTED)
PVDD_X
Hi-Z
OUT_X IS SWITCHING (MUTE)
OUT_X IS SWITCHING (MUTE)
0V
VI_CM
DC_RAMP
0V
50%
PVDD_X/2
0V
SPEAKER OUT_X
tStartup Ramp
tStartup Ramp
INPUT_X IS SWITCHING (MUTE)
NOISE SHAPER ON
UNUSED OUTPUT CHANNELS
If all available output channels are not used, it is recommended to disable switching of unused output nodes to
reduce power consumption. Furthermore by disabling unused output channels the cost of unused output LC
demodulation filters can be avoided.
Disabling a channel is done by leave the bootstrap capacitor (BST) unstuffed and connecting the respective input
to GND. The unused output pin(s) can be left floating. Please note that the PVDD decoupling capacitors still
need to be mounted.
Table 2. Unused Output Channels
Operating
Mode
PWM
Input
Output
Configuration
Unused
Channel
INPUT_A
INPUT_B
INPUT_C
INPUT_D
Unstuffed Component
000
001
010
2N + 1
1N + 1
2N + 1
AB
CD
GND
PWMa
GND
PWMb
PWMc
GND
PWMd
GND
BST_A & BST_B capacitor
BST_C & BST_D capacitor
2 x BTL
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Table 2. Unused Output Channels (continued)
Operating
Mode
PWM
Input
Output
Configuration
Unused
Channel
INPUT_A
INPUT_B
INPUT_C
INPUT_D
Unstuffed Component
A
B
C
D
GND
PWMb
GND
PWMc
PWMc
GND
PWMd
PWMd
PWMd
GND
BST_A capacitor
BST_B capacitor
BST_C capacitor
BST_D capacitor
PWMa
PWMa
PWMa
101
1N + 1
4 x SE
PWMb
PWMb
PWMc
DEVICE PROTECTION SYSTEM
The TAS5614LA contains advanced protection circuitry carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions
such as short circuits, overload, overtemperature, and undervoltage. The TAS5614LA responds to a fault by
immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In
situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault
condition has been removed, i.e., the supply voltage has increased.
The device will function on errors, as shown in the following table.
Table 3. Device Protection
BTL Mode
Channel Fault
PBTL Mode
Channel Fault
SE Mode
Channel Fault
Turns Off
Turns Off
Turns Off
A
B
C
D
A+B
A
B
C
D
A+B+C+D
A
B
C
D
A+B
C+D
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective high-side FET.
spacer
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND or PVDD_X. For comparison, the OC protection system detects an over current after the
demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at
startup i.e. when VDD is supplied, consequently a short to either GND or PVDD_X after system startup will not
activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges
are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence and starts
switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no
shorts from OUT_X to GND, the second step tests that there are no shorts from OUT_X to PVDD_X. The total
duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is
<15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will not react to changes
applied to the RESET pins. If no shorts are present the PPSC detection passes, and FAULT is released. A
device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it
is recommended not to insert resistive load to GND or PVDD_X.
OVERTEMPERATURE PROTECTION
The TAS5614LA has a two-level temperature-protection system that asserts an active-low warning signal (OTW)
when the device junction temperature exceeds 125°C (typical). If the device junction temperature exceeds 155°C
(typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-
impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,
RESET must be asserted. Thereafter, the device resumes normal operation.
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OVERTEMPERATURE WARNING, OTW
The over temperature warning OTW asserts when the junction temperature has exceeded recommended
operating temperature. Operation at junction temperatures above OTW threshold is exceeding recommended
operation conditions and is strongly advised to avoid.
If OTW asserts, action should be taken to reduce power dissipation to allow junction temperature to decrease
until it gets below the OTW hysteresis threshold. This action can be decreasing audio volume or turning on a
system cooling fan.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5614LA fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
ERROR REPORTING
Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system micro controller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and OTW
outputs.
The FAULT, OTW, pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a
PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125°C (see the following table).
Table 4. Error Reporting
FAULT
OTW
DESCRIPTION
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
Overload (OLP) or undervoltage (UVP)
0
0
1
1
0
1
0
1
Junction temperature higher than 125°C (overtemperature warning)
Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
FAULT HANDLING
If a fault situation occurs while in operation, the device will act accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and will cause all PWM activity of the device to be shut down,
and will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires
resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW signal is cleared (high). A channel fault will result in shutdown of the PWM activity of
the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults
being present. TI recommends monitoring the OTW signal using the system micro controller and responding to
an over temperature warning signal by, e.g., turning down the volume to prevent further heating of the device
resulting in device shutdown (OTE).
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Table 5. Fault Handling
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Fault/Event
Action needed to Clear
Output FETs
PVDD_X UVP
VDD UVP
Increase affected supply
voltage
Voltage Fault
Global
FAULT Pin
Self Clearing
Hi-Z
GVDD_X UVP
AVDD UVP
Power On
Reset
POR (DVDD UVP)
BST UVP
Global
FAULT Pin
None
Self Clearing
Self Clearing
Self Clearing
Latched
Allow DVDD to rise
H-Z
HighSide Off
Normal operation
Hi-Z
Allow BST cap to recharge
(low side on, VDD 12V)
Channel (half
bridge)
Voltage Fault
Thermal
Warning
Cool below lower OTW
threshold
OTW
Global
Global
OTW Pin
FAULT Pin
Thermal
Shutdown
OTE (OTSD)
Toggle RESET
OLP (CBC >2.6ms)
OC shutdown
OC shutdown
Channel
Channel
FAULT Pin
FAULT Pin
Latched
Latched
Toggle RESET
Toggle RESET
Hi-Z
Hi-Z
Latched OC (ROC >47k)
reduce signal level or
remove short
Flip state, cycle by
cycle at fs/2
CBC (24k<ROC<33k)
OC Limiting
No PWM
Channel
Channel
Global
None
None
None
Self Clearing
Self Clearing
Self Clearing
Stuck at Fault(1) (1 to 3
channels)
Stuck at Fault(2) (All
channels)
resume PWM
resume PWM
Hi-Z
Hi-Z
No PWM
(1) Stuck at Fault occurs when input PWM drops below minimum PWM frame rate given in Recommended Operating Conditions.
(2) Stuck at Fault occurs when input PWM drops below minimum PWM frame rate given in Recommended Operating Conditions.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the
FAULT output, i.e., FAULT is forced high. A rising-edge transition on reset input allows the device to resume
operation after an overload fault. To ensure thermal reliability, the rising edge of RESET must occur no sooner
than 4 ms after the falling edge of FAULT.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply audio only according to the timing information for startup and shutdown sequence. That will start and stop
the amplifier without audible artifacts in the output transducers.
The CLIP signal indicates that the output is approaching clipping (when output PWM starts skipping pulses due
to loop filter saturation). The signal can be used to initiate an audio volume decrease or to adjust the power
supply rail.
The device inverts the audio signal from input to output.
The DVDD and AVDD pins are not recommended to be used as a voltage source for external circuitry.
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APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 Glass Epoxy material with 1 oz. (35 μm) is recommended for use with the TAS5614LA. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50 V should support most
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with
high-speed switching.
DECOUPLING CAPACITOR RECOMMENDATION
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, good quality decoupling capacitors should be used. In practice, X5R or better should be used in
this application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the close decoupling capacitor that is placed on the power supply to each half-bridge. It must
withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power
output, and the ripple current created by high power output. A minimum voltage rating of 50V is required for use
with a 36 V power supply.
See the TAS5614LADDVEVM User's Guide for more details including layout and Bill-of-Materials.
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TYPICAL BTL APPLICATION
TAS5614LA
Figure 13. Typical Differential (2N) BTL Application with AD Modulation Filters
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TYPICAL SE CONFIGURATION
TAS5614LA
Figure 14. Typical (1N) SE Application
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TYPICAL PBTL CONFIGURATION
TAS5614LA
Figure 15. Typical Differential (2N) PBTL Application with AD Modulation Filter
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CIRCUIT COMPONENT AND PRINTED CIRCUIT BOARD RECOMMENDATION
These requirements must be followed to achieve best performance and reliability and minimum ground bounce at
rated output power of TAS5614LA.
CIRCUIT COMPONENT REQUIREMENTS
A number of circuit components are critical to performance and reliability. They include LC filter inductors and
capacitors, decoupling capacitors and the heatsink. The best detailed reference for these is the TAS5614LA
EVM BOM in the user's guide, which includes components that meet all the following requirements.
•
High frequency decoupling capacitors: small high frequency decoupling capacitors are placed next to the IC
to control switching spikes and keep high frequency currents in a tight loop to achieve best performance and
reliability and EMC. They must be high quality ceramic parts with material like X7R or X5R and voltage
ratings at least 30% greater than PVDD, to minimize loss of capacitance caused by applied DC voltage.
(Capacitors made of materials like Y5V or Z5U should never be used in decoupling circuits or audio circuits
because their capacitance falls dramatically with applied DC and AC voltage, often to 20% of rated value or
less.)
•
•
Bulk decoupling capacitors: large bulk decoupling capacitors are placed as close as possible to the IC to
stabilize the power supply at lower frequencies. They must be high quality aluminum parts with low ESR and
ESL and voltage ratings at least 25% more than PVDD to handle power supply ripple currents and voltages
LC filter inductors: to maintain high efficiency, short circuit protection and low distortion, LC filter inductors
must be linear to at least the OCP limit and must have low DC resistance and core losses. For SCP,
minimum working inductance, including all variations of tolerance, temperature and current level, must be
5µH. Inductance variation of more than 1% over the output current range can cause increased distortion.
•
•
LC filter capacitors: to maintain low distortion and reliable operation, LC filter capacitors must be linear to
twice the peak output voltage. For reliability, capacitors must be rated to handle the audio current generated
in them by the maximum expected audio output voltage at the highest audio frequency.
Heatsink:The heatsink must be fabricated with the PowerPad contact area spaced 1.0mm +/-0.01mm above
mounting areas that contact the PCB surface. It must be supported mechanically at each end of the IC. This
mounting ensures the correct pressure to provide good mechanical, thermal and electrical contact with
TAS5614LA PowerPAD. The PowerPAD contact area must be bare and must be interfaced to the PowerPAD
with a thin layer (about 1mil) of a thermal compound with high thermal conductivity.
PRINTED CIRCUIT BOARD REQUIREMENTS
PCB layout, audio performance, EMC and reliability are linked closely together, and solid grounding improves
results in all these areas. The circuit produces high, fast-switching currents, and care must be taken to control
current flow and minimize voltage spikes and ground bounce at IC ground pins. Critical components must be
placed for best performance and PCB traces must be sized for the high audio currents that the IC circuit
produces.
Grounding: ground planes must be used to provide the lowest impedance and inductance for power and audio
signal currents between the IC and its decoupling capacitors, LC filters and power supply connection. The area
directly under the IC should be treated as central ground area for the device, and all IC grounds must be
connected directly to that area. A matrix of vias must be used to connect that area to the ground plane. Ground
planes can be interrupted by radial traces (traces pointing away from the IC), but they must never be interrupted
by circular traces, which disconnect copper outside the circular trace from copper between it and the IC. Top and
bottom areas that do not contain any power or signal traces should be flooded and connected with vias to the
ground plane.
Decoupling capacitors: high frequency decoupling capacitors must be located within 2mm of the IC and
connected directly to PVDD and GND pins with solid traces. Vias must not be used to complete these
connections, but several vias must be used at each capacitor location to connect top ground directly to the
ground plane. Placement of bulk decoupling capacitors is less critical, but they still must be placed as close as
possible to the IC with strong ground return paths. Typically the heatsink sets the distance.
LC filters: LC filters must be placed as close as possible to the IC after the decoupling capacitors. The capacitors
must have strong ground returns to the IC through top and bottom grounds for effective operation.
Copyright © 2012, Texas Instruments Incorporated
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TAS5614LA
SLAS846 –MAY 2012
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PCB copper must be at least 1 ounce thickness. PVDD and output traces must be wide enough to carry
expected average currents without excessive temperature rise. PWM input traces must be kept short and close
together on the input side of the IC and must be shielded with ground flood to avoid interference from high power
switching signals.
The heatsink must be grounded well to the PCB near the IC, and a thin layer of highly conductive thermal
compound (about 1mil) must be used to connect the heatsink to the PowerPAD.
T5
T1
T2
T3
T5
T6
Note T1: Bottom and top layer ground plane areas are used to provide strong ground connections. The area under
the IC must be treated as central ground, with IC grounds connected there and a strong via matrix connecting the
area to bottom ground plane. The ground path from the IC to the power supply ground through top and bottom layers
must be strong to provide very low impedance to high power and audio currents.
Note T2: Low impedance X7R or X5R ceramic high frequency decoupling capacitors must be placed within 2mm of
PVDD and GND pins and connected directly to them and to top ground plane to provide good decoupling of high
frequency currents for best performance and reliability. Their DC voltage rating must be 2 times PVDD.
Note T3: Low impedance electrolytic bulk decoupling capacitors must be placed as close as possible to the IC.
Typically the heat sink sets the distance. Wide PVDD traces are routed on the top layer with direct connections to the
pins, without going through vias.
Note T4: LC filter inductors and capacitors must be placed as close as possible to the IC after decoupling capacitors.
Inductors must have low DC resistance and switching losses and must be linear to at least the OCP (over current
protection) limit. Capacitors must be linear to at least twice the maximum output voltage and must be capable of
conducting currents generated by the maximum expected high frequency output.
Note T5: Bulk decoupling capacitors and LC filter capacitors must have strong ground return paths through ground
plane to the central ground area under the IC.
Note T6: The heatsink must have a good thermal and electrical connection to PCB ground and to the IC PowerPAD.
It must be connected to the PowerPAD through a thin layer, about 1 mil, of highly conductive thermal compound.
Figure 16. Printed Circuit Board - Top Layer
24
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TAS5614LA
TAS5614LA
www.ti.com
SLAS846 –MAY 2012
B1
B1
B2
Note B1: A wide PVDD bus and a wide ground path must be used to provide very low impedance to high power and
audio currents to the power supply. Top and bottom ground planes must be connected with vias at many points to
reinforce the ground connections.
Note B2: Wide output traces can be routed on the bottom layer and connected to output pins with strong via arrays.
Figure 17. Printed Circuit Board - Bottom Layer
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TAS5614LADDV
TAS5614LADDVR
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DDV
DDV
44
44
35
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5614LADDVR
HTSSOP DDV
44
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DDV 44
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
TAS5614LADDVR
2000
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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