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TAS5806MD

ZHCSJT7 –MAY 2019

具有增强处理能力和 DirectPath^TMHP 驱动器的 TAS5806MD 23W、无电

感器、数字输入、立体声、闭环 D 类音频放大器

1 特性

2 应用

1

•

支持多路输出配置：

•

LCD 电视、OLED 电视

无线扬声器、智能扬声器（带语音助理）

条形音箱、有线扬声器、书架立体声系统

AV 接收器、智能家居和物联网电器

–

2.0 模式（8Ω、21V、THD+N=1%）下可提供

2 × 23W 的功率

–

单声道模式（4Ω、21V、THD+N=1%）下可提

供 45W 的功率

3 说明

•

优异的音频性能

–

1W、1kHz、PVDD = 12V 的条件下，THD+N

≤ 0.03%

TAS5806MD 是一款高效立体声闭环 D 类放大器，可

提供具有低功率耗散和丰富声音且具有成本效益的数字

输入解决方案。该器件的集成音频处理器和 96kHz 架

构支持高级音频处理流程（包括 SRC、每通道 15 个

BQ、音量控制、音频混合、3 频带 4 阶 DRC、全频带

AGL、THD 管理器和电平计）。

–

SNR ≥ 107dB（A 加权），噪声级别

< 40µVrms

•

灵活的电源配置

–

PVDD：4.5V 至 26.4V

DVDD 和 I/O：1.8V 或 3.3V

TAS5806MD 采用 TI 的专有混合调制方案，消耗极低

的静态电流（13.5V PVDD 下为 16.5mA），从而能够

延长便携式音频应用中的电池寿命。凭借先进的 EMI

抑制技术，对低于 10W 的应用，设计人员可利用廉

价的铁氧体磁珠滤波器来减小其布板空间并降低系统成

本。该器件配有集成 DirectPath^TM耳机放大器和线路

驱动器，可提高系统级集成度并降低解决方案总成本。

灵活的音频 I/O

–

I²S、LJ、RJ、TDM、3 线数字音频接口（无需

MCLK）

–

支持 32、44.1、48、88.2、96kHz 采样率

用于音频监控、子通道或回声消除的 SDOUT

•

增强的音频处理能力

–

多频带高级 DRC 和 AGL

器件信息⁽¹⁾

2×15 个 BQ、热折返、直流阻断

输入混合器、输出交叉开关、电平计

器件型号

封装

封装尺寸（标称值）

5 个 BQ + 单频带 DRC + THD 管理器（用于低

音炮通道）

TAS5806MD

TSSOP (38)

9.7mm × 4.4mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

–

声场定位器选项

Speaker

L Channel

Speaker

R Channel

•

集成式自保护功能

–

邻近的引脚对引脚短路且无损坏

过流错误

过温警告和错误

欠压、过压锁定（UVLO、OVLO）

可轻松进行系统集成

–

I²C 软件控制

解决方案尺寸更小

1.8V or 3.3V

–

与开环器件相比，所需的无源器件更少

4.5V-26.4V

3.3V

对于 PVDD ≤ 14V 的大多数情况，可实现无

电感器运行（铁氧体磁珠）

System

Processor

Headphone IN

(Single-Ended)

Digital Audio Source

Copyright

–

立体声耳机和立体声线路驱动器通过 I²C 调

节增益

DirectPath 技术不再需要大容量的隔直电容

器

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEO2

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

9.4 Device Functional Modes........................................ 29

9.5 Programming and Control....................................... 34

9.6 Register Maps......................................................... 40

10 Application and Implementation........................ 73

10.1 Application Information.......................................... 73

10.2 Typical Applications ............................................. 75

11 Power Supply Recommendations ..................... 81

11.1 DVDD Supply........................................................ 81

11.2 PVDD Supply ........................................................ 82

12 Layout................................................................... 83

12.1 Layout Guidelines ................................................. 83

12.2 Layout Example .................................................... 85

13 器件和文档支持 ..................................................... 86

13.1 器件支持................................................................ 86

13.2 接收文档更新通知 ................................................. 86

13.3 社区资源................................................................ 87

13.4 商标....................................................................... 87

13.5 静电放电警告......................................................... 87

13.6 Glossary................................................................ 87

14 机械、封装和可订购信息....................................... 87

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements ............................................... 9

7.7 Typical Characteristics............................................ 10

Parametric Measurement Information ............... 22

Detailed Description ............................................ 23

9.1 Overview ................................................................. 23

9.2 Functional Block Diagram ....................................... 23

9.3 Feature Description................................................. 24

8

9

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2019 年 5 月

*

初始发行版。

2

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

5 Device Comparison Table

ORDERABLE PART

NUMBER

RECOMMENDED

PVDD RANGE

Headphone/Line

Driver integrated

R_DS(ON)OPTION

Package

TAS5806MD

TAS5806M

TAS5805M

TAS5825M

4.5 V to 26.4 V

180 mΩ

90 mΩ

TSSOP38 (DCP)

TSSOP28 (PWP)

QFN32 (RHB)

YES

NO

6 Pin Configuration and Functions

DCP Package

38-Pin TSSOP

Top View

BST_A-

OUT_A-

PGND

1

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

BST_B-

2

OUT_B-

PGND

BST_B+

OUT_B+

PVDD

AGND

AVDD

PDN

3

BST_A+

OUT_A+

PVDD

4

5

6

PVDD

7

DGND

8

DVDD

9

Thermal

Pad

ADR/FAULT

VR_DIG

DGND

10

11

12

13

14

15

16

17

18

19

SCL

SDA

LRCLK

SCLK

SDOUT

CPP

SDIN

NC

HP_GND

HPVDD

HPR_IN

HPL_IN

CPN

HPVSS

HPL_OUT

HPR_OUT

Not to scale

3

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate

drive for OUT_A-

BST_A-

1

P

OUT_A-

PGND

2

AO

G

Negative pin for differential speaker amplifier output A-

3, 36

Ground reference for power device circuitry. Connect this pin to system ground.

Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side

gate drive for OUT_A+

BST_A+

OUT_A+

PVDD

4

5

P

AO

P

Positive pin for differential speaker amplifier output A+

PVDD voltage input

6, 7, 32,

33

DGND

DVDD

8, 12

9

G

P

Digital ground

3.3-V or 1.8-V digital power supply

Different I²C device address can be set by selecting different pull up resistor to DVDD, see Table 3 for details.

After power up, ADR/FAULT can be redefine as FAULT, go to Page0, Book0, set register 0x61 = 0x0b first, then

set register 0x60 = 0x01

ADR/FAULT

VR_DIG

10

11

13

DIO

P

Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices

Word select clock for the digital signal that is active on the serial port's input data line. In I²S, LJ and RJ, this

corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync

boundary.

LRCLK

DI

SCLK

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DI

G

Bit clock for the digital signal that is active on the input data line of the serial data port.

Data line to the serial data port

SDIN

HP_GND

HPVDD

HPR_IN

HPL_IN

HPR_OUT

HPL_OUT

HPVSS

CPN

Headphone Ground

P

Headphone Positive Power Supply

AI

AO

P

Headphone In Right

Headphone In Left

Headphone Out Right

Headphone Out Left

Headphone Negative Power Supply (Generated Internally)

Negative connection point for charge pump fly cap

No Connect Pin. Can be shorted to PVCC or shorted to GND or left open.

Positive connection point for charge pump fly cap

Serial Audio data output, the source data can select as Pre-DSP or Post DSP, by setting the register 0x30h.

I2C serial control data interface input/output

I2C serial control clock input

NC

CPP

SDOUT

SDA

DO

DI/O

DI

SCL

Power Down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators. Low, Power Down

Device; High, Enable Device.

PDN

29

DI

AVDD

30

31

34

P

G

Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices

Analog ground

AGND

OUT_B+

AO

Positive pin for differential speaker amplifier output B+

Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side

gate drive for OUT_B+

BST_B+

35

37

38

P

AO

P

OUT_B-

Negative pin for differential speaker amplifier output B

Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate

drive for OUT_B-

BST_B-

PowerPAD™

P

Connect to the system Ground

(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =

Power, G = Ground (0 V)

4

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

7 Specifications

7.1 Absolute Maximum Ratings

Free-air room temperature 25°C (unless otherwise noted)

(1)

MIN

–0.3

MAX

3.9

UNIT

V

DVDD, HPVDD

PVDD

Low-voltage digital supply

PVDD supply

30

V

-(HPVDD +

0.5)

+(HPVDD +

0.5)

Input Voltage

HPL_IN, HPR_IN

V

V_I(DigIn)

V_{I(SPK_OUTxx)}

T_A

DVDD referenced digital inputs⁽²⁾

Voltage at speaker output pins

Ambient operating temperature,

Storage temperature

–0.5

–0.3

–25

–40

V_DVDD+ 0.5

V

32

85

°C

T_stg

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) DVDD referenced digital pins include: ADR/FAULT, LRCLK, SCLK, SCL, SDA, SDIN, PDN

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3

NOM

MAX

3.63

26.4

UNIT

HPVDD

3.3

V_(POWER)

Power supply inputs

DVDD

1.62

4.5

3.2

4.8

1.6

2.4

1

V

PVDD

BTL Mode (4.5V<PVDD<16V)

BTL Mode (16V<PVDD<24V)

PBLT Mode (4.5V<PVDD<16V)

PBLT Mode (16V<PVDD<24V)

4

6

Ω

R_SPK

Minimum speaker load

2

Ω

3

Ω

L_OUT

Minimum inductor value in LC filter under short-circuit condition

4.7

µH

Headphone-mode load

impedance (HPL/HPR)

R_hp_L

16

1

32

10

Ω

Line-driver-mode load

impedance (HPL/HPR)

R_ln_L

kΩ

7.4 Thermal Information

TAS5806MD

TSSOP (DCP)

38 PINS

THERMAL METRIC⁽¹⁾

UNIT

JEDEC

STANDARD

2-LAYER PCB

JEDEC

STANDARD

4-LAYER PCB

TAS5806MDEVM-4

4-LAYER PCB

R_θJA

Junction-to-ambient thermal resistance

-

29.2

23.3

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

18

-

9.6

0.8

9.5

2.4

-

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.5

8.4

-

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

7.5 Electrical Characteristics

Free-air room temperature 25°C, DVDD=3.3V, 1SPW Modulation Mode with LC filter, BD Modulation Mode with Ferrite bead

filter (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL I/O

|I_IH

Input logic high current level

for DVDD referenced digital

input pins

|

V_IN(DigIn)= V_DVDD

10

µA

Input logic low current level

for DVDD referenced digital

input pins

|I_IL|

V_IN(DigIn)= 0 V

–10

Input logic high threshold for

DVDD referenced digital

inputs

V_IH(Digin)

70%

80%

V_DVDD

Input logic low threshold for

DVDD referenced digital

inputs

V_IL(Digin)

30%

V_DVDD

Output logic high voltage

level

V_OH(Digin)

I_OH= 2 mA

V_DVDD

V_OL(Digin)

Output logic low voltage level I_OH= –2 mA

20%

400

I²C CONTROL PORT

Allowable load capacitance

for each I²C Line

C_L(I2C)

pF

f_SCL(fast)

f_SCL(slow)

SERIAL AUDIO PORT

Support SCL frequency

No wait states, fast mode

No wait states, slow mode

400

100

kHz

Support SCL frequency

Required LRCK/FS to SCLK

rising edge delay

t_DLY

5

ns

D_SCLK

f_S

f_SCLK

Allowable SCLK duty cycle

Supported input sample rates

Supported SCLK frequencies

SCLK frequency

40%

32

60%

96

kHz

f_S

32

64

24.576

MHz

SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)

t_off

Turn-off Time

Excluding volume ramp

10

ms

V

Value represents the "peak voltage" disregarding

clipping due to lower PVDD.

A_{V(SPK_AMP)}

Programmable Gain

4.95

29.5

Measured at 0 dB input(1FS)

ΔA_{V(SPK_AMP)}

Amplifier gain error

Gain = 29.5 Vp

0.5

384

768

dB

kHz

Switching frequency of the

speaker amplifier

f_{SPK_AMP}

Drain-to-source on resistance

of the individual output

MOSFETs

R_DS(on)

FET + Metallization.

180

mΩ

Over-Current Error Threshold Any short to supply, ground, or other channels

5

A

OCE_THRES

Over-Current cycle-by-cycle

limit

4.2

PVDD over voltage error

threshold

OVE_THRES(PVDD)

UVE_THRES(PVDD)

OTE_THRES

28

4.2

160

10

V

PVDD under voltage error

threshold

V

Over temperature error

threshold

°C

Over temperature error

hysteresis

OTE_Hystersis

Over temperature warning

Read by register 0x73 bit3

level 3

OTW_THRES

135

SPEAKER AMPLIFIER (STEREO BTL)

6

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

Electrical Characteristics (continued)

Free-air room temperature 25°C, DVDD=3.3V, 1SPW Modulation Mode with LC filter, BD Modulation Mode with Ferrite bead

filter (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mA

µA

PDN=2V, DVDD=3.3V, Play mode

18

PDN=2V, DVDD=3.3V, Sleep mode

PDN=2V, DVDD=3.3V, Deep Sleep mode

PDN=0V, DVDD=3.3V, Shutdown mode

PDN=2V, V_PVDD=13.5V, LC filter=10uH+0.68uF,

0.75

5.5

Quiescent supply current

on DVDD

I_CC

32.5

16.5

mA

Fsw=768kHz, BD Modulation, Play mode, BTL

mode

PDN=2V, V_PVDD=13.5V, LC filter=22uH+0.68uF,

Fsw=384kHz, Hybrid or 1SPW Modulation, Play

mode, BTL Mode

Quiescent supply current on

PVDD

I_CC

PDN=2V, V_PVDD=13.5V, Output Hiz Mode

PDN=2V, V_PVDD=13.5V, Sleep Mode

10.4

7.2

mA

µA

PDN=2V, V_PVDD=13.5V, Deep Sleep Mode

PDN=0V, V_PVDD=13.5V, Shutdown Mode

120

7.2

µA

Measured differentially with zero input data,

programmable gain configured with 29.5 Vp gain,

V_PVDD= 24 V

|Vos|

Amplifier offset voltage

-6.5

6.5

mV

V_PVDD= 12 V, R_SPK= 6 Ω, f = 1 kHz THD+N =

10%

12

9.9

25

W

P_O(SPK)

Output power (per channel)

V_PVDD= 12 V, R_SPK= 6 Ω, f = 1 kHz THD+N = 1%

V_PVDD= 18 V, R_SPK= 6 Ω, f = 1 kHz THD+N =

10%

V_PVDD= 18 V, R_SPK= 6 Ω, f = 1 kHz THD+N = 1%

21

V_PVDD= 21 V, R_SPK= 8 Ω, f = 1 kHz THD+N =

10%

27.5

V_PVDD= 21 V, R_SPK= 8 Ω, f = 1 kHz THD+N = 1%

23

Total harmonic distortion and V_PVDD= 12 V, SPK_GAIN = 29.5 Vp, LC-filter

noise

0.03%

THD+N_SPK

(P_O= 1 W, f = 1 KHz, R_SPK

=

V_PVDD= 24 V, SPK_GAIN = 29.5 Vp, LC-filter

0.03%

6 Ω)

A-weighted (AES17), V_PVDD= 12 V, LC-filter, R_SPK

= 6 Ω

37

38

I_CN(SPK)

Idle channel noise

Dynamic range

µVrms

A-weighted (AES17), V_PVDD= 24 V, LC-filter, R_SPK

= 6 Ω

A-Weighted, -60 dBFS method. V_PVDD= 24 V,

SPK_GAIN = 29.5 Vp, R_SPK= 6 Ω

DR

112

111

107.5

72

dB

A-Weighted, referenced to 1% THD+N Output

Level, V_PVDD=24V

SNR

Signal-to-noise ratio

A-Weighted, referenced to 1% THD+N Output

Level, V_PVDD=14.4V

Injected Noise = 1 KHz, 1 V_rms, V_PVDD= 14.4 V,

input audio signal = digital zero

PSRR

Power supply rejection ratio

Cross-talk (worst case

between left-to-right and

right-to-left coupling)

X-talk_SPK

f = 1 KHz

100

dB

SPEAKER AMPLIFIER (MONO PBTL)

Measured differentially with zero input data,

programmable gain configured with 29.5 Vp gain,

V_PVDD= 24 V

|V_OS

|

Amplifier offset voltage

–8

8

mV

V_PVDD= 12 V, R_SPK= 4Ω, f = 1KHz, THD+N = 1%

15.4

18.5

W

V_PVDD= 12 V, R_SPK= 4 Ω, f = 1KHz, THD+N =

10%

P_O(SPK)

Output Power

V_PVDD= 18 V, R_SPK= 4 Ω, f = 1KHz, THD+N =

1%

33.6

41

W

V_PVDD= 18 V, R_SPK= 4 Ω, f = 1KHz, THD+N =

10%

7

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

Electrical Characteristics (continued)

Free-air room temperature 25°C, DVDD=3.3V, 1SPW Modulation Mode with LC filter, BD Modulation Mode with Ferrite bead

filter (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total harmonic distortion and V_PVDD= 12 V, LC-filter, R_SPK= 4 Ω

0.015%

noise

(P_O= 1 W, f = 1 KHz

THD+N_SPK

DR

V_PVDD= 24 V, LC-filter R_SPK= 4 Ω

0.015%

111

A-Weighted, -60 dBFS method. V_PVDD= 24 V,

SPK_GAIN = 29.5 Vp

Dynamic range

dB

A-Weighted, referenced to 1% THD+N Output

Level, V_PVDD=13.5V

108

111

72

SNR

Signal-to-noise ratio

A-Weighted, referenced to 1% THD+N Output

Level, V_PVDD=24V

Injected Noise = 1 KHz, 1 V_rms, V_PVDD= 19 V,

Power supply rejection ratio

PSRR

input audio signal = digital zero

Headphone Amplifier

Headphone power output per

channel

P_o(hp)

SNR_hp

SNR_ln

f_cp

HPVDD = 3.3 V (Rhp = 32 Ω; THD = 1%)

Rhp = 32 Ω

30

40

101

105

360

mW

dB

Signal -to-noise ratio

(headphone mode)

Signal-to-noise ratio (line

driver mode)

2-V_RMSoutput

dB

Charge-pump switching

frequency

kHz

8

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

Serial Audio Port Timing

f_SCLK

t_SCLK

t_SCLKL

t_SCLKH

t_SL

SCLK frequency

1.024

40

16

8

MHz

ns

SCLK period

SCLK pulse width, low

ns

SCLK pulse width, high

ns

SCLK rising to LRCK/FS edge

LRCK/FS Edge to SCLK rising edge

Data setup time, before SCLK rising edge

Data hold time, after SCLK rising edge

Data delay time from SCLK falling edge

ns

t_LS

8

ns

t_SU

8

ns

t_DH

8

ns

t_DFS

15

ns

I²C Bus Timing – Standard

f_SCL

SCL clock frequency

100

kHz

µs

ns

t_BUF

Bus free time between a STOP and START condition

Low period of the SCL clock

4.7

t_LOW

t_HI

4.7

High period of the SCL clock

Setup time for (repeated) START condition

Hold time for (repeated) START condition

Data setup time

4

t_RS-SU

t_S-HD

t_D-SU

t_D-HD

t_SCL-R

4.7

4

250

Data hold time

0

900

Rise time of SCL signal

20 + 0.1C_B

1000

Rise time of SCL signal after a repeated START condition and after an

acknowledge bit

t_SCL-R1

20 + 0.1C_B

1000

ns

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

Fall time of SCL signal

20 + 0.1C_B

4

1000

ns

µs

Rise time of SDA signal

Fall time of SDA signal

Setup time for STOP condition

I²C Bus Timing –

Fast

f_SCL

SCL clock frequency

400

kHz

µs

ns

t_BUF

Bus free time between a STOP and START condition

Low period of the SCL clock

High period of the SCL clock

Setup time for (repeated)START condition

Hold time for (repeated)START condition

Data setup time

1.3

t_LOW

t_HI

1.3

600

t_RS-SU

t_RS-HD

t_D-SU

t_D-HD

t_SCL-R

600

100

Data hold time

0

900

300

Rise time of SCL signal

20 + 0.1C_B

Rise time of SCL signal after a repeated START condition and after an

acknowledge bit

t_SCL-R1

20 + 0.1C_B

300

ns

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

t_SP

Fall time of SCL signal

20 + 0.1C_B

600

300

ns

Rise time of SDA signal

Fall time of SDA signal

Setup time for STOP condition

Pulse width of spike suppressed

50

9

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

7.7 Typical Characteristics

7.7.1 Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5806MDEVM

board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All

measurements taken with audio frequency set to 1 kHz and device PWM Modulation mode set to 1 SPW mode

with Class D Bandwidth =120 kHz for 576kHz Fsw and Class D Bandwidth = 175 kHz for 768 kHz Fsw (Listed in

Register 0x53) unless otherwise noted.

10

5

10

5

PVcc=5V

T_A=25èC

R_L=4W

PVcc=7.4V

T_A=25èC

R_L=4W

P _O=0.5W

P_O=1W

P _O=0.5W

P_O=1W

P_O=2.5W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D010324

D0103412

PVDD = 5 V

4.7 µH + 0.68 µF

1 SPW Modulation

PVDD = 7.4 V

F_SW= 576 kHz

4.7 µH + 0.68 µF

1SPW Modulation

F_SW= 576 kHz

Load = 4 Ω

图 1. THD+N vs Frequency-BTL

图 2. THD+N vs Frequency-BTL

10

5

10

5

PVcc=12V

T_A=25èC

R_L=4W

PVcc=12V

T_A=25èC

R_L=6W

P _O=1W

P_O=2.5W

P_O=5W

P _O=1W

P_O=2.5W

P_O=5W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D10092

D01023

PVDD = 12 V

4.7 µH + 0.68 µF

1SPW Modulation

PVDD = 12 V

4.7 µH + 0.68 µF

1SPW Modulation

F_SW= 768 kHz

Load = 4 Ω

F_SW= 768 kHz

Load = 6 Ω

图 3. THD+N vs Frequency-BTL

图 4. THD+N vs Frequency-BTL

10

5

10

5

PVcc=18V

T_A=25èC

R_L=6W

PVcc=24V

T_A=25èC

R_L=6W

P _O=1W

P_O=2.5W

P_O=5W

P _O=1W

P_O=2.5W

P_O=5W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D10042

D01025

PVDD = 18 V

10 µH + 0.68 µF

1SPW Modulation

PVDD = 24 V

10 µH + 0.68 µF

1SPW Modulation

F_SW= 768 kHz

Load = 6 Ω

F_SW= 768 kHz

Load = 6 Ω

图 5. THD+N vs Frequency-BTL

图 6. THD+N vs Frequency-BTL

10

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (接下页)

10

5

10

5

PVcc=12V

T_A=25èC

R_L=8W

PVcc=18V

T_A=25èC

R_L=8W

P _O=1W

P_O=2.5W

P_O=5W

P _O=1W

P_O=2.5W

P_O=5W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

D01027

Frequency (Hz)

D10062

PVDD = 12 V

4.7 µH + 0.68 µF

1SPW Modulation

PVDD = 18 V

10 µH + 0.68 µF

F_SW= 768 kHz

Load = 8 Ω

F_SW= 768 kHz

1SPW Modulation

Load = 8 Ω

图 7. THD+N vs Frequency-BTL

图 8. THD+N vs Frequency-BTL

10

5

10

5

PVcc=24V

T_A=25èC

R_L=8W

PVcc=19V

T_A=25èC

R_L=6W

BD Mode

1SPW Mode

Hybrid Mode

P _O=1W

P_O=2.5W

P_O=5W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D10082

D010120

PVDD = 24 V

10 µH + 0.68 µF

1SPW Modulation

PVDD = 19 V

Hybrid, BD

P_O= 5 W

Load = 6 Ω

F_SW= 768 kHz

Load = 8 Ω

F_SW= 384 kHz

1 SPW Modulation

图 9. THD+N vs Frequency-BTL

图 10. THD+N vs Frequency-BTL

10

5

10

5

PV_CC=5V

T_A=25èC

R_L=4W

PV_CC=12V

T_A=25èC

R_L=4W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

f= 20Hz

0.005

f= 1kHz

f= 10KHz

f= 1kHz

f= 10KHz

0.002

0.001

0.002

0.001

0.01

0.1

1

10

0.01

0.1

1

10

Output Power (W)

D101027

D010173

PVDD = 5 V

1SPW Modulation

4.7 µH + 0.68 µF

PVDD = 12 V

1SPW Modulation

4.7 µH + 0.68 µF

F_SW= 768 kHz

Load = 4 Ω

F_SW= 768 kHz

Load = 4 Ω

图 11. THD+N vs Output Power-BTL

图 12. THD+N vs Output Power-BTL

11

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (接下页)

10

5

10

5

PV_CC=12V

T_A=25èC

R_L=6W

PV_CC=18V

T_A=25èC

R_L=6W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

f= 20Hz

0.005

f= 1kHz

f= 10KHz

f= 1kHz

f= 10KHz

0.002

0.001

0.002

0.001

0.01

0.1

1

10

0.01

0.1

1

10 20

Output Power (W)

D101047

D010175

PVDD = 12 V

1SPW Modulation

4.7 µH + 0.68 µF

PVDD = 18 V

1SPW Modulation

10 µH + 0.68 µF

F_SW= 768 kHz

Load = 6 Ω

F_SW= 768 kHz

Load = 6 Ω

图 13. THD+N vs Output Power-BTL

图 14. THD+N vs Output Power-BTL

10

5

10

5

PV_CC=24V

T_A=25èC

R_L=6W

PV_CC=12V

T_A=25èC

R_L=8W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

f= 20Hz

0.005

f= 1kHz

f= 10KHz

f= 1kHz

f= 10KHz

0.002

0.001

0.002

0.001

0.01

0.1

1

10 20

0.01

0.1

1

10

Output Power (W)

D101067

D01017

PVDD = 24 V

1SPW Modulation

10 µH + 0.68 µF

PVDD = 12 V

1SPW Modulation

10 µH + 0.68 µF

F_SW= 768 kHz

Load = 6 Ω

F_SW= 768 kHz

Load = 8 Ω

图 15. THD+N vs Output Power-BTL

图 16. THD+N vs Output Power-BTL

10

5

10

5

PV_CC=18V

T_A=25èC

R_L=8W

PV_CC=24V

T_A=25èC

R_L=8W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

f= 20Hz

0.005

f= 1kHz

f= 10KHz

f= 1kHz

f= 10KHz

0.002

0.001

0.002

0.001

0.01

0.1

1

10 20

0.01

0.1

1

10 20

Output Power (W)

D01014087

D010179

PVDD = 18 V

1SPW Modulation

10 µH + 0.68 µF

PVDD = 24 V

1SPW Modulation

10 µH + 0.68 µF

F_SW= 768 kHz

Load = 8 Ω

F_SW= 768 kHz

Load = 8 Ω

图 17. THD+N vs Output Power-BTL

图 18. THD+N vs Output Power-BTL

12

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (接下页)

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

THD+N=1%, R _L=4W

THD+N=10%, R _L=4W

THD+N=1%, R _L=6W

THD+N=10%, R _L=6W

BTL Mode

T_A=25èC

BTL Mode

T_A=25èC

0

4.5

6.5

8.5

10.5

12.5

14.5

16

4.5

6.5

8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24

Supply Voltage (V)

D014

D013270

D014

D013271

Dashed lines represent thermally limited region for the continuous

output power.

Dashed lines represent thermally limited region for the continuous

output power.

PVDD = 4.5V~16V

1SPW Modulation

4.7 µH + 0.68 µF

PVDD = 4.5V~24V

1SPW Modulation

10 µH + 0.68 µF

F_SW= 768 kHz

Load = 4 Ω

F_SW= 768 kHz

Load = 6 Ω

图 19. Output Power vs Supply Voltage

图 20. Output Power vs Supply Voltage

40

35

30

25

20

15

10

5

100

90

80

70

60

50

40

30

20

10

0

THD+N=1%, R _L=8W

THD+N=10%, R _L=8W

T_A=25èC

R_L=4W

BTL Mode

PV_CC= 7.4V

PV_CC= 12 V

PV_CC= 4.5V

BTL Mode

T_A=25èC

0

4.5

6.5

8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24

Supply Voltage (V)

0

10

20

30

Output Power (W)

D014

D013272

D01243

Dashed lines represent thermally limited region for the continuous

output power.

PVDD = 4.5 V, 7.4 V, 12 V

F_SW= 768 kHz Load = 4 Ω

1 SPW Modulation

4.7 µH + 0.68 µF

PVDD = 4.5V~24V

1SPW Modulation

10 µH + 0.68 µF

F_SW= 768 kHz

Load = 8 Ω

图 22. Efficiency vs Supply Voltage

图 21. Output Power vs Supply Voltage

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PV_CC= 7.4V

PV_CC= 12 V

PV_CC= 18 V

PV_CC= 24 V

PV_CC= 7.4V

T_A=25èC

R_L=6W

BTL Mode

T_A=25èC

R_L=8W

BTL Mode

PV_CC= 12 V

PV_CC= 18 V

PV_CC= 24 V

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

Output Power (W)

D091060

D091061

PVDD = 7.4 V, 12 V, 18 V, 24 V

F_SW= 768 kHz Load = 6 Ω

10 µH + 0.68 µF

PVDD = 7.4 V, 12 V, 18 V, 24 V

F_SW= 768 kHz Load = 8 Ω

10 µH + 0.68 µF

1SPW Modulation

1 SPW Modulation

图 23. Efficiency vs Supply Voltage

图 24. Efficiency vs Supply Voltage

13

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (接下页)

80

60

40

20

0

Fsw=768kHz, Channel A

Fsw=768kHz, Channel B

PVDD=12V, LC filter=4.7uH+0.68uF

Ch A to Ch B

-20

Ch B to Ch A

-40

-60

-80

-100

-120

5

10

15

Supply Voltage (V)

18

20

100

1k

10k 20k

Frequency (Hz)

D10230706

D0102318

PVDD = 4.5V~24V

F_SW= 768 kHz

1 SPW Modulation

10 µH + 0.68 µF

PVDD = 12 V

1 SPW Modulation

4.7 µH + 0.68 µF

Load = 8 Ω

F_SW= 768 kHz

Load = 6 Ω

P_O= 1 W

图 25. Idle Channel Noise vs Supply Voltage

图 26. Crosstalk

0

-20

PVDD=18V, LC filter=4.7uH+0.68uF

Ch A to Ch B

PVDD=24V, LC filter=4.7uH+0.68uF

Ch A to Ch B

Ch B to Ch A

-20

Ch B to Ch A

-40

-60

-40

-60

-80

-100

-120

20

100

1k

Frequency (Hz)

10k 20k

100

1k

Frequency (Hz)

10k 20k

D0103310

D0102319

PVDD = 18 V

1 SPW Modulation

10 µH + 0.68 µF

P_O= 1 W

PVDD = 24 V

1 SPW Modulation

10 µH + 0.68 µF

F_SW= 768 kHz

Load = 6 Ω

F_SW= 768 kHz

Load = 6 Ω

P_O= 1 W

图 27. Crosstalk

图 28. Crosstalk

0

-20

0

-20

PVDD=12V, LC filter=4.7uH+0.68uF

PVDD=18V, LC filter=4.7uH+0.68uF

Ch A to Ch B

Ch B to Ch A

Ch A to Ch B

Ch B to Ch A

-40

-60

-80

-100

-120

20

-120

20

100

1k

Frequency (Hz)

10k 20k

D010331

100

1k

Frequency (Hz)

10k 20k

D0103312

PVDD = 12 V

1 SPW Modulation

4.7 µH + 0.68 µF

PVDD = 18 V

1 SPW Modulation

10 µH + 0.68 µF

F_SW= 768 kHz

Load = 8 Ω

P_O= 1 W

F_SW= 768 kHz

Load = 8 Ω

P_O= 1 W

图 29. Crosstalk

图 30. Crosstalk

14

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode (接下页)

0

PVDD=24V, LC filter=4.7uH+0.68uF

Ch A to Ch B

-20

-40

Ch B to Ch A

-60

-80

-100

-120

20

100

1k

Frequency (Hz)

10k 20k

D010313

PVDD = 24 V

1 SPW Modulation

10 µH + 0.68 µF

P_O= 1 W

F_SW= 768 kHz

Load = 8 Ω

图 31. Crosstalk

15

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

7.7.2 Bridge Tied Load (BTL) Configuration Curves

Free-air room temperature 25°C (unless otherwise noted), Measurements were made using TAS806MDEVM

board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All

measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 384 kHz, with Class D

Bandwidth=80kHz (Listed in Register 0x53), Spread Spectrum Enable, Ferrite bead + Capacitor as the output

filter, BD Modulation, unless otherwise noted.

10

5

10

5

PVcc=12V

T_A=25èC

R_L=6W

PVcc=12V

T_A=25èC

R_L=8W

P _O=1W

P_O=2.5W

P_O=5W

P _O=1W

P_O=2.5W

P_O=5W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D103052

D010326

PVDD = 12 V

Ferrite bead +

Capacitor

Spread Spectrum

Enable

PVDD = 12 V

Ferrite bead +

Capacitor

Spread Spectrum

Enable

F_SW= 384 kHz

BD Modulation

Load = 6 Ω

F_SW= 384 kHz

BD Modulation

Load = 8 Ω

图 32. THD+N vs Frequency

图 33. THD+N vs Frequency

20

10

PV_CC=7.4V

T_A=25èC

R_L=4W

THD+N=1%, R _L=8W

THD+N=10%, R _L=8W

5

2

1

15

10

5

0.5

0.2

0.1

0.05

0.02

0.01

f= 20Hz

f= 1kHz

f= 10KHz

0.005

BTL Mode

T_A=25èC

0.002

0.001

0

4.5

6.5

8.5

10.5

12.5

14.5

16

0.01

0.1

1

10

Supply Voltage (V)

Output Power (W)

D014

D0137

D011304087

PVDD = 4.5V~16V

F_SW= 384 kHz

Ferrite bead +

Capacitor

BD Modulation

Spread Spectrum

Enable

Load = 8 Ω

PVDD = 7.4V

Ferrite bead +

Capacitor

BD Modulation

Spread Spectrum

Enable

Load = 4 Ω

F_SW= 384 kHz

图 34. Output Power vs Supply Voltage

图 35. THD+N vs Output Power

10

5

10

5

PV_CC=12V

_A=25èC

R_L=8W

PV_CC=12V

T_A=25èC

R_L=6W

T

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

f= 20Hz

f= 1kHz

f= 10KHz

f= 20Hz

f= 10kHz

f= 1KHz

0.005

0.002

0.001

0.002

0.001

0.01

0.1

1

10

0.01

0.1

1

10

Output Power (W)

D103097

D010470

PVDD = 12V

Ferrite bead +

Capacitor

Spread Spectrum

Enable

PVDD = 12V

Ferrite bead +

Capacitor

Spread Spectrum

Enable

F_SW= 384 kHz

BD Modulation

Load = 6 Ω

F_SW= 384 kHz

BD Modulation

Load = 8 Ω

图 36. THD+N vs Output Power

图 37. THD+N vs Output Power

16

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

Bridge Tied Load (BTL) Configuration Curves (接下页)

0

-20

PVDD=12V, Ferrite Bead + Capacitor

Ch A to Ch B

PVDD=12V, Ferrite bead + Capacitor

Ch 1 to Ch 2

-20

-40

Ch B to Ch A

Ch 2 to Ch 1

-40

-60

-80

-100

-120

20

100

1k

10k 20k

20

100

1k

10k 20k

D0104312

Frequency (Hz)

D010431

PVDD = 12 V

Ferrite bead +

Capacitor

Spread Spectrum

Enable

PVDD = 12V

Ferrite bead +

Capacitor

Spread Spectrum

Enable

F_SW= 384 kHz

BD Modulation

Load = 6 Ω, P_O= 1

F_SW= 384 kHz

BD Modulation

Load = 8 Ω , P_O=

W

1 W

图 38. Crosstalk

图 39. Crosstalk

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

T_A=25èC

R_L=4W

T_A=25èC

R_L=8W

PV_CC= 5V

PV_CC= 7.4V

PV_CC= 12 V

10

0

10

20

Output Power (W)

D104234

Spread Spectrum

Enable

D01244

PVDD = 5V, 7.4V

F_SW= 384 kHz

Ferrite bead +

Capacitor

BD Modulation

PVDD = 7.4V, 12V

F_SW= 384 kHz

Ferrite bead +

Capacitor

BD Modulation

Spread Spectrum

Enable

Load = 8 Ω

Load = 4 Ω

图 40. Efficiency vs Output Power

图 41. Efficiency vs Output Power

100

90

80

70

60

50

40

30

20

T_A=25èC

R_L=6W

PV_CC= 7.4V

PV_CC= 12 V

10

0

10

20

30

Output Power (W)

D104254

PVDD = 7.4V, 12V

F_SW= 384 kHz

Ferrite bead + Capacitor

BD Modulation

Spread Spectrum Enable

Load = 6 Ω

图 42. Efficiency vs Output Power

17

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ZHCSJT7 –MAY 2019

www.ti.com.cn

7.7.3 Parallel Bridge Tied Load (PBTL) Configuration

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5806MDEVM

board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All

measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 576kHz, the LC filter

used was 4.7 μH / 0.68 μF, 1SPW modulation with Class D Bandwidth =120kHz (Listed in Register 0x53) unless

otherwise noted.

10

5

10

5

PVcc=7.4V

T_A=25èC

R_L=4W

PVcc=12V

T_A=25èC

R_L=4W

P _O=1W

P_O=2.5W

P_O=4W

P _O=1W

P_O=2.5W

P_O=5W

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D104062

D010427

PVDD = 7.4 V

F_SW= 576 kHz

1SPW Modulation

4.7 µH + 0.68 µF

PVDD = 12 V

1SPW Modulation

4.7 µH + 0.68 µF

Load = 4 Ω

F_SW= 576 kHz

Load = 4 Ω

图 43. THD+N vs Frequency

图 44. THD+N vs Frequency

10

PV_CC=5V

T_A=25èC

R_L=2W

PVcc=24V

T_A=25èC

R_L=4W

P _O=1W

P_O=2.5W

P_O=5W

5

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

f= 20Hz

f= 10kHz

f= 1KHz

0.005

0.002

0.001

20

100

1k

10k 20k

0.01

0.1

1

10

Frequency (Hz)

Output Power (W)

D104082

D010479

PVDD = 24 V

1SPW Modulation

4.7 µH + 0.68 µF

PVDD = 5 V

1SPW Modulation

4.7 µH + 0.68 µF

F_SW= 576 kHz

Load = 4 Ω

F_SW= 576 kHz

Load = 2 Ω

图 45. THD+N vs Frequency

图 46. THD+N vs Output Power

10

5

PV_CC=5V

T_A=25èC

PV_CC=12V

5

T_A=25èC

R_L=4W

2

1

2

1

R_L=4W

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

f= 20Hz

0.005

f= 10kHz

f= 1KHz

f= 10kHz

f= 1KHz

0.002

0.001

0.002

0.001

0.01

0.1

1

10

0.01

0.1

1

10 20

Output Power (W)

D105007

D010571

PVDD = 5 V

1SPW Modulation

4.7 µH + 0.68 µF

PVDD = 12 V

1SPW Modulation

4.7 µH + 0.68 µF

F_SW= 576 kHz

Load = 4 Ω

F_SW= 576 kHz

Load = 4 Ω

图 47. THD+N vs Output Power

图 48. THD+N vs Output Power

18

TAS5806MD

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ZHCSJT7 –MAY 2019

Parallel Bridge Tied Load (PBTL) Configuration (接下页)

10

5

PV_CC=18V

T_A=25èC

PV_CC=24V

T_A=25èC

R_L=4W

5

2

1

2

1

R_L=4W

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

f= 20Hz

0.005

f= 10kHz

f= 1KHz

f= 10kHz

f= 1KHz

0.002

0.001

0.002

0.001

0.01

0.1

1

10 20

0.01

0.1

1

10 20

Output Power (W)

D105027

D010573

PVDD = 18V

1SPW Modulation

4.7 µH + 0.68 µF

PVDD = 24V

1SPW Modulation

4.7 µH + 0.68 µF

F_SW= 576 kHz

Load = 4 Ω

F_SW= 576 kHz

Load = 4 Ω

图 49. THD+N vs Output Power

图 50. THD+N vs Output Power

80

60

40

20

0

100

90

80

70

60

50

40

30

20

10

0

Fsw=768kHz, PBTL Mode

PV_CC= 5V

PV_CC= 7.4 V

PV_CC= 12 V

PV_CC= 18 V

PV_CC= 24 V

T_A=25èC

R_L=4W

PBTL Mode

5

10

15

18

20

0

5

10 15 20 25 30 35 40 45 50

Output Power (W)

Supply Voltage (V)

D10530705

D091062

PVDD = 4.5V~24V

F_SW= 576 kHz

1SPW Modulation

4.7 µH + 0.68 µF

PVDD = 5 V, 7.4 V, 12 V, 18 V, 24 V

F_SW= 576 kHz Load = 4 Ω

1 SPW Modulation

4.7 µH + 0.68 µF

Load = 4 Ω

图 51. Idle Channel Noise vs Supply Voltage

图 52. Efficiency vs Output Power

19

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ZHCSJT7 –MAY 2019

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7.7.4 Headphone Driver

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5807MDREF

board and Audio Precision System 2722 with Analog Analyzer filter set to 20 kHz brickwall filter. HPVDD = 3.3V.

All measurement taken with audio frequency set to 1 kHz.

10

5

10

5

HPVDD=3.3V

T_A=25èC

R_L=16W

HPVDD=3.3V

T_A=25èC

R_L=16W

Vout=0.1Vrms

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

f= 1kHz

20

100

1k

10k 20k

0.01

0.1

1

Frequency (Hz)

Output Voltage (Vrms)

D30002

D03071

HPVDD = 3.3 V

V_O= 0.1 Vrms

Load = 16 Ω

HPVDD = 3.3 V

f = 1kHz

Load = 16 Ω

图 53. THD+N vs Frequency

图 54. THD+N vs Output Voltage

0

10

5

HPVDD=3.3V

T_A=25èC

R_L=16W

HPVDD=3.3V

V_out=1Vrms

T_A=25èC

R_L=32W

-20

-40

2

1

Vout=0.1Vrms

0.5

0.2

0.1

-60

-80

0.05

0.02

0.01

-100

-120

-140

0.005

Right to Left

Left to Right

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D0310328

D03023

HPVDD = 3.3 V

V_O= 0.1 Vrms

Load = 16 Ω

HPVDD = 3.3 V

V_O= 1 Vrms

Load = 32 Ω

图 55. Crosstalk vs Frequency

图 56. THD+N vs Frequency

10

0

HPVDD=3.3V

T_A=25èC

R_L=32W

HPVDD=3.3V

T_A=25èC

R_L=32W

5

-20

-40

2

1

V_out=1Vrms

0.5

0.2

0.1

-60

-80

0.05

0.02

0.01

-100

-120

-140

0.005

Right to Left

Left to Right

0.002

0.001

f= 1kHz

0.01

0.1

1

20

100

1k

10k 20k

Output Voltage (Vrms)

Frequency (Hz)

D30047

D0310358

HPVDD = 3.3 V

f = 1 kHz

Load = 32 Ω

HPVDD = 3.3 V

V_O= 1 Vrms

Load = 32 Ω

图 57. THD+N vs Output Voltage

图 58. Crosstalk vs Frequency

20

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7.7.5 Line Driver

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5807MDREF

board and Audio Precision System 2722 with Analog Analyzer filter set to 20 kHz brickwall filter. HPVDD = 3.3 V.

All measurements taken with audio frequency set to 1 kHz.

10

5

10

5

HPVDD=3.3V

T_A=25èC

R_L=5kW

HPVDD=3.3V

T_A=25èC

R_L=5kW

V_out=1Vrms

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

f= 1kHz

20

100

1k

10k 20k

0.01

0.1

1

Frequency (Hz)

Output Voltage (Vrms)

D40002

D04071

HPVDD = 3.3 V

V_O= 1 Vrms

Load = 5 kΩ

HPVDD = 3.3 V

f = 1 kHz

Load = 5 kΩ

图 59. THD+N vs Frequency

图 60. THD+N vs Output Voltage

0

10

5

HPVDD=3.3V

T_A=25èC

R_L=5kW

HPVDD=3.3V

V_out=1Vrms

T_A=25èC

R_L=10kW

-20

-40

2

1

V_out=1Vrms

0.5

0.2

0.1

-60

-80

0.05

0.02

0.01

-100

-120

-140

0.005

Right to Left

Left to Right

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D0410318

D04023

HPVDD = 3.3 V

V_O= 1 Vrms

Load = 5 kΩ

HPVDD = 3.3 V

V_O= 1 Vrms

Load = 10 kΩ

图 61. Crosstalk vs Frequency

图 62. THD+N vs Frequency

10

HPVDD=3.3V

T_A=25èC

R_L=10kW

5

2

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

0.001

f= 1kHz

0.01

0.1

1

Output Voltage (Vrms)

D40047

HPVDD = 3.3 V

f = 1 kHz

Load = 10 kΩ

图 63. THD+N vs Output Voltage

21

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ZHCSJT7 –MAY 2019

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8 Parametric Measurement Information

LRCK/FS

(Input)

0.5 × DVDD

t

SCLKL

SCLKH

t

LS

SCLK

(Input)

t

SL

SCLK

DATA

(Input)

0.5 × DVDD

t

DH

SU

t

DFS

DATA

(Output)

图 64. Serial Audio Port Timing in Slave Mode

Repeated

START

STOP

t

P-SU

t

D-SU

D-HD

SDA-F

SDA-R

t

BUF.

SDA

t

SP

SCL-R.

RS-HD

t

LOW.

SCL

t

HI.

t

RS-SU

t

SCL-F.

S-HD.

图 65. I²C Communication Port Timing Diagram

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9 Detailed Description

9.1 Overview

The TAS5806MD device integrates 5 main building blocks together into a single cohesive device that maximizes

sound quality, flexibility, and easy of use. The 5 main building blocks are listed as follows:

•

A stereo audio DAC.

An Audio DSP subsystem.

A flexible close-loop amplifier capable of operating in stereo or mono, at several different switching

frequencies, and with a variety of output voltages and loads.

•

An I²C control port for communication with the device

An Integrated Directpath^TMHeadphone amplifier and line driver

The device requires only three power supplies for proper operation. A DVDD supply is required to power the low

voltage digital circuitry. A HPVDD supply is required to power the charge pump for Headphone/Line driver.

Another supply, called PVDD, is required to provide power to the output stage of the audio amplifier. Onel LDO

converts PVDD to 5 V for AVDD and internal GVDD, another one converts DVDD to 1.5V for internal digital core.

9.2 Functional Block Diagram

4.5-26.4V

3.3/1.8V

DVDD

VR_DIG

AVDD

PVDD1/2/3/4

LDO 1.5V

LDO 5V

BST_A+

Close Loop Feedback

IO

OUT_A+

I2S/TDM

ADR/FAULT

OUT_A-

BST_A-

H Bridge

&

Gate Driver

&

PDN

PDM

Modulator

SDIN

SCLK

LRCLK

Digital to PWM

Conversion

BST_B-

OC/DC Protect

PLL & OSC

OUT_B-

SDOUT

SCL

BST_B+

OUT_B+

Audio DSP

Subsystem

& I2C Block

SDA

Close Loop Feedback

Headphone control (By I2C Register)

HPL_OUT

HPR_OUT

Charge Pump

HP_GND PGND 1/2

AGND

DGND

HPVSS CPP CPN

HPVDD HPL_IN HPR_IN

3.3 V

23

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ZHCSJT7 –MAY 2019

www.ti.com.cn

9.3 Feature Description

9.3.1 Power Supplies

To facilitate system design, TAS5806MD needs only a 3.3-V or 1.8-V supply in addition to the (typical) 12 V or

24 V power-stage supply. Two internal voltage regulators provide suitable voltage levels for the gate drive

circuitry and internal circuitry. The external pins are provided only as a connection point for off-chip bypass

capacitors to filter the supply. Connecting external circuitry to these regulator outputs may result in reduced

performance and damage to the device. Additionally, all circuitry requiring a floating voltage supply, e.g., the

high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In

order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is

designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins

(BST_x). The gate drive voltages (AVDD) are derived from the PVDD voltage. Special attention should be paid to

placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between

the power-supply pins and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a

small ceramic capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin

(OUT_x). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode

connected between the gate-drive regulator output pin (AVDD) and the bootstrap pin. When the power-stage

output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable

voltage supply for the high-side gate driver.

9.3.2 Device Clocking

The TAS5806MD devices have flexible systems for clocking. Internally, the device requires a number of clocks,

mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio

Interface.

LRCLK/FS

DSPCLK

OSRCLK

DACCLK

DSP

(Including

interpolator)

Serial Audio

Interface (Input)

Delta Sigma

Modulator

DAC

Audio In

图 66. Audio Flow with Respective Clocks

图 66 shows the basic data flow and clock Distribution.

The Serial Audio Interface typically has 3 connection pins which are listed as follows:

•

SCLK (Bit Clock)

LRCLK/FS (Left/Right Word Clock and Frame Sync)

SDIN (Input Data)

The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP

and the DAC clock.

The TAS5806MD device has an audio sampling rate detection circuit that automatically senses which frequency

the sampling rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96

kHz are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.

9.3.3 Serial Audio Port – Clock Rates

The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK , and SDIN. SCLK is the

serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio

interface. Serial data is clocked into the TAS5806MD device on the rising edge of SCLK. The LRCK/FS pin is the

serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

表 1. Audio Data Formats, Bit Depths and Clock Rates

MAXIMUM LRCLK/FS FREQUENCY

FORMAT

DATA BITS

SCLK RATE (f_S)

(kHz)

I²S/LJ/RJ

32, 24, 20, 16

32 to 96

64, 32

24

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ZHCSJT7 –MAY 2019

Feature Description (接下页)

表 1. Audio Data Formats, Bit Depths and Clock Rates (接下页)

MAXIMUM LRCLK/FS FREQUENCY

(kHz)

FORMAT

DATA BITS

SCLK RATE (f_S)

32

44.1,48

96

128

TDM

32, 24, 20, 16

128,256,512

128,256

Before DSP register initialize with I²C during the startup , TAS5806MD requires stable I²S ready. When Clock

halt, non-supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in Register 113

(Register Address 0x71).

9.3.4 Clock Halt Auto-recovery

As some of host processor will Halt the I²S clock when there is no audio playing. When Clock halt, the device

puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After audio

clocks recovery, the device automatically returns to the previous state.

9.3.5 Sample Rate on the Fly Change

TAS5806MD supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32kHz to 48kHz or

96kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 100us before changing to the

new sample rate.

9.3.6 Serial Audio Port - Data Formats and Bit Depths

The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and

TDM/DSP data. Data formats are selected via Register (P0-R51-D[5:4]). If the high width of LRCK/FS in

TDM/DSP mode is less than 8 cycles of SCK, the register (P0-R51-D[3:2]) should set to 01. All formats require

binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats, word

length and clock rate supported by this device are shown in Table 1. The data formats are detailed in Figure 1

through Figure 6. The word length are selected via Register (P0-R51-D[1:0]). The offsets of data are selected via

Register (P0-R51-D[7]) and Register (P0-R52-D[7:0]). Default setting is I2S and 24 bit word length.

1 t_S

LRCLK/FS

SCLK

Right-channel

Left-channel

Audio data word = 16-bit, SCLK = 32, 64f_s

DATA

1

2

15 16

1

2

15 16

MSB

LSB

MSB

LSB

Audio data word = 24-bit, SCLK = 64f_s

DATA

1

2

23 24

MSB

LSB

Audio data word = 32-bit, SCLK = 64f_s

DATA

1

2

31 32

MSB

LSB

图 67. Left Justified Audio Data Format

25

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

1 t_S

LRCLK/FS

Right-channel

Left-channel

SCLK

Audio data word = 16-bit, SCLK = 32, 64f_s

DATA

1

2

15 16

1

2

15 16

MSB LSB

Audio data word = 24-bit, SCLK = 64f_s

DATA

1

2

23 24

MSB

LSB

Audio data word = 32-bit, SCLK = 64f_s

DATA

1

2

31 32

MSB

LSB

I²S Data Format; L-channel = LOW, R-channel = HIGH

图 68. I²S Audio Data Format

1 t_S

LRCLK/FS

SCLK

Right-channel

Left-channel

Audio data word = 16-bit, SCLK = 32, 64f_s

DATA

1

2

15 16

1

2

15 16

MSB LSB

Audio data word = 24-bit, SCLK = 64f_s

DATA

1

2

23 24

1

2

23 24

MSB

LSB

Audio data word = 32-bit, SCLK = 64f_s

DATA

1

2

31 32

1

2

31 32

MSB

LSB

Right-Justified Data Format; L-channel = HIGH, R-channel = LOW

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

图 69. Right Justified Audio Data Format

26

TAS5806MD

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ZHCSJT7 –MAY 2019

1 /f_{S .}

LRCK/FS

SCLK

…

Audio data word = 16-bit, Offset = 0

…

1

2

15 16

1

2

15 16

1

DATA

Data Slot 1

Data Slot 2

LSB

MSB

LSB

MSB

Audio data word = 24-bit, Offset = 0

-

,

…

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

LSB

MSB

Audio data word = 32-bit, Offset = 0

…

1

2

31 32

LSB

1

2

31 32

LSB

DATA

MSB

TDM Data Format with OFFSET = 0

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

图 70. TDM 1 Audio Data Format

1 /f_{S .}

OFFSET = 1

LRCK/FS

SCLK

…

Audio data word = 16-bit, Offset = 1

…

1

2

15 16

1

2

15 16

1

DATA

Data Slot 1

LSB

Data Slot 2

LSB

MSB

Audio data word = 24-bit, Offset = 1

…

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

Data Slot 2

LSB

MSB

Audio data word = 32-bit, Offset = 1

…

1

2

31 32

LSB

1

2

31 32

DATA

Data Slot 1

Data Slot 2

LSB

MSB

TDM Data Format with OFFSET = 1

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

图 71. TDM 2 Audio Data Format

27

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

The I2S slave timing is shown in .

9.3.7 Digital Audio Processing

TAS5806MD DSP has ROM fixed process flows which are same with TAS5805M for different applications, refer

to application note, TAS5805M Process Flows for details.

9.3.8 Class D Audio Amplifier

Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose

first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two

pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker

amplifier. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and

increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D

amplifier section of the device.

9.3.8.1 Speaker Amplifier Gain Select

A combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. As seen

in 图 72, the audio path of the TAS5806MD consists of a digital audio input port, a digital audio path, a digital to

PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds the output

information back into the DPC block to correct for distortion sensed on the output pins. The total amplifier gain is

comprised of digital gain, shown in the digital audio path and the analog gain from the input of the analog

modulator to the output of the speaker amplifier power stage.

Analog Gain

Digital Gain

Closed Loop Class D Amplifier

SPK_OUTA+

Full Bridge Power

Stage

A

Stage

Gate

Drivers

SPK_OUTA-

Serial

Audio Processing

(Flexible Audio Process Flows)

Serial

Audio In

Digital to PWM

Conversion

Audio

Port

SPK_OUTB+

Gate

Drivers

Full Bridge Power

Stage

B

SPK_OUTB-

SCL

I2C Interface

Control Register

Closed Loop Class D Amplifier

SDA

图 72. Speaker Amplifier Gain

As shown in 图 72, the first gain stage for the speaker amplifier is present in the digital audio path. It consists of

the volume control and the digital boost block. The volume control is set to 0dB by default, it does not change.

For all settings of the register 0x54, AGAIN[4:0], the digital boost block remains at 0 dB. These gain settings

ensure that the output signal is not clipping at different PVDD levels. 0dBFS output is 29.5-V peak output voltage

表 2. Analog Gain Setting

AGAIN <4:0>

00000

GAIN (dBFS)

AMPLIFIER OUTPUT PEAK VOLTAGE (V)

0

29.5

27.85

…….

4.95

00001

-0.5

…….

……..

-15.5

11111

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9.4 Device Functional Modes

9.4.1 Software Control

The TAS5806MD device is configured via an I²C communication port.

The I2C Communication Protocol is detailed in the I²C Communication Port section. The I²C timing requirements

are described in the I²C Bus Timing – Standard and I²C Bus Timing – Fast sections.

9.4.2 Speaker Amplifier Operating Modes

The TAS5806MD device can be used in two different amplifier configurations:

•

BTL Mode

PBTL Mode

9.4.2.1 BTL Mode

In BTL mode , the TAS5806MD device amplifies two independent signals, which represent the left and right

portions of a stereo signal. The amplified left signal is presented on differential output pair shown as OUT_A+

and OUT_A-, the amplified right signal is presented on differential output pair shown as OUT_B+ and OUT_B-.

9.4.2.2 PBTL Mode

The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in

parallel with one another to increase the power sourcing capabilities of the device. On the output side of the

TAS5806MD device, the summation of the devices can be done before the filter in a configuration called Pre-

Filter Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the

inductor portion of the output filter. Doing so does require two additional inductors, but allows smaller, less

expensive inductors to be used because the current is divided between the two inductors. The process is called

Post-Filter PBTL. On the input side of the TAS5806MD device, the input signal to the PBTL amplifier is left frame

of I2S or TDM data.

9.4.3 Low EMI Modes

TAS5806MD employs several modes to minimize EMI during playing audio, and they can be used based on

different applications.

9.4.3.1 Minimize EMI with Spread Spectrum

This device supports spread spectrum with triangle mode, Spread spectrum is used to minimize the EMI noise.

User need configure register SS_CTRL0 (0x6B) to Enable triangle mode and enable spread spectrum, and

select spread spectrum frequency and range with SS_CTRL1 (0x6C). For 384kHz FSW which configured by

DEVICE_CTRL1 (0x02), the spread spectrum frequency and range are described in Table 3.

表 3. Spread Spectrum Setting

SS_TRI_CTR

0

1

2

3

4

5

6

7

L[3:0]

Triangle Freq

24k

48k

Spread

Spectrum

Range

5%

10%

20%

25%

5%

10%

20%

25%

User Application example-Central Switching Frequency is 384kHz, Triangle Frequency is 24kHz, take I²C device

address 0x58 as an example:

w 58 6b 03 //Enable Spread Spectrum.

w 58 6c 03 //SS_TRI_CTRL[3:0]0011, Triangle Frequency = 24kHz, Spread Spectrum Range should be 25%

(336kHz~432kHz).

9.4.3.2 Channel to Channel Phase shift

This device support channel to channel 180 degree PWM phase shift to minimize the EMI.

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9.4.3.3 Multi-Devices PWM Phase Synchronization

This device support up to 4 phases selection for the multi devices application system. For example, when a

system integrated 4 devices, user can select phase 0/1/2/3 for each device by register PHASE_CTRL (0x6A),

which means there is a 45 degree phase shift between each device to minimize the EMI.

Recommend to do the Phase Synchronization with I²S clock during the Startup Phase.

1. Halt I²S clock.

2. Configure each device phase selection and enable the phase synchronization. For example: Register 0x6A =

0x03 for device 0; Register 0x6A = 0x07 for device 1; Register 0x6A = 0x0B for device 2; Register 0x6A =

0x0F for device 3. There should be a 45 degree PWM phase shift between each device to minimize the EMI.

3. Configure each device into HIZ mode.

4. Provide I²S to each device. Phase synchronization for all 4 devices will be automatically done by internal

sequence.

5. Initialize the DSP code. (This step can be skipped if only need to do the PWM Phase Synchronization).

6. Device to Device PWM phase shift should be fixed with 45 degree.

9.4.4 Thermal Foldback

The Thermal Foldback (TFB), is designed to protect TAS5806MD from excessive die temperature increases, in

case the device operates beyond the recommended temperature/power limit, or with a weaker thermal system

design than recommended. It allows the TAS5806MD to play as loud as possible without triggering unexpected

thermal shutdown. When the die temperature triggers the over-temperature warning (OTW) level (135C typ), an

internal AGL (Automatic Gain Limiter) will reduce the digital gain automatically. Once the die temperature drops

below the OTW, the device’s digital gain gradually returns to the former setting. Both the attenuation gain and

adjustable rate are programmable. The TFB gain regulation speed (attack rate and release rate) settings are the

same as a regular AGL, which is also configurable with TAS5806MD App in PurePathTM Console3.

9.4.5 Headphone Control

TAS5806MD supports Headphone/Line driver control with I²C command which includes Headphone/Line driver

gain control and Mute/Shutdown control.

Register 0x77,

Bit[7:3] HP_GAIN

Register 0x77, Bit[2] HP_MUTEZ

Register 0x77, Bit[1] HP_SDZ

Headphone/Line

Out

Headphone/Line

Input

Headphone/Line Driver Gain

(0dB~24dB, 1dB/Step)

Headphone/Line Driver

Mute /Shutdown

图 73. Headphone/Line driver control with I²C

9.4.6 Device State Control

TAS5806MD has 5 states with different power dissipation which listed in the Electrical Characteristics Table.

•

Shutdown Mode. With PDN pin pull down to GND. All internal LDOs (1.5V for digital core, 5V for analog) are

disabled, all registers will be cleared to default value.

注

Exit from Shutdown Mode and re-enter into Play mode, need reload all register

configurations (which generated by PurePath Console3) again.

•

Deep Sleep Mode. Deep Sleep Mode. Register 0x03h -D[1:0]=00, device stays in Deep Sleep Mode. In this

mode, I2C block and 1.5V LDO for digital core still working, but internal 5V LDO (For AVDD and MOSFET

gate driver) is disabled for low power dissipation. This mode can be used to extend the battery life in some

portable speaker applications. If the host processor stops playing audio for a long time, TAS5806MD can be

set to Deep Sleep Mode to minimize power dissipation until host processor starts playing audio again. Unlike

the Shutdown Mode (Pulling PDN Low), entering or exiting Deep Sleep Mode, the DSP keeps active.

•

Sleep Mode. Register 0x03h -D[1:0]=01, device stays in Sleep Mode. In this mode, I²C block, Digital core,

DSP Memory , 5V Analog LDO are stilling working. Unlike the Shutdown Mode (Pull PDN Low), enter or exit

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Sleep Mode, DSP keeps active. Exit from this mode and re-enter into play mode, only need to set Register

0x03h -D[1:0]=11.

•

Output Hiz Mode. Register 0x03h -D[1:0]=10, device stays in Hiz Mode. In this mode, only output driver is set

to be Hi-Z state, all other block operate normally. Exit from this mode and re-enter into play mode, only need

to set Register 0x03h -D[1:0]=11.

Play Mode. Register 0x03h -D[1:0]=11, device stays in Play Mode.

9.4.7 Device Modulation

TAS5806MD has 3 modulation schemes: BD Modulation, 1SPW modulation and Hybrid modulation. Select

modulation schemes for with Register 0x02 [1:0]-DAMP_MOD.

9.4.7.1 BD Modulation

This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is

driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.

The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the

speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.

The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The

voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which

reduces any I²R losses in the load.

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OUTP

OUTN

No Output

0V

OUTP-OUTN

Speaker

Current

OUTP

OUTN

Positive Output

PVCC

0V

-

OUTP OUTN

Speaker

Current

0A

OUTP

Negative Output

OUTN

0V

OUTP-_OUTN

-

PVCC

0A

Speaker

Current

图 74. BD Mode Modulation

9.4.7.2 1SPW Modulation

The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty

in THD degradation and more attention required in the output filter selection. In Low Idle Current mode the

outputs operate at ~14% modulation during idle conditions. When an audio signal is applied one output will

decrease and one will increase. The decreasing output signal will quickly rail to GND at which point all the audio

modulation takes place through the rising output. The result is that only one output is switching during a majority

of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses.

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OUTP

OUTN

No Output

0V

OUTP-OUTN

Speaker

Current

OUTP

OUTN

Positive Output

PVCC

OUTP-OUTN

0V

Speaker

Current

0A

OUTP

Negative Output

OUTN

0V

-PVCC

OUTP

-OUTN

0

A

Speaker

Current

图 75. 1SPW Mode Modulation

9.4.7.3 Hybrid Modulation

Hybrid Modulation is designed for minimized power loss without compromising the THD+N performance, and is

optimized for battery-powered applications. With Hybrid modulation, TAS5806MD will detect the input signal level

and adjust PWM duty cycle dynamically based on PVDD. Hybrid modulation achieves ultra low idle current and

maintains the same audio performance level as the Hybrid Modulation.

注

To use the Hybrid Modulation, users need to enter the system's PVDD value on the

TAS5806MD PPC3 App.

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9.5 Programming and Control

9.5.1 I²C Serial Communication Bus

The device has a bidirectional serial control interface that is compatible with the I²C bus protocol and supports

100 and 400-kHz data transfer rates for random and sequential write and read operations as a slave device.

Because the TAS5806MD register map and DSP memory spans multi pages, the user should change from page

to page before writing individual register or DSP memory. Changing from page to page is accomplished via

register 0 on each page. This register value selects the page address, from 0 to 255.

9.5.2 Slave Address

The TAS5806MD device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are

factory preset to 01011(0x5x). The next two bits of address byte are the device select bits which can be user-

defined by ADR/FAULT pin in 表 4.

表 4. I²C Slave Address Configuration

ADR/FAULT PIN

MSBs

User Define

LSB

Configuration

4.7k Ω to DVDD

15kΩ to DVDD

47kΩ to DVDD

120kΩ to DVDD

0

1

0

1

0

1

0

1

0

1

R/W

9.5.2.1 Random Write

As shown in 图 76, a single-byte data-write transfer begins with the master device transmitting a start condition

followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data

transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I²C device address and the

read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte

corresponding to the internal memory address being accessed. After receiving the address byte, the device

again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the

memory address being accessed. After receiving the data byte, the device again responds with an acknowledge

bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Start

Condition

Acknowledge

ACK

A4

R/W

A7

ACK

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5

ACK

A6 A5

A3 A2 A1 A0

D4 D3 D2 D1 D0

I²C Device Address

and R/W Bit

Stop

Condition

Subaddress

Data Byte

图 76. Random Write Transfer

9.5.2.2 Sequential Write

A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are

transmitted by the master to the device as shown in 图 77. After receiving each data byte, the device responds

with an acknowledge bit and the I²subaddress is automatically incremented by one.

Start

Condition

Acknowledge

A5

A0

A4 A3

A0

ACK

A1

R/W ACK

A6 A5

ACK

D0

A6

A7

A1

D7

D0

D7

D0

D7

I²C Device Address

and R/W Bit

Stop

Condition

Subaddress

First Data Byte

Other Data Byte

Last Data Byte

图 77. Sequential Write Transfer

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9.5.2.3 Random Read

As shown in 图 78, a single-byte data-read transfer begins with the master device transmitting a start condition

followed by the I²C device address and the read/write bit. For the data-read transfer, both a write followed by a

read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be

read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the device responds

with an acknowledge bit. In addition, after sending the internal memory address byte, the master device transmits

another start condition followed by the address and the read/write bit again. This time the read/write bit is a 1,

indicating a read transfer. After receiving the address and the read/write bit, the device again responds with an

acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving

the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the

single-byte data-read transfer.

Repeat Start

Condition

Acknowledge

Start

Condition

Not

Acknowledge

R/W ACK

ACK

R/W ACK

ACK

D0 D6

A6 A5

A1 A0

A7 A6 A5 A4

A0

A6 A5

A1 A0

D7 D6

I²C Device Address

and R/W Bit

I²C Device Address

and R/W Bit

Stop

Condition

Subaddress

Data Byte

图 78. Random Read Transfer

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9.5.2.4 Sequential Read

A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are

transmitted by the device to the master device as shown in 图 79. Except for the last data byte, the master

device responds with an acknowledge bit after receiving each data byte and automatically increments the I²C sub

address by one. After receiving the last data byte, the master device transmits a not-acknowledge followed by a

stop condition to complete the transfer.

Repeat Start

Condition

Acknowledge

Start

Condition

Not

Acknowledge

R/W ACK

ACK

R/W ACK

ACK

D0

A6

A0

A7 A6 A5

A0

A6

A0

D7

D0

D7

D0

D7

I²C Device Address

and R/W Bit

I²C Device Address

and R/W Bit

Stop

Condition

Subaddress

First Data Byte Other Data Byte Last Data Byte

图 79. Sequential Read Transfer

9.5.2.5 DSP Memory Book, Page and BQ update

The TAS5806MD device supports the I²C serial bus and the data transmission protocol for standard and fast

mode as a slave device.

The DSP memory is arranged in books, pages, and registers. Each book has several pages and each page has

several registers.

Because the TAS5806MD register map spans several books and pages, the user must select the correct book

and page before writing individual register bits or bytes.

To change the book, the user must be on page 0x00. In register 0x7f on page 0x00 you can change the book.

On page 0x00 of each book, register 0x7f is used to change the book. Register 0x00 of each page is used to

change the page. To change a book first write 0x00 to register 0x00 to switch to page 0 then write the book

number to register 0x7f on page 0. To change between pages in a book, simply write the page number to

register 0x00.

All the Biquad Filters coefficients are addressed in Book 0xAA. The five coefficients of every Biquad Filter should

be written entirely and sequentially from the lowest address to the highest.

All DSP/Audio Process Flow Related Register are listed in Application Note, TAS5805M Process Flows

9.5.2.6 Example Use

Example 1, The following is a sample script for configuring a device on I²C slave address 0x58 and set the

device switching frequency to 768kHz with Class D loop bandwidth to 175kHz, 1SPW Modulation:

w 58 00 00 #Go to Page0

w 58 7f 00 #Change the Book to 0x00

w 58 00 00 #Go to Page 0x00

w 58 02 01 #Set switching frequency to 768kHz with 1SPW Modulation

w 58 53 60 #Set Class D Loop Bandwidth to 175kHz

Example 2, The following is a sample script for configuring a device on I2C slave address 0x58 and using the

DSP host memory to change the digital volume to the default value of 0dB:

w 58 00 00 #Go to Page 0

w 58 7f 8c #Change the Book to 0x8C

w 58 00 2a #Go to Page 0x2a

w 58 24 00 80 00 00 #change digital volume to 0dB

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9.5.2.7 Checksum

This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an

Exclusive (XOR) checksum. Register reads do not change checksum, but writes to even nonexistent registers

will change the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.

The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00) to their respective 4-byte register

locations.

9.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum

The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell

delineation, (1 + x1 + x2 + x8)). A major advantage of the CRC checksum is that it is input order sensitive. The

CRC supports all I²C transactions, excluding book and page switching. The CRC checksum is read from register

0x7E on page0 of any book (B_x, Page_0, Reg_126). The CRC checksum can be reset by writing 0x00 to the

same register locations where the CRC checksum is valid.

9.5.2.7.2 Exclusive or (XOR) Checksum

The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with

the previous 8-bit checksum register value. XOR supports only Book 0x8C, and excludes page switching and all

registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book

0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the same register

location where it is read.

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9.5.3 Control via Software

•

Startup Procedures

Shutdown Procedures

9.5.3.1 Startup Procedures

1. Configure ADR/FAULT pin with proper setting for I²C device address.

2. Bring up power supplies (it does not matter if PVDD or DVDD comes up first).

3. Once power supplies are stable, bring up PDN to High and wait 5ms at least, then start SCLK, LRCLK. .

4. Once I²S clocks are stable, set the device into HiZ state and enable DSP via the I2C control port.

5. Wait 5ms at least. Then initialize the DSP Coefficient, then set the device to Play state.

6. The device is now in normal operation.

Initialization

Normal Oper

ation

DVDD

PVDD

PDN

0 ns

5ms

I2S

I2C

Set to HiZ state

(Enable DSP)

DSP Coeff

Play

Deep sleep

5 ms for device settle down

图 80. Start-up Sequence

9.5.3.2 Shutdown Procedures

1. The device is in normal operation.

2. Configure the Register 0x03h -D[1:0]=10 (Hi-Z) via the I2C control port or Pull PDN low.

3. Wait at least 6 ms (this time depends on the LRCLK/FS rate ,digital volume and digital volume ramp down

rate).

4. Bring down power supplies.

5. The device is now fully shutdown and powered off.

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PDN

6ms

4.5V

0ms

PVDD

DVDD

I²C

6ms

I²C

Output Hiz

(1) Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I²C.

(2) At least 6 ms delay needed based on LRCLK (Fs) = 48 kHz. Digital volume ramp down update every sample period,

decreased by 0.5 dB for each update, digital volume = 24 dB. Change the value of register 0x4C and 0x4E or change

the LRCLK rate, the delay changes.

图 81. Power-down Sequence

9.5.3.3 Protection and Monitoring

9.5.3.3.1 Overcurrent Shutdown (OCSD)

Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector,

and the affected channel shuts down in < 100 ns if the peak current are enough. The shutdown speed depends

on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. The

user may restart the affected channel via I²C. An OCSD event activates the fault pin, and the I²fault register

saves a record. If the supply or ground short is strong enough to exceed the peak current threshold but not

severe enough to trigger the OSCD, the peak current limiter prevents excess current from damaging the output

FETs, and operation returns to normal after the short is removed.

9.5.3.3.2 DC Detect

If the TAS5806MD device measures a DC offset in the output voltage, the FAULTZ line is pulled low and the

OUTxx outputs transition to high impedance, signifying a fault.

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9.6 Register Maps

9.6.1 CONTROL PORT Registers

Table 5 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in

Table 5 should be considered as reserved locations and the register contents should not be modified.

Table 5. CONTROL PORT Registers

Offset

1h

Acronym

Register Name

Register 1

Section

Go

RESET_CTRL

DEVICE_CTRL_1

DEVICE_CTRL_2

I2C_PAGE_AUTO_INC

SIG_CH_CTRL

CLOCK_DET_CTRL

SDOUT_SEL

2h

Register 2

3h

Register 3

Fh

Register 15

Register 40

Register 41

Register 48

Register 49

Register 51

Register 52

Register 53

Register 55

Register 56

Register 57

Register 58

Register 76

Register 78

Register 79

Register 80

Register 81

Register 83

Register 84

Register 92

Register 93

Register 96

Register 97

Register 102

Register 103

Register 104

Register 105

Register 106

Register 107

Register 108

Register 109

Register 110

Register 111

Register 112

Register 113

Register 114

Register 115

Register 116

Register 117

28h

29h

30h

31h

33h

34h

35h

37h

38h

39h

40h

4Ch

4Eh

4Fh

50h

51h

53h

54h

5Ch

5Dh

60h

61h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

75h

I2S_CTRL

SAP_CTRL1

SAP_CTRL2

SAP_CTRL3

FS_MON

BCK_MON

CLKDET_STATUS

CHANNEL_FORCE_HIZ

DIG_VOL_CTRL

DIG_VOL_CTRL2

DIG_VOL_CTRL3

AUTO_MUTE_CTRL

AUTO_MUTE_TIME

ANA_CTRL

AGAIN

BQ_WR_CTRL1

DAC_CTRL

ADR_PIN_CTRL

ADR_PIN_CONFIG

DSP_MISC

DIE_ID

POWER_STATE

AUTOMUTE_STATE

PHASE_CTRL

SS_CTRL0

SS_CTRL1

SS_CTRL2

SS_CTRL3

SS_CTRL4

CHAN_FAULT

GLOBAL_FAULT1

GLOBAL_FAULT2

OT WARNING

PIN_CONTROL1

PIN_CONTROL2

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Table 5. CONTROL PORT Registers (continued)

Offset

76h

Acronym

Register Name

Register 118

Register 119

Register 120

Section

Go

MISC_CONTROL

HP_CONTROL

FAULT_CLEAR

77h

Go

78h

Go

Complex bit access types are encoded to fit into small table cells. Table 6 shows the codes that are used for

access types in this section.

Table 6. CONTROL PORT Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

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9.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]

RESET_CTRL is shown in Figure 82 and described in Table 7.

Return to Summary Table.

Figure 82. RESET_CTRL Register

7

6

5

4

RST_MOD

W

3

2

RESERVED

R

1

0

RST_REG

W

RESERVED

R/W

Table 7. RESET_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

RST_MOD

R/W

000

This bit is reserved

W

0

WRITE CLEAR BIT

Reset Modules

WRITE CLEAR BIT Reset full digital core This bit resets full digital

signal chain (Include DSP and Control Port Registers). Since the

DSP is also reset, the coeffient RAM content will also be cleared by

the DSP.

0: Normal

1: Reset modules

3-1

0

RESERVED

R

000

0

This bit is reserved

RST_CONTROL_REG

W

WRITE CLEAR BIT

Reset Registers

This bit resets the control port registers back to their initial values.

The RAM content is not cleared.

0: Normal

1: Reset control port registers

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9.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]

DEVICE_CTRL_1 is shown in Figure 83 and described in Table 8.

Return to Summary Table.

Figure 83. DEVICE_CTRL_1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W

FSW_SEL

R/W

RESERVED

R/W

DAMP_PBTL

R/W

DAMP_MOD

R/W

Table 8. DEVICE_CTRL_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

FSW_SEL

R/W

0

This bit is reserved

6-4

R/W

000

SELECT FSW

000:768K

001:384K

011:480K

100:576K

010:Reserved

101:Reserved

110:Reserved

111:Reserved

3

2

RESERVED

DAMP_PBTL

R/W

0

This bit is reserved

0: SET DAMP TO BTL MODE

1: SET DAMP TO PBTL MODE

1-0

DAMP_MOD

R/W

00

00:BD MODE

01:1SPW MODE

10:HYBRID MODE

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9.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]

DEVICE_CTRL_2 is shown in Figure 84 and described in Table 9.

Return to Summary Table.

Figure 84. DEVICE_CTRL_2 Register

7

6

5

4

3

2

1

0

RESERVED

R/W

DIS_DSP

R/W

MUTE

R/W

RESERVED

R/W

CTRL_STATE

R/W

Table 9. DEVICE_CTRL_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

DIS_DSP

R/W

000

This bit is reserved

DSP reset

R/W

1

When the bit is made 0, DSP will start powering up and send out

data. This needs to be made 0 only after all the input clocks are

settled so that DMA channels do not go out of sync.

0: Normal operation

1: Reset the DSP

3

MUTE

R/W

0

Mute Both Left /Right Channel

This bit issues soft mute request for the left/right channel. The

volume will be smoothly ramped down/up to avoid pop/click noise.

0: Normal volume

1: Mute

2

RESERVED

R/W

0

This bit is reserved

1-0

CTRL_STATE

00

Device state control register

00: Deep Sleep

01: Sleep

10: Hiz (Set both A channel and B channel to Hiz)

Notes: For separate channel Hiz, see details in Table 21

11: PLAY

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9.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]

I2C_PAGE_AUTO_INC is shown in Figure 85 and described in Table 10.

Return to Summary Table.

Figure 85. I2C_PAGE_AUTO_INC Register

7

6

5

4

3

2

1

0

RESERVED

R/W

PAGE_AUTOIN

C_REG

RESERVED

R/W

Table 10. I2C_PAGE_AUTO_INC Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3

RESERVED

R/W

0000

This bit is reserved

PAGE_AUTOINC_REG

R/W

0

Page auto increment disable

Disable page auto increment mode for non -zero books. When end

of page is reached it goes back to 8th address location of next page

when this bit is 0. When this bit is 1 it goes to 0th location of current

page itself like in older part.

0: Enable Page auto increment

1: Disable Page auto increment

2-0

RESERVED

R/W

000

This bit is reserved

9.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]

SIG_CH_CTRL is shown in Figure 86 and described in Table 11.

Return to Summary Table.

Figure 86. SIG_CH_CTRL Register

7

6

5

4

3

2

1

0

BCK_RATIO_CONFIGURE

R/W

FS_MODE

R/W

Table 11. SIG_CH_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

BCK_RATIO_CONFIGUR R/W

E

0000

These bits indicate the configured BCK ratio, the number of BCK

clocks in one audio frame.

0011: 32FS

0101: 64FS

0111: 128FS

1001: 256FS

1011: 512FS

3-0

FS_MODE

R/W

0000

FS Speed Mode These bits select the FS operation mode, which

must be set according to the current audio sampling rate.

0000: Auto detection

0110: 32KHz

1000: 44.1KHz

1001: 48KHz

1010: 88.2KHz

1011: 96KHz

Others Reserved

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9.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]

CLOCK_DET_CTRL is shown in Figure 87 and described in Table 12.

Return to Summary Table.

Figure 87. CLOCK_DET_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

DIS_DET_PLL DIS_DET_BCL DIS_DET_FS DIS_DET_BCL DIS_DET_MIS

RESERVED

K_RANGE

K

S

R/W

Table 12. CLOCK_DET_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0

This bit is reserved

6

DIS_DET_PLL

R/W

0

Ignore PLL overate Detection

This bit controls whether to ignore the PLL overrate detection. The

PLL must be slow than 150MHz or an error will be reported. When

ignored, a PLL overrate error will not cause a clock error.

0: Regard PLL overrate detection

1: Ignore PLL overrate detection

5

DIS_DET_BCLK_RANGE R/W

0

Ignore BCK Range Detection

This bit controls whether to ignore the BCK range detection. The

BCK must be stable between 256KHz and 50MHz or an error will be

reported. When ignored, a BCK range error will not cause a clock

error.

0: Regard BCK Range detection

1: Ignore BCK Range detection

4

3

DIS_DET_FS

R/W

0

Ignore FS Error Detection

This bit controls whether to ignore the FS Error detection. When

ignored, FS error will not cause a clock error.But CLKDET_STATUS

will report fs error.

0: Regard FS detection

1: Ignore FS detection

DIS_DET_BCLK

Ignore BCK Detection

This bit controls whether to ignore the BCK detection against LRCK.

The BCK must be stable between 32FS and 512FS inclusive or an

error will be reported. When ignored, a BCK error will not cause a

clock error.

0: Regard BCK detection

1: Ignore BCK detection

2

DIS_DET_MISS

R/W

0

Ignore BCK Missing Detection

This bit controls whether to ignore the BCK missing detection. When

ignored an BCK missing will not cause a clock error.

0: Regard BCK missing detection

1: Ignore BCK missing detection

1

0

RESERVED

R/W

0

This bit is reserved

9.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]

SDOUT_SEL is shown in Figure 88 and described in Table 13.

Return to Summary Table.

Figure 88. SDOUT_SEL Register

7

6

5

4

3

2

1

0

RESERVED

SDOUT_SEL

R/W

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Table 13. SDOUT_SEL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

0

This bit is reserved

0

SDOUT_SEL

R

0

SDOUT Select. This bit selects what is being output as SDOUT pin.

0: SDOUT is the DSP output (post-processing)

1: SDOUT is the DSP input (pre-processing)

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9.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]

I2S_CTRL is shown in Figure 89 and described in Table 14.

Return to Summary Table.

Figure 89. I2S_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W

BCK_INV

R/W

RESERVED

R

RESERVED

R/W

R

Table 14. I2S_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RESERVED

BCK_INV

R/W

00

This bit is reserved

BCK Polarity

R/W

0

This bit sets the inverted BCK mode. In inverted BCK mode, the

DAC assumes that the LRCK and DIN edges are aligned to the

rising edge of the BCK. Normally they are assumed to be aligned to

the falling edge of the BCK.

0: Normal BCK mode

1: Inverted BCK mode

4-0

RESERVED

R/W

00000

This bit is reserved

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9.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]

SAP_CTRL1 is shown in Figure 90 and described in Table 15.

Return to Summary Table.

Figure 90. SAP_CTRL1 Register

7

6

5

4

3

2

1

0

I2S_SHIFT_MS

B

RESERVED

DATA_FORMAT

I2S_LRCLK_PULSE

WORD_LENGTH

R/W

Table 15. SAP_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

I2S_SHIFT_MSB

RESERVED

R/W

0

I2S Shift MSB

6

R/W

0

This bit is reserved

I2S Data Format

5-4

DATA_FORMAT

00

These bits control both input and output audio interface formats for

DAC operation.

00: I2S

01: TDM/DSP

10: RTJ

11: LTJ

3-2

1-0

I2S_LRCLK_PULSE

WORD_LENGTH

R/W

00

10

01: lrclk pulse < 8 SCLK. If the high width of LRCLK/FS in TDM/DSP

mode is less than 8 cycles of SCK, these two bits need set to 01.

I2S Word Length

These bits control both input and output audio interface sample word

lengths for DAC operation.

00: 16 bits

01: 20 bits

10: 24 bits

11: 32 bits

9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]

SAP_CTRL2 is shown in Figure 91 and described in Table 16.

Return to Summary Table.

Figure 91. SAP_CTRL2 Register

7

6

5

4

3

2

1

0

I2S_SHIFT

R/W

Table 16. SAP_CTRL2 Register Field Descriptions

Bit

7-0

Field

I2S_SHIFT

Type

Reset

Description

R/W

00000000

I2S Shift LSB

These bits control the offset of audio data in the audio frame for both

input and output. The offset is defined as the number of BCK from

the starting (MSB) of audio frame to the starting of the desired audio

sample.

000000000: offset = 0 BCK (no offset)

000000001: ofsset = 1 BCK

000000010: offset = 2 BCKs

and

111111111: offset = 512 BCKs

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9.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]

SAP_CTRL3 is shown in Figure 92 and described in Table 17.

Return to Summary Table.

Figure 92. SAP_CTRL3 Register

7

6

5

4

3

2

1

0

RESERVED

R/W

LEFT_DAC_DPATH

R/W

RESERVED

R/W

RIGHT_DAC_DPATH

R/W

Table 17. SAP_CTRL3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-4

RESERVED

R/W

00

This bit is reserved

LEFT_DAC_DPATH

R/W

01

Left DAC Data Path. These bits control the left channel audio data

path connection.

00: Zero data (mute)

01: Left channel data

10: Right channel data

11: Reserved (do not set)

3-2

1-0

RESERVED

R/W

00

01

This bit is reserved

RIGHT_DAC_DPATH

Right DAC Data Path. These bits control the right channel audio

data path connection.

00: Zero data (mute)

01: Right channel data

10: Left channel data

11: Reserved (do not set)

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9.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]

FS_MON is shown in Figure 93 and described in Table 18.

Return to Summary Table.

Figure 93. FS_MON Register

7

6

5

4

3

2

1

0

RESERVED

R/W

BCLK_RATIO_HIGH

R

FS

R

Table 18. FS_MON Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-4

3-0

RESERVED

BCLK_RATIO_HIGH

FS

R/W

00

This bit is reserved

2 msbs of detected BCK ratio

R

00

0000

These bits indicate the currently detected audio sampling rate.

0000: FS Error

0110: 32KHz

1000: Reserved

1001: 48KHz

1011: 96KHz

Others Reserved

9.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]

BCK_MON is shown in Figure 94 and described in Table 19.

Return to Summary Table.

Figure 94. BCK_MON Register

7

6

5

4

3

2

1

0

BCLK_RATIO_LOW

R

Table 19. BCK_MON Register Field Descriptions

Bit

7-0

Field

BCLK_RATIO_LOW

Type

Reset

Description

R

00000000

These bits indicate the currently detected BCK ratio, the number of

BCK clocks in one audio frame.

BCK = 32 FS~512 FS

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9.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]

CLKDET_STATUS is shown in Figure 95 and described in Table 20.

Return to Summary Table.

Figure 95. CLKDET_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R/W

DET_STATUS

R

Table 20. CLKDET_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

00

This bit is reserved

5

4

3

DET_STATUS

R

0

This bit indicates whether the BCLK is overrate or underrate

This bit indicates whether the PLL is overrate

This bit indicates whether the PLL is locked or not. The PLL will be

reported as unlocked when it is disabled.

2

1

DET_STATUS

R

0

This bit indicates whether the BCK is missing or not.

This bit indicates whether the BCK is valid or not. The BCK ratio

must be stable and in the range of 32-512FS to be valid.

0

DET_STATUS

R

0

In auto detection mode(reg_fsmode=0),this bit indicated whether the

audio sampling rate is valid or not. In non auto detection

mode(reg_fsmode!=0), Fs error indicates that configured fs is

different with detected fs. Even FS Error Detection Ignore is set, this

flag will be also asserted.

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9.6.1.15 CHANNEL_FORCE_HIZ Register (Offset = 40h) [reset = 0x01]

CHANNEL_FORCE_HIZ is shown in Figure 96 and described in Table 21.

Return to Summary Table.

Figure 96. CHANNEL_FORCE_HIZ Register

7

6

5

4

3

2

1

0

RESERVED

R/W

CH_A_HIZ

R/W

CH_B_HIZ

R/W

RESERVED

R/W

Table 21. CHANNEL_FORCE_HIZ Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

R/W

000

These bits are reserved

CH_A_HIZ

CH_B_HIZ

RESERVED

R/W

0

1: Force Channel A (L channel) to Hiz mode.

0: Exit Force Hi-Z mode, Channel A is now controlled by Register

0x03, see Table 9.

Notes: If channel has been forced to Hiz, only method to exit Force

Hi-Z mode is set this bit to 0. This function is disabled in PBTL

mode.

3

0

1: Force Channel B (R channel) to Hiz mode.

0: Exit Force Hi-Z mode, Channel B is now controlled by Register

0x03, see Table 9.

Notes: If channel has been forced to Hiz, only method to exit Force

Hi-Z mode is set this bit to 0. This function is disabled in PBTL

mode.

2-0

001

These bits are reserved.

9.6.1.16 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]

DIG_VOL_CTL is shown in Figure 97 and described in Table 22.

Return to Summary Table.

Figure 97. DIG_VOL_CTL Register

7

6

5

4

3

2

1

0

PGA

R/W

Table 22. DIG_VOL_CTR Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

PGA

R/W

00110000

Digital Volume

These bits control both left and right channel digital volume. The

digital volume is 24 dB to -103 dB in -0.5 dB step.

00000000: +24.0 dB

00000001: +23.5 dB

........

and 00101111: +0.5 dB

00110000: 0.0 dB

00110001: -0.5 dB

.......

11111110: -103 dB

11111111: Mute

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9.6.1.17 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]

DIG_VOL_CTRL2 is shown in Figure 98 and described in Table 23.

Return to Summary Table.

Figure 98. DIG_VOL_CTRL2 Register

7

6

5

4

3

2

1

0

PGA_RAMP_DOWN_SPEED

R/W

PGA_RAMP_DOWN_STEP

R/W

PGA_RAMP_UP_SPEED

R/W

PGA_RAMP_UP_STEP

R/W

Table 23. DIG_VOL_CTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

PGA_RAMP_DOWN_SPE R/W

ED

00

Digital Volume Normal Ramp Down Frequency

These bits control the frequency of the digital volume updates when

the volume is ramping down.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly set the volume to zero (Instant mute)

5-4

3-2

1-0

PGA_RAMP_DOWN_STE R/W

P

11

00

11

Digital Volume Normal Ramp Down Step

These bits control the step of the digital volume updates when the

volume is ramping down.

00: Decrement by 4 dB for each update

01: Decrement by 2 dB for each update

10: Decrement by 1 dB for each update

11: Decrement by 0.5 dB for each update

PGA_RAMP_UP_SPEED R/W

Digital Volume Normal Ramp Up Frequency

These bits control the frequency of the digital volume updates when

the volume is ramping up.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly restore the volume (Instant unmute)

PGA_RAMP_UP_STEP

R/W

Digital Volume Normal Ramp Up Step

These bits control the step of the digital volume updates when the

volume is ramping up.

00: Increment by 4 dB for each updat

01: Increment by 2 dB for each update

10: Increment by 1 dB for each update

11: Increment by 0.5 dB for each update

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9.6.1.18 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]

DIG_VOL_CTRL3 is shown in Figure 99 and described in Table 24.

Return to Summary Table.

Figure 99. DIG_VOL_CTRL3 Register

7

6

5

4

3

2

1

0

FAST_RAMP_DOWN_SPEED

R/W

FAST_RAMP_DOWN_STEP

R/W

RESERVED

R/W

Table 24. DIG_VOL_CTRL3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

FAST_RAMP_DOWN_SP R/W

EED

00

Digital Volume Emergency Ramp Down Frequency

These bits control the frequency of the digital volume updates when

the volume is ramping down due to clock error or power outage,

which usually needs faster ramp down compared to normal soft

mute.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly set the volume to zero (Instant mute)

5-4

3-0

FAST_RAMP_DOWN_ST R/W

EP

11

Digital Volume Emergency Ramp Down Step

These bits control the step of the digital volume updates when the

volume is ramping down due to clock error or power outage, which

usually needs faster ramp down compared to normal soft mute.

00: Decrement by 4 dB for each update

01: Decrement by 2 dB for each update

10: Decrement by 1 dB for each update

11: Decrement by 0.5 dB for each update

RESERVED

R/W

0000

This bit is reserved

9.6.1.19 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]

AUTO_MUTE_CTRL is shown in Figure 100 and described in Table 25.

Return to Summary Table.

Figure 100. AUTO_MUTE_CTRL Register

7

6

5

4

3

2

1

REG_AUTO_MUTE_CTRL

R/W

0

RESERVED

R/W

Table 25. AUTO_MUTE_CTRL Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7-3

2

R/W

00000

This bit is reserved

REG_AUTO_MUTE_CTR R/W

L

1

0: Auto mute left channel and right channel independently.

1: Auto mute left and right channels only when both channels are

about to be auto muted

1

0

REG_AUTO_MUTE_CTR R/W

L

1

0: Disable right channel auto mute

1: Enable right channel auto mute

REG_AUTO_MUTE_CTR R/W

L

0: Disable left channel auto mute

1: Enable left channel auto mute bit2: .

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9.6.1.20 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]

AUTO_MUTE_TIME is shown in Figure 101 and described in Table 26.

Return to Summary Table.

Figure 101. AUTO_MUTE_TIME Register

7

6

5

AUTOMUTE_TIME_LEFT

R/W

4

3

2

1

0

RESERVED

R/W

RESERVED

R/W

AUTOMUTE_TIME_RIGHT

R/W

Table 26. AUTO_MUTE_TIME Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7

R/W

0

This bit is reserved

6-4

AUTOMUTE_TIME_LEFT R/W

000

Auto Mute Time for Left Channel

These bits specify the length of consecutive zero samples at left

channel before the channel can be auto muted. The times shown are

for 96 kHz sampling rate and will scale with other rates.

000: 11.5 ms

001: 53 ms

010: 106.5 ms

011: 266.5 ms

100: 0.535 sec

101: 1.065 sec

110: 2.665 sec

111: 5.33 sec

3

RESERVED

R/W

0

This bit is reserved

2-0

AUTOMUTE_TIME_RIGH R/W

T

000

Auto Mute Time for Right Channel

These bits specify the length of consecutive zero samples at right

channel before the channel can be auto muted. The times shown are

for 96 kHz sampling rate and will scale with other rates.

000: 11.5 ms

001: 53 ms

010: 106.5 ms

011: 266.5 ms

100: 0.535 sec

101: 1.065 sec

110: 2.665 sec

111: 5.33 sec

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9.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0x00]

ANA_CTRL is shown in Figure 102 and described in Table 27.

Return to Summary Table.

Figure 102. ANA_CTRL Register

7

6

5

4

3

2

1

0

ANA_CTRL

R/W

Table 27. ANA_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

ANA_CTRL

R/W

0

This bit is reserved

6-5

R/W

00

Class-D bandwidth control.

00: 80kHz;

01: 100kHz;

10: 120kHz;

11: 175kHz.

With Fsw=768kHz, 175kHz bandwidth should be selected for high

audio performance. With Fsw=384kHz, bandwidth should ≤ 120kHz.

4-0

RESERVED

R/W

0000

These bits are reserved

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9.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]

AGAIN is shown in Figure 103 and described in Table 28.

Return to Summary Table.

Figure 103. AGAIN Register

7

6

5

4

3

2

1

0

RESERVED

R/W

ANA_GAIN

R/W

Table 28. AGAIN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RESERVED

ANA_GAIN

R/W

000

This bit is reserved

R/W

00000

Analog Gain Control , with 0.5dB one step

This bit controls the analog gain.

00000: 0 dB (29.5V peak voltage)

00001: -0.5db

11111: -15.5 dB

9.6.1.23 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]

BQ_WR_CTRL1 is shown in Figure 104 and described in Table 29.

Return to Summary Table.

Figure 104. BQ_WR_CTRL1 Register

7

6

5

4

3

2

1

0

RESERVED

BQ_WR_FIRST

_COEF

R/W

Table 29. BQ_WR_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

R/W

0000000

This bit is reserved

BQ_WR_FIRST_COEF

R/W

0

Indicate the first coefficient of a BQ is starting to write.

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9.6.1.24 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]

DAC_CTRL is shown in Figure 105 and described in Table 30.

Return to Summary Table.

Figure 105. DAC_CTRL Register

7

6

5

4

3

2

1

0

DAC_FREQUE

NCY_SEL

DAC_DITHER_EN

DAC_DITHER

DAC_CTRL_DEM_SEL

R/W

Table 30. DAC_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DAC_FREQUENCY_SEL R/W

1

DAC Frequency Select

0: 6.144MHz

1: 3.072MHz

6-5

4-2

DAC_DITHER_EN

DAC_DITHER

R/W

11

DITHER_EN,

00: disable both stage dither

01: enable main stage dither

10: enable second stage dither

11: enbale both stage dither

110

Dither level

100: -2^-7

101: -2^-8

110: -2^-9

111: -2^-10

000: -2^-13

001: -2^-14

010: -2^-15

011: -2^-16

1-0

DAC_CTRL_DEM_SEL

R/W

00

00: Enable DEM

11: Disable DEM

9.6.1.25 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]

ADR_PIN_CTRL is shown in Figure 106 and described in Table 31.

Return to Summary Table.

Figure 106. ADR_PIN_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

ADR_OE

R/W - 0x0

Table 31. ADR_PIN_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

ADR_OE

R/W

0000000

This bit is reserved

R/W

0

ADR Output Enable This bit sets the direction of the ADR pin

0: ADR is input

1: ADR is output

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9.6.1.26 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]

ADR_PIN_CONFIG is shown in Figure 107 and described in Table 32.

Return to Summary Table.

Figure 107. ADR_PIN_CONFIG Register

7

6

5

4

3

2

ADR_PIN_CONFIG

R/W

1

0

RESERVED

Table 32. ADR_PIN_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RESERVED

R/W

000

These bits are reserved

00000: off (low)

ADR_PIN_CONFIG

R/W

00000

00011: Auto mute flag (asserted when both L and R channels are

auto muted)

00100: Auto mute flag for left channel 0101: Auto mute flag for right

channel

00110: Clock invalid flag (clock error or clock missing)

00111: Reserved

01001: Reserved

01011: ADR as FAULTZ output

9.6.1.27 DSP_MISC Register (Offset = 66h) [reset = 0h]

DSP_MISC is shown in Figure 108 and described in Table 33.

Return to Summary Table.

Figure 108. DSP_MISC Register

7

6

5

4

3

2

1

0

BYPASS_CONTROL

R/W

Table 33. DSP_MISC Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3

RESERVED

R/W

0000

These bits are reserved

BYPASS CONTROL

R/W

0

1: Left and Right will have use unique coef 0->Right channel will

share left channel coefficient

2

1

0

BYPASS CONTROL

R/W

0

1: bypass 128 tap FIR

1: bypass DRC (Only bypass DRC in L/R channel)

1: bypass EQ (Only bypass EQs in L/R channel)

9.6.1.28 DIE_ID Register (Offset = 67h) [reset = 0h]

DIE_ID is shown in Figure 109 and described in Table 34.

Return to Summary Table.

Figure 109. DIE_ID Register

7

6

5

4

3

2

1

0

DIE_ID

R-0h

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Table 34. DIE_ID Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DIE_ID

R

0h

DIE ID

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9.6.1.29 POWER_STATE Register (Offset = 68h) [reset = 0x00]

POWER_STATE is shown in Figure 110 and described in Table 35.

Return to Summary Table.

Figure 110. POWER_STATE Register

7

6

5

4

3

2

1

0

STATE_RPT

R

Table 35. POWER_STATE Register Field Descriptions

Bit

7-0

Field

STATE_RPT

Type

Reset

Description

R

00000000

0: Deep sleep

1: Sleep

2: HIZ

3: Play

Others: reserved

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9.6.1.30 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]

AUTOMUTE_STATE is shown in Figure 111 and described in Table 36.

Return to Summary Table.

Figure 111. AUTOMUTE_STATE Register

7

6

5

4

3

2

1

0

RESERVED

R

ZERO_RIGHT_ ZERO_LEFT_

MON

R

Table 36. AUTOMUTE_STATE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

1

RESERVED

R

000000

This bit is reserved

ZERO_RIGHT_MON

R

0

This bit indicates the auto mute status for right channel.

0: Not auto muted

1: Auto muted

0

ZERO_LEFT_MON

This bit indicates the auto mute status for left channel.

0: Not auto muted

1: Auto muted

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9.6.1.31 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]

PHASE_CTRL is shown in Figure 112 and described in Table 37.

Return to Summary Table.

Figure 112. PHASE_CTR Register

7

6

5

4

3

2

1

0

RESERVED

R/W

RAMP_PHASE_SEL

PHASE_SYNC PHASE_SYNC

_SEL

_EN

R/W

Table 37. PHASE_CTR Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3-2

RESERVED

R/W

0000

This bit is reserved

RAMP_PHASE_SEL

R/W

00

Select ramp clock phase when multi devices integrated in one

system to reduce EMI and peak supply peak current, it is

recomended set all devices the same RAMP frequency and same

spread spectrum. it must be set before driving device into PLAY

mode if this feature is needed.

00: phase0

01: phase1

10: phase2

11: phase3

1

0

I2S_SYNC_EN

R/W

0

Use I2S to synchronize output PWM phase

0: Disable

1: Enable

PHASE_SYNC_EN

0: RAMP phase sync disable

1: RAMP phase sync enable

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9.6.1.32 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]

SS_CTRL0 is shown in Figure 113 and described in Table 38.

Return to Summary Table.

Figure 113. SS_CTRL0 Register

7

6

5

4

3

2

1

0

RESERVED

SS_PRE_DIV_ SS_MANUAL_

RESERVED

R/W

SS_RDM_EN

SS_TRI_EN

SEL

MODE

R/W

Table 38. SS_CTRL0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0

This bit is reserved

6

5

RESERVED

R/W

0

SS_PRE_DIV_SEL

SS_MANUAL_MODE

RESERVED

Select pll clock divide 2 as source clock in manual mode

Set ramp ss controller to manual mode

This bit is reserved

4

3-2

1

SS_RDM_EN

SS_TRI_EN

Random SS enable

0

Triangle SS enable

9.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]

SS_CTRL1 is shown in Figure 114 and described in Table 39.

Return to Summary Table.

Figure 114. SS_CTRL1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W

SS_RDM_CTRL

R/W

SS_TRI_CTRL

R/W

Table 39. SS_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0

This bit is reserved

6-4

3-0

SS_RDM_CTRL

SS_TRI_CTRL

R/W

000

Random SS range control

Triangle SS frequency and range control

0000

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9.6.1.34 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]

SS_CTRL2 is shown in Figure 115 and described in Table 40.

Return to Summary Table.

Figure 115. SS_CTRL2 Register

7

6

5

4

3

2

1

0

TM_FREQ_CTRL

R/W

Table 40. SS_CTRL2 Register Field Descriptions

Bit

7-0

Field

TM_FREQ_CTRL

Type

Reset

Description

Control ramp frequency in manual mode, F=61440000/N

R/W

01010000

9.6.1.35 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]

SS_CTRL3 is shown in Figure 116 and described in Table 41.

Return to Summary Table.

Figure 116. SS_CTRL3 Register

7

6

5

4

3

2

1

0

TM_DSTEP_CTRL

R/W

TM_USTEP_CTRL

R/W

Table 41. SS_CTRL3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

SS_TM_DSTEP_CTRL

R/W

0001

Control triangle mode spread spectrum fall step in ramp ss manual

mode

3-0

SS_TM_USTEP_CTRL

R/W

0001

Control triangle mode spread spectrum rise step in ramp ss manual

mode

9.6.1.36 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]

SS_CTRL4 is shown in Figure 117 and described in Table 42.

Return to Summary Table.

Figure 117. SS_CTRL4 Register

7

6

5

4

3

2

SS_TM_PERIOD_BOUNDRY

R/W

1

0

RESERVED

R/W

TM_AMP_CTRL

R/W

Table 42. SS_CTRL4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0

This bit is reserved

6-5

4-0

TM_AMP_CTRL

R/W

01

Control ramp amp ctrl in ramp ss manual model

SS_TM_PERIOD_BOUN R/W

DRY

00100

Control triangle mode spread spectrum boundary in ramp ss manual

mode

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9.6.1.37 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]

CHAN_FAULT is shown in Figure 118 and described in Table 43.

Return to Summary Table.

Figure 118. CHAN_FAULT Register

7

6

5

4

3

2

CH2_DC_1

R

1

CH1_OC_I

R

0

CH2_OC_I

R

RESERVED

R

CH1_DC_1

R

Table 43. CHAN_FAULT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3

RESERVED

CH1_DC_1

CH2_DC_1

CH1_OC_I

CH2_OC_I

R

0000

This bit is reserved

R

0

Left channel DC fault

Right channel DC fault

Left channel over current fault

Right channel over current fault

2

1

0

9.6.1.38 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]

GLOBAL_FAULT1 is shown in Figure 119 and described in Table 44.

Return to Summary Table.

Figure 119. GLOBAL_FAULT1 Register

7

6

5

4

3

2

1

0

OTP_CRC_ER BQ_WR_ERRO

CLK_FAULT_I

PVDD_OV_I

PVDD_UV_I

ROR

R

Table 44. GLOBAL_FAULT1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

OTP_CRC_ERROR

BQ_WR_ERROR

RESERVED

R

0h

Indicate OTP CRC check error.

The recent BQ is written failed

This bit is reserved

Clock fault

R

0h

5-3

2

CLK_FAULT_I

PVDD_OV_I

1

PVDD OV fault

0

PVDD_UV_I

PVDD UV fault

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9.6.1.39 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]

GLOBAL_FAULT2 is shown in Figure 120 and described in Table 45.

Return to Summary Table.

Figure 120. GLOBAL_FAULT2 Register

7

6

5

RESERVED

R

4

3

2

1

0

OTSD_I

R

RESERVED

R

Table 45. GLOBAL_FAULT2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

OTSD_I

R

0000000

This bit is reserved

R

0

Over temperature shut down fault

9.6.1.40 OT WARNING Register (Offset = 73h) [reset = 0x00]

OT_WARNING is shown in Figure 121 and described in Table 46.

Return to Summary Table.

Figure 121. OT_WARNING Register

7

6

5

4

3

2

OTW

R

1

0

RESERVED

R

RESERVED

R

Table 46. OT_WARNING Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-3

2

RESERVED

OTW

R

00

This bit is reserved

Over temperature warning ,135C

This bit is reserved

R

000

0

1-0

RESERVED

00

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9.6.1.41 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]

PIN_CONTROL1 is shown in Figure 122 and described in Table 47.

Return to Summary Table.

Figure 122. PIN_CONTROL1 Register

7

6

5

4

3

2

1

0

MASK_OTSD MASK_DVDD_ MASK_DVDD_ MASK_CLK_F MASK_PVDD_ MASK_PVDD_

MASK_DC

MASK_OC

UV

OV

AULT

UV

OV

R/W

Table 47. PIN_CONTROL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

MASK_OTSD

R/W

0

Mask OTSD fault report

Mask DVDD UV fault report

Mask DVDD OV fault report

Mask clock fault report

Mask PVDD UV fault report

Mask PVDD OV fault report

Mask DC fault report

MASK_DVDD_UV

MASK_DVDD_OV

MASK_CLK_FAULT

MASK_PVDD_UV

MASK_PVDD_OV

MASK_DC

R/W

0

MASK_OC

Mask OC fault report

9.6.1.42 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]

PIN_CONTROL2 is shown in Figure 123 and described in Table 48.

Return to Summary Table.

Figure 123. PIN_CONTROL2 Register

7

6

5

4

3

2

1

0

RESERVED

CLKFLT_LATC OTSD_LATCH OTW_LATCH_

MASK_OTW

RESERVED

H_EN

_EN

EN

R/W

Table 48. PIN_CONTROL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RESERVED

R/W

11

This bit is reserved

CLKFLT_LATCH_EN

OTSD_LATCH_EN

OTW_LATCH_EN

MASK_OTW

R/W

1

Enable clock fault latch

Enable OTSD fault latch

Enable OT warning latch

Mask OT warning report

This bit is reserved

4

1

3

1

2

0

1-0

RESERVED

00

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9.6.1.43 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]

MISC_CONTROL is shown in Figure 124 and described in Table 49.

Return to Summary Table.

Figure 124. MISC_CONTROL Register

7

6

5

4

3

2

1

0

DET_STATUS_

LATCH

RESERVED

R/W

OTSD_AUTO_

REC_EN

RESERVED

R/W

Table 49. MISC_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DET_STATUS_LATCH

R/W

0

1:Latch clock detection status

0:Don't latch clock detection status

6-5

4

RESERVED

R/W

00

This bit is reserved

OTSD_AUTO_REC_EN

RESERVED

0

OTSD auto recovery enable

This bit is reserved

3-0

0000

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9.6.1.44 HP_CONTROL Register (Offset = 77h) [reset = 0x00]

HP_CONTROL is shown in Figure 125 and described in Table 50.

Return to Summary Table.

Figure 125. HP_CONTROL Register

7

6

5

4

3

2

1

0

HP_GAIN

HP_MUTEZ

HP_SDZ

HP_FAST_STA

RT_UP

R/W

Table 50. HP_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

7:3

HP_GAIN

R/W

00000

Headphone gain

0: 0dB

1: 1dB

...

24: 24dB

25~31: reserved

2

1

0

HP_MUTEZ

HP_SDZ

R/W

0

0: Mute Headphone

1: Un-mute Headphone

0: Shutdown Headphone

1: Enable Headphone

RESERVED

This bit is reserved

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9.6.1.45 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]

FAULT_CLEAR is shown in Figure 126 and described in Table 51.

Return to Summary Table.

Figure 126. FAULT_CLEAR Register

7

6

5

4

3

2

1

0

ANALOG_FAU

LT_CLEAR

RESERVED

W

R/W

Table 51. FAULT_CLEAR Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ANALOG_FAULT_CLEAR

RESERVED

W

0

WRITE CLEAR BIT.

Once write this bit to 1, device will clear analog fault

6-0

R/W

0000000

This bit is reserved

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10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section details the information required to configure the device for several popular configurations and

provides guidance on integrating the TAS5806MD device into the larger system.

10.1.1 Bootstrap Capacitors

The output stage of the TAS5806MD uses a high-side NMOS driver, rather than a PMOS driver. To generate the

gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating

power supply for the switching cycle. Use 0.22-µF capacitors to connect the appropriate output pin (OUT_X) to

the bootstrap pin (BST_X). For example, connect a 0.22-µF capacitor between OUT_A and BST_A for

bootstrapping the A channel. Similarly, connect another 0.22-µF capacitor between the OUT_B and BST_B pins

for the B channel inverting output.

10.1.2 Inductor Selections

It is required that the peak current is smaller than the OCP (Over current protection) value which is 5A, there are

3 cases which cause high peak current flow through inductor.

1. During power up (idle state, no audio input), the duty cycle increases from 0 to θ.

I_{peak _ power _up}ö PVDD ì C / L ìsin(1/ LìC ìq / F_sw)

(1)

注

θ = 0.5 (BD Modulation), 0.14 (1SPW Modulation), 0.14 (Hybrid Modulation)

表 52. Peak current during power up

PWM

Modulatio PVDD

n

L (uH)

C (uF)

Fsw (kHz)

I_{peak_power_up}

Comments

24

12

4.7

10

0.68

384 (80kHz BW)

768 (175kHz BW)

6.07A (>5A OCP)

1. Lower Switching Frequency only permits low

Class D Loop Bandwidth, which cause worse

THD+N.

3A

4.7

10

3.32A

1.55A

3.25A

2. Lower Switching Frequency cause higher

startup peak current, which needs Inductor

supports higher saturation current.

12

BD

24

4.7

Modulation

(θ=0.5)

3. BD Mode has more switching loss than 1SPW

mode, so the thermal performance is worse

with high PVDD, recommend 1SPW mode for

high PVDD case (Typical >16V case).

24

10

0.68

768 (175kHz BW)

1.55A

4. Saturation

current

.

of

Inductor

needs

>I_{peak_power_up}

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Application Information (接下页)

表 52. Peak current during power up (接下页)

PWM

Modulatio PVDD

n

L (uH)

C (uF)

Fsw (kHz)

I_{peak_power_up}

Comments

24

12

4.7

10

0.68

384 (80kHz BW)

768 (175kHz BW)

1.84A

0.87A

0.92A

0.44A

0.46A

0.93A

1. 1SPW mode with smaller duty cycle during

start up cause smaller I_{peak_power_up}

4.7

10

1SPW

Modulation

(θ=0.14)

12

24

4.7

1. Even with same Inductor value, higher

switching

frequency

cause

smaller

I_{peak_power_up}which means some lower cost

inductor with less saturation current is

permitted.

24

10

0.68

768 (175kHz BW)

0.87A

2. 768kHz switching frequency,175kHz Loop

Bandwidth with 1SPW mode is a good balance

for both thermal and audio performance.

2. During music playing, some audio burst signal (high frequency) with very hard PVDD clipping will cause

PWM duty cycle increase dramatically. This is the worst case and it rarely happens.

I_{peak _clipping}ö PVDDì(1-q)/(F ì L)

sw

(2)

表 53. Peak current during PVDD clipping with Burst Signal

PWM

Modulation

PVDD L (uH)

Fsw (kHz)

I_{peak_clipping}

Comments

24

12

24

12

10

4.7

10

4.7

768

576

384

768

384

768

2.68A

3.58A

1SPW

5.37A (>5A OCP)

1.34A

For high PVDD case, 1SPW mode is a good option to improve

thermal performance, but switching frequency can't be too low.

2.86A

1.56

3.12

BD

0.78

1.66

3. Peak current due to Max output power. Ignore the ripple current flow through capacitor here.

I_{peak _ output _ power}ö 2ì Max _Output _ Power / R_{spea ker_ Load}

(3)

Same PVDD and switching frequency, larger inductance means smaller idle current for lower power dissipation.

It's suggested that inductor's saturation current Isat, is larger than the amplifier's peak current during power-up

and play audio.

I_SATí max(I_{peak_ power_up},I _{peak_clipping},I_{peak_output_ power}

)

(4)

In addition, the effective inductance at the peak current is required to be at least 80% of the inductance value in

表 54 to meet datasheet specifications. The minimum inductance is given in 表 54 .

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表 54. LC filter recommendation

Recommended Minimum Inductance (µH)

for LC filter design

Switching Frequency (kHz)

Modulation Scheme

≤12

>12

≤12

>12

4.7 µH + 0.68 µF

10 µH + 0.68 µF

15 µH + 0.68 µF

384

BD

1 SPW/Hybrid

For higher switching frequency (Fsw), select inductors with minimum inductance to be 384 kHz/F_sw× L.

10.1.3 Power Supply Decoupling

To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise

transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency

components that extend into the hundreds of megahertz. The power supply input must be decoupled with some

good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to

the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the

PVDD pins of the device.

10.1.4 Output EMI Filtering

The TAS5806MD device is often used with a low-pass filter, which is used to filter out the carrier frequency of the

PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive

element L and a capacitive element C to make up the 2-pole filter.

The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current

waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several

system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a

simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that

are commonly used. In other high-power applications, large toroid inductors are required for maximum power and

film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter Design

(SLOA119) for a detailed description on the proper component selection and design of an L-C filter based upon

the desired load and response.

10.2 Typical Applications

10.2.1 2.0 (Stereo BTL) System

In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels are

amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated based

upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered 2.0.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the

audio for the left channel and the other channel containing the audio for the right channel. While certainly the two

channels can contain any two audio channels, such as two surround channels of a multi-channel speaker

system, the most popular occurrence in two channels systems is a stereo pair.

图 127 shows the 2.0 (Stereo BTL) system application.

75

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

Typical Applications (接下页)

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图 127. 2.0 (Stereo BTL) System Application Schematic

10.2.2 Design Requirements

•

Power supplies:

–

3.3-V or 1.8-V supply for DVDD.

3.3V for HPVDD.

4.5-V to 24-V supply for PVDD.

•

Communication: host processor serving as I²C compliant master.

Externa memory (Such as EEPROM or FLASH) used for coefficients.

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Typical Applications (接下页)

10.2.3 Detailed Design Procedure

The design procedure can be used for Stereo 2.0, Mono, 2.1 system

10.2.3.1 Step 1: Hardware Integration

•

Use the Typical Application Schematic as a guide, integrate the hardware into the system schematic.

Follow the recommended component placement, board layout, and routing given in the example layout

above, integrate the device and its supporting components into the system PCB file.

–

The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the

high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they

are given precedent as design trade-offs are made is recommended.

–

For questions and support, go to the E2E forums (E2E.ti.com). If deviating from the recommended layout

is necessary, go to the E2E forum to request a layout review.

10.2.3.2 Step2: Speaker Tuning

Use the TAS5806MDEVM board and the TAS5806MD tuning software to configure the desired device settings.

10.2.3.3 Software Integration

Use the End System Integration feature of the TAS5806MD tuning software app to generate a baseline

configuration file.

Generate additional configuration files based upon operating modes of the end-equipment and integrate static

configuration information into initialization files.

Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the

main system program.

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ZHCSJT7 –MAY 2019

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Typical Applications (接下页)

10.2.4 Application Curves

10

5

PVcc=12V

T_A=25èC

R_L=6W

PVcc=18V

T_A=25èC

R_L=8W

P _O=1W

P_O=2.5W

P_O=5W

P _O=1W

P_O=2.5W

P_O=5W

5

2

1

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0.2

0.1

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0.002

0.001

0.002

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D10032

D01027

PVDD = 12 V

BTL Load = 6 Ω

PVDD = 18 V

BTL Load = 8 Ω

LC filter = 10 µH + 0.68 µF

Fsw = 768 kHz

LC filter = 4.7 µH + 0.68 µF

Fsw = 768 kHz

图 128. THD+N vs Frequency (1 SPW Mode, PVDD = 12 V,

Load = 6 Ω, BTL Mode)

图 129. THD+N vs Frequency (1 SPW Mode, PVDD = 18 V,

Load = 8 Ω, BTL Mode)

10

PV_CC=12V

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PV_CC=18V

T_A=25èC

5

2

1

2

1

R_L=6W

R_L=8W

0.5

0.2

0.1

0.2

0.1

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0.01

0.02

0.01

f= 20Hz

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f= 10KHz

f= 1kHz

f= 10KHz

0.002

0.001

0.002

0.001

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0.1

1

10

0.01

0.1

1

10 20

Output Power (W)

D101047

D01014087

PVDD = 12 V

BTL Load = 6 Ω

LC filter = 4.7 µH + 0.68 µF

PVDD = 18 V

BTL Load = 8 Ω

LC filter = 10 µH + 0.68 µF

Fsw = 768 kHz

图 130. THD+N vs Output Power (1SPW Mode, PVDD = 12

V, Load = 6 Ω, BTL Mode)

图 131. THD+N vs Output Power (1 SPW Mode, PVDD = 18

V, Load = 8 Ω, BTL Mode)

10

HPVDD=3.3V

T_A=25èC

HPVDD=3.3V

T_A=25èC

5

2

1

2

1

R_L=32W

R_L=10kW

0.5

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f= 1kHz

0.01

0.1

1

0.01

0.1

1

Output Voltage (Vrms)

D30047

D04074

HPVDD = 3.3 V

f = 1 kHz

BTL Load = 32 Ω

HPVDD = 3.3 V

f = 1kHz

BTL Load = 10 kΩ

图 132. THD+N vs Output Voltage

(Headphone load = 32 Ω)

图 133. THD+N vs Output Voltage

(Line driver load = 10 kΩ)

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Typical Applications (接下页)

10.2.5 Mono (PBTL) system

In MONO application, TAS5806MD can be used as PBTL mode to drive sub-woofer with more output power.

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图 134. Mono (PBTL) System Application Schematic

79

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

Typical Applications (接下页)

10.2.6 Application Curves

10

5

10

PV_CC=24V

T_A=25èC

R_L=4W

PVcc=24V

T_A=25èC

R_L=4W

P _O=1W

P_O=2.5W

P_O=5W

5

2

1

2

1

0.5

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0.1

0.2

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f= 20Hz

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f= 1KHz

0.002

0.001

0.002

0.001

20

100

1k

10k 20k

0.01

0.1

1

10 20

Frequency (Hz)

Output Power (W)

D104082

D010573

PVDD = 24 V

1 SPW Mode

PBTL Load = 4 Ω

PVDD = 24 V

1 SPW Mode

PBTL Load = 4 Ω

Fsw = 576 kHz

LC filter = 4.7 µH + 0.68 µF

Fsw = 576 kHz

LC filter = 4.7 µH + 0.68 µF

图 135. THD+N vs Frequency

图 136. THD+N vs Output Power

80

TAS5806MD

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ZHCSJT7 –MAY 2019

11 Power Supply Recommendations

The TAS5806MD device requires three power supplies for proper operation. A high-voltage supply calls PVDD is

required to power the output stage of the speaker amplifier and its associated circuitry. One low-voltage power

supply which is calls DVDD is required to power the various low-power portions of the device. Another low-

voltage power supply which is calls HPVDD for headphone driver. The allowable voltage range for both PVDD,

DVDD and HPVDD supply are listed in the Recommended Operating Conditions table. The two power supplies

do not have a required power-up sequence. The power supplies can be powered on in any order. But once the

device has been initialized, PVDD must keep within the normal operation voltage. Once PVDD lower than 3.5V,

all registers need re-initialize again.

Internal Digital

Digital IO

Circuitry

DVDD

(1.8V/3.3V)

VR_DIG

1.5V

LDO

External Filtering/Decoupling

DVDD

Gate Drive/Internal

Analog Circuitry

Output Stage

Power Supply

PVDD

4.5V~26.4V

AVDD

5V

LDO

External Filtering/Decoupling

PVDD

HPVDD

3.3V

Headphone Driver

(Charge Pump )

HPVDD

图 137. Power Supply Function Block Diagram

11.1 DVDD Supply

The DVDD supply that is required from the system is used to power several portions of the device. As shown in

图 137, it provides power to the DVDD pin. Proper connection, routing and decoupling techniques are highlighted

in the Application and Implementation section and the Layout Example section and must be followed as closely

as possible for proper operation and performance.

Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.

To simplify the power supply requirements for the system, the TAS5806MD device includes an integrated low

dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD

supply and its output is presented on the VR_DIG pin, providing a connection point for an external bypass

capacitor. It is important to note that the linear regulator integrated in the device has only been designed to

support the current requirements of the internal circuitry, and should not be used to power any additional external

circuity. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and

operation of the device.

81

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ZHCSJT7 –MAY 2019

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11.2 PVDD Supply

The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which

provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are

highlighted in the TAS5806MD MEVM and must be followed as closely as possible for proper operation and

performance. Due to the high-voltage switching of the output stage, it is particularly important to properly

decouple the output power stages in the manner described in the TAS5806MD device Application and

Implementation. Lack of proper decoupling, like that shown in the Application and Implementation, results in

voltage spikes which can damage the device.

A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker

amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is

provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note

that the linear regulator integrated in the device has only been designed to support the current requirements of

the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this

pin could cause the voltage to sag, negatively affecting the performance and operation of the device.

Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.

AVDD pin is provided for the attachment of decoupling capacitor for the TAS5806MD internal circuitry. It is

important to note that the linear regulator integrated in the device has only been designed to support the current

requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional

loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the

device.

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TAS5806MD

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12 Layout

12.1 Layout Guidelines

12.1.1 General Guidelines for Audio Amplifiers

Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and

the layout of the supporting components used around them. The system level performance metrics, including

thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all

affected by the device and supporting component layout.

Ideally, the guidance provided in the applications section with regard to device and component selection can be

followed by precise adherence to the layout guidance shown in the Layout Example section. These examples

represent exemplary baseline balance of the engineering trade-offs involved with lying out the device. These

designs can be modified slightly as needed to meet the needs of a given application. In some applications, for

instance, solution size can be compromised to improve thermal performance through the use of additional

contiguous copper neat the device. Conversely, EMI performance can be prioritized over thermal performance by

routing on internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it

is recommended to start from the guidance shown in the Layout Example section and work with TI field

application engineers or through the E2E community to modify it based upon the application specific goals.

12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network

Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This

applies to DVDD, AVDD and PVDD. However, the capacitors on the PVDD net for the TAS5806MD device

deserve special attention.

The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as

possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in

the system, but doing so can also negatively affect the reliability of the device. Placement of these components

too far from the TAS5806MD device can cause ringing on the output pins that can cause the voltage on the

output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging

the deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD

pins than what is shown in the example layouts in the Layout Example section.

12.1.3 Optimizing Thermal Performance

Follow the layout example shown in the 图 138 to achieve the best balance of solution size, thermal, audio, and

electromagnetic performance. In some cases, deviation from this guidance can be required due to design

constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can

get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device

naturally travels away from the device and into the lower temperature structures around the device.

12.1.3.1 Device, Copper, and Component Layout

Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.

These tips should be followed to achieve that goal:

•

Avoid placing other heat producing components or structures near the amplifier (including above or below in

the end equipment).

•

If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5806MD device

and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top

and bottom layer.

•

Place the TAS5806MD device away from the edge of the PCB when possible to ensure that the heat can

travel away from the device on all four sides.

Avoid cutting off the flow of heat from the TAS5806MD device to the surrounding areas with traces or via

strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular

to the device.

•

Unless the area between two pads of a passive component is large enough to allow copper to flow in

between the two pads, orient it so that the narrow end of the passive component is facing the TAS5806MD

device.

Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane

83

TAS5806MD

ZHCSJT7 –MAY 2019

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Layout Guidelines (接下页)

from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.

12.1.3.2 Stencil Pattern

The recommended drawings for the TAS5806MD device PCB foot print and associated stencil pattern are shown

at the end of this document in the package addendum. Additionally, baseline recommendations for the via

arrangement under and around the device are given as a starting point for the PCB design. This guidance is

provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all

other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this

guidance may be too conservative and advanced PCB design techniques may be used to improve thermal

performance of the system.

注

The customer must verify that deviation from the guidance shown in the package

addendum, including the deviation explained in this section, meets the customer’s quality,

reliability, and manufacturability goals.

12.1.3.2.1 PCB footprint and Via Arrangement

The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the

shape and position of the copper patterns to which the TAS5806MD device will be soldered. This footprint can be

followed directly from the guidance in the package addendum at the end of this data sheet. It is important to

make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the

TAS5806MD device, be made no smaller than what is specified in the package addendum. This ensures that the

TAS5806MD device has the largest interface possible to move heat from the device to the board.

The via pattern shown in the package addendum provides an improved interface to carry the heat from the

device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)

present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away

from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the

Layout Example section, this interface can benefit from improved thermal performance.

注

Vias can obstruct heat flow if they are not constructed properly.

More notes on the construction and placement of vias are as follows:

•

Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.

Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the

additional cost of filled vias.

•

The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding

planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,

minimum spacing should be determined by the voltages present on the planes surrounding the via and

minimized wherever possible.

•

Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding

area. This arrangement is shown in the Layout Example section.

Ensure that vias do not cut off power current flow from the power supply through the planes on internal

layers. If needed, remove some vias that are farthest from the TAS5806MD device to open up the current

path to and from the device.

12.1.3.2.2 Solder Stencil

During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste

on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity

and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most

cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the

thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to

84

TAS5806MD

www.ti.com.cn

ZHCSJT7 –MAY 2019

Layout Guidelines (接下页)

manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste

to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is

called an aperture array, and is shown in the Layout Example section. It is important that the total area of the

aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the

thermal pad itself.

12.2 Layout Example

Bot Layer 3D layout

Top Layer 3D layout

图 138. 2.0 (Stereo BTL) 3-D View

85

TAS5806MD

ZHCSJT7 –MAY 2019

www.ti.com.cn

13 器件和文档支持

13.1 器件支持

13.1.1 器件命名规则

Glossary 部分列出的是一个通用的术语表，其中包括常用的缩写和词语，它们都是根据一个范围广泛的 TI 计划定

义的，符合 JEDEC、IPC、IEEE 等行业标准。本部分提供的术语表定义了特定于本产品和文档、附属产品或本产

品使用的支持工具和软件的词语和缩写。如对定义和术语有其他疑问，请访问 e2e 音频放大器论坛。

桥接式负载 (BTL) 是一种输出配置，其中扬声器的两端分别连接一个半桥。

DUT 是指被测器件，用于区分不同的器件。

闭环架构是一种拓扑结构，其中放大器监视输出端子、对比输出信号与输入信号，并尝试修正输出信号的非线性。

动态控件是指系统或最终用户在正常使用时可更改的控件。

GPIO 是通用输入/输出引脚。该引脚是一个高度可配置的双向数字引脚，可执行系统所需的多种功能。

主机处理器（也称系统处理器、标量、主机或系统控制器）是指用作中央系统控制器的器件，可为与其连接的器件

提供控制信息，还可以从上游器件采集音频源数据并将其分配给其他器件。该器件通常配置音频路径中音频处理器

件（如 TAS5806MD）的控件，从而根据频率响应、时间校准、目标声压级、系统安全工作区域和用户偏好优化扬

声器的音频输出。

最大持续输出功率是指放大器在 25°C 运行环境温度下可持续（不关断）提供的最大输出功率。测试该参数时，要

求温度达到热平衡点且不再升高

并联桥接式负载 (PBTL) 是一种输出配置，其中扬声器的两端分别连接一对并行放置的半桥

r_DS(on)是指放大器输出级中所用 MOSFET 的导通电阻。

静态控件/静态配置是指系统正常使用时不发生变化的控件。

过孔是指 PCB 中的镀铜通孔。

13.1.2 开发支持

有关 RDGUI 软件，请咨询当地的现场支持工程师。

13.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

86

TAS5806MD

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13.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

13.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

87

GENERIC PACKAGE VIEW

DCP 38

4.4 x 9.7, 0.5 mm pitch

PowerPAD TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224560/B

www.ti.com

PACKAGE OUTLINE

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX

AREA

SEATING

PLANE

36X 0.5

38

1

2X

9

9.8

9.6

NOTE 3

19

20

0.27

0.17

0.08

38X

4.5

4.3

B

C A B

SEE DETAIL A

(0.15) TYP

2X 0.95 MAX

NOTE 5

19

20

2X 0.95 MAX

NOTE 5

0.25

GAGE PLANE

1.2 MAX

39

4.70

3.94

THERMAL

PAD

0.15

0.05

0.75

0.50

0 -8

A

20

DETAIL A

TYPICAL

1

38

2.90

2.43

4218816/A 10/2018

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

METAL COVERED

BY SOLDER MASK

(2.9)

SYMM

38X (1.5)

38X (0.3)

SEE DETAILS

38

1

(R0.05) TYP

36X (0.5)

3X (1.2)

SYMM

39

(4.7)

(9.7)

NOTE 9

(0.6) TYP

SOLDER MASK

DEFINED PAD

(

0.2) TYP

VIA

20

19

(1.2)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4218816/A 10/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(2.9)

BASED ON

0.125 THICK

STENCIL

38X (1.5)

38X (0.3)

METAL COVERED

BY SOLDER MASK

1

38

(R0.05) TYP

36X (0.5)

(4.7)

SYMM

39

BASED ON

0.125 THICK

STENCIL

19

20

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.24 X 5.25

2.90 X 4.70 (SHOWN)

2.65 X 4.29

0.125

0.15

0.175

2.45 X 3.97

4218816/A 10/2018

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TAS5806MDDCPR
厂家：	TEXAS INSTRUMENTS
描述：	具有处理功能和 P2P HP 的 23W 立体声、45W 单声道、4.5V 至 26.4V、数字输入 D 类音频放大器 \| DCP \| 38 \| -25 to 85 放大器音频放大器
文件：	总93页 (文件大小：2092K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TAS5806MDDCPR [TI]

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