TAS5805MPWPR [TI]
具有处理功能的 23W 立体声、45W 单声道、4.5V 至 26.4V 电源电压、数字输入 D 类音频放大器 | PWP | 28 | -25 to 85;
| 型号： | TAS5805MPWPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有处理功能的 23W 立体声、45W 单声道、4.5V 至 26.4V 电源电压、数字输入 D 类音频放大器 | PWP | 28 | -25 to 85 放大器 音频放大器 |
| 文件： | 总103页 (文件大小：4451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5805M
ZHCSI92D –MAY 2018 –REVISED NOVEMBER 2020
具有增强处理能力和低功率损耗的TAS5805M 23W、无电感器、数字输入、立
体声、闭环D 类音频放大器
• 无线扬声器、智能扬声器（带语音助理）
• 条形音箱、有线扬声器、书架立体声系统
1 特性
• 台式计算机、笔记本电脑
• AV 接收器、智能家居和物联网电器
• 支持多路输出配置
– 2.0 模式（8Ω，21V，THD+N=1%）下可提供
2 × 23W 的功率
– 单声道模式（4Ω，21V，THD+N=1%）下可提
供45W 的功率
• 优异的音频性能
3 说明
TAS5805M 是一款高效立体声闭环 D 类放大器，可提
供具有低功率耗散和丰富声音的低成本数字输入解决方
案。该器件的集成音频处理器和 96kHz 架构支持高级
音频处理流程（包括 SRC、每通道 15 个 BQ、音量控
制、音频混合、3 频带 4 阶 DRC、全频带 AGL、THD
管理器和电平计）。
– 1W、1kHz、PVDD = 12V 条件下THD+N ≤
0.03%
– SNR ≥107dB（A 加权），噪声级别<
40µVRMS
• 低静态电流（混合调制）
TAS5805M 采用 TI 的专有混合调制方案，消耗超低的
静态电流（13.5V PVDD 下为 16.5mA），从而能够延
长便携式音频应用中的电池寿命。凭借先进的 EMI 抑
制技术，设计人员可以利用廉价的铁氧体磁珠滤波器来
减小布板空间并降低系统成本。
– PVDD = 13.5V 且使用22µH + 0.68µF 滤波器的
情况下为16.5mA
• 灵活的电源配置
– PVDD：4.5V 至26.4V
– DVDD 和I/O：1.8V 或3.3V
• 灵活的音频I/O
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TAS5805M
– I2S、LJ、RJ、TDM、3 线数字音频接口（无需
TSSOP (28) PWP 9.7mm × 4.4mm
MCLK）
– 支持32、44.1、48、88.2、96kHz 采样速率
– 可支持音频监控、子通道或回声消除的SDOUT
• 增强的音频处理能力
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
Speaker
Channel
Speaker
R Channel
L
– 多频带高级DRC 和AGL
– 2×15 个BQ
– 热折返、直流阻断
– 输入混合器、输出交叉开关
– 电平计
– 5 个BQ + 单频带DRC + THD 管理器（用于低
音炮通道）
– 声场定位器(SFS) 选项
• 集成式自保护
– 邻近的引脚对引脚短路不会造成损坏
– 过流错误(OCE)
– 过热警告(OTW)
DVDD
Digital
Audio
Source
System
Processor
Copyright
© 2018, Texas Instruments Incorporated
– 过热错误(OTE)
– 欠压/过压锁定(UVLO/OVLO)
• 可轻松进行系统集成
简化版方框图
– I2C 软件控制
– 解决方案尺寸更小
• 与开环器件相比，所需的无源器件更少
• 对于PVDD ≤14V 的大多数情况，可实现无
电感器操作（铁氧体磁珠）
2 应用
• LCD 电视、OLED 电视
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEH5
TAS5805M
ZHCSI92D –MAY 2018 –REVISED NOVEMBER 2020
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................36
7.5 Programming and Control.........................................41
7.6 Register Maps...........................................................47
8 Application and Implementation..................................77
8.1 Application Information............................................. 77
8.2 Typical Applications.................................................. 79
9 Layout.............................................................................89
9.1 Layout Guidelines..................................................... 89
9.2 Layout Example........................................................ 91
10 Device and Documentation Support..........................92
10.1 Device Support....................................................... 92
10.2 Receiving Notification of Documentation Updates..93
10.3 支持资源..................................................................93
10.4 Trademarks.............................................................93
10.5 静电放电警告.......................................................... 93
10.6 术语表..................................................................... 93
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................5
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................8
6.6 Timing Requirements................................................ 11
6.7 Typical Characteristics..............................................12
7 Detailed Description......................................................29
7.1 Overview...................................................................29
7.2 Functional Block Diagram.........................................29
7.3 Feature Description...................................................29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (December 2018) to Revision D (November 2020)
Page
• Added note 1 to the Recommended Operating Conditions ............................................................................... 7
• Added capacitve load for each bus line, Cb = 400 pf to the I2C timming parameters in the Timing
Requirements ...................................................................................................................................................11
• Change the I2C BUS Timming-Standard. Data Hold Time max value from 900 ns to 3450 ns in the Timing
Requirements ...................................................................................................................................................11
• Added efficiency plot and 1%/10% THD+N output power vs PVDD plot for 4-Ωload..................................... 12
• Added notes the Hybrid Modulation section..................................................................................................... 40
• Added Speaker DC Protection, Device Over Temperature Protection, Device Over Voltage/Under Voltage
Protection, and Clock Fault sections................................................................................................................ 46
Changes from Revision B (October 2018) to Revision C (December 2018)
Page
• Added 图7-14 ..................................................................................................................................................45
• Added 图7-15 ..................................................................................................................................................45
Changes from Revision A (July 2018) to Revision B (October 2018)
Page
• 在说明中将“（13.5V PVDD 下小于16.5mA）”更改为“（13.5V PVDD 下为16.5mA）”..........................1
• Changed the Typical Characteristics graphs.................................................................................................... 12
• Added the Clock Halt Auto-recover section......................................................................................................31
• Added the Sample Rate on the Fly Change section.........................................................................................31
• Added the Thermal Foldback section............................................................................................................... 37
• Changed the Device State Control section.......................................................................................................37
• Changed the DSP Memory Book, Page and BQ Coefficients Update section................................................. 43
• Added the Example Use section.......................................................................................................................43
• Deleted 010:310K in 表7-9 ............................................................................................................................. 47
• Added the Inductor Selections section............................................................................................................. 77
• Added the Step 2: Speaker Tuning section...................................................................................................... 82
• Changed the Development Support section.....................................................................................................92
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Changes from Revision * (May 2018) to Revision A (July 2018)
Page
• 发布为“量产数据”........................................................................................................................................... 1
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Device Comparison Table
ORDERABLE PART
NUMBER
RECOMMENDED
PVDD RANGE
Audio Process Flows
RDS(ON)
TAS5805M
4.5 V to 26.4 V
8 V to 26 V
Enhanced Audio Process Flows with ROM Fixed
Basic Audio Process Flow with ROM Fixed
180 mΩ
180 mΩ
TAS5707/TAS5711
Flexible Advanced Audio Process Flows with Smart-Amp
Features
TAS5825M
4.5 V to 26.4 V
90 mΩ
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5 Pin Configuration and Functions
图5-1. PWP Package, 28-Pin TSSOP,
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
DGND
DVDD
VR_DIG
NO.
1, 5
2
P
P
P
Digital ground
3.3-V or 1.8-V digital power supply
4
Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
Different I2 C device address can be set by selecting different pull up resistor to DVDD, see 表7-5 for details. After
power up, ADR/ FAULT can be redefine as FAULT, go to Page0, Book0, set register 0x61 = 0x0b first, then set
register 0x60 = 0x01
ADR/ FAULT
LRCLK
3
6
DI/O
DI
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this
corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync
boundary
SCLK
SDIN
SDOUT
SDA
7
8
DI
DI
Bit clock for the digital signal that is active on the input data line of the serial data port.
Data line to the serial data port
9
DO
DI/O
DI
Serial Audio data output. The source data can be Pre-DSP or Post-DSP data, by setting the register 0x30h.
I2C serial control data interface input/output
10
11
SCL
I2C serial control clock input
Power Down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators. Low, Power Down
Device; High, Enable Device.
PDN
12
DI
AVDD
AGND
13
14
P
P
Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
Analog ground
15,16,27,
28
PVDD
P
PVDD voltage input
PGND
19,24
26
P
Ground reference for power device circuitry. Connect this pin to system ground.
Positive pin for differential speaker amplifier output A+
OUT_A+
O
Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_A+
BST_A+
OUT_A-
25
23
P
O
Negative pin for differential speaker amplifier output A-
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_A-
BST_A-
22
P
Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_B-
BST_B-
OUT_B-
BST_B+
21
20
18
17
P
O
P
Negative pin for differential speaker amplifier output B
Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_B+
OUT_B+
O
P
Positive pin for differential speaker amplifier output B+
Connect to the system Ground
PowerPAD™
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =
Power, G = Ground (0 V)
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6 Specifications
6.1 Absolute Maximum Ratings
Free-air room temperature 25°C (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.5
–0.3
–25
–40
MAX
UNIT
V
DVDD
PVDD
VI(DigIn)
VI(SPK_OUTxx)
TA
Low-voltage digital supply
PVDD supply
3.9
30
VDVDD + 0.5
32
V
DVDD referenced digital inputs(2)
Voltage at speaker output pins
Ambient operating temperature
Storage temperature
V
V
85
°C
°C
Tstg
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) DVDD referenced digital pins include: ADR/ FAULT, LRCLK, SCLK, SCL, SDA, SDIN, PDN
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) see (1)
MIN
1.62
4.5
NOM
MAX
3.63
26.4
UNIT
DVDD
PVDD
V(POWER)
Power supply inputs
V
VOUTPEAK
OCETHRES
/
RSPK
RSPK
LOUT
Minimum speaker load
Minimum speaker load
6
BTL Mode (4.5V≤PVDD≤26.4V)
PBTL Mode (4.5V≤PVDD≤26.4V)
Ω
VOUTPEAK
(2×OCETHRES
/
4
Ω
)
Minimum inductor value in LC filter under short-circuit condition
1
4.7
µH
(1) The minimal speaker load been limited by OCE Threshold, if output peak current <5A, TAS5805M also supports lower speaker load
with High PVDD. For BTL, the OCE Threshold is 5A (Typical); For PBTL, the OCE Threshold is 10A (Typical). The minimal speaker
load depends on the output peak voltage.
6.4 Thermal Information
TAS5805M
TSSOP (PWP)
28 PINS
THERMAL METRIC(1)
UNIT
JEDEC
STANDARD
2-LAYER PCB
JEDEC
STANDARD
4-LAYER PCB
TAS5805MEVM-4
4-LAYER PCB
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
N/A
N/A
N/A
N/A
N/A
N/A
29.1
21.8
8.2
24
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
N/A
N/A
1.5
7.6
N/A
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
8.1
ψJB
RθJC(bot)
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL I/O
Input logic high current level
for DVDD referenced digital
input pins
|IIH|
VIN(DigIn) = VDVDD
10
µA
µA
Input logic low current level for
DVDD referenced digital input VIN(DigIn) = 0 V
pins
|IIL|
–10
Input logic high threshold for
DVDD referenced digital inputs
VIH(Digin)
VIL(Digin)
70%
80%
VDVDD
VDVDD
Input logic low threshold for
DVDD referenced digital inputs
30%
20%
400
VOH(Digin)
VOL(Digin)
I2C CONTROL PORT
Output logic high voltage level IOH = 2 mA
VDVDD
VDVDD
Output logic low voltage level
IOH = –2 mA
Allowable load capacitance for
CL(I2C)
pF
each I2C line
fSCL(fast)
fSCL(slow)
SERIAL AUDIO PORT
Support SCL frequency
No wait states, fast mode
No wait states, slow mode
400
100
kHz
kHz
Support SCL frequency
Required LRCLK/FS to SCLK
rising edge delay
tDLY
5
ns
DSCLK
fS
fSCLK
fSCLK
Allowable SCLK duty cycle
Supported input sample rates
Supported SCLK frequencies
SCLK frequency
40%
32
60%
96
kHz
fS
32
64
24.576
MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
Quiescent supply current on
DVDD
Icc
Icc
Icc
Icc
Icc
Icc
Icc
Icc
Icc
PDN=2V, DVDD=3.3V, Play mode
18
0.75
0.75
5.5
mA
mA
mA
µA
Quiescent supply current on
DVDD
PDN=2V, DVDD=3.3V, Sleep mode
PDN=2V, DVDD=3.3V, Deep Sleep mode
PDN=0V, DVDD=3.3V, Shutdown mode
Quiescent supply current on
DVDD
Quiescent supply current on
DVDD
Quiescent supply current on
PVDD
PDN=2V,, PVDD=13.5V, LC filter=10uH+0.68uF,
Fsw=768kHz, BD Modulation, Play mode
32.5
16.5
10.4
7.2
mA
mA
mA
mA
µA
Quiescent supply current on
PVDD
PDN=2V,, PVDD=13.5V, LC filter=22uH+0.68uF,
Fsw=384kHz, Hybrid Modulation, Play mode
Quiescent supply current on
PVDD
PDN=2V, PVDD=13.5V, Output Hiz Mode
PDN=2V, PVDD=13.5V, Sleep Mode
PDN=2V, PVDD=13.5V, Deep Sleep Mode
Quiescent supply current on
PVDD
Quiescent supply current on
PVDD
120
7.2
Quiescent supply current on
PVDD
Icc
toff
PDN=0V, PVDD=13.5V, Shutdown Mode
Excluding volume ramp
µA
ms
Turn-off Time
10
Value represents the "peak voltage" disregarding
clipping due to lower PVDD).
Measured at 0 dB input(1FS)
AV(SPK_AMP)
Programmable Gain
Amplifier gain error
4.87
29.5
V
Gain = 29.5 Vp/FS
0.5
384
768
dB
ΔAV(SPK_AMP)
kHz
kHz
Switching frequency of the
speaker amplifier
fSPK_AMP
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Drain-to-source on resistance
of the individual output
MOSFETs
RDS(on)
FET + Metallization
180
mΩ
OCETHRES
Over-Current Error Threshold OUTxx Overcurrent Error Threshold
5
A
V
PVDD over voltage error
threshold
OVETHRES(PVDD
28
PVDD under voltage error
threshold
UVETHRES(PVDD
OTETHRES
4.2
160
10
V
Over temperature error
threshold
°C
°C
°C
Over temperature error
hysteresis
OTEHystersis
OTWTHRES
Over temperature warning
Read by register 0x73 bit3
level
135
SPEAKER AMPLIFIER (STEREO BTL)
Measured differentially with zero input data,
programmable gain configured with 29.5 Vp gain,
VPVDD = 12 V, BD Mode
|VOS
|
Amplifier offset voltage
6.5
mV
–6.5
VPVDD = 21V, SPK_GAIN = 24.8 Vp/FS, RSPK = 8
Ω, f = 1 kHz, THD+N = 1%, 1SPW Mode
23
27.5
21
W
W
W
W
W
W
W
W
VPVDD = 21 V, SPK_GAIN = 24.8 Vp/FS, RSPK = 8
Ω, f = 1 kHz, THD+N = 10%, 1SPW Mode
VPVDD = 18 V, SPK_GAIN = 20.8 Vp/FS, RSPK = 6
Ω, f = 1 kHz, THD+N = 1%, BD Mode
VPVDD = 18 V, SPK_GAIN = 20.8 Vp/FS, RSPK = 6
Ω, f = 1 kHz, THD+N = 10%, BD Mode
25
Continuous Output power (per
channel)
PO(SPK)
VPVDD = 12 V, SPK_GAIN = 13.9 Vp/FS, RSPK = 6
Ω, f = 1 kHz THD+N = 1%, BD Mode
9.9
VPVDD = 12 V, SPK_GAIN = 13.9 Vp/FS, RSPK = 6
Ω, f = 1 kHz THD+N = 10%, BD Mode
12
VPVDD = 13.5 V, SPK_GAIN = 15.6 Vp/FS, RSPK
= 6 Ω, f = 1 kHz THD+N = 1%, BD Mode
12
VPVDD = 13.5 V, SPK_GAIN = 15.6 Vp/FS, RSPK
= 6 Ω, f = 1 kHz THD+N = 10%, BD Mode
15
VPVDD = 12 V, Fsw=768kHz, SPK_GAIN = 13.9
Vp/FS, LC-filter, BD Mode
Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz, RSPK = 6
Ω)
0.03%
0.03%
THD+NSPK
VPVDD = 18 V, Fsw=768kHz, SPK_GAIN = 20.8
Vp/FS, LC-filter, BD Mode
37
38
VPVDD = 12 V, Fsw=768kHz, LC-filter, Load=6 Ω
VPVDD = 18 V, Fsw=768kHz, LC-filter, Load=6 Ω
ICN(SPK)
Idle channel noise(A-weighted)
Dynamic range
µVrms
A-Weighted, -60 dBFS method. PVDD = 24 V,
SPK_GAIN = 29.5 Vp/FS
DR
106
111
dB
dB
dB
dB
A-Weighted, referenced to 1% THD+N output level,
PVDD=24V
SNR
Signal-to-noise ratio
A-Weighted, referenced to 1% THD+N output level,
PVDD=13.5V
107.5
72
Injected Noise = 1 KHz, 1 Vrms, PVDD = 12 V, input
audio signal = digital zero
KSVR
Power supply rejection ratio
Cross-talk (worst case
X-talkSPK
between left-to-right and right- f = 1 kHz
to-left coupling)
100
dB
SPEAKER AMPLIFIER (MONO PBTL)
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPVDD = 12 V, SPK_GAIN = 13.9 Vp/FS, RSPK = 4
Ω, f = 1kHz, THD+N = 1%, BD Mode
15.4
W
VPVDD = 12 V, SPK_GAIN = 13.9 Vp/FS, RSPK = 4
Ω, f = 1kHz, THD+N = 10%, BD Mode
18.5
33.6
41
W
W
W
PO(SPK)
Continuous Output Power
VPVDD = 18V, SPK_GAIN = 22.1 Vp/FS, RSPK = 4
Ω, f = 1kHz, THD+N = 1%, BD Mode
VPVDD = 18 V, SPK_GAIN = 22.1 Vp/FS, RSPK = 4
Ω, f = 1kHz, THD+N = 10%, BD Mode
VPVDD = 12 V, SPK_GAIN = 16.5 Vp/FS, 4.7uH +
0.68uF filter, RSPK = 4 Ω, BD Mode
0.06%
0.07%
106
Total harmonic distortion and
noise
(PO = 1 W, f = 1 kHz)
THD+NSPK
VPVDD = 24 V, SPK_GAIN = 29.5 Vp/FS, 4.7uH +
0.68uF filter, RSPK = 4 Ω, 1SPW Mode
A-Weighted, -60 dBFS method, PVDD = 24V,
SPK_GAIN = 29.5 Vp/FS
DR
Dynamic range
dB
dB
dB
dB
A-Weighted, referenced to 1% THD+N output level,
PVDD=13.5V
107.7
111
SNR
Signal-to-noise ratio
Power supply rejection ratio
A-Weighted, referenced to 1% THD+N output level,
PVDD=24V
Injected Noise = 1 KHz, 1 Vrms, PVDD = 19 V, input
audio signal = digital zero
KSVR
72
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
Serial Audio Port Timing
fSCLK
tSCLK
tSCLKL
tSCLKH
tSL
SCLK frequency
1.024
40
16
16
8
MHz
ns
SCLK period
SCLK pulse width, low
ns
SCLK pulse width, high
ns
SCLK rising to LRCK/FS edge
LRCK/FS Edge to SCLK rising edge
Data setup time, before SCLK rising edge
Data hold time, after SCLK rising edge
Data delay time from SCLK falling edge
ns
tLS
8
ns
tSU
8
ns
tDH
8
ns
tDFS
15
ns
I2C Bus Timing –Standard
fSCL
SCL clock frequency
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
4.7
tLOW
tHI
4.7
High period of the SCL clock
Setup time for (repeated) START condition
Hold time for (repeated) START condition
Data setup time
4
tRS-SU
tS-HD
tD-SU
tD-HD
tSCL-R
4.7
4
250
Data hold time
0
3450
1000
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
tSCL-R1
20 + 0.1CB
1000
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
CB
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
4
1000
1000
1000
ns
ns
ns
µs
pf
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Capacitve load for each bus line
400
400
I2C Bus Timing –
Fast
fSCL
SCL clock frequency
kHz
µs
µs
ns
ns
ns
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for (repeated)START condition
Hold time for (repeated)START condition
Data setup time
1.3
tLOW
tHI
1.3
600
tRS-SU
tRS-HD
tD-SU
tD-HD
tSCL-R
600
600
100
Data hold time
0
900
300
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
tSCL-R1
20 + 0.1CB
300
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
tSP
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
600
300
300
300
ns
ns
ns
ns
ns
pf
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Pulse width of spike suppressed
Capacitve load for each bus line
50
CB
400
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6.7 Typical Characteristics
6.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Mode
Free-air room temperature 25°C (unless otherwise noted.) Measurements were made using TAS5805MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM Modulation mode set to 1SPW mode
with Class D Bandwidth = 120 kHz for 576 kHz Fsw and Class D Bandwidth = 175 kHz for 768 kHz Fsw (Listed
in Register 0x53) unless otherwise noted.
10
5
10
5
PVcc=5V
TA=25èC
RL=4W
PVcc=7.4V
TA=25èC
RL=4W
P O=0.5W
PO =1W
P O=0.5W
PO =1W
PO=2.5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D010324
D0103412
PVDD = 5 V
4.7µH+0.68µF
PVDD = 7.4 V
FSW = 576 kHz
4.7µH+0.68µF
FSW = 576 kHz
1SPW Modulation
1SPW Modulation
Load = 4Ω
Load = 4Ω
图6-1. THD+N vs Frequency-BTL
图6-2. THD+N vs Frequency-BTL
10
10
PVcc=12V
TA=25èC
RL=4W
Fsw=768kHz
1SPW Mode
PVcc=18V
TA=25èC
RL=4W
Fsw=768kHz
1SPW Mode
P O=1W
PO=2.5W
PO=5W
P O=1W
PO=2.5W
PO=5W
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
DF01021
DF0102
PVDD = 12 V
10µH+0.68µF
PVDD = 18 V
10µH+0.68µF
FSW = 768 kHz
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
Load = 4Ω
Load = 4Ω
图6-3. THD+N vs Frequency-BTL
图6-4. THD+N vs Frequency-BTL
10
10
PVcc=24V
TA=25èC
RL=4W
Fsw=768kHz
1SPW Mode
PVcc=12V
TA=25èC
RL=6W
P O=1W
PO=2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
DF01023
D01023
PVDD = 24 V
10µH+0.68µF
PVDD = 12 V
4.7µH+0.68µF
FSW = 768 kHz
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
Load = 4Ω
Load = 6Ω
图6-5. THD+N vs Frequency-BTL
图6-6. THD+N vs Frequency-BTL
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10
10
5
PVcc=18V
TA=25èC
RL=6W
PVcc=24V
TA=25èC
RL=6W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D10042
D01025
PVDD = 18 V
10µH+0.68µF
PVDD = 24 V
10µH+0.68µF
FSW = 768 kHz
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
Load = 6Ω
Load = 6Ω
图6-7. THD+N vs Frequency-BTL
图6-8. THD+N vs Frequency-BTL
10
10
PVcc=12V
TA=25èC
RL=8W
PVcc=18V
TA=25èC
RL=8W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D10062
D01027
PVDD = 12 V
4.7uH+0.68uF
PVDD = 18 V
10µH+0.68µF
FSW = 768 kHz
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
Load = 8Ω
Load = 8Ω
图6-9. THD+N vs Frequency-BTL
图6-10. THD+N vs Frequency-BTL
10
10
PVcc=24V
TA=25èC
RL=8W
PVcc=19V
TA=25èC
RL=6W
P O=1W
PO =2.5W
PO=5W
BD Mode
1SPW Mode
Hybrid Mode
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D10082
D010120
PVDD = 24 V
10µH+0.68µF
PVDD = 19 V
10µH+0.68µF
POUT = 5W
FSW = 768 kHz
1SPW Modulation
FSW = 384 kHz
BD/1SPW/Hybrid
Load = 8Ω
Load = 6Ω
图6-11. THD+N vs Frequency-BTL
图6-12. THD+N vs Frequency-BTL
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40
45
40
35
30
25
20
15
10
5
TA=25èC
RL=4W
Fsw=768kHz
BTL Mode
1SPW Mode
THD+N=1%, R L=6W
THD+N=10%, R L=6W
35
30
25
20
15
10
5
BTL Mode
TA=25èC
THD+N=1%
THD+N=10%
0
0
4
6
8
10
12
14
16
Supply Voltage (V)
18
20
22
24
4.5
6.5
8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24
Supply Voltage (V)
D014
DF033071
D014
D013271
NOTE: Dashed lines represent thermally limited region for the
continuous output power.
NOTE: Dashed lines represent thermally limited region for the
continuous output power.
PVDD = 4.5 V~24V 10µH+0.68µF
PVDD = 4.5 V~24V 10µH+0.68µF
FSW = 768 kHz
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
Load = 4Ω
Load = 6Ω
图6-13. Output Power vs Supply Voltage-BTL
图6-14. Output Power vs Supply Voltage-BTL
40
10
PVCC=5V
TA=25èC
RL=4W
THD+N=1%, R L=8W
THD+N=10%, R L=8W
5
35
30
25
20
15
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.005
BTL Mode
TA=25èC
0.002
0.001
0
4.5
6.5
8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24
Supply Voltage (V)
0.01
0.1
1
10
Output Power (W)
D014
D013272
D010172
PVDD = 4.5 V~24V 10µH+0.68µF
FSW = 768 kHz 1SPW Modulation
PVDD = 5V
FSW = 768 kHz
4.7µH+0.68µF
1SPW Modulation
Load = 8Ω
Load = 4Ω
图6-15. Output Power vs Supply Voltage-BTL
图6-16. THD+N vs Output Power-BTL
10
10
PVCC=12V
TA=25èC
RL=4W
BTL Mode
PVCC=18V
TA=25èC
RL=4W
BTL Mode
5
5
2
2
1
1
Fsw=768kHz
1SPW Mode
Fsw=768kHz
1SPW Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 1kHz
f= 10KHz
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
DF02071
DF02072
PVDD = 12V
10µH+0.68µF
PVDD = 18V
10µH+0.68µF
FSW = 768 kHz
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
Load = 4Ω
Load = 4Ω
图6-17. THD+N vs Output Power-BTL
图6-18. THD+N vs Output Power-BTL
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10
10
5
PVCC=12V
TA=25èC
RL=6W
PVCC=18V
TA=25èC
RL=6W
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 1kHz
f= 10KHz
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10
0.01
0.1
1
Output Power (W)
10 20
D101047
D010175
PVDD = 12V
FSW = 768 kHz
4.7µH+0.68µF
PVDD = 18V
FSW = 768 kHz
10µH+0.68µF
1SPW Modulation
1SPW Modulation
Load = 6Ω
Load = 6Ω
图6-19. THD+N vs Output Power-BTL
图6-20. THD+N vs Output Power-BTL
10
10
PVCC=24V
TA=25èC
RL=6W
PVCC=12V
TA=25èC
RL=8W
5
5
2
2
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 1kHz
f= 10KHz
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
10
Output Power (W)
D101067
D01017
PVDD = 24V
FSW = 768 kHz
10µH+0.68µF
PVDD = 12V
FSW = 768 kHz
4.7µH+0.68µF
1SPW Modulation
1SPW Modulation
Load = 6Ω
Load = 8Ω
图6-21. THD+N vs Output Power-BTL
图6-22. THD+N vs Output Power-BTL
10
10
PVCC=18V
TA=25èC
RL=8W
PVCC=24V
TA=25èC
RL=8W
5
5
2
2
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 1kHz
f= 10KHz
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D01014087
D010179
PVDD = 18V
FSW = 768 kHz
10µH+0.68µF
PVDD = 24V
FSW = 768 kHz
10µH+0.68µF
1SPW Modulation
1SPW Modulation
Load = 8Ω
Load = 8Ω
图6-23. THD+N vs Output Power-BTL
图6-24. THD+N vs Output Power-BTL
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80
0
-20
Fsw=768kHz, Channel A
Fsw=768kHz, Channel B
PVDD=12V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
60
40
20
0
-40
-60
-80
-100
-120
5
10
15
Supply Voltage (V)
18
20
20
100
1k
Frequency (Hz)
10k 20k
D10032760
D0102318
PVDD = 4.5V~24V 10µH+0.68µF
FSW = 768 kHz 1SPW Modulation
PVDD = 12V
4.7µH+0.68µF
Pout=1W
FSW = 768 kHz
1SPW Modulation
Load = 8Ω
Load = 6Ω
图6-25. Idle Channel Noise vs PVDD-BTL
图6-26. Crosstalk
0
0
PVDD=18V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
PVDD=24V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
-20
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D0102319
D0103310
PVDD = 18V
10µH+0.68µF
Pout=1W
PVDD = 24V
10µH+0.68µF
Pout=1W
FSW = 768 kHz
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
Load = 6Ω
Load = 6Ω
图6-27. Crosstalk
图6-28. Crosstalk
0
0
PVDD=12V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
PVDD=18V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
-20
-40
-20
-40
-60
-60
-80
-80
-100
-100
-120
-120
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D010331
D0103312
PVDD = 12V
4.7µH+0.68µF
Pout=1W
PVDD = 18V
10µH+0.68µF
Pout=1W
FSW = 768 kHz
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
Load = 8Ω
Load = 8Ω
图6-29. Crosstalk
图6-30. Crosstalk
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0
90
80
70
60
50
40
30
20
10
0
PVDD=24V, LC filter=4.7uH+0.68uF
Ch A to Ch B
Ch B to Ch A
-20
-40
TA=25èC
RL=4W
BTL Mode
Fsw=768kHz
1SPW Mode
-60
-80
PVCC = 12V
PVCC = 18 V
PVCC = 24 V
-100
-120
20
100
1k
Frequency (Hz)
10k 20k
0
5
10
15
20
25
30
Output Power (W)
35
40
45
50
D010313
DF01060
PVDD = 24V
10µH+0.68µF
Pout=1W
PVDD =
10µH+0.68µF
1SPW Modulation
FSW = 768 kHz
1SPW Modulation
12V/18V/24V
Load = 8Ω
FSW = 768 kHz
Load = 4Ω
图6-31. Crosstalk
图6-32. Efficiency vs Output Power-BTL
90
80
70
60
50
40
30
20
10
0
100
90
80
TA=25èC
RL=6W
BTL Mode
Fsw=768kHz
1SPW Mode
70
60
50
40
30
20
10
0
TA=25èC
RL=8W
BTL Mode
Fsw=768kHz
1SPW Mode
PVCC = 12V
PVCC = 18 V
PVCC = 24 V
PVCC = 12V
PVCC = 18 V
PVCC = 24 V
0
5
10
15
20
Output Power (W)
25
30
35
40
45
50
0
5
10
15
20
Output Power (W)
25
30
35
40
45
50
DF01061
DF01062
PVDD =
10µH+0.68µF
1SPW Modulation
PVDD =
12V/18V/24V
FSW = 768 kHz 1SPW Modulation
10µH+0.68µF
12V/18V/24V
FSW = 768 kHz
Load = 6Ω
Load = 8Ω
图6-33. Efficiency vs Output Power-BTL
图6-34. Efficiency vs Output Power-BTL
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6.7.2 Bridge Tied Load (BTL) Configuration Curves with BD Mode
Free-air room temperature 25°C (unless otherwise noted.) Measurements were made using TAS5805MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM Modulation mode set to BD mode with
Class D Bandwidth = 175kHz (Listed in Register 0x53) unless otherwise noted.
10
5
10
5
PVcc=5V
TA=25èC
RL=4W
PVcc=7.4V
TA=25èC
RL=4W
P O=0.5W
PO =1W
P O=0.5W
PO =1W
PO=2.5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D60002
D06021
PVDD = 5V
10µH+0.68µF
BD Modulation
PVDD = 7.4V
10µH+0.68µF
BD Modulation
FSW = 768 kHz
FSW = 768 kHz
Load = 4Ω
Load = 4Ω
图6-35. THD+N vs Frequency
图6-36. THD+N vs Frequency
10
5
10
5
PVcc=12V
TA=25èC
RL=4W
PVcc=12V
TA=25èC
RL=6W
P O=1W
PO=2.5W
PO=5W
P O=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D6002
D06023
PVDD = 12V
10µH+0.68µF
BD Modulation
PVDD = 12V
10µH+0.68µF
BD Modulation
FSW = 768 kHz
FSW = 768 kHz
Load = 4Ω
Load = 6Ω
图6-37. THD+N vs Frequency
图6-38. THD+N vs Frequency
10
5
10
5
PVcc=18V
TA=25èC
RL=6W
PVcc=12V
TA=25èC
RL=8W
P O=1W
PO=2.5W
PO=5W
P O=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D60042
D06025
PVDD = 18V
10µH+0.68µF
BD Modulation
PVDD = 12V
10µH+0.68µF
BD Modulation
FSW = 768 kHz
FSW = 768 kHz
Load = 6Ω
Load = 8Ω
图6-39. THD+N vs Frequency
图6-40. THD+N vs Frequency
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10
10
5
PVcc=18V
TA=25èC
RL=8W
PVCC=5V
P O=1W
PO=2.5W
PO=5W
5
TA=25èC
BTL Mode
Load=4W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f = 20Hz
f = 1kHz
f = 10KHz
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
0.01
0.1
1
10
Output Power (W)
D60062
D0607
PVDD = 18V
10µH+0.68µF
BD Modulation
PVDD = 5V
FSW = 768 kHz
10µH+0.68µF
BD Modulation
FSW = 768 kHz
Load = 8Ω
Load = 4Ω
图6-41. THD+N vs Frequency
图6-42. THD+N vs Output Power
10
5
10
PVCC=12V
TA=25èC
BTL Mode
PVCC=12V
TA=25èC
BTL Mode
5
2
1
2
1
Load=4W
Load=6W
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f = 20Hz
f = 1kHz
f = 10kHz
f = 20Hz
f = 1kHz
f = 10KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10
D60087
D06079
PVDD = 12V
FSW = 768 kHz
10µH+0.68µF
BD Modulation
PVDD = 12V
FSW = 768 kHz
10µH+0.68µF
BD Modulation
Load = 4Ω
Load = 6Ω
图6-43. THD+N vs Output Power
图6-44. THD+N vs Output Power
10
10
PVCC=18V
TA=25èC
BTL Mode
PVCC=12V
TA=25èC
BTL Mode
5
5
2
1
2
1
Load=6W
Load=8W
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f = 20Hz
f = 1kHz
f = 10KHz
f = 20Hz
f = 1kHz
f = 10KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10
D601007
D060171
PVDD = 18V
FSW = 768 kHz
10µH+0.68µF
BD Modulation
PVDD = 12V
FSW = 768 kHz
10µH+0.68µF
BD Modulation
Load = 6Ω
Load = 8Ω
图6-45. THD+N vs Output Power
图6-46. THD+N vs Output Power
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10
40
35
30
25
20
15
10
5
PVCC=18V
TA=25èC
BTL Mode
THD+N=1%, R L=4W
THD+N=10%, R L=4W
5
2
1
Load=8W
0.5
0.2
0.1
0.05
0.02
0.01
f = 20Hz
f = 1kHz
f = 10KHz
0.005
BTL Mode
TA=25èC
0.002
0.001
0
0.01
0.1
1
Output Power (W)
10 20
4
6
8
10 12
Supply Voltage (V)
14
16
18 19
D014
D063173
D601027
PVDD = 18V
FSW = 768 kHz
10µH+0.68µF
BD Modulation
NOTE: Dashed lines represent thermally limited region for the
continuous output power.
Load = 8Ω
10µH+0.68µF
图6-47. THD+N vs Output Power
FSW = 768 kHz
BD Modulation
Load = 4Ω
图6-48. Output Power vs Supply Voltage
50
45
THD+N=1%, R L=6W
THD+N=10%, R L=6W
THD+N=1%, R L=8W
THD+N=10%, R L=8W
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
BTL Mode
TA=25èC
BTL Mode
TA=25èC
5
0
0
4
6
8
10
12
Supply Voltage (V)
14
16
18
20
22
24
4
6
8
10
12
Supply Voltage (V)
14
16
18
20
22
24
D014
D063174
D014
D063175
NOTE: Dashed lines represent thermally limited region for the
continuous output power.
NOTE: Dashed lines represent thermally limited region for the
continuous output power.
10µH+0.68µF
10µH+0.68µF
FSW = 768 kHz
BD Modulation
FSW = 768 kHz
BD Modulation
Load = 6Ω
Load = 8Ω
图6-49. Output Power vs Supply Voltage
图6-50. Output Power vs Supply Voltage
60
100
90
80
70
60
50
40
30
20
40
20
BTL Mode
A=25èC
RL=4W
PVCC = 4.5V
PVCC = 7.4 V
PVCC = 12 V
T
10
0
Fsw = 768kHz, BD Mode
18 20
0
5
10
15
Supply Voltage (V)
25
0
10
20 30
Output Power (W)
40
50
D60130706
D062148
10µH+0.68µF
BD Modulation
10µH+0.68µF
BD Modulation
FSW = 768 kHz
FSW = 768 kHz
Load = 6Ω
Load = 4Ω
图6-51. Idle Channel Noise vs Supply Voltage
图6-52. Efficiency vs Output Power
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100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
BTL Mode
TA=25èC
RL=6W
BTL Mode
TA=25èC
RL=8W
PVCC = 7.4V
PVCC = 12 V
PVCC = 18 V
PVCC = 7.4V
PVCC = 12 V
PVCC = 18 V
0
10
20
30
Output Power (W)
40
50
60
0
10
20
Output Power (W)
30
40
D601294
D06240
10µH+0.68µF
BD Modulation
10µH+0.68µF
BD Modulation
FSW = 768 kHz
FSW = 768 kHz
Load = 6Ω
Load = 8Ω
图6-53. Efficiency vs Output Power
图6-54. Efficiency vs Output Power
0
0
PVDD=12V, Load=6W
Ch 1 to Ch 2
Ch 2 to Ch 1
PVDD=18V, Load=6W
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-20
-40
-60
-40
-60
-80
-80
-100
-100
-120
-120
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D060231
D0602312
PVDD=12V
10µH+0.68µF
BD Modulation
PVDD=18V
10µH+0.68µF
BD Modulation
FSW = 768 kHz
FSW = 768 kHz
Load = 6Ω
Load = 6Ω
图6-55. Crosstalk
图6-56. Crosstalk
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6.7.3 Bridge Tied Load (BTL) Configuration Curves with Ferrite Bead + Capacitor as the Output Filter
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5805MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 384 kHz, with Class D
Bandwidth = 80 kHz (Listed in Register 0x53), Spread Spectrum Enable, Ferrite bead + Capacitor as the output
filter, BD Modulation, unless otherwise noted.
10
5
10
5
PVcc=12V
TA=25èC
RL=6W
PVcc=12V
TA=25èC
RL=8W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D103052
D010326
PVDD = 12V
Ferrite Bead +
Capacitor
Spread Spectrum
Enable
PVDD = 12V
Ferrite Bead +
Capacitor
Spread Spectrum
Enable
FSW = 384 kHz
BD Modulation
FSW = 384 kHz
BD Modulation
Load = 6Ω
Load = 8Ω
图6-57. THD+N vs Frequency-BTL
图6-58. THD+N vs Frequency-BTL
20
10
PVCC=7.4V
TA=25èC
RL=4W
THD+N=1%, R L=8W
THD+N=10%, R L=8W
5
2
15
10
5
1
0.5
0.2
0.1
0.05
0.02
0.01
f= 20Hz
f= 1kHz
f= 10KHz
0.005
BTL Mode
TA=25èC
0.002
0.001
0
4.5
6.5
8.5 10.5
Supply Voltage (V)
12.5
14.5
16
0.01
0.1
1
10
Output Power (W)
D014
D0137
D011304087
PVDD = 4.5V~16V Ferrite Bead +
Capacitor
Spread Spectrum
Enable
PVDD = 7.4V
FSW = 384 kHz
Ferrite Bead +
Capacitor
Spread Spectrum
Enable
FSW = 384 kHz
BD Modulation
BD Modulation
Load = 8Ω
Load = 4Ω
图6-59. Output Power vs Supply Voltage-BTL
图6-60. THD+N vs Output Power-BTL
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10
10
5
PVCC=12V
A=25èC
RL=8W
PVCC=12V
TA=25èC
RL=6W
5
T
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 1kHz
f= 10KHz
f= 20Hz
f= 10kHz
f= 1KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10
0.01
0.1
1
Output Power (W)
10
D103097
D010470
PVDD = 12V
FSW = 384 kHz
Ferrite Bead +
Capacitor
Spread Spectrum
Enable
PVDD = 12V
FSW = 384 kHz
Ferrite Bead +
Capacitor
Spread Spectrum
Enable
BD Modulation
BD Modulation
Load = 6Ω
Load = 8Ω
图6-61. THD+N vs Output Power-BTL
图6-62. THD+N vs Output Power-BTL
0
100
90
80
70
60
50
40
30
20
PVDD=12V, Ferrite Bead + Capacitor
Ch A to Ch B
Ch B to Ch A
-20
-40
-60
-80
-100
TA=25èC
RL=4W
PVCC = 5V
PVCC = 7.4V
10
0
-120
20
100
1k
Frequency (Hz)
10k 20k
0
10
Output Power (W)
D010431
D012443
PVDD = 12V,
Pout=1W
Ferrite Bead +
Capacitor
Spread Spectrum
Enable
PVDD = 5V/7.4V
FSW = 384 kHz
Ferrite Bead +
Capacitor
Spread Spectrum
Enable
FSW = 384 kHz
BD Modulation
BD Modulation
Load = 6Ω
Load = 4Ω
图6-63. Crosstalk
图6-64. Efficiency vs Output Power-BTL
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
TA=25èC
RL=8W
TA=25èC
RL=6W
PVCC = 7.4V
PVCC = 12 V
PVCC = 7.4V
PVCC = 12 V
10
10
0
0
0
10
Output Power (W)
20
0
10
20
30
Output Power (W)
D10424
D012445
PVDD = 7.4V/12V Ferrite Bead +
Capacitor
Spread Spectrum
Enable
PVDD = 7.4V/12V Ferrite Bead +
Capacitor
Spread Spectrum
Enable
FSW = 384 kHz
BD Modulation
FSW = 384 kHz
BD Modulation
Load = 8Ω
Load = 6Ω
图6-65. Efficiency vs Output Power-BTL
图6-66. Efficiency vs Output Power-BTL
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6.7.4 Parallel Bridge Tied Load (PBTL) Configuration with 1SPW Modulation
Free-air room temperature 25°C (unless otherwise noted.) Measurements were made using TAS5805MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 576 kHz, the LC filter
used was 4.7 μH / 0.68 μF, 1SPW modulation with Class D Bandwidth = 120kHz (Listed in Register 0x53)
unless otherwise noted.
10
5
10
5
PVcc=7.4V
TA=25èC
RL=4W
PVcc=12V
TA=25èC
RL=4W
P O=1W
PO=2.5W
PO=4W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D104062
D010427
PVDD = 7.4V
4.7uH + 0.68uF
PVDD = 12V
4.7uH + 0.68uF
FSW = 576 kHz
1SPW Modulation
FSW = 576 kHz
1SPW Modulation
Load = 4Ω
Load = 4Ω
图6-67. THD+N vs Frequency-PBTL
图6-68. THD+N vs Frequency-PBTL
10
10
PVcc=24V
TA=25èC
RL=4W
PVCC=5V
TA=25èC
RL=2W
P O=1W
PO=2.5W
PO=5W
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 10kHz
f= 1KHz
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
0.01
0.1
1
10
Output Power (W)
D104082
D010479
PVDD = 24V
4.7uH + 0.68uF
PVDD = 5V
FSW = 576 kHz
4.7uH + 0.68uF
1SPW Modulation
FSW = 576 kHz
1SPW Modulation
Load = 4Ω
Load = 2Ω
图6-69. THD+N vs Frequency-PBTL
图6-70. THD+N vs Output Power-PBTL
10
10
PVCC=5V
TA=25èC
RL=4W
PVCC=12V
TA=25èC
RL=4W
5
5
2
2
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 10kHz
f= 1KHz
f= 20Hz
f= 10kHz
f= 1KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
10
0.01
0.1
1
Output Power (W)
10 20
Output Power (W)
D105007
D010571
PVDD = 5V
FSW = 576 kHz
4.7uH + 0.68uF
1SPW Modulation
PVDD = 12V
FSW = 576 kHz
4.7uH + 0.68uF
1SPW Modulation
Load = 4Ω
Load = 4Ω
图6-71. THD+N vs Output Power-PBTL
图6-72. THD+N vs Output Power-PBTL
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10
10
5
PVCC=18V
TA=25èC
RL=4W
PVCC=24V
TA=25èC
RL=4W
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 10kHz
f= 1KHz
f= 20Hz
f= 10kHz
f= 1KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D105027
D010573
PVDD = 18V
FSW = 576 kHz
4.7uH + 0.68uF
PVDD = 24V
4.7uH + 0.68uF
1SPW Modulation
FSW = 576kHz
1SPW Modulation
Load = 4Ω
Load = 4Ω
图6-73. THD+N vs Output Power-PBTL
图6-74. THD+N vs Output Power-PBTL
70
80
THD+N=1%, R L=4W
THD+N=10%, R L=4W
Fsw=768kHz, PBTL Mode
65
60
55
50
45
40
35
30
25
20
15
10
5
60
40
20
0
PBTL Mode
TA=25èC
0
4.5
6.5
8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24
Supply Voltage (V)
5
10
15
Supply Voltage (V)
18
20
D014
D013574
D01035705
PVDD = 4.5V~24V 4.7uH + 0.68uF
FSW = 576 kHz 1SPW Modulation
PVDD = 4.5V~24V 4.7uH + 0.68uF
FSW = 576 kHz 1SPW Modulation
Load = 4Ω
Load = 4Ω
图6-75. Output Power vs Supply Voltage-PBTL
图6-76. Idle Channel Noise vs Supply Voltage-
PBTL
100
90
80
70
60
50
40
30
PVCC = 5V
PVCC = 7.4 V
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
20
TA=25èC
RL=4W
PBTL Mode
10
0
0
10
20
30 40
Output Power (W)
50
60
D105264
PVDD = 5V/7.4V/12V/18V/24V
FSW = 576 kHz
4.7uH + 0.68uF
1SPW Modulation
Load = 4Ω
图6-77. Efficiency vs Output Power
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6.7.5 Parallel Bridge Tied Load (PBTL) Configuration with BD Modulation
Free-air room temperature 25°C (unless otherwise noted.) Measurements were made using TAS5805MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter
used was 10 μH / 0.68 μF, BD Modulation with Class D Bandwidth = 175kHz (Listed in Register 0x53), unless
otherwise noted.
10
5
10
5
PVcc=7.4V
TA=25èC
RL=4W
PVcc=12V
TA=25èC
RL=4W
P O=1W
PO=2.5W
PO=5W
P O=1W
PO=2.5W
PO=5W
2
1
2
1
PBTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D70012
D0702
PVDD = 7.4V
10µH+0.68µF
BD Modulation
PVDD = 12V
10µH+0.68µF
BD Modulation
FSW = 768 kHz
FSW = 768 kHz
Load = 4Ω
Load = 4Ω
图6-78. THD+N vs Frequency
图6-79. THD+N vs Frequency
10
5
10
5
PVCC=12V
TA=25èC
PBTL Mode
PVCC=18V
TA=25èC
PBTL Mode
2
1
2
1
Load=4W
Load=4W
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f = 20Hz
f = 1kHz
f = 10kHz
f=20Hz
f=1kHz
f=10kHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D70047
D07075
PVDD = 12V
FSW = 768 kHz
10µH+0.68µF
BD Modulation
PVDD = 18V
FSW = 768 kHz
10µH+0.68µF
BD Modulation
Load = 4Ω
Load = 4Ω
图6-80. THD+N vs Output Power
图6-81. THD+N vs Output Power
10
60
PVCC=5V
TA=25èC
PBTL Mode
5
2
1
Load=2W
0.5
40
20
0
0.2
0.1
0.05
0.02
0.01
f=20Hz
f=1kHz
f=10kHz
0.005
0.002
0.001
PBTL Mode
20
0.01
0.1
1
10
5
10
15
Supply Voltage (V)
18
Output Power (W)
D7007
D073007
PVDD = 5V
10µH+0.68µF
BD Modulation
10µH+0.68µF
BD Modulation
FSW = 768 kHz
FSW = 768 kHz
Load = 2Ω
Load = 4Ω
图6-82. THD+N vs Output Power
图6-83. Idle Channel Noise vs Supply Voltage
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100
90
80
70
60
50
40
30
20
10
0
PVCC = 5V
PBTL Mode
TA=25èC
RL=4W
PVCC = 7.4 V
PVCC = 12 V
PVCC = 18 V
0
10
20
Output Power (W)
30
40
D700284
10µH+0.68µF
BD Modulation
FSW = 768 kHz
Load = 4Ω
图6-84. Efficiency vs Output Power
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Parameter Measurement Information
LRCK/FS
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
SCLKL
SCLKH
t
LS
SCLK
(Input)
t
t
SL
SCLK
DATA
(Input)
0.5 × DVDD
0.5 × DVDD
STOP
t
t
DH
SU
t
DFS
DATA
(Output)
图7-1. Serial Audio Port Timing in Slave Mode
Repeated
START
START
t
t
t
t
P-SU
t
D-SU
D-HD
SDA-F
SDA-R
t
BUF.
SDA
t
t
t
SP
SCL-R.
RS-HD
t
LOW.
SCL
t
HI.
t
RS-SU
t
t
SCL-F.
S-HD.
图7-2. I2C Communication Port Timing Diagram
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7 Detailed Description
7.1 Overview
The TAS5805M device integrates 4 main building blocks together into a single cohesive device that maximizes
sound quality, flexibility, and ease of use. The 4 main building blocks are listed as follows:
• A stereo audio DAC.
• An Audio DSP subsystem.
• A flexible closed-loop amplifier capable of operating in stereo or mono, at different switching frequencies, and
supporting a variety of output voltages and loads.
• An I2C control port for communication with the device
The device requires only two power supplies for proper operation. A DVDD supply is required to power the low
voltage digital circuitry. Another supply, called PVDD, is required to provide power to the output stage of the
audio amplifier. Two internal LDOs convert PVDD to 5 V for GVDD and AVDD and to 1.5V for DVDD
respectively.
7.2 Functional Block Diagram
4.5-26.4V
3.3/1.8V
DVDD
VR_DIG
AVDD
PVDD1/2/3/4
LDO 1.5V
LDO 5V
BST_A+
Closed-Loop Feedback
IO
IO
OUT_A+
I2S/TDM
ADR/FAULT
OUT_A-
BST_A-
PDN
H Bridge
&
Gate Driver
&
Audio DSP
Subsystem
SDIN
SCLK
LRCLK
Digital to PWM
Conversion
BST_B-
OC/DC Protect
PDM
OUT_B-
Modulator
SDOUT
SCL
BST_B+
OUT_B+
PLL & OSC
SDA
Closed-Loop Feedback
PGND 1/2
AGND
DGND
7.3 Feature Description
7.3.1 Power Supplies
To facilitate system design, TAS5805M needs only a 3.3-V or 1.8-V supply in addition to the (typical) 12-V or 24-
V power-stage supply. Two internal voltage regulators provide suitable voltage levels for the gate drive circuitry
and internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to
filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and
damage to the device. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive,
is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide good
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electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical,
independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x). The gate drive
voltages (AVDD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling
capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins
and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic
capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the
power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the
gate-drive regulator output pin (AVDD) and the bootstrap pin. When the power-stage output is high, the
bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for
the high-side gate driver.
7.3.2 Device Clocking
The TAS5805M devices have flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface.
DACCLK
LRCLK/FS
DSPCLK
OSRCLK
DSP
(Including
interpolator)
Serial Audio
Interface (Input)
Delta Sigma
Modulator
Audio In
DAC
图7-1. Audio Flow with Respective Clocks
图7-1 shows the basic data flow and clock distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
• SCLK (Bit Clock)
• LRCLK/FS (Left Right Word Clock and Frame Sync)
• SDIN (Input Data)
The device has an internal PLL that is used to take SCLK (Bit Clock) as reference clock and create the higher
rate clocks required by the DSP and the DAC clock.
The TAS5805M device has an audio sampling rate detection circuit that automatically senses the sampling
frequency. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96 kHz are
supported. The sampling frequency detector sets the clock for DAC and DSP automatically.
7.3.3 Serial Audio Port –Clock Rates
The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS, SCLK, and SDIN. SCLK is the
serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio
interface. Serial data is clocked into the TAS5805M device on the rising edge of SCLK. The LRCK/FS pin is the
serial audio left/right word clock or frame sync when the device is operated in TDM Mode.
表7-1. Audio Data Formats, Bit Depths and Clock Rates
MAXIMUM LRCLK/FS FREQUENCY
FORMAT
DATA BITS
SCLK RATE (fS)
(kHz)
32 to 96
32
I2S/LJ/RJ
32, 24, 20, 16
64, 32
128
TDM
32, 24, 20, 16
44.1,48
96
128,256,512
128,256
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Before DSP register initialize with I2C during the startup , TAS5805M requires stable I2S ready. When Clock halt,
non-supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in Register 113 (Register
Address 0x71).
7.3.4 Clock Halt Auto-recovery
As some of host processor will Halt the I2S clock when there is no audio playing. When Clock halt, the device
puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After audio
clocks recovery, the device automatically returns to the previous state.
7.3.5 Sample Rate on the Fly Change
TAS5805M supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32kHz to 48kHz or
96kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 100us before changing to the
new sample rate.
7.3.6 Serial Audio Port - Data Formats and Bit Depths
The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and
TDM/DSP data. Data formats are selected via Register (P0-R51-D[5:4]). If the high width of LRCK/FS in
TDM/DSP mode is less than 8 cycles of SCK, the register (P0-R51-D[3:2]) should be set to 01. All formats
require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats,
word length and clock rate supported by this device are shown in 表 7-1. The data formats are detailed in 图 7-2
through 图 7-6. The word length are selected via Register (P0-R51-D[1:0]). The offsets of data are selected via
Register (P0-R51-D[7]) and Register (P0-R52-D[7:0]). Default setting is I2S and 24 bit word length.
1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
1
1
2
2
2
15 16
MSB
LSB
MSB
MSB
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
23 24
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
31 32
MSB
LSB
LSB
图7-2. Left-Justified Audio Data Format
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1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
1
1
2
2
2
15 16
MSB LSB
MSB LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
23 24
MSB
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
31 32
MSB
MSB
LSB
LSB
I2S Data Format; L-channel = LOW, R-channel = HIGH
I2S Data Format; L-channel = LOW, R-channel = HIGH
图7-3. I2S Audio Data Format
1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
2
15 16
MSB LSB
MSB LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
1
2
23 24
MSB
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
1
2
31 32
MSB
MSB
LSB
LSB
Right-Justified Data Format; L-channel = HIGH, R-channel = LOW
Right-Justified Data Format; L-channel = HIGH, R-channel = LOW
图7-4. Right-Justified Audio Data Format
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1 /fS .
LRCK/FS
SCLK
…
…
…
…
…
…
Audio data word = 16-bit, Offset = 0
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
Data Slot 2
LSB
MSB
LSB
MSB
Audio data word = 24-bit, Offset = 0
,
-
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 0
…
…
1
2
31 32
LSB
1
2
31 32
LSB
DATA
MSB
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
图7-5. TDM 1 Audio Data Format
1 /fS .
OFFSET = 1
LRCK/FS
…
…
…
…
…
SCLK
Audio data word = 16-bit, Offset = 1
…
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
LSB
Data Slot 2
LSB
MSB
MSB
Audio data word = 24-bit, Offset = 1
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
Data Slot 2
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 1
…
…
1
2
31 32
LSB
1
2
31 32
DATA
Data Slot 1
Data Slot 2
LSB
MSB
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
图7-6. TDM 2 Audio Data Format
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7.3.7 Digital Audio Processing
TAS5805M DSP has advanced process flows for different applications, refer to application note, TAS5805
Process Flows for details or request the PPC3 access for TAS5805M app .
7.3.8 Class D Audio Amplifier
Following the digital clipper, the interpolated audio data is next sent to the closed-Loop Class-D amplifier, whose
first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two
pairs of complimentary pulse-width- modulated (PWM) signals which are used to drive the outputs of the speaker
amplifier. Feedback loops around the DPC ensure constant gain across supply voltages, reducing distortion and
improving immunity to the power supply noise. The analog gain is also applied in the Class-D amplifier section of
the device.
7.3.8.1 Speaker Amplifier Gain Select
A combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. As
seen in 图 7-7, the audio path of the TAS5805M consists of a digital audio input port, a digital audio path, a
digital to PWM converter (DPC), a gate driver stage, a Class-D power stage, and a feedback loop which feeds
the output information back into the DPC block to correct for distortion sensed on the output pins. The total
amplifier gain consists of digital gain shown in the digital audio path, and the analog gain from the input of the
analog modulator to the output of the speaker amplifier power stage.
Digital Gain
Analog Gain
Closed-Loop Class D Amplifier
Gate Drives
SPK_OUTA+
SPK_OUTA-
Full Bridge
Power Stage
A
Serial
Audio
Port
Audio processing
DSP
Serial
Audio In
Digital to PWM
Conersion
SPK_OUTB+
SPK_OUTB-
Full Bridge
Power Stage
B
Gate Drives
SCL
SDA
I2C Interface
Control Register
Closed-Loop Class D Amplifier
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图7-7. Speaker Amplifier Gain
As shown in 图 7-7, the first gain stage of the speaker amplifier is present in the digital audio path. Digital gain
consists of the volume control, input Mixer or output Crossbar. The digital gain is set to 0dB by default. Change
analog gain via register 0x54, AGAIN[4:0] which supports 32 steps analog gain setting (0.5dB per step). These
analog gain settings ensure that the output signal is not clipped at different PVDD levels. 0dBFS output
corresponds to 29.5-V peak output voltage.
表7-2. Analog Gain Setting
AGAIN <4:0>
00000
GAIN (dBFS)
AMPLIFIER PEAK OUTPUT VOLTAGE (V)
0
29.5
27.85
…….
4.95
00001
-0.5
…….
……..
-15.5
11111
7.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
TAS5805M closed loop structure provides Loop bandwidth setting option (Setting by register 83 -Register
address 0x53h-D[6-5]) to co-work with different switching frequency (Setting by register 2 -Register address
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0x02h-D[6-4] ). 表7-3 shows recommended settings for the Loop Bandwidth and Switching Frequency selection.
Same Fsw, Better THD+N performance with higher BW.
表7-3. Loop Bandwidth and Switching Frequency Setting
Modulation
Scheme
Fsw
BW (Loop Band Width)
Notes
384kHz
480kHz
576kHz
768kHz
384kHz
480kHz
576kHz
768kHz
80kHz
80kHz, 100kHz
Principle: Fsw (Switching Frequency) ≥4.2 × Loop
Hybrid, 1SPW
Bandwidth
80kHz, 100kHz, 120kHz
80kHz, 100kHz, 120kHz, 175kHz
80kHz, 100kHz, 120kHz
80kHz, 100kHz, 120kHz
80kHz, 100kHz, 120kHz, 175kHz
80kHz, 100kHz, 120kHz, 175kHz
Principle: Fsw (Switching Frequency) ≥3 × Loop
BD
Bandwidth
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7.4 Device Functional Modes
7.4.1 Software Control
The TAS5805M device is configured via an I2 C communication port.
The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements
are described in the I2C Bus Timing –Standard and I2C Bus Timing –Fast sections.
7.4.2 Speaker Amplifier Operating Modes
The TAS5805M device can be used in two different amplifier configurations:
• BTL Mode
• PBTL Mode
7.4.2.1 BTL Mode
In BTL mode, the TAS5805M amplifies two independent signals, which represent the left and right portions of a
stereo signal. The amplified left signal is presented on differential output pair shown as OUT_A+ and OUT_A-,
the amplified right signal is presented on differential output pair shown as OUT_B+ and OUT_B-.
7.4.2.2 PBTL Mode
The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in
parallel with one another to increase the power sourcing capabilities of the device. On the output side of the
TAS5805M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter
Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the inductor
portion of the output filter. Doing so does require two additional inductors, but allows for smaller, less-expensive
inductors to be used because the current is divided between the two inductors. The process is called Post-Filter
PBTL. On the input side of the TAS5805M device, the input signal to the PBTL amplifier is left frame of I2S or
TDM data.
7.4.3 Low EMI Modes
TAS5805M employs several modes to minimize EMI during playing audio, and they can be used based on
different applications.
7.4.3.1 Spread Spectrum
Spread spectrum is used in some inductor free case to minimize EMI noise. The TAS5805M supports Spread
Spectrum with triangle mode.
User needs to configure register SS_CTRL0 (0x6B) to enable Spread Spectrum with triangle mode, and select
spread spectrum frequency and range with SS_CTRL1 (0x6C). For 384kHz FSW which configured by
DEVICE_CTRL1 (0x02), the Spread Spectrum frequency and range are described in 表7-4
表7-4. Triangle Mode Spread Spectrum Frequency and Range Selection
SS_TRI_CT
RL[3:0]
0
1
2
3
4
5
6
7
Triangle
Freq
24k
48k
Spread
Spectrum
Range
5%
10%
20%
25%
5%
10%
20%
25%
User Application example-Central Switching Frequency is 384kHz, Triangle Frequency is 24kHz:
w 58 6b 03 //Enable Spread Spectrum
w 58 6c 03 //SS_TRI_CTRL[3:0]0011, Triangle Frequency = 24kHz, Spread Spectrum Range should be 25%
(336kHz~432kHz)
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7.4.3.2 Channel to Channel Phase Shift
This device supports channel to channel 180-degree PWM phase shift to minimize the EMI.
7.4.3.3 Multi-Devices PWM Phase Synchronization
This device supports up to 4 phases selection for the multi devices application system. For example, when a
system integrated 4 pieces of TAS5805M devices, user can select phase 0/1/2/3 for each device with register
PHASE_CTRL (0x6A), which means there is a 45-degree phase shift between each device to minimize the EMI.
Recommend to do the Phase Synchronization with I2S clock during the Startup Phase:
1. Halt I2S clock.
2. Configure each device phase selection and enable the phase synchronization. For example: Register 0x6A
= 0x03 for device 0; Register 0x6A = 0x07 for device 1; Register 0x6A = 0x0B for device 2; Register 0x6A =
0x0F for device 3. There should be a 45-degree PWM phase shift between each device to minimize the EMI.
3. Configure each device into Hi-Z mode.
4. Provide I2S to each device. Phase synchronization for all 4 devices will be automatically done by internal
sequence.
5. Initialize the DSP code. (This step can be skipped if only need to do the PWM Phase Synchronization).
6. Device to Device PWM phase shift should be fixed with 45 degree.
7.4.4 Thermal Foldback
The Thermal Foldback (TFB), is designed to protect TAS5805M from excessive die temperature increases, in
case the device operates beyond the recommended temperature/power limit, or with a weaker thermal system
design than recommended. It allows the TAS5805M to play as loud as possible without triggering unexpected
thermal shutdown. When the die temperature triggers the over-temperature warning (OTW) level (135C typ), an
internal AGL (Automatic Gain Limiter) will reduce the digital gain automatically. Once the die temperature drops
below the OTW, the device’s digital gain gradually returns to the former setting. Both the attenuation gain and
adjustable rate are programmable. The TFB gain regulation speed (attack rate and release rate) settings are the
same as a regular AGL, which is also configurable with TAS5805M App in PurePathTM Console3.
7.4.5 Device State Control
TAS5805M has 5 states with different power dissipation which listed in the Electrical Characteristics Table.
• Shutdown Mode. With PDN pin pull down to GND. All internal LDOs (1.5V for digital core, 5V for analog) are
disabled, all registers will be cleared to default value.
备注
Exit from Shutdown Mode and re-enter into Play mode, need reload all register configurations
(which generated by PurePath Console3) again.
• Deep Sleep Mode. Register 0x03h -D[1:0]=00, device stays in Deep Sleep Mode. In this mode, I2C block and
1.5V LDO for digital core still working, but internal 5V LDO (For AVDD and MOSFET gate driver) is disabled
for low power dissipation. This mode can be used to extend the battery life in some portable speaker
applications. If the host processor stops playing audio for a long time, TAS5805M can be set to Deep Sleep
Mode to minimize power dissipation until host processor starts playing audio again. Unlike the Shutdown
Mode (Pulling PDN Low), entering or exiting Deep Sleep Mode, the DSP keeps active.
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备注
As in Deep Sleep Mode, the internal 5V LDO (For AVDD and internal MOSFET gate driver) is
disabled. Exit from Deep Sleep Mode (Register 0x03h -D[1:0]=00) and re-enter into Play mode
(Register 0x03h -D[1:0]=11), Below sequence is required for internal Finite-state machine fast
setting (Take TAS5805M I2C device address = 0x58 as example).
w 58 00 00 #Go to page 0
w 58 7f 00 #Change the book to 0x00
w 58 03 02 #Change the device into Hiz Mode
w 58 03 00 #Change the device into Deep Sleep Mode
w 58 00 00 #Go to page 0
w 58 7f 00 #Change the book to 0x00
w 58 03 02 #Change the device into Hiz Mode
w 58 03 03 #Change the device into Play Mode
• Sleep Mode. Register 0x03h -D[1:0]=01, device stays in Sleep Mode. In this mode, I2 C block, Digital core,
DSP Memory , 5V Analog LDO are stilling working. Unlike the Shutdown Mode (Pull PDN Low), enter or exit
Sleep Mode, DSP is kept active. Exit from this mode and re-enter into play mode, only need to set Register
0x03h -D[1:0]=11.
• Output Hiz Mode. Register 0x03h -D[1:0]=10, device stays in Hiz Mode. In this mode, only output driver is set
to be Hi-Z state, all other block operate normally. Exit from this mode and re-enter into play mode, only need
to set Register 0x03h -D[1:0]=11.
• Play Mode. Register 0x03h -D[1:0]=11, device stays in Play Mode.
7.4.6 Device Modulation
TAS5805M has 3 modulation schemes: BD Modulation, 1SPW modulation and Hybrid modulation. Select
modulation schemes for TAS5805M with Register 0x02 [1:0]-DAMP_MOD.
7.4.6.1 BD Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
0V
-
OUTP OUTN
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
图7-8. BD Mode Modulation
7.4.6.2 1SPW Modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In Low Idle Current mode the
outputs operate at ~14% modulation during idle conditions. When an audio signal is applied one output will
decrease and one will increase. The decreasing output signal will quickly rail to GND at which point all the audio
modulation takes place through the rising output. The result is that only one output is switching during a majority
of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
图7-9. 1SPW Mode Modulation
7.4.6.3 Hybrid Modulation
Hybrid Modulation is designed to minimized power loss without compromising the THD+N performance, and is
optimized for battery-powered applications. With Hybrid modulation enabled, device detects the input signal level
and adjust PWM duty cycle dynamically based on PVDD. Hybrid modulation achieves ultra low idle current and
maintains the same audio performance level as the BD Modulation. In order to minimize the power dissipation,
low switching frequency (For example, Fsw = 384 kHz) with proper LC filter (15 µH + 0.68 µF or 22 µH + 0.68
µF) is recommended.
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备注
1) With Hybrid Modulation, users need to input the system's PVDD value via device development App.
2) With Hybrid Modulation, Change device state from Deep Sleep Mode to Play Mode, specific
sequence is required:
1. Set device's PWM Modulation to BD or 1SPW mode via Register (Book0/Page0/Register0x02h,
Bit [1:0]).
2. Set device to Hi-Z state via Register (Book0/Page0/Register0x03h, Bit [1:0]).
3. Delay 2ms.
4. Set device's PWM Modulation to Hybrid mode via Register (Book0/Page0/Register0x02h, Bit
[1:0]).
5. Delay 15ms.
6. Set device to Play state via Register (Book0/Page0/Register0x03h, Bit [1:0]).
7.5 Programming and Control
7.5.1 I2 C Serial Communication Bus
The device has a bidirectional serial control interface that is compatible with the Inter IC ( I2)C bus protocol and
supports 100 and 400-kHz data transfer rates for random and sequential write and read operations as a slave
device. Because the TAS5805M register map and DSP memory spans multiple pages, users should change
from page to page before writing individual registes or DSP memory. Changing from page to page is
accomplished by writing to register 0 on each page. Its register value selects the page address, from 0 to 255.
7.5.2 Slave Address
The TAS5805M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are
factory preset to 01011(0x5x). The next two bits of address byte are the device select bits which can be user-
defined by ADR pin in 表7-5.
表7-5. I2 C Slave Address Configuration
ADR PIN Configuration
4.7k Ω to DVDD
15kΩ to DVDD
MSBs
User Define
LSB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
R/ W
R/ W
R/ W
R/ W
47kΩ to DVDD
120kΩ to DVDD
7.5.2.1 Random Write
As shown in 图7-10, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address and the
read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图7-10. Random Write Transfer
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7.5.2.2 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in 图7-11. After receiving each data byte, the device responds
with an acknowledge bit and the I2 subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
R/W ACK
A4 A3
A0
ACK
ACK
ACK
ACK
D0
A6
A1
A7
A6
A5
A1
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
图7-11. Sequential Write Transfer
7.5.2.3 Random Read
As shown in 图7-12, a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a
read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be
read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the device responds
with an acknowledge bit. In addition, after sending the internal memory address byte, the master device
transmits another start condition followed by the address and the read/write bit again. This time the read/write bit
is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device again responds
with an acknowledge bit. Next, the device transmits the data byte from the memory address being read. After
receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete
the single-byte data-read transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
Subaddress
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Data Byte
图7-12. Random Read Transfer
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7.5.2.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in 图 7-13. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
sub address by one. After receiving the last data byte, the master device transmits a not-acknowledge followed
by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
图7-13. Sequential Read Transfer
7.5.2.5 DSP Memory Book, Page and BQ Coefficients Update
The TAS5805M device supports the I2C serial bus and the data transmission protocol for standard and fast
mode as a slave device.
The DSP memory is arranged in books, pages, and registers. Each book has several pages and each page has
several registers.
Because the TAS5805M register map spans several books and pages, the user must select the correct book and
page before writing individual register bits or bytes.
To change the book, the user must be on page 0x00. In register 0x7f on page 0x00 you can change the book.
On page 0x00 of each book, register 0x7f is used to change the book. Register 0x00 of each page is used to
change the page. To change a book first write 0x00 to register 0x00 to switch to page 0 then write the book
number to register 0x7f on page 0. To change between pages in a book, simply write the page number to
register 0x00.
All the Biquad Filters coefficients are addressed in Book 0xAA. The five coefficients of every Biquad Filter should
be written entirely and sequentially from the lowest address to the highest .
All DSP/Audio Process Flow Related Register are listed in Application Note, TAS5805M Process Flows
7.5.2.6 Example Use
Example 1, The following is a sample script for configuring a device on I2C slave address 0x58 and set the
device switching frequency to 768kHz with Class D loop bandwidth to 175kHz, BD Modulation:
w 58 00 00 #Go to Page0
w 58 7f 00 #Change the Book to 0x00
w 58 00 00 #Go to Page 0x00
w 58 02 00 #Set switching frequency to 768kHz with BD Modulation
w 58 53 60 #Set Class D Loop Bandwidth to 175kHz
Example 2, The following is a sample script for configuring a device on I2C slave address 0x58 and using the
DSP host memory to change the digital volume to the default value of 0dB:
w 58 00 00 #Go to Page 0
w 58 7f 8c #Change the Book to 0x8C
w 58 00 2a #Go to Page 0x2a
w 58 24 00 80 00 00 #change digital volume to 0dB
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7.5.2.7 Checksum
This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an
Exclusive (XOR) checksum. Register reads do not change checksum, but writes to even nonexistent registers
will change the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.
The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00) to their respective 4-byte register
locations.
7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell
delineation, (1 + x1 + x2 + x8)). A major advantage of the CRC checksum is that it is input order sensitive. The
CRC supports all I2C transactions, excluding book and page switching. The CRC checksum is read from register
0x7E on page0 of any book (B_x, Page_0, Reg_126). The CRC checksum can be reset by writing 0x00 to the
same register locations where the CRC checksum is valid.
7.5.2.7.2 Exclusive or (XOR) Checksum
The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with
the previous 8-bit checksum register value. XOR supports only Book 0x8C, and excludes page switching and all
registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book
0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the same register
location where it is read.
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7.5.3 Control via Software
• Startup Procedures
• Shutdown Procedures
7.5.3.1 Startup Procedures
1. Configure ADR/ FAULT pin with proper settings for I2C device address.
2. Bring up power supplies (it does not matter if PVDD or DVDD comes up first).
3. Once power supplies are stable, bring up PDN to High and wait 5ms at least, then start SCLK, LRCLK.
4. Once I2S clocks are stable, set the device into HiZ state and enable DSP via the I2C control port.
5. Wait 5ms at least. Then initialize the DSP Coefficient, then set the device to Play state.
6. The device is now in normal operation.
Initialization
Normal Op
eration
DVDD
PVDD
PDN
0 ns
0 ns
0 ns
5ms
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2C
Set to HiZ state
(Enable DSP)
DSP Coeff
Play
Deep sleep
5 ms for device settle down
图7-14. Start-up Sequence
7.5.3.2 Shutdown Procedures
1. The device is in normal operation.
2. Configure the Register 0x03h -D[1:0]= 10 (Hiz) via the I2C control port or Pull PDN low.
3. Wait at least 6ms (this time depends on the LRCLK rate ,digital volume and digital volume ramp down rate).
4. Bring down power supplies.
5. The device is now fully shut down and powered off.
PDN
6ms
4.5V
PVDD
0ms
DVDD
6ms
I2C
I2C
I2C
I2C
Output Hiz
ñ
ñ
Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I2C.
At least 6ms delay needed based on LRCLK (Fs) = 48kHz,Digital volume ramp down update every sample period,
decreased by 0.5dB for each update, digital volume =24dB. Change the value of register 0x4C and 0x4E or change
the LRCLK rate, the delay changes.
图7-15. Power-Down Sequence
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7.5.3.3 Protection and Monitoring
7.5.3.3.1 Overcurrent Shutdown (OCSD)
Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector,
and the affected channel shuts down in < 100 ns if the peak current are big enough. The shutdown speed
depends on a number of factors, such as the impedance of the short circuit, supply voltage, and switching
frequency. The user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the I2C
fault register saves a record. If the supply or ground short is strong enough to exceed the peak current threshold
but not severe enough to trigger the OSCD, the peak current limiter prevents excess current from damaging the
output FETs, and operation returns to normal after the short is removed.
7.5.3.3.2 Speaker DC Protection
If the device measures a >1.9 V (Typical) DC offset and continue more than 570 ms (typical) on the output stage,
the ADR/ FAULT line will be pulled low and set the OUTxx outputs to Hi-Z state to protect speaker, signifying a
fault in Register 0x70 in Book0/Page0. This fault report bit in Register 0x70 keeps 1 and device keeps in Hi-Z
mode unless clear it by Register 0x78 in Book0/Page0 manually.
7.5.3.3.3 Device Over Temperature Protection
Once the die temperature exceed 160°C (Typical), device will set the output driver from Play mode to Hi-Z Mode.
Over temperature shutdown fault reported by Register 0x72 in Book0/Page0. Set this fault's behavior to Auto-
recovery mode, device will come back to play mode automatically once the die temperature drop down to 150°C
or device needs re-enter into play mode by clearing fault with Register 0x78 in Book0/Page0.
7.5.3.3.4 Device Over Voltage/Under Voltage Protection
7.5.3.3.4.1 Over Voltage Protection
Once the PVDD voltage exceed the OVETHRES(PVDD) (28.1 V Typical), device will set the output driver from Play
mode to Hi-Z mode. Over voltage fault reported by Regoster 0x71 in Book0/Page0. Once PVDD drop below 27.5
V (Typical), device will come back to Play mode. But this bit still keeps 1 unless clear it by Registerr 0x78 in
Book0/Page0 manually.
7.5.3.3.4.2 Under Voltage Protection
Once the PVDD voltage drop below the UVETHRES(PVDD) (4 V Typical), device will set the output driver from Play
mode to Hi-Z mode. Under voltage fault reported by Register 0x71 in Book0/Page0. Once PVDD rise above 4.25
V (Typical), device will come back to Play mode. But this bit still keeps 1 unless clear it by Register 0x78 in
Book0/Page0 manually.
7.5.3.3.5 Clock Fault
Once there has any Clock error occurs (Clock Halt, SCLK/LRCLK Ratio Error, Pll unlock, FS error) , Register
0x37 and Register 0x39 monitor these errors and real-time report with details, device will enter into Hi-Z mode.
Clock Fault reported in Register 0x71 in Book0/Page0. Once the clock error been removed, device will come
back to play mode automatically. But this bit still keeps 1 unless clear it by Register 0x78 in Book0/Page0
manually.
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7.6 Register Maps
7.6.1 CONTROL PORT Registers
表 7-6 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in 表
7-6 should be considered as reserved locations and the register contents should not be modified.
表7-6. CONTROL PORT Registers
Offset
1h
Acronym
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
RESET_CTRL
DEVICE_CTRL_1
DEVICE_CTRL_2
I2C_PAGE_AUTO_INC
SIG_CH_CTRL
CLOCK_DET_CTRL
SDOUT_SEL
Register 1
2h
Register 2
3h
Register 3
Fh
Register 15
Register 40
Register 41
Register 48
Register 49
Register 51
Register 52
Register 53
Register 55
Register 56
Register 57
Register 76
Register 78
Register 79
Register 80
Register 81
Register 83
Register 84
Register 92
Register 93
Register 96
Register 97
Register 102
Register 103
Register 104
Register 105
Register 106
Register 107
Register 108
Register 109
Register 110
Register 111
Register 112
Register 113
Register 114
Register 115
Register 116
28h
29h
30h
31h
33h
34h
35h
37h
38h
39h
4Ch
4Eh
4Fh
50h
51h
53h
54h
5Ch
5Dh
60h
61h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
I2S_CTRL
SAP_CTRL1
SAP_CTRL2
SAP_CTRL3
FS_MON
BCK_MON
CLKDET_STATUS
DIG_VOL_CTRL
DIG_VOL_CTRL2
DIG_VOL_CTRL3
AUTO_MUTE_CTRL
AUTO_MUTE_TIME
ANA_CTRL
AGAIN
BQ_WR_CTRL1
DAC_CTRL
ADR_PIN_CTRL
ADR_PIN_CONFIG
DSP_MISC
DIE_ID
POWER_STATE
AUTOMUTE_STATE
PHASE_CTRL
SS_CTRL0
SS_CTRL1
SS_CTRL2
SS_CTRL3
SS_CTRL4
CHAN_FAULT
GLOBAL_FAULT1
GLOBAL_FAULT2
OT WARNING
PIN_CONTROL1
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表7-6. CONTROL PORT Registers (continued)
Offset
75h
Acronym
Register Name
Register 117
Register 118
Register 120
Section
Go
PIN_CONTROL2
MISC_CONTROL
FAULT_CLEAR
76h
Go
78h
Go
Complex bit access types are encoded to fit into small table cells. 表 7-7 shows the codes that are used for
access types in this section.
表7-7. CONTROL PORT Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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7.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]
RESET_CTRL is shown in 图7-12 and described in 表7-8.
Return to Summary Table.
图7-12. RESET_CTRL Register
7
6
5
4
RST_MOD
W
3
2
RESERVED
R
1
0
RST_REG
W
RESERVED
R/W
表7-8. RESET_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
RST_MOD
R/W
000
This bit is reserved
W
0
WRITE CLEAR BIT
Reset Modules
WRITE CLEAR BIT Reset full digital core This bit resets full digital
signal chain (Include DSP and Control Port Registers). Since the
DSP is also reset, the coeffient RAM content will also be cleared by
the DSP.
0: Normal
1: Reset modules
3-1
0
RESERVED
R
000
0
This bit is reserved
RST_CONTROL_REG
W
WRITE CLEAR BIT
Reset Registers
This bit resets the control port registers back to their initial values.
The RAM content is not cleared.
0: Normal
1: Reset control port registers
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7.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
DEVICE_CTRL_1 is shown in 图7-13 and described in 表7-9.
Return to Summary Table.
图7-13. DEVICE_CTRL_1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
FSW_SEL
R/W
RESERVED
R/W
DAMP_PBTL
R/W
DAMP_MOD
R/W
表7-9. DEVICE_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
FSW_SEL
R/W
0
This bit is reserved
6-4
R/W
000
SELECT FSW
000:768K
001:384K
011:480K
100:576K
010:Reserved
101:Reserved
110:Reserved
111:Reserved
3
2
RESERVED
DAMP_PBTL
R/W
R/W
0
0
This bit is reserved
0: SET DAMP TO BTL MODE
1: SET DAMP TO PBTL MODE
1-0
DAMP_MOD
R/W
00
00:BD MODE
01:1SPW MODE
10:HYBRID MODE
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7.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]
DEVICE_CTRL_2 is shown in 图7-14 and described in 表7-10.
Return to Summary Table.
图7-14. DEVICE_CTRL_2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DIS_DSP
R/W
MUTE
R/W
RESERVED
R/W
CTRL_STATE
R/W
表7-10. DEVICE_CTRL_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
DIS_DSP
R/W
000
This bit is reserved
DSP reset
R/W
1
When the bit is made 0, DSP will start powering up and send out
data. This needs to be made 0 only after all the input clocks are
settled so that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3
MUTE
R/W
0
Mute Both Left /Right Channel
This bit issues soft mute request for the left/right channel. The
volume will be smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2
RESERVED
R/W
R/W
0
This bit is reserved
1-0
CTRL_STATE
00
Device state control register
00: Deep Sleep
01: Sleep
10: Hi-Z,
11: PLAY
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7.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
I2C_PAGE_AUTO_INC is shown in 图7-15 and described in 表7-11.
Return to Summary Table.
图7-15. I2C_PAGE_AUTO_INC Register
7
6
5
4
3
2
1
0
RESERVED
R/W
PAGE_AUTOIN
C_REG
RESERVED
R/W
R/W
表7-11. I2C_PAGE_AUTO_INC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
R/W
0000
This bit is reserved
Page auto increment disable
PAGE_AUTOINC_REG
R/W
0
Disable page auto increment mode. for non -zero books. When end
of page is reached it goes back to 8th address location of next page
when this bit is 0. When this bit is 1 it goes to 0 th location of current
page itself like in older part.
0: Enable Page auto increment
1: Disable Page auto increment
2-0
RESERVED
R/W
000
This bit is reserved
7.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
SIG_CH_CTRL is shown in 图7-16 and described in 表7-12.
Return to Summary Table.
图7-16. SIG_CH_CTRL Register
7
6
5
4
3
2
1
0
BCK_RATIO_CONFIGURE
R/W
FS_MODE
R/W
表7-12. SIG_CH_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
BCK_RATIO_CONFIGUR R/W
E
0000
These bits indicate the configured BCK ratio, the number of BCK
clocks in one audio frame.
0011: 32FS
0101: 64FS
0111: 128FS
1001: 256FS
1011: 512FS
3-0
FS_MODE
R/W
0000
FS Speed Mode These bits select the FS operation mode, which
must be set according to the current audio sampling rate.
0000: Auto detection
0010: 8KHz
0100: 16KHz
0110: 32KHz
1000: 44.1KHz
1001: 48KHz
1010: 88.2KHz
1011: 96KHz
Others Reserved
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7.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
CLOCK_DET_CTRL is shown in 图7-17 and described in 表7-13.
Return to Summary Table.
图7-17. CLOCK_DET_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
DIS_DET_PLL DIS_DET_BCL DIS_DET_FS DIS_DET_BCL DIS_DET_MISS RESERVED
RESERVED
K_RANGE
K
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表7-13. CLOCK_DET_CTRL Register Field Descriptions
Bit
Field
RESERVED
DIS_DET_PLL
Type
Reset
Description
7
R/W
0
This bit is reserved
Ignore PLL overate Detection
6
R/W
0
This bit controls whether to ignore the PLL overrate detection. The
PLL must be slow than 150MHz or an error will be reported. When
ignored, a PLL overrate error will not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5
DIS_DET_BCLK_RANGE R/W
0
Ignore BCK Range Detection
This bit controls whether to ignore the BCK range detection. The
BCK must be stable between 256KHz and 50MHz or an error will be
reported. When ignored, a BCK range error will not cause a clock
error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4
3
DIS_DET_FS
R/W
R/W
0
0
Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When
ignored, FS error will not cause a clock error.But CLKDET_STATUS
will report fs error.
0: Regard FS detection
1: Ignore FS detection
DIS_DET_BCLK
Ignore BCK Detection
This bit controls whether to ignore the BCK detection against LRCK.
The BCK must be stable between 32FS and 512FS inclusive or an
error will be reported. When ignored, a BCK error will not cause a
clock error.
0: Regard BCK detection
1: Ignore BCK detection
2
DIS_DET_MISS
R/W
0
Ignore BCK Missing Detection
This bit controls whether to ignore the BCK missing detection. When
ignored an BCK missing will not cause a clock error.
0: Regard BCK missing detection
1: Ignore BCK missing detection
1
0
RESERVED
RESERVED
R/W
R/W
0
0
This bit is reserved
This bit is reserved
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7.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]
SDOUT_SEL is shown in 图7-18 and described in 表7-14.
Return to Summary Table.
图7-18. SDOUT_SEL Register
7
6
5
4
3
2
1
0
RESERVED
SDOUT_SEL
R/W
表7-14. SDOUT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
SDOUT_SEL
0
This bit is reserved
R
0
SDOUT Select. This bit selects what is being output as SDOUT pin.
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
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7.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in 图7-19 and described in 表7-15.
Return to Summary Table.
图7-19. I2S_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
BCK_INV
R/W
RESERVED
RESERVED
R
RESERVED
R/W
R/W
R
表7-15. I2S_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
BCK_INV
R/W
00
This bit is reserved
BCK Polarity
R/W
0
This bit sets the inverted BCK mode. In inverted BCK mode, the
DAC assumes that the LRCK and DIN edges are aligned to the rising
edge of the BCK. Normally they are assumed to be aligned to the
falling edge of the BCK.
0: Normal BCK mode
1: Inverted BCK mode
4-0
RESERVED
R/W
00000
This bit is reserved
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7.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
SAP_CTRL1 is shown in 图7-20 and described in 表7-16.
Return to Summary Table.
图7-20. SAP_CTRL1 Register
7
6
5
4
3
2
1
0
I2S_SHIFT_MS
B
RESERVED
DATA_FORMAT
R/W
I2S_LRCLK_PULSE
R/W
WORD_LENGTH
R/W
R/W
R/W
表7-16. SAP_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
I2S_SHIFT_MSB
RESERVED
R/W
0
I2S Shift MSB
6
R/W
R/W
0
This bit is reserved
I2S Data Format
5-4
DATA_FORMAT
00
These bits control both input and output audio interface formats for
DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2
1-0
I2S_LRCLK_PULSE
WORD_LENGTH
R/W
R/W
00
10
01: lrclk pulse < 8 SCLK. If the high width of LRCLK/FS in TDM/DSP
mode is less than 8 cycles of SCK, these two bits need set to 01.
I2S Word Length
These bits control both input and output audio interface sample word
lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
7.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
SAP_CTRL2 is shown in 图7-21 and described in 表7-17.
Return to Summary Table.
图7-21. SAP_CTRL2 Register
7
6
5
4
3
2
1
0
I2S_SHIFT
R/W
表7-17. SAP_CTRL2 Register Field Descriptions
Bit
7-0
Field
I2S_SHIFT
Type
Reset
Description
R/W
00000000
I2S Shift LSB
These bits control the offset of audio data in the audio frame for both
input and output. The offset is defined as the number of BCK from
the starting (MSB) of audio frame to the starting of the desired audio
sample.
000000000: offset = 0 BCK (no offset)
000000001: ofsset = 1 BCK
000000010: offset = 2 BCKs
and
111111111: offset = 512 BCKs
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7.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
SAP_CTRL3 is shown in 图7-22 and described in 表7-18.
Return to Summary Table.
图7-22. SAP_CTRL3 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
LEFT_DAC_DPATH
R/W
RESERVED
R/W
RIGHT_DAC_DPATH
R/W
表7-18. SAP_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-4
RESERVED
R/W
00
This bit is reserved
LEFT_DAC_DPATH
R/W
01
Left DAC Data Path. These bits control the left channel audio data
path connection.
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
3-2
1-0
RESERVED
R/W
R/W
00
01
This bit is reserved
RIGHT_DAC_DPATH
Right DAC Data Path. These bits control the right channel audio data
path connection.
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)
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7.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
FS_MON is shown in 图7-23 and described in 表7-19.
Return to Summary Table.
图7-23. FS_MON Register
7
6
5
4
3
2
1
0
RESERVED
R/W
BCLK_RATIO_HIGH
R
FS
R
表7-19. FS_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-4
3-0
RESERVED
BCLK_RATIO_HIGH
FS
R/W
00
This bit is reserved
2 msbs of detected BCK ratio
R
R
00
0000
These bits indicate the currently detected audio sampling rate.
0000: FS Error
0010: 8KHz
0100: 16KHz
0110: 32KHz
1000: Reserved
1001: 48KHz
1011: 96KHz
Others Reserved
7.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]
BCK_MON is shown in 图7-24 and described in 表7-20.
Return to Summary Table.
图7-24. BCK_MON Register
7
6
5
4
3
2
1
0
BCLK_RATIO_LOW
R
表7-20. BCK_MON Register Field Descriptions
Bit
7-0
Field
BCLK_RATIO_LOW
Type
Reset
Description
R
00000000
These bits indicate the currently detected BCK ratio, the number of
BCK clocks in one audio frame.
BCK = 32 FS~512 FS
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7.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
CLKDET_STATUS is shown in 图7-25 and described in 表7-21.
Return to Summary Table.
图7-25. CLKDET_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DET_STATUS
R
表7-21. CLKDET_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
00
This bit is reserved
5
4
3
DET_STATUS
DET_STATUS
DET_STATUS
R
R
R
0
0
0
This bit indicates whether the BCLK is overrate or underrate
This bit indicates whether the PLL is overrate
This bit indicates whether the PLL is locked or not. The PLL will be
reported as unlocked when it is disabled.
2
1
DET_STATUS
DET_STATUS
R
R
0
0
This bit indicates whether the BCK is missing or not.
This bit indicates whether the BCK is valid or not. The BCK ratio
must be stable and in the range of 32-512FS to be valid.
0
DET_STATUS
R
0
In auto detection mode(reg_fsmode=0),this bit indicated whether the
audio sampling rate is valid or not. In non auto detection
mode(reg_fsmode!=0), Fs error indicates that configured fs is
different with detected fs. Even FS Error Detection Ignore is set, this
flag will be also asserted.
7.6.1.15 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]
DIG_VOL_CTL is shown in 图7-26 and described in 表7-22.
Return to Summary Table.
图7-26. DIG_VOL_CTL Register
7
6
5
4
3
2
1
0
PGA
R/W
表7-22. DIG_VOL_CTR Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
PGA
R/W
00110000
Digital Volume
These bits control both left and right channel digital volume. The
digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute
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7.6.1.16 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]
DIG_VOL_CTRL2 is shown in 图7-27 and described in 表7-23.
Return to Summary Table.
图7-27. DIG_VOL_CTRL2 Register
7
6
5
4
3
2
1
0
PGA_RAMP_DOWN_SPEED
R/W
PGA_RAMP_DOWN_STEP
R/W
PGA_RAMP_UP_SPEED
R/W
PGA_RAMP_UP_STEP
R/W
表7-23. DIG_VOL_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PGA_RAMP_DOWN_SPE R/W
ED
00
Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
3-2
1-0
PGA_RAMP_DOWN_STE R/W
P
11
00
11
Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
PGA_RAMP_UP_SPEED R/W
Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
PGA_RAMP_UP_STEP
R/W
Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the
volume is ramping up.
00: Increment by 4 dB for each updat
01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update
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7.6.1.17 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL3 is shown in 图7-28 and described in 表7-24.
Return to Summary Table.
图7-28. DIG_VOL_CTRL3 Register
7
6
5
4
3
2
1
0
FAST_RAMP_DOWN_SPEED
R/W
FAST_RAMP_DOWN_STEP
R/W
RESERVED
R/W
表7-24. DIG_VOL_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
FAST_RAMP_DOWN_SP R/W
EED
00
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down due to clock error or power outage,
which usually needs faster ramp down compared to normal soft
mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
FAST_RAMP_DOWN_ST R/W
EP
11
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down due to clock error or power outage, which
usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0
RESERVED
R/W
0000
This bit is reserved
7.6.1.18 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
AUTO_MUTE_CTRL is shown in 图7-29 and described in 表7-25.
Return to Summary Table.
图7-29. AUTO_MUTE_CTRL Register
7
6
5
4
3
2
1
REG_AUTO_MUTE_CTRL
R/W
0
RESERVED
R/W
表7-25. AUTO_MUTE_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7-3
2
R/W
00000
This bit is reserved
REG_AUTO_MUTE_CTR R/W
L
1
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are
about to be auto muted
1
0
REG_AUTO_MUTE_CTR R/W
L
1
1
0: Disable right channel auto mute
1: Enable right channel auto mute
REG_AUTO_MUTE_CTR R/W
L
0: Disable left channel auto mute
1: Enable left channel auto mute bit2: .
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7.6.1.19 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
AUTO_MUTE_TIME is shown in 图7-30 and described in 表7-26.
Return to Summary Table.
图7-30. AUTO_MUTE_TIME Register
7
6
5
AUTOMUTE_TIME_LEFT
R/W
4
3
2
1
0
RESERVED
R/W
RESERVED
R/W
AUTOMUTE_TIME_RIGHT
R/W
表7-26. AUTO_MUTE_TIME Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-4
AUTOMUTE_TIME_LEFT R/W
000
Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
3
RESERVED
R/W
0
This bit is reserved
2-0
AUTOMUTE_TIME_RIGH R/W
T
000
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
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7.6.1.20 ANA_CTRL Register (Offset = 53h) [reset = 0x00]
ANA_CTRL is shown in 图7-31 and described in 表7-27.
Return to Summary Table.
图7-31. ANA_CTRL Register
7
6
5
4
3
2
1
0
ANA_CTRL
R/W
表7-27. ANA_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
ANA_CTRL
R/W
0
This bit is reserved
6-5
R/W
00
Class-D bandwidth control.
00: 80kHz;
01: 100kHz;
10: 120kHz;
11: 175kHz.
With Fsw=768kHz, 175kHz bandwidth should be selected for high
audio performance.
4-0
RESERVED
R/W
00000
These bits are reserved
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7.6.1.21 AGAIN Register (Offset = 54h) [reset = 0x00]
AGAIN is shown in 图7-32 and described in 表7-28.
Return to Summary Table.
图7-32. AGAIN Register
7
6
5
4
3
2
1
0
RESERVED
R/W
ANA_GAIN
R/W
表7-28. AGAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4-0
RESERVED
ANA_GAIN
R/W
000
This bit is reserved
R/W
00000
Analog Gain Control , with 0.5dB one step
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001: -0.5db
11111: -15.5 dB
7.6.1.22 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
BQ_WR_CTRL1 is shown in 图7-33 and described in 表7-29.
Return to Summary Table.
图7-33. BQ_WR_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
BQ_WR_FIRST
_COEF
R/W
R/W
表7-29. BQ_WR_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
R/W
0000000
This bit is reserved
BQ_WR_FIRST_COEF
R/W
0
Indicate the first coefficient of a BQ is starting to write.
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7.6.1.23 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
DAC_CTRL is shown in 图7-34 and described in 表7-30.
Return to Summary Table.
图7-34. DAC_CTRL Register
7
6
5
4
3
2
1
0
DAC_FREQUE
NCY_SEL
DAC_DITHER_EN
DAC_DITHER
DAC_CTRL_DEM_SEL
R/W
R/W
R/W
R/W
表7-30. DAC_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC_FREQUENCY_SEL R/W
1
DAC Frequency Select
0: 6.144MHz
1: 3.072MHz
6-5
4-2
DAC_DITHER_EN
DAC_DITHER
R/W
R/W
11
DITHER_EN,
00: disable both stage dither
01: enable main stage dither
10: enable second stage dither
11: enbale both stage dither
110
Dither level
100: -2^-7
101: -2^-8
110: -2^-9
111: -2^-10
000: -2^-13
001: -2^-14
010: -2^-15
011: -2^-16
1-0
DAC_CTRL_DEM_SEL
R/W
00
00: Enable DEM
11: Disable DEM
7.6.1.24 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]
ADR_PIN_CTRL is shown in 图7-35 and described in 表7-31.
Return to Summary Table.
图7-35. ADR_PIN_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
ADR_OE
R/W - 0x0
表7-31. ADR_PIN_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
ADR_OE
R/W
0000000
This bit is reserved
R/W
0
ADR Output Enable This bit sets the direction of the ADR pin
0: ADR is input
1: ADR is output
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7.6.1.25 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]
ADR_PIN_CONFIG is shown in 图7-36 and described in 表7-32.
Return to Summary Table.
图7-36. ADR_PIN_CONFIG Register
7
6
5
4
3
2
ADR_PIN_CONFIG
R/W
1
0
RESERVED
表7-32. ADR_PIN_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4-0
RESERVED
R/W
000
These bits are reserved
ADR_PIN_CONFIG
R/W
00000
00000: off (low)
00011: Auto mute flag (asserted when both L and R channels are
auto muted)
00100: Auto mute flag for left channel 0101: Auto mute flag for right
channel
00110: Clock invalid flag (clock error or clock missing)
00111: Reserved
01001: Reserved
01011: ADR as FAULTZ output
7.6.1.26 DSP_MISC Register (Offset = 66h) [reset = 0h]
DSP_MISC is shown in 图7-37 and described in 表7-33.
Return to Summary Table.
图7-37. DSP_MISC Register
7
6
5
4
3
2
1
0
BYPASS_CONTROL
R/W
表7-33. DSP_MISC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
R/W
0000
These bits are reserved
BYPASS CONTROL
R/W
0
1: Left and Right will have use unique coef 0->Right channel will
share left channel coefficient
2
1
0
BYPASS CONTROL
BYPASS CONTROL
BYPASS CONTROL
R/W
R/W
R/W
0
0
0
1: bypass 128 tap FIR
1: bypass DRC (Only bypass DRC in L/R channel)
1: bypass EQ (Only bypass EQs in L/R channel)
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7.6.1.27 DIE_ID Register (Offset = 67h) [reset = 0h]
DIE_ID is shown in 图7-38 and described in 表7-34.
Return to Summary Table.
图7-38. DIE_ID Register
7
6
5
4
3
2
1
0
DIE_ID
R-0h
表7-34. DIE_ID Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIE_ID
R
0h
DIE ID
7.6.1.28 POWER_STATE Register (Offset = 68h) [reset = 0x00]
POWER_STATE is shown in 图7-39 and described in 表7-35.
Return to Summary Table.
图7-39. POWER_STATE Register
7
6
5
4
3
2
1
0
STATE_RPT
R
表7-35. POWER_STATE Register Field Descriptions
Bit
7-0
Field
STATE_RPT
Type
Reset
Description
R
00000000
0: Deep sleep
1: Sleep
2: HIZ
3: Play
Others: reserved
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7.6.1.29 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
AUTOMUTE_STATE is shown in 图7-40 and described in 表7-36.
Return to Summary Table.
图7-40. AUTOMUTE_STATE Register
7
6
5
4
3
2
1
0
RESERVED
R
ZERO_RIGHT_ ZERO_LEFT_M
MON
ON
R
R
表7-36. AUTOMUTE_STATE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
1
RESERVED
R
000000
This bit is reserved
ZERO_RIGHT_MON
R
R
0
0
This bit indicates the auto mute status for right channel.
0: Not auto muted
1: Auto muted
0
ZERO_LEFT_MON
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
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7.6.1.30 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]
PHASE_CTRL is shown in 图7-41 and described in 表7-37.
Return to Summary Table.
图7-41. PHASE_CTR Register
7
6
5
4
3
2
1
0
RESERVED
RAMP_PHASE_SEL
R/W
PHASE_SYNC PHASE_SYNC
_SEL
_EN
R/W
R/W
R/W
表7-37. PHASE_CTR Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-2
RESERVED
R/W
0000
This bit is reserved
RAMP_PHASE_SEL
R/W
00
Select ramp clock phase when multi devices integrated in one
system to reduce EMI and peak supply peak current, it is
recomended set all devices the same RAMP frequency and same
spread spectrum. it must be set before driving device into PLAY
mode if this feature is needed.
00: phase 0
01: phase1
10: phase2
11: phase3
1
0
I2S_SYNC_EN
R/W
R/W
0
0
Use I2S to synchronize output PWM phase
0: Disable
1: Enable
PHASE_SYNC_EN
0: RAMP phase sync disable
1: RAMP phase sync enable
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7.6.1.31 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
SS_CTRL0 is shown in 图7-42 and described in 表7-38.
Return to Summary Table.
图7-42. SS_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
SS_PRE_DIV_ SS_MANUAL_
RESERVED
R/W
SS_RDM_EN
SS_TRI_EN
SEL
MODE
R/W
R/W
R/W
R/W
R/W
R/W
表7-38. SS_CTRL0 Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R/W
0
This bit is reserved
This bit is reserved
6
5
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
SS_PRE_DIV_SEL
SS_MANUAL_MODE
RESERVED
Select pll clock divide 2 as source clock in manual mode
Set ramp ss controller to manual mode
This bit is reserved
4
3-2
1
SS_RDM_EN
Random SS enable
0
SS_TRI_EN
Triangle SS enable
7.6.1.32 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in 图7-43 and described in 表7-39.
Return to Summary Table.
图7-43. SS_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SS_RDM_CTRL
R/W
SS_TRI_CTRL
R/W
表7-39. SS_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-4
3-0
SS_RDM_CTRL
SS_TRI_CTRL
R/W
R/W
000
Random SS range control
0000
Triangle SS frequency and range control
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7.6.1.33 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]
SS_CTRL2 is shown in 图7-44 and described in 表7-40.
Return to Summary Table.
图7-44. SS_CTRL2 Register
7
6
5
4
3
2
1
0
TM_FREQ_CTRL
R/W
表7-40. SS_CTRL2 Register Field Descriptions
Bit
7-0
Field
TM_FREQ_CTRL
Type
Reset
Description
R/W
01010000
Control ramp frequency in manual mode, F=61440000/N
7.6.1.34 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
SS_CTRL3 is shown in 图7-45 and described in 表7-41.
Return to Summary Table.
图7-45. SS_CTRL3 Register
7
6
5
4
3
2
1
0
TM_DSTEP_CTRL
R/W
TM_USTEP_CTRL
R/W
表7-41. SS_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SS_TM_DSTEP_CTRL
R/W
0001
Control triangle mode spread spectrum fall step in ramp ss manual
mode
3-0
SS_TM_USTEP_CTRL
R/W
0001
Control triangle mode spread spectrum rise step in ramp ss manual
mode
7.6.1.35 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
SS_CTRL4 is shown in 图7-46 and described in 表7-42.
Return to Summary Table.
图7-46. SS_CTRL4 Register
7
6
5
4
3
2
SS_TM_PERIOD_BOUNDRY
R/W
1
0
RESERVED
R/W
TM_AMP_CTRL
R/W
表7-42. SS_CTRL4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-5
4-0
TM_AMP_CTRL
R/W
01
Control ramp amp ctrl in ramp ss manual model
SS_TM_PERIOD_BOUND R/W
RY
00100
Control triangle mode spread spectrum boundary in ramp ss manual
mode
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7.6.1.36 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
CHAN_FAULT is shown in 图7-47 and described in 表7-43.
Return to Summary Table.
图7-47. CHAN_FAULT Register
7
6
5
4
3
CH1_DC_1
R
2
CH2_DC_1
R
1
CH1_OC_I
R
0
CH2_OC_I
R
RESERVED
R
表7-43. CHAN_FAULT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
CH1_DC_1
CH2_DC_1
CH1_OC_I
CH2_OC_I
R
0000
This bit is reserved
R
R
R
R
0
0
0
0
Left channel DC fault
Right channel DC fault
Left channel over current fault
Right channel over current fault
2
1
0
7.6.1.37 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
GLOBAL_FAULT1 is shown in 图7-48 and described in 表7-44.
Return to Summary Table.
图7-48. GLOBAL_FAULT1 Register
7
6
5
4
3
2
1
0
OTP_CRC_ER BQ_WR_ERRO
CLK_FAULT_I
R
PVDD_OV_I
PVDD_UV_I
ROR
R
R
R
R
R
表7-44. GLOBAL_FAULT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
OTP_CRC_ERROR
BQ_WR_ERROR
RESERVED
R
0h
Indicate OTP CRC check error.
R
R
R
R
R
0h
0h
0h
0h
0h
The recent BQ is written failed
This bit is reserved
Clock fault
5-3
2
CLK_FAULT_I
PVDD_OV_I
1
PVDD OV fault
0
PVDD_UV_I
PVDD UV fault
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7.6.1.38 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
GLOBAL_FAULT2 is shown in 图7-49 and described in 表7-45.
Return to Summary Table.
图7-49. GLOBAL_FAULT2 Register
7
6
5
4
3
2
1
0
OTSD_I
R
RESERVED
R
RESERVED
R
表7-45. GLOBAL_FAULT2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
OTSD_I
R
0000000
This bit is reserved
R
0
Over temperature shut down fault
7.6.1.39 OT WARNING Register (Offset = 73h) [reset = 0x00]
OT_WARNING is shown in 图7-50 and described in 表7-46.
Return to Summary Table.
图7-50. OT_WARNING Register
7
6
5
4
3
2
OTW
R
1
0
RESERVED
R
RESERVED
RESERVED
R
R
R
R
表7-46. OT_WARNING Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-3
2
RESERVED
RESERVED
OTW
R
00
This bit is reserved
R
R
R
000
0
This bit is reserved
Over temperature warning ,135C
This bit is reserved
1-0
RESERVED
00
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7.6.1.40 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
PIN_CONTROL1 is shown in 图7-51 and described in 表7-47.
Return to Summary Table.
图7-51. PIN_CONTROL1 Register
7
6
5
4
3
2
1
0
MASK_OTSD MASK_DVDD_ MASK_DVDD_ MASK_CLK_FA MASK_PVDD_ MASK_PVDD_
MASK_DC
MASK_OC
UV
OV
ULT
UV
OV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表7-47. PIN_CONTROL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
2
1
0
MASK_OTSD
R/W
0
Mask OTSD fault report
Mask DVDD UV fault report
Mask DVDD OV fault report
Mask clock fault report
Mask PVDD UV fault report
Mask PVDD OV fault report
Mask DC fault report
MASK_DVDD_UV
MASK_DVDD_OV
MASK_CLK_FAULT
MASK_PVDD_UV
MASK_PVDD_OV
MASK_DC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
MASK_OC
Mask OC fault report
7.6.1.41 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
PIN_CONTROL2 is shown in 图7-52 and described in 表7-48.
Return to Summary Table.
图7-52. PIN_CONTROL2 Register
7
6
5
4
3
2
1
0
RESERVED
CLKFLT_LATC OTSD_LATCH_ OTW_LATCH_
MASK_OTW
RESERVED
H_EN
EN
EN
R/W
R/W
R/W
R/W
表7-48. PIN_CONTROL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R/W
11
This bit is reserved
CLKFLT_LATCH_EN
OTSD_LATCH_EN
OTW_LATCH_EN
MASK_OTW
R/W
R/W
R/W
R/W
R/W
1
Enable clock fault latch
Enable OTSD fault latch
Enable OT warning latch
Mask OT warning report
This bit is reserved
4
1
3
1
2
0
1-0
RESERVED
00
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7.6.1.42 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
MISC_CONTROL is shown in 图7-53 and described in 表7-49.
Return to Summary Table.
图7-53. MISC_CONTROL Register
7
6
5
4
3
2
1
0
DET_STATUS_
LATCH
RESERVED
R/W
OTSD_AUTO_
REC_EN
RESERVED
R/W
R/W
R/W
表7-49. MISC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DET_STATUS_LATCH
R/W
0
1:Latch clock detection status
0:Don't latch clock detection status
6-5
4
RESERVED
R/W
R/W
R/W
00
This bit is reserved
OTSD_AUTO_REC_EN
RESERVED
0
OTSD auto recovery enable
This bit is reserved
3-0
0000
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7.6.1.43 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
FAULT_CLEAR is shown in 图7-54 and described in 表7-50.
Return to Summary Table.
图7-54. FAULT_CLEAR Register
7
6
5
4
3
2
1
0
ANALOG_FAUL
T_CLEAR
RESERVED
R/W
W
表7-50. FAULT_CLEAR Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ANALOG_FAULT_CLEAR
W
0
WRITE CLEAR BIT.
Once write this bit to 1, device will clear analog fault
6-0
RESERVED
R/W
0000000
This bit is reserved
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8 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
This section details the information required to configure the device for several popular configurations and
provides guidance on integrating the TAS5805M device into the larger system.
8.1.1 Bootstrap Capacitors
The output stage of the TAS5805M uses a high-side NMOS driver, rather than a PMOS driver. To generate the
gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating
power supply for the switching cycle. Use 0.22-µF capacitors to connect the appropriate output pin (OUT_X) to
the bootstrap pin (BST_X). For example, connect a 0.22-µF capacitor between OUT_A and BST_A for
bootstrapping the A channel. Similarly, connect another 0.22-µF capacitor between the OUT_B and BST_B pins
for the B channel inverting output.
8.1.2 Inductor Selections
It is required that the peak current is smaller than the OCP (Over current protection) value which is 5A, there are
3 cases which cause high peak current flow through inductor.
1. During power up (idle state, no audio input), the duty cycle increases from 0 to θ.
Ipeak _ power _up ö PVDD ì C / L ìsin(1/ LìC ì
q
/ Fsw )
(1)
备注
θ=0.5 (BD Modulation), 0.14 (1SPW Modulation), 0.14 (Hybrid Modulation). This formula just
provide a rough estimation, suggest to measure the start-up current based on your LC filter.
表8-1. Peak current during power up
PVDD
L (uH)
C (uF)
Fsw (kHz)
Ipeak_power_up
6.07A (>5A OCP), not
recommended
24
4.7
0.68
384
24
24
24
12
12
4.7
10
10
4.7
10
0.68
0.68
0.68
0.68
0.68
768
384
768
384
384
3.25A
3A
1.55A
3.32A
1.55A
2. During music playing, some audio burst signal (high frequency) with very hard PVDD clipping will cause
PWM duty cycle increase dramatically. This is the worst case and it rarely happens.
Ipeak _clipping ö PVDDì(1-q)/(F ì L)
sw
(2)
3. Peak current due to Max output power. Ignore the ripple current flow through capacitor here.
Ipeak _ output _ power ö 2ì Max _Output _ Power / Rspea ker_ Load
(3)
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Same PVDD and switching frequency, larger inductance means smaller idle current for lower power dissipation.
It's suggested that inductor's saturation current Isat, is larger than the amplifier's peak current during power-up
and play audio.
ISAT í max(Ipeak_ power_up,I peak_clipping,Ipeak_output_ power
)
(4)
In addition, the effective inductance at the peak current is required to be at least 80% of the inductance value in
表8-2, to meet datasheet specifications.
The minimum inductance is given in 表8-2
表8-2. LC filter recommendation
Recommended Minimum
Inductance (uH) for LC filter design
PVDD (V)
Switching Frequency (kHz)
Modulation Scheme
4.7uH + 0.68uF
≤12
>12
384
BD
10uH + 0.68uF
10uH + 0.68uF
≤12
>12
384
1SPW/Hybrid
15uH + 0.68uF
For higher switching frequency (Fsw), select inductors with minimum inductance to be 384kHz/Fsw×L.
8.1.3 Power Supply Decoupling
To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise
transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. The power supply input must be decoupled with some
good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to
the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the
PVDD pins of the device.
8.1.4 Output EMI Filtering
The TAS5805M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that
are commonly used. In other high-power applications, large toroid inductors are required for maximum power
and film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter
Design (SLOA119) for a detailed description on the proper component selection and design of an L-C filter
based upon the desired load and response.
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8.2 Typical Applications
8.2.1 2.0 (Stereo BTL) System
In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels
are amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated
based upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered
2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
图8-1 shows the 2.0 (Stereo BTL) system application.
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图8-1. 2.0 (Stereo BTL) System Application Schematic with Ferrite Bead as the output filter
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图8-2. 2.0 (Stereo BTL) System Application Schematic with Inductor as the output filter
8.2.1.1 Design Requirements
• Power supplies:
– 3.3-V or 1.8-V supply
– 4.5-V to 24-V supply
• Communication: host processor serving as I2C compliant master
• External memory (Such as EEPROM and FLASH) used for coefficients
The requirement for the supporting components for the TAS5805M device in a Stereo 2.0 (BTL) system is
provide in 表8-3 and 表8-4
表8-3. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Ferrite bead as output
filter)
REFERENCE
VALUE
SIZE
DETAILED DESCRIPTION
DESIGNATOR
C1,C2,C5,C6
C3,C4
22uF
0.1uF
4.7uF
0.1uF
1uF
0805
0402
0603
0603
0603
CAP, CERM, 22 µF, 35 V, +/- 20%, JB, 0805
CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R, 0402
CAP, CERM, 4.7 µF, 10 V, +/- 10%, X5R, 0603
CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0603
CAP, CERM, 1 µF, 16 V, +/- 10%, X5R, 0603
C7
C8
C9,C10
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表8-3. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Ferrite bead as output
filter) (continued)
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
R1
R2
4.70k
10.0k
0402
0404
0603
RES, 4.70 k, 1%, 0.0625 W, 0402
RES, 10.0 k, 1%, 0.063 W, 0402
C11,C12,C13,C14
0.22uF
CAP, CERM, 0.22 µF, 50 V, +/- 10%, X7R, 0603
C15,C16,C17,C18,C19,C
20,C21,C22,C23
2200pF
0603
CAP, CERM, 2200 pF, 100 V,+/- 10%, X7R, 0603
R3,R4,R5,R6
L1,L2,L3,L4
L5
68 ohm
300 ohm
100 ohm
0603
0806
0806
ES, 68, 5%, 0.1 W, 0603
Ferrite Bead, 300 ohm @ 100 MHz, 3.1 A, 0806
Ferrite Bead, 100 ohm @ 100 MHz, 4 A, 0806
With Low EMI technology, TAS5805M keeps enough EMI margin for most of application cases where PVDD <
14V with ferrite bead (Low BOM cost). With Ferrite Bead and capacitor as the output filter, 图 8-1 and 表 8-3
includes a good configuration (Proper value of Ferrite bead, Capacitor, Resistor) to achieve enough EMI margin
for the typical case which PVDD = 12V, Speaker Load = 8Ω/6Ω, each speaker wire with 1m length, Output
Power = 1W/4W/8W for each channel.
• Select Ferrite bead (L1~L5). The trade-off is impedance and rated current. If the rated current meet the
system's requirement, larger impedance means larger EMI margin for the EMI, especially for the frequency
band 5 MHz~50 MHz. The typical ferrite bead recommend for TAS5805M is NFZ2MSM series (Murata) and
UPZ2012E series (Sunlord). 300 ohm at 100 MHz ferrite bead is a typical value which can pass EMI for most
of application cases.
• Select capacitor (C15~C23). The trade-off is capacitor value and idle current. Larger capacitor means larger
idle current, increase the capacitor value from 1nF to 2.2nF makes much help for frequency band 5 MHz~100
MHz.
• Using Ferrite bead as the output filter, recommend designer to use Fsw = 384 kHz with Spread spectrum
enable, BD Modulation, refer to 节7.4.3.1
• With Ferrite bead as the output power. In order to pass EMI (AC Conducted Emission) standard, an AC to DC
adapter with EMI filter in it is needed. For most of applications (TV/Voice Control Speaker/Wireless speaker/
Soundbar) which need a 110 V~220 V power supply usually has a EMI filter in the AC to DC adapter. Some
cases use DC power supply and also need to test the DC Conducted Emission , this applications
(Automotive/Industry) need a simple EMI filter on PVDD for TAS5805M. Refer to application note: AN-2162
Simple Success With Conducted EMI From DC to DC Converters.
表8-4. Supporting Component Requirements for Stereo 2.0 (BTL) system (With Inductor as output filter)
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C1,C6
390 µF
22 µF
10mmx10mm
0603
CAP, AL, 390 µF, 35 V, ±20%, 0.08 ohm, SMD
CAP, CERM, 22 µF, 35 V, ±20%, JB, 0805
CAP, CERM, 0.1 µF, 50 V, ±10%, X7R, 0402
CAP, CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 1 µF, 16 V, ±10%, X5R, 0603
RES, 4.70 k, 1%, 0.0625 W, 0402
C2,C5
C3,C4
0.1 µF
4.7 µF
0.1 µF
1 µF
0402
C7
C8
0603
0603
C9,C10
0603
R1
4.70 k
10.0 k
0.22 µF
0.68 µF
10 µH
0402
R2
0404
RES, 10.0 k, 1%, 0.063 W, 0402
C11,C12,C13,C14
C15,C16,C17,C18
L1,L2,L3,L4
0603
CAP, CERM, 0.22 µF, 50 V, ±10%, X7R, 0603
CAP, CERM, 0.68 µF, 50 V, ±10%, X7R, 0805
Inductor, Shielded, 10 µH, 4.4 A, 0.023 ohm, SMD
0805
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With Inductor as the output filter, designers can achieve ultra low idle current (with Hybrid Modulation or 1SPW
Modulation) and keep large EMI margin. As the switching frequency of TAS5805M can be adjustable from 384
kHz to 768 kHz. Higher switching frequency means smaller Inductor value needed.
• With 768 kHz switching frequency. Designers can select 10uH + 0.68 µF or 4.7 µH +0.68 µF as the output
filter, this will help customer to save the Inductor size with the same rated current during the inductor
selection. With 4.7uH + 0.68uF, make sure PVDD ≤12V to avoid the large ripple current to trigger the OC
threshold (5A).
• With 384 kHZ switching frequency. Designers can select 22 µH + 0.68 µF or 15 µH + 0.68 µF or 10 µH + 0.68
µF as the output filter, this will help customer to save power dissipation for some battery power supply
application. With 10 µH + 0.68 µF, make sure PVDD ≤12 V to avoid the large ripple current to trigger the OC
threshold (5 A).
8.2.1.2 Detailed Design Procedures
The design procedure can be used for Stereo 2.0, Mono, 2.1 system.
8.2.1.2.1 Step 1: Hardware Integration
• Use the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
• Follow the recommended component placement, board layout, and routing given in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the
high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they
are given precedent as design trade-offs are made is recommended.
– For questions and support, go to the E2E forums (E2E.ti.com). If deviating from the recommended layout
is necessary, go to the E2E forum to request a layout review.
8.2.1.2.2 Step 2: Speaker Tuning
Use the TAS5805MEVM evaluation module and the PPC3 app to configure the desired device settings.
8.2.1.2.3 Step 3: Software Integration
• Use the End System Integration feature of the PPC3 app to generate a baseline configuration file.
• Generate additional configuration files based upon operating modes of the end-equipment and integrate
static configuration information into initialization files.
• Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
8.2.1.3 Application Curves
8.2.1.3.1 Audio Performance
10
5
10
5
PVCC=12V
TA=25èC
RL=6W
PVCC=18V
TA=25èC
RL=8W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
f= 20Hz
f= 1kHz
f= 10KHz
f= 20Hz
f= 1kHz
f= 10KHz
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10
0.01
0.1
1
Output Power (W)
10 20
D103097
D01014087
图8-3. THD+N vs Frequency (Ferrite bead as
图8-4. THD+N vs Frequency (Inductor as Output
Output Filter, BD Modulation, BTL Mode)
Filter, Hybrid Modulation, BTL Mode)
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8.2.1.3.2 EN55022 Conducted Emissions Results with Ferrite Bead as output filter
With (Ferrite Bead as the output filter), 220 V to 12 V adapter from a major TV customer, 8-Ω speaker, Spread
Spectrum Enabled, Stereo Output Power = 8W/CH, 1 meter speaker cable for each channel.
图8-5. Conducted Emission with Ferrite Bead
图8-6. Conducted Emission with Ferrite Bead
Filter - Line
Filter - Neutral
8.2.1.3.3 EN55022 Radiated Emissions Results with Ferrite Bead as output filter
With (Ferrite Bead as the output filter), 220 V to 12 V adapter from a major TV customer, 8-Ω speaker, Spread
Spectrum Enabled, Stereo Output Power = 8W/CH, 1 meter speaker cable for each channel.
图8-7. Radiated Emission with Ferrite Bead Filter - 图8-8. Radiated Emission with Ferrite Bead Filter -
Horizontal
Vertical
With Inductor as the output filter, the EMI margin reserve ≥ 15dB Margin for both Conducted Emission and
Radiated Emission. More data are included in the application note -TAS5805M Design Considerations for EMC.
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8.2.2 MONO (PBTL) Systems
In MONO mode, TAS5805M can be used as PBTL mode to drive sub-woofer with more output power.
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图8-9. Mono (PBTL) System Application Schematic
8.2.2.1 Design Requirements
• Power supplies:
– 3.3-V or 1.8-V supply
– 4.5-V to 24-V supply
• Communication: host processor serving as I2C compliant master
• External memory (Such as EEPROM and FLASH) used for coefficients
The requirement for the supporting components for the TAS5805M device in a MONO (PBTL) system is provide
in 表8-5
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表8-5. Supporting Component Requirements for MONO (PBTL) system (With Inductor as output filter)
REFERENCE
VALUE
SIZE
DETAILED DESCRIPTION
DESIGNATOR
C24,C25
C27,C30
C28,C29
C33
390uF
22uF
10mmx10mm
0603
CAP, AL, 390 µF, 35 V, +/- 20%, 0.08 ohm, SMD
CAP, CERM, 22 µF, 35 V, +/- 20%, JB, 0805
CAP, CERM, 0.1 µF, 50 V, +/- 10%, X7R, 0402
CAP, CERM, 4.7 µF, 10 V, +/- 10%, X5R, 0603
CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0603
CAP, CERM, 1 µF, 16 V, +/- 10%, X5R, 0603
RES, 4.70 k, 1%, 0.0625 W, 0402
0.1uF
4.7uF
0.1uF
1uF
0402
0603
C34
0603
C37,C39
R7
0603
4.70k
10.0k
0.22uF
0.68uF
10uH
0402
R8
0404
RES, 10.0 k, 1%, 0.063 W, 0402
C35,C38,C40,C41
C32,C36
L1,L2
0603
CAP, CERM, 0.22 µF, 50 V, +/- 10%, X7R, 0603
CAP, CERM, 0.68 µF, 50 V, +/- 10%, X7R, 0805
Inductor, Shielded, 10 µH, 7A, 0.023 ohm, SMD
0805
8.2.2.2 Detailed Design Procedure
For information about the Detailed Design Procedure, see the 节8.2.1.2 section.
8.2.2.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
10
5
PVCC=18V
TA=25èC
RL=4W
2
1
0.5
0.2
0.1
0.05
0.02
0.01
PVCC = 5V
PVCC = 7.4 V
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
TA=25èC
RL=4W
PBTL Mode
f= 20Hz
f= 10kHz
f= 1KHz
0.005
0.002
0.001
0
10
20
30 40
Output Power (W)
50
60
0.01
0.1
1
Output Power (W)
10 20
D105264
D010572
图8-10. Efficiency vs Output Power (Inductor as
图8-11. THD+N vs Output Power (Inductor as
Output Filter, Hybrid modulation, PBTL mode)
Output Filter, Hybrid Modulation, PBTL mode)
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8.2.3 Advanced 2.1 System (Two TAS5805M Devices)
In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was
done in the high-frequency channels. To accomplish this, two TAS5805M devices are used - one for the high
frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can
be sent from the TAS5805M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept
the same digital input as the stereo, which might come from a central systems processor. 图 8-12 shows the 2.1
(Stereo BTL with Two TAS5805M devices) system application.
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图8-12. 2.1 (2.1 CH with Two TAS5805M Devices) Application Schematic
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Power Supply Recommendations
The TAS5805M device requires two power supplies for proper operation. A high-voltage supply calls PVDD is
required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low-
voltage power supply which is calls DVDD is required to power the various low-power portions of the device. The
allowable voltage range for both PVDD and DVDD supply are listed in the Recommended Operating Conditions
table. Once the device has been initialized, PVDD must keep within the normal operation voltage. Once PVDD
lower than 3.5V, all registers need re-initialize again.
Internal Digital
Digital IO
Circuitry
DVDD
1.8V/3.3VÅ
VR_DIG
1.5V
LDO
External Filtering/Decoupling
DVDD
Gate Drive/Internal
Analog Circuitry
Output Stage
Power Supply
PVDD
4.5V~26.4V
AVDD
5V
LDO
External Filtering/Decoupling
PVDD
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图9-1. Power Supply Function Block Diagram
9.1 DVDD Supply
The DVDD supply that is required from the system is used to power several portions of the device. As shown in
图9-1, it provides power to the DVDD pin. Proper connection, routing and decoupling techniques are highlighted
in the 节 8 section and the 节 9.2 section and must be followed as closely as possible for proper operation and
performance.
Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.
To simplify the power supply requirements for the system, the TAS5805M device includes an integrated low
dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
9.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques
are highlighted in the TAS5805MEVM and must be followed as closely as possible for proper operation and
performance. Due to the high-voltage switching of the output stage, it is particularly important to properly
decouple the output power stages in the manner described in the TAS5805M device 节 8. Lack of proper
decoupling, like that shown in the 节8, results in voltage spikes which can damage the device.
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A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is
provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note
that the linear regulator integrated in the device has only been designed to support the current requirements of
the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this
pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.
AVDD pin is provided for the attachment of decoupling capacitor for the TAS5805M internal circuitry. It is
important to note that the linear regulator integrated in the device has only been designed to support the current
requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional
loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the
device.
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9 Layout
9.1 Layout Guidelines
9.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in the 节 9.2 section. These examples represent
exemplary baseline balance of the engineering trade-offs involved with lying out the device. These designs can
be modified slightly as needed to meet the needs of a given application. In some applications, for instance,
solution size can be compromised to improve thermal performance through the use of additional contiguous
copper neat the device. Conversely, EMI performance can be prioritized over thermal performance by routing on
internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it is
recommended to start from the guidance shown in the 节9.2 section and work with TI field application engineers
or through the E2E community to modify it based upon the application specific goals.
9.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This
applies to DVDD, AVDD, GVDD and PVDD. However, the capacitors on the PVDD net for the TAS5805M device
deserve special attention.
The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as
possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in
the system, but doing so can also negatively affect the reliability of the device. Placement of these components
too far from the TAS5805M device can cause ringing on the output pins that can cause the voltage on the output
pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the
deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD
pins than what is shown in the example layouts in the 节9.2 section.
9.1.3 Optimizing Thermal Performance
Follow the layout example shown in the 图 9-1 to achieve the best balance of solution size, thermal, audio, and
electromagnetic performance. In some cases, deviation from this guidance can be required due to design
constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can
get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device
naturally travels away from the device and into the lower temperature structures around the device.
9.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
• Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5805M device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
• Place the TAS5805M device away from the edge of the PCB when possible to ensure that the heat can travel
away from the device on all four sides.
• Avoid cutting off the flow of heat from the TAS5805M device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
• Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5805M
device.
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• Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
9.1.3.2 Stencil Pattern
The recommended drawings for the TAS5805M device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system.
备注
The customer must verify that deviation from the guidance shown in the package addendum, including
the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability
goals.
9.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5805M device will be soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5805M
device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5805M
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the 节
9.2 section, this interface can benefit from improved thermal performance.
备注
Vias can obstruct heat flow if they are not constructed properly.
More notes on the construction and placement of vias are as follows:
• Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
• The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding
planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing should be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
• Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the 节9.2 section.
• Ensure that vias do not cut off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias that are farthest from the TAS5805M device to open up the current path
to and from the device.
9.1.3.2.2 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the
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thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to
manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste
to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is
called an aperture array, and is shown in the 节 9.2 section. It is important that the total area of the aperture
array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the thermal
pad itself.
9.2 Layout Example
Top Layer 3D view
Top Layer Layout
Bot Layer Layout
图9-1. 2.0 (Stereo BTL with Ferrite Bead as Output Filter) Layout View
Top Layer 3D view
Top Layer Layout
Bot Layer 3D view
Bot Layer Layout
图9-2. 2.0 (Stereo BTL with Inductor as Output Filter) Layout View
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Device Nomenclature
The glossary is general commonly used acronyms and words which are defined in accordance with a broad TI
initiative to comply with industry standards such as JEDEC, IPC, IEEE, and others. The glossary provided in this
section defines words, phrases, and acronyms that are unique to this product and documentation, collateral, or
support tools and software used with this product. For any additional questions regarding definitions and
terminology, please see the e2e Audio Amplfier Forum.
Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one half-
bridge and the other terminal is connected to another half-bridge.
DUT refers to a device under test to differentiate one device from another.
Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing
the output signal to the input signal and attempts to correct for non-linearities in the output.
Dynamic controls are those which are changed during normal use by either the system or the end-user.
GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform
many functions as required by the system.
Host processor (also known as System Processor, Scalar, Host, or System Controller) refers to device
which serves as a central system controller, providing control information to devices connected to it as well as
gathering audio source data from devices upstream from it and distributing it to other devices. This device often
configures the controls of the audio processing devices (like the TAS5805M) in the audio path in order to
optimize the audio output of a loudspeaker based on frequency response, time alignment, target sound pressure
level, safe operating area of the system, and user preference.
Maximum continuous output power refers to the maximum output power that the amplifier can continuously
deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period
of time required that their temperatures reach thermal equilibrium and are no longer increasing
Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to
two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half
bridges placed in parallel
rDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.
Static controls/Static configurations are controls which do not change while the system is in normal use.
Vias are copper-plated through-hole in a PCB.
10.1.2 Development Support
For TAS5805M Evaluation Module, TAS5805MEVM
Request PurePathTM Console Graphical Development Suite for Audio System Design and
Development,PUREPATHCONSOLE
Request TAS5805M PPC3 app access by click 'Request Now' in TAS5805M product folder,TAS5805M
Or contact TI field support team to get the PPC3 platform access and TAS5805M app access.
Application notes: Minimize Idle Current in Portable Audio With TAS5805M Hybrid Mode
Application notes: TAS5805M Process Flows
Class-D LC Filter Design,Class-D LC Filter Design
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10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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93
Product Folder Links: TAS5805M
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5805MPWP
TAS5805MPWPR
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
28
28
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-25 to 85
-25 to 85
5805
5805
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5805MPWPR
HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
TAS5805MPWPR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TAS5805MPWP
TAS5805MPWP
PWP
PWP
HTSSOP
HTSSOP
28
28
50
50
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
PACKAGE OUTLINE
PWP0028M
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
8.45
NOTE 3
14
15
0.30
0.19
28X
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.82 MAX
NOTE 5
14
15
2X 0.825 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
4.05
3.53
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
28
3.10
2.58
4224480/A 08/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0028M
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
26X (0.65)
SYMM
(4.05)
(0.6)
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
(
0.2) TYP
VIA
14
15
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4224480/A 08/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0028M
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28X (0.45)
28
(R0.05) TYP
26X (0.65)
SYMM
(4.05)
BASED ON
0.125 THICK
STENCIL
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.47 X 4.53
3.10 X 4.05 (SHOWN)
2.83 X 3.70
0.125
0.15
0.175
2.62 X 3.42
4224480/A 08/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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