TAS5822M [TI]
TAS5822M 35-W, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier with 96kHz Enhanced Processing;
| 型号： | TAS5822M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TAS5822M 35-W, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier with 96kHz Enhanced Processing |
| 文件： | 总90页 (文件大小：3944K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5822M
SLASEV8 – DECEMBER 2020
TAS5822M 35-W, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier with
96kHz Enhanced Processing
1 Features
2 Applications
•
Flexible audio I/O:
•
•
•
Sounds bars, PC audio
Wireless, Bluetooth speakers
DTV, HDTV, UHD and multi-purpose monitors
– Supports 32, 44.1, 48, 88.2, 96 kHz sample
rates
– I2S, LJ, RJ, TDM
– SDOUT for audio monitoring, sub-channel or
echo cancellation
– PLL integrated, supports 3-Wire digital audio
interface (no MCLK required)
3 Description
The TAS5822M is a High Efficiency digital input
Class-D audio amplifier for driving loudspeakers used
in consumer, commercial, and industrial electronics. .
– Supports stereo bridge-tied or mono parallel
bridge-tied loads (BTL and PBTL)
Efficient class-D operation:
– > 90% power efficiency, 90 mΩ RDSon
Supports multiple output configurations
– 2 × 35 W in 2.0 Mode (8-Ω, 24 V, THD+N=1%)
– 2 × 22 W in 2.0 Mode (6-Ω, 18 V, THD+N=1%)
Excellent audio performance:
The high-performance closed loop architecture and
wide-switching frequency range reduces the solution
size by reducing passive components and minimize
the inductor size in most applications. TAS5822M has
an integrated audio processor with up to 96-kHz
architecture support advanced process flow.
•
•
This device supports high efficiency 1SPW
modulation with adjustable Class D loop bandwidth to
achieve good audio performance.
•
•
– THD+N ≤ 0.06% at 1 W, 1 kHz, PVDD = 24 V
– SNR ≥ 110 dB (A-weighted), ICN ≤ 40 μVRMS
Enhanced audio processing:
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
– Sample rate convertor
TAS5822M
HTSSOP (38) DCP 9.7 mm × 4.4 mm
– 96-kHz processor sampling
– DC blocking, 2 ×14 BQs, THD manager
– DPEQ, Volume Control
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Speaker
Speaker
– Input Mixer, Output Crossbar
– 4th order 2-Band DRC + AGL
– Over temperature fold back
Flexible power supply configurations
– PVDD: 4.5 V to 26.4 V
– DVDD and I/O: 1.8 V or 3.3 V
Excellent Integrated self-protection:
– Over-current error (OCE)
L Channel
R Channel
•
•
– Over-temperature warning (OTW)
– Over-temperature error (OTE)
– Under/over-voltage lock-out (UVLO/OVLO)
Easy system integration
•
– I2C Software Control
1.8V or 3.3V
4.5V-26.5V
– Reduced solution size
•
Less passives required compared with open
loop devices
System
Processor
Digital Audio Source
Copyright © 2019, Texas Instruments Incorporated
•
•
Ultra Low EMI with latest EMI technology
No large inductors required for most
applications
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5822M
SLASEV8 – DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................7
6.6 Timing Requirements ...............................................10
6.7 Typical Characteristics..............................................12
6.8 Parametric Measurement Information.......................21
7 Detailed Description......................................................22
7.1 Overview...................................................................22
7.2 Functional Block Diagram.........................................22
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................28
7.5 Programming and Control.........................................33
7.6 Register Maps...........................................................38
8 Application and Implementation..................................71
8.1 Application Information............................................. 71
8.2 Typical Applications.................................................. 71
9 Power Supply Recommendations................................77
9.1 DVDD Supply............................................................77
9.2 PVDD Supply............................................................78
10 Layout...........................................................................79
10.1 Layout Guidelines................................................... 79
10.2 Layout Example...................................................... 81
11 Device and Documentation Support..........................82
11.1 Support Resources................................................. 82
11.2 Trademarks............................................................. 82
11.3 Electrostatic Discharge Caution..............................82
11.4 Glossary..................................................................82
12 Mechanical, Packaging, and Orderable
Information.................................................................... 82
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
December 2020
*
Initial release.
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Device Comparison Table
ORDERABLE PART
NUMBER
RECOMMENDED PVDD Typical Peak Current
RDS(ON) OPTION
180 mΩ
Package
RANGE
(speaker current)
TAS5805M
TAS5806M
4.5 V to 26.4 V
5A
TSSOP 28
TSSOP 38 (Pin to Pin with
TAS5822M)
4.5 V to 26.4 V
4.5 V to 26.4 V
5A
7A
180 mΩ
TSSOP 38 (Pin to Pin with
TAS5806M)
TAS5822M
90 mΩ
5 Pin Configuration and Functions
BST_A-
OUT_A-
PGND
BST_A+
OUT_A+
PVDD
PVDD
DGND
DVDD
ADR/FAULT
VR_DIG
DGND
LRCLK
SCLK
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
BST_B-
OUT_B-
PGND
BST_B+
OUT_B+
PVDD
PVDD
AGND
AVDD
PDN
2
3
4
5
6
7
8
9
Thermal
Pad
10
11
12
13
14
15
16
17
18
19
SCL
SDA
SDOUT
NC
SDIN
NC
NC
NC
NC
NC
NC
NC
NC
NC
Not to scale
Figure 5-1. DCP Package, 38-Pin TSSOP, Top View
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
DGND
DVDD
VR_DIG
NO.
8,12
9
G
P
P
Digital ground
3.3-V or 1.8-V digital power supply
11
Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
Different I2 C device address can be set by selecting different pull up resistor to DVDD, see Table 4 for details.
This pin can be programed by writing 1 to a register bit after Power up bit. In this mode, the ADR/ FAULT Is
redefined as FAULT,go to Page 0, Book 0, set register 0x61 = 0x0b first, then set register 0x60 = 0x01
ADR/ FAULT
LRCLK
10
13
DIO
DI
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this
corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync
boundary.
SCLK
SDIN
14
15
26
DI
DI
Bit clock for the digital signal that is active on the input data line of the serial data port.
Data line to the serial data port
SDOUT
DO
Serial Audio data output, the source data can select as Pre-DSP or Post DSP
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Table 5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
SDA
NO.
27
28
29
30
31
6
DI/O
DI
DI
P
I2C serial control data interface input/output
SCL
I2C serial control clock input
PDN
Power Down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
Analog ground
AVDD
AGND
G
P
7
P
PVDD
PVDD voltage input
32
33
3
P
P
G
PGND
Ground reference for power device circuitry. Connect this pin to system ground.
Positive pin for differential speaker amplifier output A+
36
5
G
OUT_A+
BST_A+
OUT_A-
BST_A-
O
Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_A+
4
2
1
P
O
P
Negative pin for differential speaker amplifier output A-
Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_A-
Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_B-
BST_B-
OUT_B-
BST_B+
38
37
35
P
O
P
Negative pin for differential speaker amplifier output B
Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_B+
OUT_B+
NC
34
18
19
20
21
17
16
22
25
23
24
O
-
Positive pin for differential speaker amplifier output B+
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
Connect to the system Ground
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
PowerPAD™
G
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =
Power, G = Ground (0 V)
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6 Specifications
6.1 Absolute Maximum Ratings
Free-air room temperature 25°C (unless otherwise noted) (1)
MIN
–0.3
–0.3
MAX
3.9
UNIT
V
DVDD
PVDD
VI(DigIn)
VI(SPK_OUTxx)
TA
Low-voltage digital supply
PVDD supply
30
V
DVDD referenced digital inputs(2)
Voltage at speaker output pins
Ambient operating temperature,
Operating junction temperature
Storage temperature
–0.5 VDVDD + 0.5
V
–0.3
–40
-40
32
85
V
°C
°C
°C
TJ
160
125
Tstg
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) DVDD referenced digital pins include: ADR/FAULT, LRCLK, SCLK, SDIN, SDOUT, SCL, SDA, PDN
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.62
4.5
NOM
MAX
3.63
26.4
UNIT
DVDD
V(POWER)
Power supply inputs
V
PVDD
BTL mode, Speaker Load =4Ω
(+/-20% Variation)
4.5
4.5
4.5
4.5
4.5
4.5
20.8
26
V
V
V
V
V
V
V
BTL mode, Speaker Load =5Ω
(+/-20% Variation)
BTL mode, Speaker Load =6Ω
(+/-20% Variation)
26.4
26.4
21
Recommended PVDD
Range(1)
BTL mode, Speaker Load =8Ω
(+/-20% Variation)
PBTL mode, Speaker Load =2Ω
(+/-20% Variation)
PBTL mode, Speaker Load =3Ω
(+/-20% Variation)
26.4
26.4
PBTL mode, Speaker Load =4Ω
(+/-20% Variation)
4.5
VIH(DigIn)
VIL(DigIn)
Input logic high for DVDD referenced digital inputs
Input logic low for DVDD referenced digital inputs
0.9 × VDVDD
DVDD
V
V
0.1 × VDVDD
Minimum inductor value in LC filter under short-circuit
condition
LOUT
1
µH
(1) The Max Recommended PVDD value is limited by OCETHRES, if the Class D amplifier's output peak current lower than OCETHRES, 4Ω
BTL load and 2Ω PBTL load also supports higher PVDD up to 26.4V
6.4 Thermal Information
TAS5822M
TSSOP (DCP)
38 PINS
THERMAL METRIC(1)
UNIT
JEDEC
STANDARD
4-LAYER PCB
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
28.4
13.5
8.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
8.6
RθJC(bot)
1.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Free-air room temperature 25°C, 1SPW Mode, LC filter=4.7uH+0.68uF, Fsw=768kHz, Class D Bandwidth=175kHz, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital I/O
Input logic high current
level
|IIH|
for DVDD referenced
digital
VIN(DigIn) = VDVDD
10
uA
input pins
Input logic low current level
for DVDD referenced
digital
|IIL|
VIN(DigIn) = 0 V
–10
uA
input pins
Input logic high threshold
for
VIH(Digin)
70%
80%
VDVDD
DVDD referenced digital
inputs
Input logic low threshold
for
DVDD referenced digital
inputs
VIL(Digin)
30%
VDVDD
Output logic high voltage
level
VOH(Digin)
VOL(Digin)
IOH = 4 mA
VDVDD
VDVDD
Output logic low voltage
level
IOH = –4 mA
20%
400
I2C CONTROL PORT
Allowable load capacitance
CL(I2C)
pF
for each I2C Line
fSCL(fast)
fSCL(slow)
Support SCL frequency
Support SCL frequency
No wait states, fast mode
No wait states, slow mode
400
100
kHz
kHz
SERIAL AUDIO PORT
Required LRCLK/FS to
SCLK
tDLY
5
ns
rising edge delay
DSCLK
fS
fSCLK
fSCLK
Allowable SCLK duty cycle
40%
32
60%
96
Supported input sample
rates
kHz
Supported SCLK
frequencies
32
64
fS
SCLK frequency
24.576
MHz
AMPLIFIER OPERATING MODE AND DC PRAMETERS
toff
Turn-off Time
Excluding volume ramp
10
ms
Value represents the "peak voltage"
disregarding
clipping due to lower PVDD
Measured at 0 dB input(1FS)
AV(SPK_AMP)
Programmable Gain
Amplifier gain error
13.75
29.4
dBV
ΔAV(SPK_AMP)
Gain = 29.4dBV
0.5
384
dB
kHz
kHz
kHz
kHz
kHz
480
Switching frequency of the
speaker amplifier
fSPK_AMP
576
768
1024
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C, 1SPW Mode, LC filter=4.7uH+0.68uF, Fsw=768kHz, Class D Bandwidth=175kHz, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Drain-to-source on
resistance
of the individual output
MOSFETs
FET + Metallization. VPVDD=24V, I(OUT)=500mA,
TJ=25℃
RDS(on)
90
mΩ
PROTECTION
Speaker Output Current (Post LC filter),
Speaker
current
Over-Current Error
Threshold
OCETHRES
6
7
A
PVDD under voltage error
threshold
UVETHRES(PVDD)
3.7
27
4
4.2
V
V
PVDD over voltage error
threshold
OVETHRES(PVDD)
28.1
29.2
Class D Amplifier's output DC voltage cross
speaker load to trigger Output DC Fault
protection
Output DC Error protection
threshold
DCETHRES
1.9
V
Class D Amplifier's output remain at or
above DCETHRES
TDCDET
Output DC Detect time
570
160
10
ms
℃
Over temperature error
threshold
OTETHRES
OTEHystersis
OTWTHRES
Over temperature error
hysteresis
℃
Over temperature warning
level
Read by register 0x73 bit3
135
°C
OL
SL
Open Load Detection
Short Load Detection
Open Load Detection for ChA or ChB or both
Short Load Detection for ChA or ChB or both
40
70
2
Ω
Ω
AUDIO PERFORMACNE (STEREO BTL)
Measured differentially with zero input data,
programmable gain configured with 29.4dBV
|VOS
|
Amplifier offset voltage
–6.5
6.5
mV
analog gain, VPVDD
=
18 V, 1SPW Modulation
VPVDD = 13.5 V, RSPK = 6 Ω, f = 1 KHz, THD
+N =10%
15
13
27
23
35
W
W
W
W
W
VPVDD = 13.5 V, RSPK = 6 Ω, f = 1 KHz, THD
+N =1%
Output Power (Per
Channel)
VPVDD = 18 V, RSPK = 6 Ω, f = 1 KHz, THD
+N =10%
PO(SPK)
VPVDD = 18 V, RSPK = 6 Ω, f = 1 KHz, THD
+N =1%
VPVDD = 24 V, RSPK = 8 Ω, f = 1 KHz, THD+N
=1%
Total harmonic distortion
and
noise
VPVDD = 13.5 V
VPVDD = 18 V
0.03
0.02
%
%
THD+NSPK
(PO = 1 W, f = 1 KHz, RSPK
VPVDD = 24 V
0.02
%
=
6 Ω)
Idle channel
noise(Aweighted,
AES17)
VPVDD = 13.5 V, LC-filter, Load=6 Ω
VPVDD = 18 V, LC-filter ,Load=6 Ω
35
35
µVrms
µVrms
ICN(SPK)
A-Weighted, -60 dBFS method. VPVDD = 24
DR
Dynamic range
V,
111
dB
Analog Gain = 29.4dBV
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C, 1SPW Mode, LC filter=4.7uH+0.68uF, Fsw=768kHz, Class D Bandwidth=175kHz, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A-Weighted, referenced to 1% THD+N
Output
111
dB
Level, VPVDD=24V
SNR
Signal-to-noise ratio
A-Weighted, referenced to 1% THD+N
Output
106
72
dB
dB
dB
Level, VPVDD=13.5V
Injected Noise = 1 KHz, 1 Vrms, VPVDD
13.5 V,
input audio signal = digital zero
=
Power supply rejection
ratio
PSRR
Cross-talk (worst case
between left-to-right and
right-to-left coupling)
f = 1 KHz, based on Inductor
(DFEG7030D-4R7)
from Murata
X-talkSPK
100
AUDIO PERFORMANCE (MONO PBTL)
Measured differentially with zero input data,
programmable gain configured with 29.4dBV
Analog gain, VPVDD = 18 V, 1SPW
Modulation
|VOS
|
Amplifier offset voltage
Output Power
–6.5
6.5
mV
VPVDD = 24 V, RSPK = 4 Ω, f = 1KHz, THD+N
=1%
65
45
W
W
VPVDD = 18 V, RSPK = 3 Ω, f = 1KHz, THD+N
=1%
PO(SPK)
VPVDD = 18 V, RSPK = 3 Ω, f = 1KHz, THD+N
=10%
55
W
%
Total harmonic distortion
VPVDD = 18 V, LC-filter, RSPK = 3 Ω
0.05
and
noise
(PO = 1 W, f = 1 KHz)
THD+NSPK
DR
VPVDD = 24 V, LC-filter, RSPK = 4 Ω
0.02
111
%
A-Weighted, -60 dBFS method, VPVDD=24V,
RSPK= 3 Ω.
Dynamic range
dB
A-Weighted, referenced to 1% THD+N
Output
Level, VPVDD=18V, RSPK = 3 Ω
108
106
72
dB
dB
dB
SNR
Signal-to-noise ratio
A-Weighted,referenced to 1% THD+N
Output
Level, VPVDD=13.5V, RSPK = 2 Ω
Injected Noise = 1 KHz, 1 Vrms,VPVDD = 18
V,
Power supply rejection
ratio
PSRR
input audio signal = digital zero
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UNIT
SLASEV8 – DECEMBER 2020
6.6 Timing Requirements
MIN
NOM
MAX
Serial Audio Port Timing - Slave Mode
fSCLK
tSCLK
tSCLKL
tSCLKH
tSL
SCLK frequency
1.024
40
16
16
8
MHz
ns
SCLK period
SCLK pulse width, low
ns
SCLK pulse width, high
ns
SCLK rising to LRCLK/FS edge
LRCK/FS Edge to SCLK rising edge
Data setup time, before SCLK rising edge
Data hold time, after SCLK rising edge
Data delay time from SCLK falling edge
ns
tLS
8
ns
tSU
8
ns
tDH
8
ns
tDFS
15
ns
I2C Bus Timing – Standard
fSCL
SCL clock frequency
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
4.7
tLOW
tHI
4.7
High period of the SCL clock
Setup time for (repeated) START condition
Hold time for (repeated) START condition
Data setup time
4
tRS-SU
tS-HD
tD-SU
tD-HD
tSCL-R
4.7
4
250
Data hold time
0
3450
1000
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
tSCL-R1
20 + 0.1CB
1000
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
CB
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
4
1000
1000
1000
ns
ns
ns
µs
pf
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Capacitive load for each bus line
400
400
I2C Bus Timing – Fast
fSCL
SCL clock frequency
kHz
µs
µs
ns
ns
ns
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for (repeated)START condition
Hold time for (repeated)START condition
Data setup time
1.3
tLOW
tHI
1.3
600
tRS-SU
tRS-HD
tD-SU
tD-HD
tSCL-R
600
600
100
Data hold time
0
900
300
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
tSCL-R1
20 + 0.1CB
300
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
tSP
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
600
300
300
300
ns
ns
ns
ns
ns
pf
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Pulse width of spike suppressed
Capacitive load for each bus line
50
CB
400
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LRCK/FS
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
SCLKL
SCLKH
t
LS
SCLK
(Input)
t
t
SL
SCLK
DATA
(Input)
0.5 × DVDD
t
t
DH
SU
t
DFS
DATA
(Output)
0.5 × DVDD
Figure 6-1. Serial Audio Port Timing in Slave Mode
Repeated
START
START
STOP
t
t
t
t
P-SU
t
D-SU
D-HD
SDA-F
SDA-R
t
BUF.
SDA
t
t
t
SP
SCL-R.
RS-HD
t
LOW.
SCL
t
HI.
t
RS-SU
t
t
SCL-F.
S-HD.
Figure 6-2. I2C Communication Port Timing Diagram
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6.7 Typical Characteristics
6.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5822MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, 1SPW
Mode, the LC filter used was 10μH / 0.68 μF, Class D bandwidth = 175 kHz, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
TA=25èC
TA=25èC
RL=4W
BTL Mode
Fsw=768kHz
RL=6W
BTL Mode
Fsw=768kHz
PVDD = 18V
PVDD = 24 V
PVDD = 18V
PVDD = 24 V
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Output Power (W)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Output Power (W)
D900106
D091061
FSW = 768 kHz
Load=4Ω
1SPW Mode
FSW = 768 kHz
Load=6Ω
1SPW Mode
Figure 6-3. Efficiency vs Output Power-BTL
Figure 6-4. Efficiency vs Output Power-BTL
100
90
80
70
60
50
40
100
Fsw=768kHz
1SPW Modulation
BTL Mode
80
60
40
20
0
30
TA=25èC
20
RL=8W
BTL Mode
Fsw=768kHz
Load=4W
Load=6W
Load=8W
PVDD = 18V
PVDD = 24 V
10
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Output Power (W)
5
10
15
Supply Voltage (V)
18
20
D900126
D0930704
FSW = 768 kHz
Load=8Ω
1SPW Mode
FSW = 768 kHz
1SPW Mode
Figure 6-5. Efficiency vs Output Power-BTL
Figure 6-6. Idle Channel Noise vs Supply Voltage
60
Fsw=768kHz
55
60
THD+N=1%, Load=6W
THD+N=1%, Load=8W
THD+N=10%, Load=6W
THD+N=10%, Load=8W
55
TA=25èC
50
50
RL=4W
1SPW Mode
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
THD+N=1%, 2CH run
THD+N=1%, 1CH run
THD+N=10%, 2CH run
THD+N=10%, 1CH run
Fsw=768kHz
TA=25èC
1SPW Mode
10
5
0
0
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
D014
D093075
D014
D093076
Continuous Output Power, 2CH run, High PVDD, RDSon
increase due to die temperature increase.
6Ω and 8Ω efficiency is higher than 4Ω, better thermal
performance, 2CH and 1CH data almost same.
FSW = 768 kHz
1SPW Mode
Load=4Ω
FSW = 768 kHz
1SPW Mode
Load=6Ω or 8Ω
Figure 6-7. Output Power vs Supply Voltage
Figure 6-8. Output Power vs Supply Voltage
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10
5
10
5
PVCC=18V
TA=25èC
RL=4W
PVCC=22V
TA=25èC
RL=4W
2
1
2
1
BTL Mode
BTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D09017
D901067
FSW = 768 kHz
Load=4Ω
PVDD = 18V
FSW = 768 kHz
Load=4Ω
PVDD = 22V
Figure 6-9. THD+N vs Output Power-BTL
Figure 6-10. THD+N vs Output Power-BTL
10
10
PVCC=24V
TA=25èC
RL=4W
BTL Mode
PVCC=18V
TA=25èC
RL=6W
BTL Mode
5
5
2
2
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D901087
D090179
FSW = 768 kHz
Load=4Ω
PVDD = 24V
FSW = 768 kHz
Load=6Ω
PVDD = 18V
Figure 6-11. THD+N vs Output Power-BTL
Figure 6-12. THD+N vs Output Power-BTL
10
10
PVCC=22V
TA=25èC
RL=6W
BTL Mode
PVCC=24V
TA=25èC
RL=6W
BTL Mode
5
5
2
2
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D902007
D090271
FSW = 768 kHz
Load=6Ω
PVDD = 22V
FSW = 768 kHz
Load=6Ω
PVDD = 24V
Figure 6-13. THD+N vs Output Power-BTL
Figure 6-14. THD+N vs Output Power-BTL
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10
10
5
PVCC=18V
TA=25èC
RL=8W
BTL Mode
PVCC=22V
TA=25èC
RL=8W
5
2
2
1
BTL Mode
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D902027
D090273
FSW = 768 kHz
Load=8Ω
PVDD = 18V
FSW = 768 kHz
Load=8Ω
PVDD = 22V
Figure 6-15. THD+N vs Output Power-BTL
Figure 6-16. THD+N vs Output Power-BTL
10
10
PVCC=24V
TA=25èC
RL=8W
BTL Mode
PVDD=18V
TA=25èC
RL=4W
PO=1W
PO=2.5W
PO=5W
5
5
2
2
1
BTL Mode
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
20
100
1k
Frequency (Hz)
10k 20k
D902047
D09027
FSW = 768 kHz
Load=8Ω
PVDD = 24V
FSW = 768 kHz
Load=4Ω
PVDD = 18V
Figure 6-17. THD+N vs Output Power-BTL
Figure 6-18. THD+N vs Frequency-BTL
10
10
PVDD=22V
TA=25èC
RL=4W
PVDD=24V
TA=25èC
RL=4W
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
5
5
2
1
2
1
BTL Mode
BTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D90082
D09029
FSW = 768 kHz
Load=4Ω
PVDD = 22V
FSW = 768 kHz
Load=4Ω
PVDD = 24V
Figure 6-19. THD+N vs Frequency-BTL
Figure 6-20. THD+N vs Frequency-BTL
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10
5
10
5
PVDD=18V
TA=25èC
RL=6W
PVDD=22V
TA=25èC
RL=6W
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
2
1
2
1
BTL Mode
BTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D090121
D901002
FSW = 768 kHz
Load=6Ω
PVDD = 18V
FSW = 768 kHz
Load=6Ω
PVDD = 22V
Figure 6-21. THD+N vs Frequency-BTL
Figure 6-22. THD+N vs Frequency-BTL
10
10
PVDD=24V
TA=25èC
RL=6W
PVDD=18V
TA=25èC
RL=8W
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
5
5
2
1
2
1
BTL Mode
BTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D90102
D090123
FSW = 768 kHz
Load=6Ω
PVDD = 24V
FSW = 768 kHz
Load=8Ω
PVDD = 18V
Figure 6-23. THD+N vs Frequency-BTL
Figure 6-24. THD+N vs Frequency-BTL
10
10
PVDD=22V
TA=25èC
RL=8W
PVDD=24V
TA=25èC
RL=8W
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
5
5
2
1
2
1
BTL Mode
BTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D901042
D090125
FSW = 768 kHz
Load=8Ω
PVDD = 22V
FSW = 768 kHz
Load=8Ω
PVDD = 24V
Figure 6-25. THD+N vs Frequency-BTL
Figure 6-26. THD+N vs Frequency-BTL
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0
0
-20
PVDD=18V, Load=6W, Pout=1W
Ch 1 to Ch 2
Ch 2 to Ch 1
PVDD=18V, Load=8W, Pout=1W
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D002315
D002316
Load = 6Ω
1SPW Mode
Load = 8Ω
1SPW Mode
FSW = 768 kHz
PVDD = 18V
FSW = 768 kHz
PVDD = 18V
Figure 6-27. Crosstalk vs Frequency-BTL
Figure 6-28. Crosstalk vs Frequency-BTL
0
0
PVDD=22V, Load=6W, Pout=1W
Ch 1 to Ch 2
Ch 2 to Ch 1
PVDD=24V, Load=4W, Pout=1W
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-20
-40
-60
-40
-60
-80
-80
-100
-100
-120
-120
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D002317
D002318
Load = 6Ω
1SPW Mode
Load = 4Ω
1SPW Mode
FSW = 768 kHz
PVDD = 22V
FSW = 768 kHz
PVDD = 24V
Figure 6-29. Crosstalk vs Frequency-BTL
Figure 6-30. Crosstalk vs Frequency-BTL
0
0
PVDD=24V, Load=6W, Pout=1W
Ch 1 to Ch 2
Ch 2 to Ch 1
PVDD=24V, Load=8W, Pout=1W
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-20
-40
-60
-40
-60
-80
-80
-100
-100
-120
-120
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D002319
D003310
Load = 6Ω
1SPW Mode
Load = 8Ω
1SPW Mode
FSW = 768 kHz
PVDD = 24V
FSW = 768 kHz
PVDD = 24V
Figure 6-31. Crosstalk vs Frequency-BTL
Figure 6-32. Crosstalk vs Frequency-BTL
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6.7.2 Parallel Bridge Tied Load (PBTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
Free-air room temperature 25°C (unless otherwise noted).Measurements were made using TAS5822MEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, 1SPW
Mode, the LC filter used was 10 μH / 0.68 μF, Class D bandwidth = 175 kHz, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
TA=25èC
TA=25èC
RL=4W
PBTL Mode
Fsw=768kHz
RL=3W
PBTL Mode
Fsw=768kHz
PVDD = 18V
PVDD = 22 V
PVCC = 24 V
PVDD = 18V
PVDD = 22 V
PVCC = 24 V
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Output Power (W)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Output Power (W)
D300106
D091265
FSW = 768 kHz
Load = 4Ω
PVDD =
18V/22V/24V
FSW = 768 kHz
Load = 3Ω
PVDD =
18V/22V/24V
Figure 6-33. Efficiency vs Output Power
Figure 6-34. Efficiency vs Output Power
100
90
80
70
60
50
40
30
100
Fsw=768kHz
1SPW Modulation
PBTL Mode
80
60
40
20
0
TA=25èC
20
RL=2W
PBTL Mode
Fsw=768kHz
PVDD = 18V
PVDD = 22 V
PVCC = 24 V
Load=4W
Load=3W
Load=2W
10
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Output Power (W)
5
10
15
Supply Voltage (V)
18
20
D90216
D0903207
FSW = 768 kHz
Load = 2Ω
PVDD =
18V/22V/24V
FSW = 768 kHz Load = 2Ω/3Ω/4Ω 1SPW Mode
Figure 6-36. idle Channel Noise vs PVDD
Figure 6-35. Efficiency vs Output Power
100
10
PVCC=18V
TA=25èC
RL=4W
PBTL Mode
THD+N= 1%, 4W
THD+N=10%, 4W
THD+N= 1%, 3W
THD+N=10%, 3W
5
90
2
80
1
THD+N= 1%, 2W
THD+N=10%, 2W
70
60
50
40
30
20
10
0
0.5
0.2
0.1
0.05
0.02
0.01
Fsw=768kHz
TA=25èC
1SPW Mode
0.005
f= 1kHz
f= 10kHz
0.002
0.001
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
0.01
0.1
1
Output Power (W)
10 20
D014
D093278
D090279
FSW = 768 kHz Load = 2Ω/3Ω/4Ω 1SPW Mode
FSW = 768 kHz
Load = 4Ω
PVDD = 18V
Figure 6-37. Output Power vs PVDD
Figure 6-38. THD+N vs Output Power
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10
10
5
PVCC=22V
TA=25èC
RL=4W
PBTL Mode
PVDD=24V
TA=25èC
RL=4W
5
2
2
1
PBTL Mode
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
100
D090371
D903007
FSW = 768 kHz
Load = 4Ω
PVDD=22V
FSW = 768 kHz
Load = 4Ω
PVDD = 24V
Figure 6-39. THD+N vs Output Power
Figure 6-40. THD+N vs Output Power
10
10
PVDD=18V
TA=25èC
RL=3W
PBTL Mode
PVCC=22V
TA=25èC
RL=3W
PBTL Mode
5
5
2
2
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
100
D903027
D090373
FSW = 768 kHz
Load = 3Ω
PVDD = 18V
FSW = 768 kHz
Load = 3Ω
PVDD = 22V
Figure 6-41. THD+N vs Output Power
Figure 6-42. THD+N vs Output Power
10
10
PVCC=24V
TA=25èC
RL=3W
PBTL Mode
PVCC=18V
TA=25èC
RL=2W
PBTL Mode
5
5
2
2
1
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
100
0.01
0.1
1
Output Power (W)
10 20
100
D903047
D090375
FSW = 768 kHz
Load = 3Ω
PVDD = 24V
FSW = 768 kHz
Load = 2Ω
PVDD = 18V
Figure 6-43. THD+N vs Output Power
Figure 6-44. THD+N vs Output Power
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10
5
10
5
PVCC=22V
TA=25èC
RL=2W
PVDD=18V
TA=25èC
RL=4W
PO=1W
PO=2.5W
PO=5W
2
1
2
1
PBTL Mode
PBTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
f= 1kHz
f= 10kHz
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
100
20
100
1k
Frequency (Hz)
10k 20k
D090328
D903067
FSW = 768 kHz
Load = 2Ω
PVDD = 22V
FSW = 768 kHz
Load = 4Ω
PVDD = 18V
Figure 6-45. THD+N vs Output Power
Figure 6-46. THD+N vs Frequency
10
10
PVDD=22V
TA=25èC
RL=4W
PVDD=24V
TA=25èC
RL=4W
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
5
5
2
1
2
1
PBTL Mode
PBTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D903092
D090420
FSW = 768 kHz
Load = 4Ω
PVDD = 22V
FSW = 768 kHz
Load = 4Ω
PVDD = 24V
Figure 6-47. THD+N vs Frequency
Figure 6-48. THD+N vs Frequency
10
10
PVDD=18V
TA=25èC
RL=3W
PVDD=22V
TA=25èC
RL=3W
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
5
5
2
1
2
1
PBTL Mode
PBTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D904012
D09042
FSW = 768 kHz
Load = 3Ω
PVDD = 18V
FSW = 768 kHz
Load = 3Ω
PVDD = 22V
Figure 6-49. THD+N vs Frequency
Figure 6-50. THD+N vs Frequency
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10
10
5
PVDD=24V
TA=25èC
RL=3W
PBTL Mode
PVDD=18V
TA=25èC
RL=2W
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
5
2
2
1
PBTL Mode
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D904032
D090424
FSW = 768 kHz
Load = 3Ω
PVDD = 24V
FSW = 768 kHz
Load = 2Ω
PVDD = 18V
Figure 6-51. THD+N vs Frequency
Figure 6-52. THD+N vs Frequency
10
PVDD=22V
TA=25èC
RL=2W
PO=1W
PO=2.5W
PO=5W
5
2
1
PBTL Mode
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
D904052
FSW = 768 kHz
Load = 2Ω
PVDD = 22V
Figure 6-53. THD+N vs Frequency
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6.8 Parametric Measurement Information
6.8.1 Power Consumption Summary
Free-air room temperature 25°C (unless others noted), LC filter = 10 µH + 0.68 µF, Enable DSP (96 kHz Process
Flow), 1SPW Modulation, DVDD = 3.3 V, ADR/FAULT pin pull up resistor = 4.7 kΩ, PDN pin pull up resistor = 10
kΩ.
VPVDD (V)
FSW(kHz)
State of Operation
Play (Idle)
Hi-Z
IPVDD (mA)
33.16
10.15
7.01
IDVDD (mA)
18.04
17.84
0.76
PDISS(W)
0.656
0.242
0.129
0.005
0.001
0.575
0.242
0.129
0.005
0.001
0.595
0.242
0.129
0.005
0.001
1.044
0.306
0.174
0.006
0.001
0.894
0.306
0.174
0.006
0.001
0.891
0.306
0.174
0.006
0.001
384
Sleep
Deep Sleep
Shutdown
Play (Idle)
Hi-Z
0.12
0.75
0.009
28.66
10.15
7.01
0.33
18.04
17.85
0.76
18
768
Sleep
Deep Sleep
Shutdown
Play (Idle)
Hi-Z
0.12
0.75
0.009
29.75
10.15
7.01
0.33
18.06
17.86
0.76
1024
Sleep
Deep Sleep
Shutdown
Play (Idle)
Hi-Z
0.12
0.75
0.009
41.01
10.29
7.14
0.33
18.1
17.88
0.76
384
Sleep
Deep Sleep
Shutdown
Play (Idle)
Hi-Z
0.13
0.76
0.012
34.76
10.29
7.14
0.33
18.1
17.87
0.76
24
768
Sleep
Deep Sleep
Shutdown
Play (Idle)
Hi-Z
0.13
0.76
0.011
34.64
10.29
7.15
0.33
18.1
17.86
0.76
1024
Sleep
Deep Sleep
Shutdown
0.13
0.75
0.012
0.33
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7 Detailed Description
7.1 Overview
The TAS5822M device integrates 4 main building blocks together into a single cohesive device that maximizes
sound quality, flexibility, and ease of use. The 4 main building blocks are listed as follows:
•
•
•
A stereo Digital to PWM Coversion block.
An Audio DSP subsystem.
A flexible close-loop amplifier capable of operating in stereo or mono, at several different switching
frequencies, and with a variety of output voltages and loads.
An I2C control port for communication with the device
•
The device requires only two power supplies for proper operation. A DVDD supply is required to power the low
voltage digital circuitry. Another supply, called PVDD, is required to provide power to the output stage of the
audio amplifier. One internal LDO converts PVDD to 5 V for GVDD and AVDD, another internal LDO converts
DVDD to 1.5V VR_DIG for digital core.
7.2 Functional Block Diagram
LDO Bandgap Generator
(Enable with PVDD>3.5V)
PVDD
5V Regulator
(Internal Gate Drive and
Analog Power Supply )
1.5V Regulator
(For Digital Core)
Internal Voltage Supplies
I -> V
Analog Gain Setting
Closed Loop Class D Amplifier
…DSP
Full Bridge
Power
Stage A
+
Gate
Drives
OUT_A+
OUT_A-
DAC
œ
Analog
to
PWM
Output
Current
ROM Fixed
Process Flow
Monitoring
(OC protection)
SCLK
LRCLK
SDIN
OUT_B+
OUT_B-
Full Bridge
Power
Stage B
Serial
Audio
Port
Modulator
+
Gate
Drives
DAC
œ
Die Temperature Monitoring
and UV/OV/OT Protection
Clock Monitoring
and Error Protection
Error Reporting
SDOUT
Internal Control Registers and State Machines
ADR/FAULT
SCL
SDA
PDN
SDOUT
7.3 Feature Description
7.3.1 Power Supplies
To facilitate system design, TAS5822M needs only a 3.3-V or 1.8-V supply in addition to the (typical) 12 V or 24
V power-stage supply. Two internal voltage regulators provide suitable voltage levels for the gate drive circuitry
and internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to
filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and
damage to the device. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive,
is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide good
electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical,
independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x). The gate drive
voltages (AVDD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling
capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins
and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic
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capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the
power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the
gate-drive regulator output pin (AVDD) and the bootstrap pin. When the power-stage output is high, the
bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for
the high-side gate driver.
7.3.2 Device Clocking
The TAS5822M devices have flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface.
LRCLK/FS
DSPCLK
OSRCLK
DACCLK
DSP
(Including
interpolator)
Serial Audio
Interface (Input)
Delta Sigma
Modulator
DAC
Audio In
Figure 7-1. Audio Flow with Respective Clocks
Figure 7-1 shows the basic data flow and clock Distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
•
•
•
SCLK (Bit Clock)
LRCLK/FS (Left Right Word Clock and Frame Sync)
SDIN (Input Data)
The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP
and the DAC clock.
The device has an audio sampling rate detection circuit that automatically senses which frequency the sampling
rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96 kHz are
supported. The sampling frequency detector sets the clock for DAC and DSP automatically.
7.3.3 Serial Audio Port – Clock Rates
The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK and SDIN. SCLK is the
serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio
interface. Serial data is clocked into the TAS5822M device on the rising edge of SCLK. The LRCK/FS pin is the
serial audio left/right word clock or frame sync when the device is operated in TDM Mode.
Table 7-1. Audio Data Formats, Bit Depths and Clock Rates
MAXIMUM LRCLK/FS FREQUENCY
FORMAT
DATA BITS
SCLK RATE (fS)
(kHz)
32 to 96
32
I2S/LJ/RJ
32, 24, 20, 16
64, 32
128
TDM
32, 24, 20, 16
44.1,48
96
128,256,512
128,256
Before DSP register initialize with I 2C during the startup , requires stable I 2S ready. When Clock halt, non-
supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in Register 113 (Register
Address 0x71).
7.3.4 Clock Halt Auto-recovery
As some of host processor will Halt the I2S clock when there is no audio playing. When Clock halt, the device
puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After audio
clocks recovery, the device automatically returns to the previous state.
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7.3.5 Sample Rate on the Fly Change
TAS5822M supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32kHz to 48kHz or
96kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 10ms before changing to the
new sample rate.
7.3.6 Serial Audio Port - Data Formats and Bit Depths
The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and
TDM/DSP data. Data formats are selected via Register (Register Address 0x33-D[5:4]). If the high width of
LRCLK(FS) in TDM/DSP mode is less than 8 cycles of SCLK(BCLK), the register (Register Address 0x33-D[3:2])
should set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is
accepted. All the data formats, word length and clock rate supported by this device are shown in Table 1. The
data formats are detailed in Figure 1 through Figure 6. The word length are selected via Register (Register
Address 0x33-D[1:0]).Default setting is I2S and 24 bit word length.
For TDM Mode, the offsets of data are selected via Register (Register Address 0x33-D[7-6]) and Register
(Register Address 0x34-D[7:0]).
Table 7-2. TDM Slots vs FS
LRCLK(FS)
48kHz
TDM Slots
Notes
16
8
Each Slots's position (offset) can be set by Register 51 (Register address 0x33)
and Register 52 (Register address 0x34).
96kHz
1 tS .
Right-channel
Left-channel
LRCK/FS
…
…
…
…
…
…
…
SCLK
Audio data word = 16-bit, SCLK = 32, 48, 64fS
…
1
2
15 16
1
1
1
2
15 16
DATA
LSB
LSB
MSB
MSB
Audio data word = 24-bit, SCLK = 48, 64fS
…
…
2
1
2
24
2
23 24
DATA
LSB
LSB
MSB
MSB
Audio data word = 32-bit, SCLK = 64fS
…
…
1
2
31 32
2
31 32
DATA
MSB
LSB
MSB
LSB
Figure 7-2. Left Justified Audio Data Format
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1 tS .
LRCK/FS
Left-channel
Right-channel
…
…
…
…
…
…
SCLK
Audio data word = 16-bit, SCLK = 32, 48, 64fS
…
…
1
2
15 16
1
2
15 16
DATA
LSB
LSB
MSB
MSB
Audio data word = 24-bit, SCLK = 48, 64fS
…
…
2
1
2
23 24
1
23 24
DATA
LSB
MSB
LSB
MSB
Audio data word = 32-bit, SCLK = 64fS
…
…
1
2
31 32
1
2
31 32
DATA
MSB
I2S Data Format; L-channel = LOW, R-channel = HIGH
LSB
MSB
LSB
Figure 7-3. I2S Audio Data Format
1 /fS .
Right-channel
Left-channel
LRCK/FS
SCLK
…
…
…
…
…
…
Audio data word = 16-bit, SCLK = 32, 48, 64fS
DATA
…
…
1
2
15 16
LSB
1
2
15 16
LSB
MSB
MSB
Audio data word = 24-bit, SCLK = 48, 64fS
…
…
2
1
2
24
1
2
23 24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, SCLK = 64fS
…
…
1
2
31 32
LSB
1
2
31 32
DATA
MSB
MSB
LSB
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 7-4. Right Justified Audio Data Format
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1 /fS .
LRCK/FS
SCLK
…
…
…
…
…
…
Audio data word = 16-bit, Offset = 0
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
Data Slot 2
LSB
MSB
LSB
MSB
Audio data word = 24-bit, Offset = 0
,
-
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 0
…
…
1
2
31 32
LSB
1
2
31 32
LSB
DATA
MSB
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 7-5. TDM 1 Audio Data Format
1 /fS .
OFFSET = 1
LRCK/FS
…
…
…
…
…
SCLK
Audio data word = 16-bit, Offset = 1
…
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
LSB
Data Slot 2
LSB
MSB
MSB
Audio data word = 24-bit, Offset = 1
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
Data Slot 2
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 1
…
…
1
2
31 32
LSB
1
2
31 32
DATA
Data Slot 1
Data Slot 2
LSB
MSB
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCLK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 7-6. TDM 2 Audio Data Format
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7.3.7 Digital Audio Processing
TAS5822M DSP has a ROM fixed process flow which support 96kHz DSP sample rate. Request PPC3 tuning
software for details.
AMP
Left
2 BQs
Low-band DRC
Interpolation
AMP
Right
14 .v[•
(Individual
Left/Right)
Volume
(Click & pop
free)
DC
Blocking
Input
mixer
DPEQ
Audio in
SRC
Cross bar
1 BQ
AGL
Clipper
1 BQ
(4th order)
Support
32k/48k/96K-‰96k
2 BQs
High-band DRC
I2S out
Left/Right
MUX
Level
Meter
Figure 7-7. Audio Process Flow
7.3.8 Class D Audio Amplifier
Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose
first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two
pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker
amplifier. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and
increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D
amplifier section of the device.
7.3.8.1 Speaker Amplifier Gain Select
A combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. As
seen in Figure 7-8, the audio path of the device consists of a digital audio input port, a digital audio path, a
stereo DAC, an analog to PWM modulator, a gate driver stage, a Class D power stage, and a feedback loop
which feeds the output information back into the analog to PWM Modulator to correct for distortion sensed on the
output pins. The total amplifier gain is comprised of digital gain, shown in the digital audio path and the analog
gain from the input of the analog modulator to the output of the speaker amplifier power stage.
DSP Volume
DAC Volume
Analog Gain
Book 0x78, Page 0x2A
Register 0x24/0x28/0x30
Book 0x00, Page 0x00
Register 0x4C
Book 0x00, Page 0x00
Register 0x54
I -> V
Analog Gain Setting
Closed Loop Class D Amplifier
…DSP
Full Bridge
Power
Stage A
+
Gate
Drives
OUT_A+
OUT_A-
DAC
œ
Analog
Output
Current
Monitoring
(OC protection)
SCLK
LRCLK
SDIN
Serial
Audio
Port
ROM Fixed
Process Flow
to
PWM
Modulator
OUT_B+
OUT_B-
Full Bridge
Power
Stage B
+
Gate
Drives
DAC
œ
Figure 7-8. Speaker Amplifier Gain
As shown in Figure 7-8, the first gain stage for the speaker amplifier is present in the digital audio path. It
consists of the DSP volume control and the DAC volume control. The volume control is set to 0dB by default. For
all settings of the Register 0x54, AGAIN[4:0], the digital boost block remains at 0 dB. These gain settings ensure
that the output signal is not clipping at different PVDD levels. 0dBFS output is 29.5-V peak output voltage
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Table 7-3. Analog Gain Setting
AMPLIFIER OUTPUT PEAK
AMPLIFIER OUTPUT PEAK
AGAIN[4:0]
GAIN (dBFS)
VOLTAGE (VP/FS)
29.5VP/FS (Default Setting)
27.85VP/FS
VOLTAGE (dBV/FS)
29.4dBV
28.9dBV
28.4dBV
27.9dBV
....
00000 (Default Setting)
0 (Default Setting)
00001
00010
00011
…….
-0.5
-1.0
26.29VP/FS
-1.5
24.82VP/FS
……..
-15.5
…….
11111
4.95VP/FS
13.9dBV
Table 7-4. Example of Analog Gain Setting
(Based on 6Ω speaker Load, take 0.5Ω loss for PCB, Speaker wire, Inductor DCR and RDSon)
DAC
Input
(µDSP
Output)
dBFS
Full Band AGL
Threshold
dBFS
Book0/Page0,
Register 0x54,
AGAIN[4:0]
Amplifier Output Peak
Amplifier Output
Peak Voltage
dBV
PVDD
V
Gain (dBFS)
Voltage
V
24
18
00101
01010
01111
-2.5
-5
22.5V (Without Clipping)
16.6V (Without Clipping)
12.46V (Without Clipping)
27dBV
24.35dBV
21.9dBV
0
0
13.5
-7.5
22.5V (Clipping or not,
depends on AGL time
constant tuning)
-2.5
-5
-2.5
-5
24
18
27dBV
24.35dBV
21.9dBV
16.6V (Clipping or not,
depends on AGL time
constant tuning)
00000
0
12.46V (Clipping or not,
depends on AGL time
constant tuning)
-7.5
-7.5
13.5
7.4 Device Functional Modes
7.4.1 Software Control
The TAS5822M device is configured via an I2C communication port.
The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements
are described in the I2C Bus Timing – Standard and I2C Bus Timing – Fast sections.
7.4.2 Speaker Amplifier Operating Modes
The TAS5822M device can be used in two different amplifier configurations:
•
•
BTL Mode
PBTL Mode
7.4.2.1 BTL Mode
The familiar BTL mode of operation uses the TAS5822M device to amplify two independent signals, which
represent the left and right portions of a stereo signal. The amplified left signal is presented on differential output
pair shown as OUT_A+ and OUT_A-, the amplified right signal is presented on differential output pair shown as
OUT_B+ and OUT_B-.
7.4.2.2 PBTL Mode
The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in
parallel with one another to increase the power sourcing capabilities of the device. On the output side of the
TAS5822M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter
Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the inductor
portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive
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inductors to be used because the current is divided between the two inductors. The process is called Post-Filter
PBTL. On the input side of the TAS5822M device, the input signal to the PBTL amplifier is left frame of I2S or
TDM data.
7.4.3 Minimize EMI with Spread Spectrum
This device supports spread spectrum with triangle mode, Spread spectrum is used to minimize the EMI noise.
User need configure register SS_CTRL0 (0x6B) to Enable triangle mode and enable spread spectrum, and
select spread spectrum frequency and range with SS_CTRL1 (0x6C). For 384kHz FSW which configured by
DEVICE_CTRL1 (0x02), the spread spectrum frequency and range are described in Table 3.
Table 7-5. Spread Spectrum Setting
SS_TRI_CTR
0
1
2
3
4
5
6
7
L[3:0]
Triangle Freq
24k
48k
Spread
Spectrum
Range
5%
10%
20%
25%
5%
10%
20%
25%
User Application example-Central Switching Frequency is 384kHz, Triangle Frequency is 24kHz:
w 58 6b 03 //Enable Spread Spectrum
w 58 6c 03 //SS_TRI_CTRL[3:0]0011, Triangle Frequency = 24kHz, Spread Spectrum Range should be 25%
(336kHz~432kHz)
7.4.4 Minimize EMI with channel to channel phase shift
This device support channel to channel 180 degree PWM phase shift to minimize the EMI. Bit 0 of Register 0x53
can be used to disable or enable the phase shift.
7.4.5 Minimize EMI with Multi-Devices PWM Phase Synchronization
This device support up to 4 phases selection for the multi devices application system. For example, when a
system integrated 4 TAS5822M devices, user can select phase 0/1/2/3 for each device by register
PHASE_CTRL (0x6A), which means there is a 45 degree phase shift between each device to minimize the EMI.
Recommend to do the Phase Synchronization with I2S clock during the Startup Phase.
1. Halt I2S clock.
2. Halt I2S clock.
3. Configure each device phase selection and enable the phase synchronization. For example: Register 0x6A =
0x03 for device 0; Register 0x6A = 0x07 for device 1; Register 0x6A = 0x0B for device 2; Register 0x6A =
0x0F for device 3. There should be a 45 degree PWM phase shift between each device to minimize the EMI.
4. Configure each device into Hi-Z mode.
5. Provide I2S to each device. Phase synchronization for all 4 devices will be automatically done by internal
sequence.
6. Initialize the DSP code. (This step can be skipped if only need to do the PWM Phase Synchronization).
7. Device to Device PWM phase shift should be fixed with 45 degree.
7.4.6 Thermal Foldback
The Thermal Foldback (TFB) or Over temperature foldback, is designed to protect TAS5822M from excessive
die temperature increases, in case the device operates beyond the recommended temperature/power limit, or
with a weaker thermal system design than recommended. It allows the TAS5822M to play as loud as possible
without triggering unexpected thermal shutdown. When the die temperature triggers the over-temperature
warning (OTW) level (135C typ), an internal AGL (Automatic Gain Limiter) will reduce the digital gain
automatically. Once the die temperature drops below the OTW, the device’s digital gain gradually returns to the
former setting. Both the attenuation gain and adjustable rate are programmable. The TFB gain regulation speed
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(attack rate and release rate) settings are the same as a regular AGL, which is also configurable with TAS5822M
tuning software.
7.4.7 Device State Control
TAS5822M has 5 states with different power dissipation which listed in the Electrical Characteristics Table.
•
Shutdown Mode. With PDN pin pull down to GND. All internal LDOs (1.5V for digital core, 5V for analog) are
disabled, all registers will be cleared to default value.
Note
Exit from Shutdown Mode and re-enter into Play mode, need follow up the start-up sequence and
reload all register configurations (which generated by TAS5822M tuning software) again.
•
•
Deep Sleep Mode. Deep Sleep Mode. Register 0x03h -D[1:0]=00, device stays in Deep Sleep Mode. In this
mode, I2C block and 1.5V LDO for digital core still working, but internal 5V LDO (For AVDD and MOSFET
gate driver) is disabled for low power dissipation. This mode can be used to extend the battery life in some
portable speaker applications. If the host processor stops playing audio for a long time, can be set to Deep
Sleep Mode to minimize power dissipation until host processor starts playing audio again. Unlike the
Shutdown Mode (Pulling PDN Low), entering or exiting Deep Sleep Mode, the DSP keeps active.
Sleep Mode. Register 0x03h -D[1:0]=01, device stays in Sleep Mode. In this mode, I2C block, Digital core,
DSP Memory , 5V Analog LDO are stilling working. Unlike the Shutdown Mode (Pull PDN Low), enter or exit
Sleep Mode, DSP is kept active. Exit from this mode and re-enter into play mode, only need to set Register
0x03h -D[1:0]=11.
•
•
Output Hiz Mode. Register 0x03h -D[1:0]=10, device stays in Hiz Mode. In this mode, only output driver is set
to be Hi-Z state, all other block operate normally. Exit from this mode and re-enter into play mode, only need
to set Register 0x03h -D[1:0]=11.
Play Mode. Register 0x03h -D[1:0]=11, device stays in Play Mode.
7.4.8 Device Modulation
TAS5822M has 3 modulation schemes: BD Modulation, 1SPW modulation and Hybrid modulation. Select
modulation schemes for with Register 0x02 [1:0]-DAMP_MOD.
7.4.8.1 BD Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
0V
-
OUTP OUTN
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
Figure 7-9. BD Mode Modualtion
7.4.8.2 1SPW Modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In Low Idle Current mode the
outputs operate at ~17% modulation during idle conditions. When an audio signal is applied one output will
decrease and one will increase. The decreasing output signal will quickly rail to GND at which point all the audio
modulation takes place through the rising output. The result is that only one output is switching during a majority
of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
Figure 7-10. 1SPW Mode Modulation
7.4.8.3 Hybrid Modulation
Hybrid Modulation is designed to minimized power loss without compromising the THD+N performance, and is
optimized for battery-powered applications. With Hybrid modulation enabled, device detects the input signal level
and adjust PWM duty cycle dynamically based on PVDD. Hybrid modulation achieves ultra low idle current and
maintains the same audio performance level as the BD Modulation. In order to minimize the power dissipation,
low switching frequency (For example, Fsw = 384 kHz) with proper LC filter (15 µH + 0.68 µF or 22 µH + 0.68
µF) is recommended.
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Note
1) With Hybrid Modulation, users need to input the system's PVDD value via device development App.
2) With Hybrid Modulation, Change device state from Deep Sleep Mode to Play Mode, specific
sequence is required:
1. Set device's PWM Modulation to BD or 1SPW mode via Register (Book0/Page0/Register0x02h, Bit
[1:0]).
2. Set device to Hi-Z state via Register (Book0/Page0/Register0x03h, Bit [1:0]).
3. Delay 2ms.
4. Set device's PWM Modulation to Hybrid mode via Register (Book0/Page0/Register0x02h, Bit [1:0]).
5. Delay 15ms.
6. Set device to Play state via Register (Book0/Page0/Register0x03h, Bit [1:0]).
7.5 Programming and Control
7.5.1 I2 C Serial Communication Bus
The device has a bidirectional serial control interface that is compatible with the Inter IC ( I2)C bus protocol and
supports 100 and 400-kHz data transfer rates for random and sequential write and read operations as a slave
device. Because the TAS5822M register map and DSP memory spans multi pages, the user should change from
page to page before writing individual register or DSP memory. Changing from page to page is accomplished via
register 0 on each page. This register value selects the page address, from 0 to 255.
7.5.2 Slave Address
The TAS5822M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are
factory preset to 01011(0x5x). The next two bits of address byte are the device select bits which can be user-
defined by ADR/ FAULT pin in Table 7-6.
Table 7-6. I2 C Slave Address Configuration
ADR/ FAULT PIN
MSBs
User Define
LSB
Configuration
4.7k Ω to DVDD
15kΩ to DVDD
47kΩ to DVDD
120kΩ to DVDD
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
R/ W
R/ W
R/ W
R/ W
7.5.2.1 Random Write
As shown in Figure 7-11, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
Figure 7-11. Random Write Transfer
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7.5.2.2 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in Figure 7-12. After receiving each data byte, the device
responds with an acknowledge bit and the I2 subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
R/W ACK
A4 A3
A0
ACK
ACK
ACK
ACK
D0
A6
A1
A7
A6
A5
A1
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
Figure 7-12. Sequential Write Transfer
7.5.2.3 Random Read
As shown in Figure 7-13, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I 2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the
device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the
master device transmits another start condition followed by the address and the read/write bit again. This time
the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device
again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address
being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop
condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
Subaddress
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Data Byte
Figure 7-13. Random Read Transfer
7.5.2.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in Figure 7-14. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
sub address by one. After receiving the last data byte, the master device transmits a not-acknowledge followed
by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
Figure 7-14. Sequential Read Transfer
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7.5.2.5 DSP Memory Book, Page and BQ update
The TAS5822M device supports the I2C serial bus and the data transmission protocol for standard and fast
mode as a slave device.
The DSP memory is arranged in books, pages, and registers. Each book has several pages and each page has
several registers.
Because the TAS5822M register map spans several books and pages, the user must select the correct book and
page before writing individual register bits or bytes.
To change the book, the user must be on page 0x00. In register 0x7f on page 0x00 you can change the book.
On page 0x00 of each book, register 0x7f is used to change the book. Register 0x00 of each page is used to
change the page. To change a book first write 0x00 to register 0x00 to switch to page 0 then write the book
number to register 0x7f on page 0. To change between pages in a book, simply write the page number to
register 0x00.
All the Biquad Filters coefficients are addressed in Book 0xAA. The five coefficients of every Biquad Filter should
be written entirely and sequentially from the lowest address to the highest.
7.5.2.6 Example Use
Example 1, The following is a sample script for configuring a device on I2C slave address 0x58 and set the
device switching frequency to 768kHz with Class D loop bandwidth to 175kHz, 1SPW Modulation:
w 58 00 00 #Go to Page0
w 58 7f 00 #Change the Book to 0x00
w 58 00 00 #Go to Page 0x00
w 58 02 01 #Set switching frequency to 768kHz with 1SPW Modulation
w 58 53 60 #Set Class D Loop Bandwidth to 175kHz
Example 2, The following is a sample script for configuring a device on I2C slave address 0x58 and using the
DSP host memory to change the digital volume to the default value of 0dB:
w 58 00 00 #Go to Page 0
w 58 7f 8c #Change the Book to 0x8C
w 58 00 2a #Go to Page 0x2a
w 58 24 00 80 00 00 #change digital volume to 0dB
7.5.2.7 Checksum
This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an
Exclusive (XOR) checksum. Register reads do not change checksum, but writes to even nonexistent registers
will change the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.
The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00) to their respective 4-byte register
locations.
7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell
delineation, (1 + x1 + x2 + x8)). A major advantage of the CRC checksum is that it is input order sensitive. The
CRC supports all I2C transactions, excluding book and page switching. The CRC checksum is read from register
0x7E on page0 of any book (B_x, Page_0, Reg_126). The CRC checksum can be reset by writing 0x00 to the
same register locations where the CRC checksum is valid.
7.5.2.7.2 Exclusive or (XOR) Checksum
The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with
the previous 8-bit checksum register value. XOR supports only Book 0x8C, and excludes page switching and all
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registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book
0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the same register
location where it is read.
7.5.3 Control via Software
•
•
Startup Procedures
Shutdown Procedures
7.5.3.1 Startup Procedures
1. Configure ADR/ FAULT pin with proper setting for I2C device address.
2. Bring up power supplies (it does not matter if PVDD or DVDD comes up first).
3. Once all power supplies are stable, bring up the PDN HIGH.
4. Once I2S clock are stable, configure the device via the I2C control port based on the user cases (Make sure
the PDN pin = HIGH before I2C control port operating).
5. The device is now in normal operation.
Figure 7-15. Startup sequence
Normal Operation
Initialization
DVDD
PVDD
No sequence requirement
PVDD stable
DVDD stable
PDN
No sequence requirement
I2S
I2S
I2S
I2C
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
Set to Hi-Z state
(Enable DSP)
DSP Coeff
Play
Deep sleep
5 ms for device settle down
7.5.3.2 Shutdown Procedures
1. The device is in normal operation.
2. Configure the Register 0x03h -D[1:0]=00 (DEEP SLEEP) via the I2C control port or Pull PDN low.
3. The clocks can now be stopped and the power supplies brought down.
4. The device is now fully shutdown and powered off.
PDN
6ms
4.5V
PVDD
0ms
DVDD
6ms
I2C
I2C
I2C
I2C
Output Hiz
ñ
ñ
Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I2C.
At least 6ms delay needed based on LRCLK (Fs) = 48kHz,Digital volume ramp down update every sample period,
decreased by 0.5dB for each update, digital volume =24dB. Change the value of register 0x4C and 0x4E or change
the LRCLK rate, the delay changes.
Figure 7-16. Power down sequence
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7.5.3.3 Protection and Monitoring
7.5.3.3.1 Over current Shutdown (OCSD)
Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector,
and the affected channel shuts down in < 100 ns if the peak current are enough. The shutdown speed depends
on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. The
user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the I2C fault register
saves a record. If the supply or ground short is strong enough to exceed the peak current threshold but not
severe enough to trigger the OSCD, the peak current limiter prevents excess current from damaging the output
FETs, and operation returns to normal after the short is removed.
7.5.3.3.2 Speaker DC Protection
If the device measures a >1.9 V (Typical) DC offset and continue more than 570 ms (typical) on the output stage,
the ADR/ FAULT line will be pulled low and set the OUTxx outputs to Hi-Z state to protect speaker, signifying a
fault in Register 0x70 in Book0/Page0. This fault report bit in Register 0x70 keeps 1 and device keeps in Hi-Z
mode unless clear it by Register 0x78 in Book0/Page0 manually.
7.5.3.3.3 Device Over Temperature Protection
Once the die temperature exceed 160°C (Typical), device will set the output driver from Play mode to Hi-Z Mode.
Over temperature shutdown fault reported by Register 0x72 in Book0/Page0. Set this fault's behavior to Auto-
recovery mode, device will come back to play mode automatically once the die temperature drop down to 150°C
or device needs re-enter into play mode by clearing fault with Register 0x78 in Book0/Page0.
7.5.3.3.4 Over Voltage Protection
Once the PVDD voltage exceed the OVETHRES(PVDD) (28.1 V Typical), device will set the output driver from Play
mode to Hi-Z mode. Over voltage fault reported by Register 0x71 in Book0/Page0. Once PVDD drop below 27.5
V (Typical), device will come back to Play mode. But this bit still keeps 1 unless clear it by Register 0x78 in
Book0/Page0 manually.
7.5.3.3.5 Under Voltage Protection
Once the PVDD voltage drop below the UVETHRES(PVDD) (4 V Typical), device will set the output driver from Play
mode to Hi-Z mode. Under voltage fault reported by Register 0x71 in Book0/Page0. Once PVDD rise above 4.25
V (Typical), device will come back to Play mode. But this bit still keeps 1 unless clear it by Register 0x78 in
Book0/Page0 manually.
7.5.3.3.6 Clock Fault
Once there has any Clock error occurs (Clock Halt, SCLK/LRCLK Ratio Error, Pll unlock, FS error) , Register
0x37 and Register 0x39 monitor these errors and real-time report with details, device will enter into Hi-Z mode.
Clock Fault reported in Register 0x71 in Book0/Page0. Once the clock error been removed, device will come
back to play mode automatically. But this bit still keeps 1 unless clear it by Register 0x78 in Book0/Page0
manually.
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7.6 Register Maps
7.6.1 CONTROL PORT Registers
Table 7-7 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in
Table 7-7 should be considered as reserved locations and the register contents should not be modified.
Table 7-7. CONTROL PORT Registers
Offset
1h
Acronym
Register Name
Section
RESET_CTRL
DEVICE_CTRL_1
DEVICE_CTRL_2
I2C_PAGE_AUTO_INC
SIG_CH_CTRL
CLOCK_DET_CTRL
SDOUT_SEL
Register 1
Section 7.6.1.1
Section 7.6.1.2
Section 7.6.1.3
Section 7.6.1.4
Section 7.6.1.5
Section 7.6.1.6
Section 7.6.1.7
Section 7.6.1.8
Section 7.6.1.9
Section 7.6.1.10
Section 7.6.1.11
Section 7.6.1.12
Section 7.6.1.13
Section 7.6.1.14
Section 7.6.1.15
Section 7.6.1.16
Section 7.6.1.17
Section 7.6.1.18
Section 7.6.1.19
Section 7.6.1.20
Section 7.6.1.21
Section 7.6.1.22
Section 7.6.1.23
Section 7.6.1.24
Section 7.6.1.25
Section 7.6.1.26
Section 7.6.1.27
Section 7.6.1.28
Section 7.6.1.29
Section 7.6.1.30
Section 7.6.1.31
Section 7.6.1.32
Section 7.6.1.33
Section 7.6.1.34
Section 7.6.1.35
Section 7.6.1.36
Section 7.6.1.37
Section 7.6.1.38
Section 7.6.1.39
Section 7.6.1.40
Section 7.6.1.41
2h
Register 2
3h
Register 3
Fh
Register 15
Register 40
Register 41
Register 48
Register 49
Register 51
Register 52
Register 53
Register 55
Register 56
Register 57
Register 76
Register 78
Register 79
Register 80
Register 81
Register 82
Register 83
Register 84
Register 92
Register 93
Register 96
Register 97
Register 102
Register 103
Register 104
Register 105
Register 106
Register 107
Register 108
Register 109
Register 110
Register 111
Register 112
Register 113
Register 114
Register 115
Register 116
28h
29h
30h
31h
33h
34h
35h
37h
38h
39h
4Ch
4Eh
4Fh
50h
51h
52h
53h
54h
5Ch
5Dh
60h
61h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
I2S_CTRL
SAP_CTRL1
SAP_CTRL2
SAP_CTRL3
FS_MON
BCK_MON
CLKDET_STATUS
DIG_VOL
DIG_VOL_CTRL1
DIG_VOL_CTRL2
AUTO_MUTE_CTRL
AUTO_MUTE_TIME
AMUTE_DELAY
ANA_CTRL
AGAIN
BQ_WR_CTRL1
DAC_CTRL
ADR_PIN_CTRL
ADR_PIN_CONFIG
DSP_MISC
DIE_ID
POWER_STATE
AUTOMUTE_STATE
PHASE_CTRL
SS_CTRL0
SS_CTRL1
SS_CTRL2
SS_CTRL3
SS_CTRL4
CHAN_FAULT
GLOBAL_FAULT1
GLOBAL_FAULT2
OT WARNING
PIN_CONTROL1
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Table 7-7. CONTROL PORT Registers (continued)
Offset
75h
Acronym
Register Name
Section
PIN_CONTROL2
FAULT_CLEAR
Register 117
Register 120
Section 7.6.1.42
Section 7.6.1.44
78h
Complex bit access types are encoded to fit into small table cells. Table 7-8 shows the codes that are used for
access types in this section.
Table 7-8. CONTROL PORT Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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7.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]
RESET_CTRL is shown in Figure 7-13 and described in Table 7-9.
Return to Table 7-7.
Figure 7-13. RESET_CTRL Register
7
6
5
4
RST_MOD
W
3
2
RESERVED
R
1
0
RST_REG
W
RESERVED
R/W
Table 7-9. RESET_CTRL Register Field Descriptions
Bit
Field
Type
R/W
W
Reset
000
0
Description
7-5
4
RESERVED
RST_MOD
This bit is reserved
WRITE CLEAR BIT
Reset Modules
WRITE CLEAR BIT Reset full digital core This bit resets full digital
signal chain (Include DSP and Control Port Registers). Since the
DSP is also reset, the coeffient RAM content will also be cleared by
the DSP.
0: Normal
1: Reset modules
3-1
0
RESERVED
R
000
0
This bit is reserved
RST_CONTROL_REG
W
WRITE CLEAR BIT
Reset Registers
This bit resets the control port registers back to their initial values.
The RAM content is not cleared.
0: Normal
1: Reset control port registers
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7.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
DEVICE_CTRL_1 is shown in Figure 7-14 and described in Table 7-10.
Return to Table 7-7.
Figure 7-14. DEVICE_CTRL_1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
FSW_SEL
R/W
RESERVED
R/W
DAMP_PBTL
R/W
DAMP_MOD
R/W
Table 7-10. DEVICE_CTRL_1 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
FSW_SEL
0
This bit is reserved
6-4
000
SELECT FSW. 000:768K
001:384K
010:310K
011:480K
100:576K
101:1.024MHz
110:Reserved
111:Reserved
3
2
RESERVED
DAMP_PBTL
R/W
R/W
0
0
This bit is reserved
0: SET DAMP TO BTL MODE
1:SET DAMP TO PBTL MODE
1-0
DAMP_MOD
R/W
00
00: BD MODE
01: 1SPW MODE (Recommended)
10: HYBRID MODE (Recommended)
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7.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]
DEVICE_CTRL_2 is shown in Figure 7-15 and described in Table 7-11.
Return to Table 7-7.
Figure 7-15. DEVICE_CTRL_2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DIS_DSP
R/W
MUTE
R/W
RESERVED
R/W
CTRL_STATE
R/W
Table 7-11. DEVICE_CTRL_2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
000
1
Description
7-5
4
RESERVED
DIS_DSP
This bit is reserved
DSP reset
When the bit is made 0, DSP will start powering up and send out
data. This needs to be made 0 only after all the input clocks are
settled so that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3
MUTE
R/W
0
Mute both Left Channel and Right Channel
This bit issues soft mute request for the left channel and right
channel. The volume will be smoothly ramped down/up to avoid pop/
click noise.
0: Normal volume
1: Mute
2
Reserved
R/W
R/W
0
This bit is reserved
1-0
CTRL_STATE
00
Device state control register
00: Deep Sleep
01: Sleep
10: Hiz,
11: PLAY
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7.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
I2C_PAGE_AUTO_INC is shown in Figure 7-16 and described in Table 7-12.
Return to Table 7-7.
Figure 7-16. I2C_PAGE_AUTO_INC Register
7
6
5
4
3
2
1
0
RESERVED
R/W
PAGE_AUTOIN
C_REG
RESERVED
R/W
R/W
Table 7-12. I2C_PAGE_AUTO_INC Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
0
Description
7-4
3
RESERVED
This bit is reserved
Page auto increment disable
PAGE_AUTOINC_REG
Disable page auto increment mode. for non -zero books. When end
of page is reached it goes back to 8th address location of next page
when this bit is 0. When this bit is 1 it goes to 0 th location of current
page itself like in older part.
0: Enable Page auto increment
1: Disable Page auto increment
2-0
RESERVED
R/W
000
This bit is reserved
7.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
SIG_CH_CTRL is shown in Figure 7-17 and described in Table 7-13.
Return to Table 7-7.
Figure 7-17. SIG_CH_CTRL Register
7
6
5
4
3
2
1
0
BCK_RATIO_CONFIGURE
R/W
FS_MODE
R/W
Table 7-13. SIG_CH_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
BCK_RATIO_CONFIGUR R/W
E
0000
These bits indicate the configured BCK ratio, the number of BCK
clocks in one audio frame.
4'b0011:32FS
4'b0101:64FS
4'b0111:128FS
4'b1001:256FS
4'b1011:512FS
3-0
FS_MODE
R/W
0000
FS Speed Mode These bits select the FS operation mode, which
must be set according to the current audio sampling rate.
4 'b0000 Auto detection
4 'b0110 32KHz
4 'b1000 44.1KHz
4'b1001 48KHz
4 'b1010 88.2KHz
4 'b1011 96KHz
Others Reserved
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7.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
CLOCK_DET_CTRL is shown in Figure 7-18 and described in Table 7-14.
Return to Table 7-7.
Figure 7-18. CLOCK_DET_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
DIS_DET_PLL DIS_DET_BCL DIS_DET_FS DIS_DET_BCL DIS_DET_MISS RESERVED
DIS_DET_LOC
K
K_RANGE
K
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 7-14. CLOCK_DET_CTRL Register Field Descriptions
Bit
7
Field
RESERVED
DIS_DET_PLL
Type
R/W
R/W
Reset
Description
0
0
This bit is reserved
Ignore PLL overate Detection
6
This bit controls whether to ignore the PLL overrate detection. The
PLL must be slow than 150MHz or an error will be reported. When
ignored, a PLL overrate error will not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5
DIS_DET_BCLK_RANGE R/W
0
Ignore BCK Range Detection
This bit controls whether to ignore the BCK range detection. The
BCK must be stable between 256KHz and 50MHz or an error will be
reported. When ignored, a BCK range error will not cause a clock
error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4
3
DIS_DET_FS
R/W
R/W
0
0
Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When
ignored, FS error will not cause a clock error.But CLKDET_STATUS
will report fs error.
0: Regard FS detection
1: Ignore FS detection
DIS_DET_BCLK
Ignore BCK Detection
This bit controls whether to ignore the BCK detection against LRCK.
The BCK must be stable between 32FS and 512FS inclusive or an
error will be reported. When ignored, a BCK error will not cause a
clock error.
0: Regard BCK detection
1: Ignore BCK detection
2
DIS_DET_MISS
R/W
0
Ignore BCK Missing Detection
This bit controls whether to ignore the BCK missing detection. When
ignored an BCK missing will not cause a clock error.
0: Regard BCK missing detection
1: Ignore BCK missing detection
1
0
RESERVED
R/W
R/W
0
0
This bit is reserved
This bit is reserved
DIS_DET_LOCK
7.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]
SDOUT_SEL is shown in Figure 7-19 and described in Table 7-15.
Return to Table 7-7.
Figure 7-19. SDOUT_SEL Register
7
6
5
4
3
2
1
0
RESERVED
SDOUT_SEL
R/W
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Table 7-15. SDOUT_SEL Register Field Descriptions
Bit
7-1
0
Field
Type
Reset
Description
RESERVED
SDOUT_SEL
0
0
This bit is reserved
SDOUT Select.
R
This bit selects what is being output as SDOUT pin.
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
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7.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in Figure 7-20 and described in Table 7-16.
Return to Table 7-7.
Figure 7-20. I2S_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
BCK_INV
R/W
RESERVED
RESERVED
R
RESERVED
R/W
R/W
R
Table 7-16. I2S_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
RESERVED
BCK_INV
00
This bit is reserved
BCK Polarity
0
This bit sets the inverted BCK mode. In inverted BCK mode, the
DAC assumes that the LRCK and DIN edges are aligned to the rising
edge of the BCK. Normally they are assumed to be aligned to the
falling edge of the BCK.
0: Normal BCK mode
1: Inverted BCK mode
4-0
RESERVED
R/W
00000
This bit is reserved
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7.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
SAP_CTRL1 is shown in Figure 7-21 and described in Table 7-17.
Return to Table 7-7.
Figure 7-21. SAP_CTRL1 Register
7
6
5
4
3
2
1
0
I2S_SHIFT_MSB
DATA_FORMAT
R/W
I2S_LRCLK_PULSE
R/W
WORD_LENGTH
R/W
R/W
Table 7-17. SAP_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
I2S_SHIFT_MSB
R/W
00
I2S Shift MSB [9:8].
See details in Table 7-18.
5-4
DATA_FORMAT
R/W
00
I2S Data Format
These bits control both input and output audio interface formats for
DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2
1-0
I2S_LRCLK_PULSE
WORD_LENGTH
R/W
R/W
00
10
01: lrclk pulse < 8 SCLK
I2S Word Length
These bits control both input and output audio interface sample word
lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
7.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
SAP_CTRL2 is shown in Figure 7-22 and described in Table 7-18.
Return to Table 7-7.
Figure 7-22. SAP_CTRL2 Register
7
6
5
4
3
2
1
0
I2S_SHIFT
R/W
Table 7-18. SAP_CTRL2 Register Field Descriptions
Bit
7-0
Field
I2S_SHIFT
Type
Reset
Description
R/W
00000000
I2S Shift LSB [7:0]
These bits control the offset of audio data in the audio frame for both
input and output. The offset is defined as the number of BCK from
the starting (MSB) of audio frame to the starting of the desired audio
sample. I2S Shift MSB [9:8] locates in Section 7.6.1.9 .
000000000: offset = 0 BCK (no offset)
000000001: ofsset = 1 BCK
000000010: offset = 2 BCKs
and
111111111: offset = 512 BCKs
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7.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
SAP_CTRL3 is shown in Figure 7-23 and described in Table 7-19.
Return to Table 7-7.
Figure 7-23. SAP_CTRL3 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
LEFT_DAC_DPATH
R/W
RESERVED
R/W
RIGHT_DAC_DPATH
R/W
Table 7-19. SAP_CTRL3 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5-4
RESERVED
00
This bit is reserved
LEFT_DAC_DPATH
01
Left DAC Data Path. These bits control the left channel audio data
path connection.
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
3-2
1-0
RESERVED
R/W
R/W
00
01
This bit is reserved
RIGHT_DAC_DPATH
Right DAC Data Path. These bits control the right channel audio data
path connection.
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)
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7.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
FS_MON is shown in Figure 7-24 and described in Table 7-20.
Return to Table 7-7.
Figure 7-24. FS_MON Register
7
6
5
4
3
2
1
0
RESERVED
R/W
BCLK_RATIO_HIGH
R
FS
R
Table 7-20. FS_MON Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-6
5-4
3-0
RESERVED
BCLK_RATIO_HIGH
FS
00
This bit is reserved
2 msbs of detected BCK ratio
00
R
0000
These bits indicate the currently detected audio sampling rate.
0000 FS Error
0010 8KHz
0100 16KHz
0110 32KHz
1000 Reserved
1001 48KHz
1011 96KHz
1101 192KHz
Others Reserved
7.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]
BCK_MON is shown in Figure 7-25 and described in Table 7-21.
Return to Table 7-7.
Figure 7-25. BCK_MON Register
7
6
5
4
3
2
1
0
BCLK_RATIO_LOW
R
Table 7-21. BCK_MON Register Field Descriptions
Bit
7-0
Field
BCLK_RATIO_LOW
Type
Reset
Description
R
00000000
These bits indicate the currently detected BCK ratio, the number of
BCK clocks in one audio frame.
BCK = 32 FS~512 FS
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7.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
CLKDET_STATUS is shown in Figure 7-26 and described in Table 7-22.
Return to Table 7-7.
Figure 7-26. CLKDET_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DET_STATUS
R
Table 7-22. CLKDET_STATUS Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-6
5
RESERVED
00
0
This bit is reserved
DET_STATUS
This bit indicates whether the BCLK is overrate or underrate
This bit indicates whether the PLL is overrate
4
R
0
3
R
0
This bit indicates whether the PLL is locked or not. The PLL will be
reported as unlocked when it is disabled.
2
1
R
R
0
0
This bit indicates whether the BCK is missing or not.
This bit indicates whether the BCK is valid or not. The BCK ratio
must be stable and in the range of 32-512FS to be valid.
0
R
0
In auto detection mode(reg_fsmode=0),this bit indicated whether the
audio sampling rate is valid or not. In non auto detection
mode(reg_fsmode!=0), Fs error indicates that configured fs is
different with detected fs. Even FS Error Detection Ignore is set, this
flag will be also asserted.
7.6.1.15 DIG_VOL Register (Offset = 4Ch) [reset = 30h]
DIG_VOL is shown in Figure 7-27 and described in Table 7-23.
Return to Table 7-7.
Figure 7-27. DIG_VOL Register
7
6
5
4
3
2
1
0
PGA_LEFT
R/W
Table 7-23. DIG_VOL Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
PGA
R/W
00110000
Digital Volume
These bits control both left and right channel digital volume. The
digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute
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7.6.1.16 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]
DIG_VOL_CTRL1 is shown in Figure 7-28 and described in Table 7-24.
Return to Table 7-7.
Figure 7-28. DIG_VOL_CTRL1 Register
7
6
5
4
3
2
1
0
PGA_RAMP_UP_STEP
R/W
PGA_RAMP_DOWN_SPEED
R/W
PGA_RAMP_DOWN_STEP
R/W
PGA_RAMP_UP_SPEED
R/W
Table 7-24. DIG_VOL_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PGA_RAMP_DOWN_SPE R/W
ED
00
Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
3-2
1-0
PGA_RAMP_DOWN_STE R/W
P
11
00
11
Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
PGA_RAMP_UP_SPEED R/W
Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
PGA_RAMP_UP_STEP
R/W
Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the
volume is ramping up.
00: Increment by 4 dB for each updat
e 01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update
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7.6.1.17 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL2 is shown in Figure 7-29 and described in Table 7-25.
Return to Table 7-7.
Figure 7-29. DIG_VOL_CTRL2 Register
7
6
5
4
3
2
1
0
FAST_RAMP_DOWN_SPEED
R/W
FAST_RAMP_DOWN_STEP
R/W
RESERVED
R/W
Table 7-25. DIG_VOL_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
FAST_RAMP_DOWN_SP R/W
EED
00
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down due to clock error or power outage,
which usually needs faster ramp down compared to normal soft
mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
FAST_RAMP_DOWN_ST R/W
EP
11
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down due to clock error or power outage, which
usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0
RESERVED
R/W
0000
This bit is reserved
7.6.1.18 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
AUTO_MUTE_CTRL is shown in Figure 7-30 and described in Table 7-26.
Return to Table 7-7.
Figure 7-30. AUTO_MUTE_CTRL Register
7
6
5
4
3
2
1
REG_AUTO_MUTE_CTRL
R/W
0
RESERVED
R/W
Table 7-26. AUTO_MUTE_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
00000
1
Description
7-3
2
R/W
This bit is reserved
REG_AUTO_MUTE_CTR R/W
L
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are
about to be auto muted.
1
0
1
1
0: Disable right channel auto mute
1: Enable right channel auto mute
0: Disable left channel auto mute
1: Enable left channel auto mute
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7.6.1.19 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
AUTO_MUTE_TIME is shown in Figure 7-31 and described in Table 7-27.
Return to Table 7-7.
Figure 7-31. AUTO_MUTE_TIME Register
7
6
5
AUTOMUTE_TIME_LEFT
R/W
4
3
2
1
0
RESERVED
R/W
RESERVED
R/W
AUTOMUTE_TIME_RIGHT
R/W
Table 7-27. AUTO_MUTE_TIME Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
6-4
AUTOMUTE_TIME_LEFT R/W
000
Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
3
RESERVED
R/W
0
This bit is reserved
2-0
AUTOMUTE_TIME_RIGH R/W
T
000
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
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7.6.1.20 AMUTE_DELAY Register (Offset = 52h) [reset = 0x00]
AMUTE_DELAY is shown in Figure 7-32 and described in Table 7-28.
Return to Table 7-7.
Figure 7-32. AMUTE_DELAY Register
7
6
5
4
3
2
1
0
AMUTE_DLY
R/W
Table 7-28. AMUTE_DELAY Register Field Descriptions
Bit
7-0
Field
AMUTE_DLY
Type
Reset
Description
R/W
00000000
AMUTE Delay
These bits control the delay before the complete digital mute to the
assertion of analog mute. This is to allow the non-mute audio
samples to completely flow out through analog parts before the
assertion of the analog mute.
00000000: No delay
00000001: 1 LRCK delay
00000010: 2 LRCK delay
......
11111111: 255 LRCK delay
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7.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0x00]
ANA_CTRL is shown in Figure 7-33 and described in Table 7-29.
Return to Table 7-7.
Figure 7-33. ANA_CTRL Register
7
6
5
4
3
2
1
0
ANA_CTRL
R/W
Table 7-29. ANA_CTRL Register Field Descriptions
Bit
Field
ANA_CTRL
Type
Reset
Description
7
R/W
0
Fast Hiz control enable in clock halt
6-5
00
Class-D bandwidth control, "00": 80kHz; "01": 100kHz; "10": 120kHz;
"11": 175kHz.
With 768kHz or 1.024MHz switching frequency, bandwidth need set
to 175kHz for best audio performance
4-1
0
0000
0
These bits are reserved
Channel L and R PWM output of phase control .
1: In phase
0: Out of phase
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7.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]
AGAIN is shown in Figure 7-34 and described in Table 7-30.
Return to Table 7-7.
Figure 7-34. AGAIN Register
7
6
5
4
3
2
1
0
RESERVED
R/W
ANA_GAIN
R/W
Table 7-30. AGAIN Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-5
4-0
RESERVED
ANA_GAIN
000
This bit is reserved
00000
Analog Gain Control
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001:-0.5db
11111: -15.5 dB
7.6.1.23 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
BQ_WR_CTRL1 is shown in Figure 7-35 and described in Table 7-31.
Return to Table 7-7.
Figure 7-35. BQ_WR_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
BQ_WR_FIRST
_COEF
R/W
R/W
Table 7-31. BQ_WR_CTRL1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000000
0
Description
7-1
0
RESERVED
This bit is reserved
BQ_WR_FIRST_COEF
Indicate the first coefficient of a BQ is starting to write.
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7.6.1.24 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
DAC_CTRL is shown in Figure 7-36 and described in Table 7-32.
Return to Table 7-7.
Figure 7-36. DAC_CTRL Register
7
6
5
4
3
2
1
0
DAC_FREQUE
NCY_SEL
DAC_DITHER_EN
DAC_DITHER
R/W
DAC_CTRL_DEM_SEL
R/W
R/W
R/W
Table 7-32. DAC_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DAC_FREQUENCY_SEL R/W
1
DAC Frequency Selection
0: 6.144MHz
1: 3.072MHz
6-5
4-2
DAC_DITHER_EN
DAC_DITHER
R/W
R/W
11
DITHER_EN,
00: Disable both stage dither
01: Enable main stage dither
10: Enable second stage dither
11: Enable both stage dither
110
Dither level
100: -2^-7
101: -2^-8
110: -2^-9
111: -2^-10
000: -2^-13
001: -2^-14
010: -2^-15
011: -2^-16
1-0
DAC_CTRL_DEM_SEL
R/W
00
00: Enable DAC DEM (Dynamic-Element-Matching)
11: Disable DAC DEM (Dynamic-Element-Matching)
7.6.1.25 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]
ADR_PIN_CTRL is shown in Figure 7-37 and described in Table 7-33.
Return to Table 7-7.
Figure 7-37. ADR_PIN_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
ADR_OE
R/W - 0x0
Table 7-33. ADR_PIN_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000000
0
Description
7-1
0
RESERVED
ADR_OE
This bit is reserved
ADR Output Enable
This bit sets the direction of the ADR pin
0: ADR is input
1: ADR is output
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7.6.1.26 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]
ADR_PIN_CONFIG is shown in Figure 7-38 and described in Table 7-34.
Return to Table 7-7.
Figure 7-38. ADR_PIN_CONFIG Register
7
6
5
4
3
2
ADR_PIN_CONFIG
R/W
1
0
RESERVED
Table 7-34. ADR_PIN_CONFIG Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-5
4-0
RESERVED
ADR_PIN_CONFIG
000
This bit is reserved
00000: off (low)
00000
00011: Auto mute flag (asserted when both L and R channels are
auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock missing)
00111: Reserved
01000: Reserved
01001: Reserved
01011: ADR as FAULTZ output
7.6.1.27 DSP_MISC Register (Offset = 66h) [reset = 0h]
DSP_MISC is shown in Figure 7-39 and described in Table 7-35.
Return to Table 7-7.
Figure 7-39. DSP_MISC Register
7
6
5
4
3
2
1
0
BYPASS_CONTROL
R/W
Table 7-35. DSP_MISC Register Field Descriptions
Bit
Field
BYPASS CONTROL
Type
Reset
0000
0
Description
7-4
3
R/W
These bits are reserved
1: Left and Right will have use unique coef
0: Right channel will share left channel coefficient
2
1
0
0
0
0
This bit is reserved
1: Bypass DRC
1: Bypass EQ
7.6.1.28 DIE_ID Register (Offset = 67h) [reset = 0h]
DIE_ID is shown in Figure 7-40 and described in Table 7-36.
Return to Table 7-7.
Figure 7-40. DIE_ID Register
7
6
5
4
3
2
1
0
DIE_ID
R-0h
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Table 7-36. DIE_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIE_ID
R
0h
DIE ID
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7.6.1.29 POWER_STATE Register (Offset = 68h) [reset = 0x00]
POWER_STATE is shown in Figure 7-41 and described in Table 7-37.
Return to Table 7-7.
Figure 7-41. POWER_STATE Register
7
6
5
4
3
2
1
0
STATE_RPT
R
Table 7-37. POWER_STATE Register Field Descriptions
Bit
Field
Type
Reset
000000
00
Description
7-2
1-0
Reserved
R
These bits are reserved
STATE_RPT
R
00: Deep sleep
01: Seep
10: HIZ
11: Play
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7.6.1.30 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
AUTOMUTE_STATE is shown in Figure 7-42 and described in Table 7-38.
Return to Table 7-7.
Figure 7-42. AUTOMUTE_STATE Register
7
6
5
4
3
2
1
0
RESERVED
R
ZERO_RIGHT_ ZERO_LEFT_M
MON
ON
R
R
Table 7-38. AUTOMUTE_STATE Register Field Descriptions
Bit
Field
Type
Reset
000000
0
Description
7-2
1
RESERVED
R
This bit is reserved
ZERO_RIGHT_MON
R
This bit indicates the auto mute status for right channel.
0: Not auto muted
1: Auto muted
0
ZERO_LEFT_MON
R
0
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
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7.6.1.31 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]
PHASE_CTRL is shown in Figure 7-43 and described in Table 7-39.
Return to Table 7-7.
Figure 7-43. PHASE_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
RAMP_PHASE_SEL
R/W
I2S_SYNC_EN PHASE_SYNC
_EN
R/W
R/W
R/W
Table 7-39. PHASE_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
00
Description
7-4
3-2
RESERVED
This bit is reserved
RAMP_PHASE_SEL
Select ramp clock phase when multi devices integrated in one
system to reduce EMI and peak supply peak current, it is
recomended set all devices the same RAMP frequency and same
spread spectrum. it must be set before driving device into PLAY
mode if this feature is needed.
00: phase 0
01: phase1
10: phase2
11: phase3
1
0
I2S_SYNC_EN
R/W
R/W
0
0
Use I2S to synchronize output PWM phase
0: Disable
1: Enable
PHASE_SYNC_EN
0: RAMP phase sync disable
1: RAMP phase sync enable
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7.6.1.32 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
SS_CTRL0 is shown in Figure 7-44 and described in Table 7-40.
Return to Table 7-7.
Figure 7-44. SS_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
SS_PRE_DIV_ SS_MANUAL_
RESERVED
R/W
SS_RDM_EN
SS_TRI_EN
SEL
MODE
R/W
R/W
R/W
R/W
R/W
R/W
Table 7-40. SS_CTRL0 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
0
0
0
0
0
0
0
This bit is reserved
This bit is reserved
6
RESERVED
5
SS_PRE_DIV_SEL
SS_MANUAL_MODE
RESERVED
Select pll clock divide 2 as source clock in manual mode
Set ramp ss controller to manual mode
This bit is reserved
4
3-2
1
SS_RDM_EN
Random SS enable
0
SS_TRI_EN
Triangle SS enable
7.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in Figure 7-45 and described in Table 7-41.
Return to Table 7-7.
Figure 7-45. SS_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SS_RDM_CTRL
R/W
SS_TRI_CTRL
R/W
Table 7-41. SS_CTRL1 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
Reset
Description
RESERVED
0
This bit is reserved
6-4
3-0
SS_RDM_CTRL
SS_TRI_CTRL
000
0000
Random SS range control
Triangle SS frequency and range control
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7.6.1.34 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]
SS_CTRL2 is shown in Figure 7-46 and described in Table 7-42.
Return to Table 7-7.
Figure 7-46. SS_CTRL2 Register
7
6
5
4
3
2
1
0
TM_FREQ_CTRL
R/W
Table 7-42. SS_CTRL2 Register Field Descriptions
Bit
7-0
Field
TM_FREQ_CTRL
Type
Reset
Description
R/W
01010000
Control ramp frequency in manual mode, F=61440000/N
7.6.1.35 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
SS_CTRL3 is shown in Figure 7-47 and described in Table 7-43.
Return to Table 7-7.
Figure 7-47. SS_CTRL3 Register
7
6
5
4
3
2
1
0
TM_DSTEP_CTRL
R/W
TM_USTEP_CTRL
R/W
Table 7-43. SS_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SS_TM_DSTEP_CTRL
R/W
0001
Control triangel mode spread spectrum fall step in ramp ss manual
mode
3-0
SS_TM_USTEP_CTRL
R/W
0001
Control triangle mode spread spectrum rise step in ramp ss manual
mode
7.6.1.36 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
SS_CTRL4 is shown in Figure 7-48 and described in Table 7-44.
Return to Table 7-7.
Figure 7-48. SS_CTRL4 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
TM_AMP_CTRL
R/W
SS_TM_PERIOD_BOUNDRY
R/W
Table 7-44. SS_CTRL4 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
0
This bit is reserved
6-5
4-0
TM_AMP_CTRL
01
Control ramp amp ctrl in ramp ss manual model
SS_TM_PERIOD_BOUND R/W
RY
00100
Control triangle mode spread spectrum boundary in ramp ss manual
mode
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7.6.1.37 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
CHAN_FAULT is shown in Figure 7-49 and described in Table 7-45.
Return to Table 7-7.
Figure 7-49. CHAN_FAULT Register
7
6
5
4
3
CH1_DC_1
R
2
CH2_DC_1
R
1
0
CH2_OC_I
R
RESERVED
R
CH1_OC_I
R
Table 7-45. CHAN_FAULT Register Field Descriptions
Bit
Field
Type
Reset
0000
0
Description
7-4
3
RESERVED
CH1_DC_1
R
This bit is reserved
Left channel DC fault.
R
Once there is a DC fault, this bit will set to 1. Class D output will set
to Hi-Z. Report by FAULT pin (Pin 10).
Clear this fault by setting bit 7 of Section 7.6.1.44 to 1 or this bit
keeps 1.
2
1
0
CH2_DC_1
CH1_OC_I
CH2_OC_I
R
R
R
0
0
0
Right channel DC fault.
Once there is a DC fault, this bit will set to 1. Class D output will set
to Hi-Z. Report by FAULT pin (Pin 10).
Clear this fault by setting bit 7 of Section 7.6.1.44 to 1 or this bit
keeps 1.
Left channel over current fault.
Once there is an OC fault, this bit will set to 1. Class D output will set
to Hi-Z. Report by FAULT pin (Pin 10).
Clear this fault by setting bit 7 of Section 7.6.1.44 to 1 or this bit
keeps 1.
Right channel over current fault.
Once there is an OC fault, this bit will set to 1. Class D output will set
to Hi-Z. Report by FAULT pin (Pin 10).
Clear this fault by setting bit 7 of Section 7.6.1.44 to 1 or this bit
keeps 1.
7.6.1.38 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
GLOBAL_FAULT1 is shown in Figure 7-50 and described in Table 7-46.
Return to Table 7-7.
Figure 7-50. GLOBAL_FAULT1 Register
7
6
5
4
3
2
1
0
OTP_CRC_ER BQ_WR_ERRO
CLK_FAULT_I
PVDD_OV_I
PVDD_UV_I
ROR
R
R
R
R
R
R
Table 7-46. GLOBAL_FAULT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
OTP_CRC_ERROR
BQ_WR_ERROR
RESERVED
R
0h
Indicate OTP CRC check error.
The recent BQ is written failed
This bit is reserved
Clock fault.
R
0h
5-3
2
R
0h
CLK_FAULT_I
R
0h
Once there is a Clock fault, this bit will set to 1. Class D output will
set to Hi-Z. Report by FAULT pin (Pin 10).
Clock fault works with an auto-recovery mode, once the clock error
removes, device automatically returns to the previous state.
Clear this fault by setting bit 7 of Section 7.6.1.44 to 1 or this bit
keeps 1.
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Table 7-46. GLOBAL_FAULT1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
PVDD_OV_I
R
0h
PVDD OV fault.
Once there is an OV fault, this bit will set to 1. Class D output will set
to Hi-Z. Report by FAULT pin (Pin 10). OV fault works with an auto-
recovery mode, once the OV error removes, device automatically
returns to the previous state.
Clear this fault by setting bit 7 of Section 7.6.1.44 to 1 or this bit
keeps 1.
Once OV fault been cleared by Register 0x78, even the OV fault still
exist (Device still keeps in Hi-Z state due to High PVDD),
PVDD_OV_I keeps 0 unless the OV fault been triggered again
(PVDD drop below the OV
threshold and rise again).
0
PVDD_UV_I
R
0h
PVDD UV fault.
Once there is an UV fault, this bit will set to 1. Class D output will set
to Hi-Z. Report by FAULT pin (Pin 10).
UV fault works with an auto-recovery mode, once the UV error
removes, device automatically returns to the previous state.
Clear this fault by setting bit 7 of Section 7.6.1.44 to 1 or this bit
keeps 1.
Once UV fault been cleared by Register 0x78, even the UV fault still
exist (Device still keep in Hi-Z state due to Low PVDD), PVDD_UV_I
keeps 0 unless the UV fault been triggered again (PVDD rise above
the UV threshold and fall again).
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7.6.1.39 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
GLOBAL_FAULT2 is shown in Figure 7-51 and described in Table 7-47.
Return to Table 7-7.
Figure 7-51. GLOBAL_FAULT2 Register
7
6
5
RESERVED
R
4
3
2
1
0
OTSD_I
R
RESERVED
R
Table 7-47. GLOBAL_FAULT2 Register Field Descriptions
Bit
Field
Type
Reset
0000000
0
Description
7-1
0
RESERVED
OTSD_I
R
This bit is reserved
R
Over temperature shut down fault.
Once there is an OT fault, this bit will set to 1. Class D output will set
to Hi-Z. Report by FAULT pin (Pin 10).
OT fault works with an auto-recovery mode by setting bit 4 of Section
7.6.1.43 to 1, once the OT error removes, device automatically
returns to the previous state.
Once OT fault been cleared by Register 0x78, even the OT still exist
(Junction temperature exceed 160°C), device will start playing. This
is a risk may destroy device, so suggest to set device to OT
autorecovery mode or keep Hi-Z state until the OT warning
disappear.
OTSD_I keeps 0 unless the OT fault been triggered again
(Temperature drop below the threshold and exceed the threshold
again).
7.6.1.40 OT WARNING Register (Offset = 73h) [reset = 0x00]
OT_WARNING is shown in Figure 7-52 and described in Table 7-48.
Return to Table 7-7.
Figure 7-52. OT_WARNING Register
7
6
5
4
3
2
OTW
R
1
0
RESERVED
R
RESERVED
RESERVED
R
R
R
R
Table 7-48. OT_WARNING Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-4
3
RESERVED
RESERVED
OTW
R
00
This bit is reserved
This bit is reserved
Over temperature warning ,135C
This bit is reserved
R
00
R
0
2-0
RESERVED
R
000
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7.6.1.41 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
PIN_CONTROL1 is shown in Figure 7-53 and described in Table 7-49.
Return to Table 7-7.
Figure 7-53. PIN_CONTROL1 Register
7
6
5
4
3
2
1
0
MASK_OTSD
Reserved
Reserved
MASK_CLK_FA MASK_PVDD_ MASK_PVDD_
MASK_DC
MASK_OC
ULT
UV
OV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 7-49. PIN_CONTROL1 Register Field Descriptions
Bit
7
Field
MASK_OTSD
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
0
0
0
0
0
0
0
0
Mask OTSD fault report
This bit is reserved
This bit is reserved
6
RESERVED
5
RESERVED
4
MASK_CLK_FAULT
MASK_PVDD_UV
MASK_PVDD_OV
MASK_DC
Mask clock fault report by setting this bit to 1.
Mask PVDD UV fault report by setting this bit to 1.
Mask PVDD OV fault report by setting this bit to 1.
Mask DC fault report by setting this bit to 1.
Mask OC fault report by setting this bit to 1.
3
2
1
0
MASK_OC
7.6.1.42 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
PIN_CONTROL2 is shown in Figure 7-54 and described in Table 7-50.
Return to Table 7-7.
Figure 7-54. PIN_CONTROL2 Register
7
6
5
4
3
2
1
0
RESERVED
CLKFLT_LATC OTSD_LATCH_ OTW_LATCH_
MASK_OTW
RESERVED
H_EN
EN
EN
R/W
R/W
R/W
R/W
Table 7-50. PIN_CONTROL2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
7-6
5
RESERVED
11
1
This bit is reserved
CLKFLT_LATCH_EN
OTSD_LATCH_EN
OTW_LATCH_EN
MASK_OTW
Enable clock fault latch by setting this bit to 1.
4
1
Enable OTSD fault latch by setting this bit to 1.
Enable OT warning latch by setting this bit to 1.
Mask OT warning report by setting this bit to 1.
This bit is reserved
3
1
2
0
1-0
RESERVED
00
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7.6.1.43 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
MISC_CONTROL is shown in Figure 7-55 and described in Table 7-51.
Return to Table 7-7.
Figure 7-55. MISC_CONTROL Register
7
6
5
4
3
2
1
0
DET_STATUS_
LATCH
RESERVED
R/W
OTSD_AUTO_
REC_EN
RESERVED
R/W
R/W
R/W
Table 7-51. MISC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DET_STATUS_LATCH
R/W
0
1:Latch clock detection status
0:Don't latch clock detection status
6-5
4
RESERVED
R/W
R/W
R/W
00
This bit is reserved
OTSD_AUTO_REC_EN
RESERVED
0
OTSD auto recovery enable by setting this bit to 1.
This bit is reserved
3-0
0000
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7.6.1.44 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
FAULT_CLEAR is shown in Figure 7-56 and described in Table 7-52.
Return to Table 7-7.
Figure 7-56. FAULT_CLEAR Register
7
6
5
4
3
2
1
0
ANALOG_FAUL
T_CLEAR
RESERVED
W
R/W
Table 7-52. FAULT_CLEAR Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ANALOG_FAULT_CLEAR
RESERVED
W
0
WRITE CLEAR BIT once write this bit to 1, device will clear analog
fault
6-0
R/W
0000000
This bit is reserved
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
This section details the information required to configure the device for several popular configurations and
provides guidance on integrating the TAS5822M device into the larger system.
8.2 Typical Applications
8.2.1 2.0 (Stereo BTL) System
In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels
are amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated
based upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered
2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
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8.2.2 MONO （PBTL) System
In MONO mode, TAS5822M can be used as PBTL mode to drive sub-woofer with more output power.
Figure 8-2. Mono (PBTL) System Application Schematic
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8.2.2.1 Design Requirements
Table 8-1. Design Parameters
PARAMETER
PVDD
VALUE
4.5V-24V
DVDD
1.8V or 3.3V
Speaker Load
LC Filter
6Ω/8Ω in BTL Mode, 3Ω/4Ω in PBTL Mode
10uH+0.68uF
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Bootstrap Capacitors
The output stage of the TAS5822M uses a high-side NMOS driver, rather than a PMOS driver. To generate the
gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating
power supply for the switching cycle. Use 0.47-µF capacitors to connect the appropriate output pin (OUT_X) to
the bootstrap pin (BST_X). For example, connect a 0.47-µF capacitor between OUT_A and BST_A for
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bootstrapping the A channel. Similarly, connect another 0.47-µF capacitor between the OUT_B and BST_B pins
for the B channel inverting output.
8.2.2.2.2 Inductor Selections
It is required that the peak current is smaller than the OCP (Over current protection) value which is 7A (Typical) ,
there are 3 cases which cause high peak current flow through inductor.
1. During power up (idle state, no audio input), the duty cycle increases from 0 to θ. There has a start-up current
which flow through inductor to set up the common mode voltage (PVDD×θ).
Note
θ = 0.5 (BD Modulation), 0.14 (1SPW Modulation), 0.14 (Hybrid Modulation)
Start-up Current shows the start-up current related to different Fsw, PVDD, Inductance and different PWM
modulation scheme. Start-up current should within device's OCETHRES
.
Table 8-2. Start-up Current
Modulation
Scheme
PVDD (V)
FSW ((kHz))
LC filter
Startup Peak Current (A)
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
4.7 µH + 0.68 µF
10 µH + 0.68 µF
2.88
2
384
13.5
2.64
1.84
3.84
2.64
3.52
2.4
768
384
768
384
768
384
768
384
768
384
768
BD
18
24
5.4
3.76
5
3.12
1.28
0.96
1.12
0.72
1.84
1.2
13.5
18
1SPW
1.52
1.04
2.6
1.6
24
2.4
1.36
Figure 8-3 and Figure 8-4 shows how modulation scheme affect the start-up current. OUTP_PWM is Class D
amplifier's PWM output, OUTP_FILTER is the common mode voltage on the capacitor of LC filter.
2. During music playing, some audio burst signal (high frequency) with very hard PVDD clipping will cause
PWM duty cycle increase dramatically. This is the worst case and it rarely happens.
Ipeak _clipping ö PVDDì(1-
q
)/(F ì L)
sw
(1)
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3. Peak current due to Max output power. Ignore the ripple current flow through capacitor.
Ipeak _ output _ power ö 2ì Max _Output _ Power / Rspea ker_ Load
(2)
Same PVDD and switching frequency, larger inductance means smaller idle current for lower power dissipation.
It's suggested that inductor's saturation current Isat, is larger than the amplifier's peak current during power-up
and playing audio. In addition, the effective inductance at the peak current is required to be at least 80% of the
inductance value in LC filter recommendation to meet datasheet specifications.
Table 8-3. LC filter recommendation
Recommended Minimum Inductance (uH) for LC filter
Switching Frequency (kHz)
Modulation Scheme
design
1024
768
3.3 µH (or larger) + Capacitor (0.22uF~0.68uF)
4.7 µH (or larger) + Capacitor (0.22uF~0.68uF)
10 µH (or larger) +Capacitor (0.22uF~0.68uF)
8.2uH (or Larger) +Capacitor (0.22uF~0.68uF)
1SPW
BD
384 or 480
384~1024
8.2.2.2.3 Power Supply Decoupling
To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise
transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. The power supply input must be decoupled with some
good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to
the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the
PVDD pins of the device.
8.2.2.2.4 Output EMI Filtering
The TAS5822M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that
are commonly used. In other high-power applications, large toroid inductors are required for maximum power
and film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter
Design (SLOA119) for a detailed description on the proper component selection and design of an L-C filter
based upon the desired load and response.
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8.2.2.3 Application Performance Plots
Figure 8-3. Start-up Current
Figure 8-4. Start-up Current
(Fsw = 768 kHz, LC filter = 4.7 µH + 0.68 µF, PVDD = (Fsw = 768 kHz, LC filter = 4.7 µH + 0.68 µF, PVDD =
24 V, BD Modulation) 24 V, 1SPW Modulation)
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9 Power Supply Recommendations
The device requires three power supplies for proper operation. A high-voltage supply calls PVDD is required to
power the output stage of the speaker amplifier and its associated circuitry. One low-voltage power supply which
is calls DVDD is required to power the various low-power portions of the device. The allowable voltage range for
both PVDD and DVDD supply are listed in the Recommended Operating Conditions table. The two power
supplies do not have a required power-up sequence. The power supplies can be powered on in any order. But
once the device has been initialized, PVDD must keep within the normal operation voltage. Once PVDD lower
than 3.5V, all registers need re-initialize again. Recommends waiting 1 ms to 5 ms for the DVDD power supplies
to stabilize before starting I2C communication and providing stable I2S clock before enabling the device outputs.
Internal Digital
Digital IO
Circuitry
DVDD
1.8V/3.3VÅ
VR_DIG
1.5V
LDO
External Filtering/Decoupling
DVDD
Gate Drive/Internal
Analog Circuitry
Output Stage
Power Supply
PVDD
4.5V~26.4V
AVDD
5V
LDO
External Filtering/Decoupling
PVDD
Copyright © 2018, Texas Instruments Incorporated
Figure 9-1. Power Supply Function Block Diagram
9.1 DVDD Supply
The DVDD supply that is required from the system is used to power several portions of the device. As shown in
Figure 9-1, it provides power to the DVDD pin. Proper connection, routing and decoupling techniques are
highlighted in the Section 8 section and the Section 10.2 section and must be followed as closely as possible for
proper operation and performance.
Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.
To simplify the power supply requirements for the system, the TAS5822M device includes an integrated low
dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the VR_REG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuity. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
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9.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques
are highlighted in the EVM and must be followed as closely as possible for proper operation and performance.
Due to the high-voltage switching of the output stage, it is particularly important to properly decouple the output
power stages in the manner described in the TAS5822M device . Lack of proper decoupling, like that shown in
the Section 8, results in voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is
provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note
that the linear regulator integrated in the device has only been designed to support the current requirements of
the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this
pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.
AVDD pin is provided for the attachment of decoupling capacitor for the TAS5822M internal circuitry. It is
important to note that the linear regulator integrated in the device has only been designed to support the current
requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional
loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the
device.
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10 Layout
10.1 Layout Guidelines
10.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in the Section 10.2 section. These examples
represent exemplary baseline balance of the engineering trade-offs involved with lying out the device. These
designs can be modified slightly as needed to meet the needs of a given application. In some applications, for
instance, solution size can be compromised to improve thermal performance through the use of additional
contiguous copper neat the device. Conversely, EMI performance can be prioritized over thermal performance
by routing on internal traces and incorporating a via picket-fence and additional filtering components. In all
cases, it is recommended to start from the guidance shown in the Section 10.2 section and work with TI field
application engineers or through the E2E community to modify it based upon the application specific goals.
10.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This
applies to DVDD, AVDD and PVDD. However, the capacitors on the PVDD net for the TAS5822M device
deserve special attention.
The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as
possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in
the system, but doing so can also negatively affect the reliability of the device. Placement of these components
too far from the TAS5822M device can cause ringing on the output pins that can cause the voltage on the output
pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the
deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD
pins than what is shown in the example layouts in the Section 10.2 section.
10.1.3 Optimizing Thermal Performance
Follow the layout example shown in the Figure 10-1 to achieve the best balance of solution size, thermal, audio,
and electromagnetic performance. In some cases, deviation from this guidance can be required due to design
constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can
get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device
naturally travels away from the device and into the lower temperature structures around the device.
10.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
•
Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
•
If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5822M device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
•
•
Place the TAS5822M device away from the edge of the PCB when possible to ensure that the heat can travel
away from the device on all four sides.
Avoid cutting off the flow of heat from the TAS5822MM device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
•
Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5782M
device.
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•
Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
10.1.3.2 Stencil Pattern
The recommended drawings for the TAS5822M device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system.
Note
The customer must verify that deviation from the guidance shown in the package addendum, including
the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability
goals.
10.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5822M device will be soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5822M
device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5822M
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the
Section 10.2 section, this interface can benefit from improved thermal performance.
Note
Vias can obstruct heat flow if they are not constructed properly.
More notes on the construction and placement of vias are as follows:
•
•
Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
•
The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding
planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing should be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
•
•
Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the Section 10.2 section.
Ensure that vias do not cut off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias that are farthest from the TAS5822M device to open up the current path
to and from the device.
10.1.3.2.2 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the
thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to
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manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste
to out gas during the assembly process and reduce the risk of solder bridging under the device. This structure is
called an aperture array, and is shown in the Section 10.2 section. It is important that the total area of the
aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the
thermal pad itself.
10.2 Layout Example
Top Layer 3D layout
Bot Layer 3D layout
Figure 10-1. 2.0 (Stereo BTL) 3-D View
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11 Device and Documentation Support
11.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.2 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5822MDCPR
ACTIVE
HTSSOP
DCP
38
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TAS5822M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5822MDCPR
TAS5822MDCPR
HTSSOP DCP
HTSSOP DCP
38
38
2000
2000
330.0
330.0
16.4
16.4
6.9
6.9
10.2
10.2
1.8
1.8
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TAS5822MDCPR
TAS5822MDCPR
HTSSOP
HTSSOP
DCP
DCP
38
38
2000
2000
367.0
350.0
367.0
350.0
38.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DCP 38
4.4 x 9.7, 0.22 mm pitch
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/A
www.ti.com
PACKAGE OUTLINE
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9
9.8
9.6
NOTE 3
19
20
0.27
0.17
0.08
38X
4.5
4.3
B
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
SYMM
38X (1.5)
38X (0.3)
SEE DETAILS
38
1
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
(4.7)
SYMM
39
BASED ON
0.125 THICK
STENCIL
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
0.125
0.15
0.175
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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