TAS5825MRHBR [TI]
具有 192kHz 架构的 38W 立体声、65W 单声道、4.5V 至 26V、数字输入 D 类智能音频放大器 | RHB | 32 | -25 to 85;
| 型号： | TAS5825MRHBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 192kHz 架构的 38W 立体声、65W 单声道、4.5V 至 26V、数字输入 D 类智能音频放大器 | RHB | 32 | -25 to 85 放大器 音频放大器 |
| 文件： | 总108页 (文件大小：3374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5825M
ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
TAS5825M 具有192kHz 扩展音频处理能力的4.5V 至26.4V、38W 立体声、无电
感器、数字输入、闭环D 类音频放大器
1 特性
2 应用
• 灵活的音频I/O：
• 智能扬声器（带语音助理）
• 无线、蓝牙扬声器
• DTV、HDTV、UHD 和多功能监控器
• 条形音箱和低音炮、笔记本电脑、PC 扬声器
– 支持32kHz、44.1kHz、48kHz、88.2kHz、
96kHz 和192kHz 采样速率
– I2S、LJ、RJ 或TDM
– 用于音频监控、子通道或回声消除的SDOUT
– 支持三线制数字音频接口（无需MCLK）
• 高效D 类运行模式
3 说明
TAS5825M 是一款立体声、高性能闭环 D 类放大器，
具有集成的音频处理器，支持高达192kHz 的频率。
– 电源效率高于90%，RDS(on) 为90mΩ
– 低静态电流，PVDD=12V 时小于20mA
• 支持多路输出配置
强大的音频 DSP 内核支持多种先进的音频处理流程，
例如 2×15 BQ、3 频带 DRC、全频带 AGL（自动增益
限制器）、智能放大器算法（过热和偏移保护）、低音
增强、定位器、THD 管理器、PVDD 跟踪和热折返。
TAS5825M 具有 48kHz 或 96kHz 架构，集成的 SRC
（采样率转换器）可检测到输入采样率并自动将输入采
样转换为DSP 目标采样率，从而避免音频伪影。
– 1 × 53W，1.0 模式（4Ω，22V，THD+N=1%）
– 1 × 65W，1.0 模式（4Ω，22V，
THD+N=10%）
– 2 × 30W，2.0 模式（8Ω，24V，THD+N=1%）
– 2 × 38W，2.0 模式（8Ω，24V，
THD+N=10%）
器件信息
封装(1)
• 优异的音频性能：
封装尺寸（标称值）
器件型号
TAS5825M
– 1W、1kHz、PVDD = 12V 的条件下，THD + N
≤0.03%
VQFN (32) RHB
5.00mm × 5.00mm
– SNR ≥110dB（A 加权），ICN ≤35 µVRMS
• 灵活处理特性
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Speaker
Channel
Speaker
Channel
– 3 频带高级DRC + AGL，2 × 15 BQ，
– 声场定位器(SFS)、电平计
– 96kHz、192kHz 处理器采样
– 动态EQ、低音增强和扬声器过热/偏移保护
• 灵活的电源配置
L
R
– PVDD：4.5V 至26.4V
– DVDD 和I/O：1.8V 或3.3V
• 出色的集成式自保护功能：
– 过流错误(OCE)
– 逐周期电流限制
– 过热警告(OTW)
– 过热错误(OTE)
– 欠压和过压锁定(UVLO/OVLO)
• 可轻松进行系统集成
– I2C 软件控制
Digital
Audio
Source
System
Processor
– 减小了解决方案尺寸
• 小型5 x 5mm 封装
• 与开环器件相比，所需的无源器件更少
• 大多数应用都不需要体积较大的电解电容器
或大型电感器
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEH7
TAS5825M
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
Table of Contents
9.3 Feature Description...................................................28
9.4 Device Functional Modes..........................................34
9.5 Programming and Control.........................................39
9.6 Register Maps...........................................................44
10 Application and Implementation................................84
10.1 Application Information........................................... 84
10.2 Typical Applications................................................ 86
10.3 Power Supply Recommendations...........................92
10.4 Layout..................................................................... 93
11 Device and Documentation Support..........................98
11.1 Device Support........................................................98
11.2 Receiving Notification of Documentation Updates..98
11.3 支持资源..................................................................98
11.4 Trademarks............................................................. 99
11.5 静电放电警告...........................................................99
11.6 术语表..................................................................... 99
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements................................................10
7.7 Typical Characteristics.............................................. 11
8 Parameter Measurement Information..........................26
9 Detailed Description......................................................27
9.1 Overview...................................................................27
9.2 Functional Block Diagram.........................................27
Information.................................................................... 99
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision G (July 2020) to Revision H (January 2023)
Page
• 将提到SPI 的旧术语的所有实例更改为控制器和外设........................................................................................ 1
• 将提到SPI 的旧术语的所有实例更改为POCI 和PICO......................................................................................1
• Changed figures in Typical Characteristics section...........................................................................................11
Changes from Revision F (October 2019) to Revision G (July 2020)
Page
• Changed capacitor values from 0.22 µF to 0.47 µF in the Bootstrap Capacitors section ................................85
Changes from Revision E (October 2019) to Revision F (November 2019)
Page
• 设置了首页格式，从而将特性和应用编排为一列.............................................................................................. 1
Changes from Revision D (December 2018) to Revision E (October 2019)
Page
• Added section: Class D Loop Bandwidth and Switching Frequency Setting ...................................................33
• Added NOTE to the Overcurrent Limit (Cycle-By-Cycle) section..................................................................... 43
• Added register: SAP_CTRL3 Register (Offset = 35h) [reset = 0x11] ...............................................................44
• Changed capacitor values of C6, C9, C10, and C13 from 0.22 µF to 0.47 µF in 图10-1 ............................... 86
Changes from Revision C (September 2018) to Revision D (December 2018)
Page
• Added the Thermal Foldback section............................................................................................................... 35
• Added 图9-14 ..................................................................................................................................................42
• Added 图9-15 ..................................................................................................................................................43
• Changed the Inductor Selections section......................................................................................................... 84
Changes from Revision B (August 2018) to Revision C (September 2018)
Page
• Deleted 001: 260K from 表9-9 ........................................................................................................................44
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Changes from Revision A (June 2018) to Revision B (August 2018)
Page
• 将器件状态从预告信息更改为量产数据.............................................................................................................1
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5 Device Comparison Table
DEVICE NAME
TAS5825M
RDS(on)
90 mΩ
180 mΩ
DSP Audio Process Flows
Flexible Audio Process Flows
ROM Fixed Process Flows
TAS5805M
6 Pin Configuration and Functions
BST_A+
OUT_A+
PVDD
1
2
3
4
5
6
7
8
24
BST_B+
OUT_B+
PVDD
PVDD
AGND
AVDD
GVDD
PDN
23
22
21
20
19
18
17
PVDD
Thermal
Pad
DGND
DVDD
VR_DIG
ADR
Not to scale
图6-1. RHB Package 32-Pin VQFN
表6-1. Pin Functions Table
PIN
TYPE(1)
DESCRIPTION
NAME
DGND
DVDD
VR_DIG
ADR
NO.
5
P
P
Digital ground
3.3-V or 1.8-V digital power supply
6
7
P
Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
8
AI
A table of resistor value (Pull down to GND) decides device I2C address. See 表9-5.
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x61h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
GPIO0
GPIO1
GPIO2
9
DI/O
DI/O
DI/O
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x62h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
10
11
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x63h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this
corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync
boundary.
LRCLK
SCLK(2)
12
13
DI
DI
Bit clock for the digital signal that is active on the input data line of the serial data port. Sometimes, this pin also be
written as "bit clock (BCLK)"
SDIN
SDA
SCL
PDN
14
15
16
17
DI
DI/O
DI
Data line to the serial data port
I2C serial control data interface input/output
I2C serial control clock input
DI
Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
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表6-1. Pin Functions Table (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
18
19
20
3
GVDD
P
P
P
P
P
P
P
P
P
P
P
O
Gate drive internal regulator output. This pin must not be used to drive external devices
Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
Analog ground
AVDD
AGND
4
PVDD
PGND
PVDD voltage input
21
22
25
26
31
32
23
Ground reference for power device circuitry. Connect this pin to system ground.
Positive pin for differential speaker amplifier output B
OUT_B+
BST_B+
OUT_B-
BST_B-
Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_B+
24
27
28
P
O
P
Negative pin for differential speaker amplifier output B
Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_B-
Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_A-
BST_A-
OUT_A-
BST_A+
29
30
1
P
O
P
Negative pin for differential speaker amplifier output A
Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_A+
OUT_A+
2
O
P
Positive pin for differential speaker amplifier output A
Connect to the system Ground
PowerPAD™
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =
Power, G = Ground (0 V)
(2) Typically written "bit clock (BCLK)" in some audio codecs.
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7 Specifications
7.1 Absolute Maximum Ratings
Free-air room temperature 25°C (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.5
–0.3
–25
–40
MAX
UNIT
V
DVDD
PVDD
VI(DigIn)
VI(SPK_OUTxx)
TA
Low-voltage digital supply
PVDD supply
3.9
30
V
DVDD referenced digital inputs(2)
Voltage at speaker output pins
Ambient operating temperature,
Storage temperature
VDVDD + 0.5
V
32
85
V
°C
°C
Tstg
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) DVDD referenced digital pins include: ADR, GPIO0, GPIO1,GPIO2, LRCLK, SCLK, SDIN,,SCL, SDA, PDN
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.62
4.5
3.2
1.6
1
NOM
MAX
3.63
26.4
UNIT
DVDD
V(POWER)
Power supply inputs
V
PVDD
BTL Mode
PBTL Mode
4
2
Ω
Ω
RSPK
LOUT
Minimum speaker load
Minimum inductor value in LC filter under short-circuit condition
4.7
µH
7.4 Thermal Information
TAS5825M
VQFN (RHB)
32 PINS
THERMAL METRIC(1)
UNIT
JEDEC
STANDARD
2-LAYER PCB
JEDEC
STANDARD
4-LAYER PCB
TAS5825MEVM-4
4-LAYER PCB
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
N/A
30.0
24.1
19.1
9.9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
N/A
N/A
N/A
N/A
N/A
19.1
9.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
0.9
ψJT
10.5
N/A
8.8
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL I/O
Input logic high current level
for DVDD referenced digital
input pins
|IIH|
VIN(DigIn) = VDVDD
10
µA
µA
Input logic low current level for
DVDD referenced digital input VIN(DigIn) = 0 V
pins
|IIL|
–10
Input logic high threshold for
DVDD referenced digital inputs
VIH(Digin)
VIL(Digin)
70%
80%
VDVDD
VDVDD
Input logic low threshold for
DVDD referenced digital inputs
30%
20%
400
VOH(Digin)
VOL(Digin)
I2C CONTROL PORT
Output logic high voltage level IOH = 4 mA
VDVDD
VDVDD
Output logic low voltage level
IOH = –4 mA
Allowable load capacitance for
CL(I2C)
pF
each I2C Line
fSCL(fast)
fSCL(slow)
SERIAL AUDIO PORT
Support SCL frequency
No wait states, fast mode
No wait states, slow mode
400
100
kHz
kHz
Support SCL frequency
Required LRCK/FS to SCLK
rising edge delay
tDLY
5
ns
DSCLK
fS
fSCLK
fSCLK
Allowable SCLK duty cycle
Supported input sample rates
Supported SCLK frequencies
SCLK frequency
40%
32
60%
192
kHz
fS
32
64
24.576
MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
toff
Turn-off Time
Excluding volume ramp
10
ms
Quiescent supply current of
DVDD
PDN=2V,DVDD=3.3V, Play mode, General Audio
Process flow with full DSP running
ICC
25.5
17.5
mA
Quiescent supply current of
DVDD
PDN = 2 V,DVDD = 3.3 V, Play mode, Smart Amp
Process Flows based on 48 kHz or 96 kHz
ICC
mA
mA
PDN = 2 V, DVDD = 3.3 V, Play mode, Audio
Process flow with Housekeeping mode, 192 kHz
sample rate
Quiescent supply current of
DVDD
ICC
24.8
19.3
PDN = 2 V, DVDD = 3.3 V, Play mode, Audio
Process flow with Housekeeping mode, 96 kHz
sample rate
Quiescent supply current of
DVDD
ICC
mA
Quiescent supply current of
DVDD
PDN=2V,DVDD=3.3V, Play mode, Audio Process
flow with Housekeeping mode, 48 kHz sample rate
ICC
ICC
ICC
ICC
14.8
0.87
0.82
7.4
mA
mA
mA
µA
Quiescent supply current of
DVDD
PDN = 2 V, DVDD = 3.3 V, Sleep mode
Quiescent supply current of
DVDD
PDN = 2 V, DVDD = 3.3 V, Deep Sleep mode
PDN = 0.8 V, DVDD = 3.3 V, Shutdown mode
Quiescent supply current of
DVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 10
uH + 0.68 uF, Fsw = 384 kHz, Hybrid Modulation,
Play Mode
Quiescent supply current of
PVDD
ICC
29.5
20.5
mA
mA
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 22
uH + 0.68 uF, Fsw = 384 kHz, Hybrid Modulation,
Play Mode
Quiescent supply current of
PVDD
ICC
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 10
uH + 0.68 uF, Fsw = 384 kHz, Output Hiz Mode
ICC
ICC
10.7
7.26
mA
mA
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 10
uH + 0.68 uF, Fsw = 384 kHz, Sleep Mode
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7.5 Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 10
uH + 0.68 uF, Fsw = 384 kHz, Deep Sleep Mode
ICC
ICC
12.01
µA
Quiescent supply current of
PVDD
PDN = 0.8 V, PVDD = 13.5 V, No Load, LC filter =
10 uH + 0.68 uF,Fsw = 384 kHz, Shutdown Mode
7.8
µA
V
Value represents the peak voltage disregarding
clipping due to lower PVDD).
Measured at 0 dB input (1FS)
AV(SPK_AMP)
Programmable Gain
Amplifier gain error
4.87
29.5
Gain = 29.5 Vp
0.5
384
768
dB
ΔAV(SPK_AMP)
kHz
kHz
Switching frequency of the
speaker amplifier
fSPK_AMP
Drain-to-source on resistance
of the individual output
MOSFETs
RDS(on)
FET + Metallization.
90
mΩ
Over-Current Error Threshold Any short to supply, ground, or other channels
7.5
6.5
A
A
OCETHRES
Over-Current cycle-by-cycle
limit
PVDD over voltage error
threshold
OVETHRES(PVDD
UVETHRES(PVDD
OTETHRES
28
4.2
V
PVDD under voltage error
threshold
V
Over temperature error
threshold
160
10
°C
°C
°C
°C
°C
°C
Over temperature error
hysteresis
OTEHystersis
OTWTHRES
Over temperature warning
Read by register 0x73 bit0
level 1
112
122
134
146
Over temperature warning
Read by register 0x73 bit1
level 2
OTWTHRES
Over temperature warning
Read by register 0x73 bit2
level 3
OTWTHRES
Over temperature warning
Read by register 0x73 bit3
level 4
OTWTHRES
SPEAKER AMPLIFIER (STEREO BTL)
Measured differentially with zero input data,
programmable gain configured with 29.5 Vp gain,
VPVDD = 16 V
|VOS
|
Amplifier offset voltage
7.5
mV
–7.5
VPVDD = 14.4 V, SPK_GAIN = 29.5 Vp, RSPK = 6
Ω, f = 1 kHz THD+N = 10%
17.8
14.5
W
W
VPVDD = 14.4 V, SPK_GAIN = 29.5 Vp, RSPK = 6
Ω, f = 1 kHz THD+N = 1%
PO(SPK)
Output Power (Per Channel)
VPVDD = 24 V, SPK_GAIN = 29.5 Vp, RSPK = 8 Ω, f
= 1 kHz THD+N = 10% (Instantaneous Output
Power)
38
W
W
VPVDD = 24 V, SPK_GAIN = 29.5 Vp, RSPK = 8 Ω, f
= 1 kHz THD+N = 1% (Continuous Output Power)
30
Total harmonic distortion and
VPVDD = 12 V, SPK_GAIN = 20.9 Vp, LC-filter
0.03%
noise
THD+NSPK
(PO = 1 W, f = 1 kHz, RSPK = 6
VPVDD = 24 V, SPK_GAIN = 29.5 Vp, LC-filter
0.03%
Ω)
VPVDD = 12 V, LC-filter, Load = 6 Ω, Hybrid
Modulation
ICN(SPK)
ICN(SPK)
ICN(SPK)
32
40
35
VPVDD = 12 V, LC-filter, Load = 6 Ω, BD Modulation
Idle channel noise (A-
weighted, AES17)
µVrms
VPVDD = 24 V, LC-filter ,Load = 6 Ω, Hybrid
Modulation
VPVDD = 24 V, LC-filter ,Load = 6 Ω, BD
Modulation
ICN(SPK)
DR
45
A-Weighted, -60 dBFS method. PVDD = 24 V,
SPK_GAIN = 29.5 Vp
Dynamic range
111
dB
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.5 Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A-Weighted, referenced to 1% THD+N Output
Level, PVDD = 24 V
111
dB
SNR
Signal-to-noise ratio
A-Weighted, referenced to 1% THD+N Output
Level, PVDD = 14.4 V
108
72
dB
dB
Injected Noise = 1 kHz, 1 Vrms, PVDD = 14.4 V,
input audio signal = digital zero
KSVR
Power supply rejection ratio
Crosstalk (worst case between
left-to-right and right-to-left
coupling)
CrosstalkSPK
f = 1 kHz
-100
dB
SPEAKER AMPLIFIER (MONO PBTL)
VPVDD = 19 V, SPK_GAIN = 29.5 Vp, RSPK = 3 Ω, f
= 1 kHz, THD+N = 1%
50
60
W
W
W
W
VPVDD = 19 V, SPK_GAIN = 29.5 Vp, RSPK = 3 Ω, f
= 1 kHz, THD+N = 10%
PO(SPK)
Output Power
VPVDD = 22 V, SPK_GAIN = 29.5 Vp, RSPK = 4 Ω, f
= 1 kHz, THD+N = 1%
53
VPVDD = 22 V, SPK_GAIN = 29.5 Vp, RSPK = 4 Ω, f
= 1 kHz, THD+N = 10%
65
VPVDD = 19 V, SPK_GAIN = 20.9 Vp, LC-filter RSPK
= 3 Ω)
0.03%
Total harmonic distortion and
noise
(PO = 1 W, f = 1 kHz
THD+NSPK
DR
VPVDD = 24 V, SPK_GAIN = 29.5 Vp, LC-filter RSPK
= 4 Ω)
0.03%
109
Dynamic range
A-Weighted, -60 dBFS method, PVDD=19V
dB
dB
A-Weighted, referenced to 1% THD+N Output
Level, PVDD = 19 V
109
SNR
Signal-to-noise ratio
A-Weighted, referenced to 1% THD+N Output
Level, PVDD = 24 V
111
dB
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UNIT
ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.6 Timing Requirements
MIN
NOM
MAX
Serial Audio Port Timing –Target Mode
fSCLK
tSCLK
tSCLKL
tSCLKH
tSL
SCLK frequency
1.024
40
16
16
8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
µs
µs
µs
µs
µs
ns
ns
ns
SCLK period
SCLK pulse width, low
SCLK pulse width, high
SCLK rising to LRCK/FS edge
LRCK/FS Edge to SCLK rising edge
Data setup time, before SCLK rising edge
Data hold time, after SCLK rising edge
Data delay time from SCLK falling edge
tLS
8
tSU
8
tDH
8
tDFS
15
I2C Bus Timing –Standard
fSCL
SCL clock frequency
100
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
4.7
tLOW
tHI
4.7
High period of the SCL clock
Setup time for (repeated) START condition
Hold time for (repeated) START condition
Data setup time
4
tRS-SU
tS-HD
tD-SU
tD-HD
tSCL-R
4.7
4
250
Data hold time
0
900
Rise time of SCL signal
20 + 0.1CB
1000
Rise time of SCL signal after a repeated START condition and
after an acknowledge bit
tSCL-R1
20 + 0.1CB
1000
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
4
1000
1000
1000
ns
ns
ns
µs
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
I2C Bus Timing –Fast
fSCL
SCL clock frequency
400
kHz
µs
µs
ns
ns
ns
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for (repeated)START condition
Hold time for (repeated)START condition
Data setup time
1.3
tLOW
tHI
1.3
600
tRS-SU
tRS-HD
tD-SU
tD-HD
tSCL-R
600
600
100
Data hold time
0
900
300
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and
after an acknowledge bit
tSCL-R1
20 + 0.1CB
300
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
tSP
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
600
300
300
300
ns
ns
ns
ns
ns
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Pulse width of spike suppressed
50
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7 Typical Characteristics
7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
Free-air room temperature 25°C (unless otherwise noted). Measurements were made using TAS5825MEVM board and
Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio
frequency set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter used was 10 μH / 0.68 μF, unless otherwise
noted.
10
5
10
5
PVcc=7.4V
TA=25èC
RL=8W
PVcc=7.4V
TA=25èC
RL=6W
P O=1W
PO =2.5W
P O=1W
PO =2.5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D30002
D03021
Hybrid Modulation
PO = 1W, 2.5W
BTL Mode
Hybrid Modulation
PO = 1W, 2.5W
BTL Mode
FSW = 384 kHz
FSW = 384 kHz
Load = 8 Ω
Load = Ω
图7-1. THD+N vs Frequency-BTL
图7-2. THD+N vs Frequency-BTL
10
5
10
5
PVcc=7.4V
TA=25èC
RL=4W
PVcc=12V
TA=25èC
RL=8W
P O=1W
PO =2.5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D3002
D03023
Hybrid Modulation
PO = 1W, 2.5W
BTL Mode
Hybrid Modulation PO = 1W,2.5W,5W
FSW = 384 kHz
FSW = 384 kHz
BTL Mode
Load = 4 Ω
Load = 8 Ω
图7-3. THD+N vs Frequency-BTL
图7-4. THD+N vs Frequency-BTL
10
5
10
5
PVcc=12V
TA=25èC
RL=6W
P O=1W
PO =2.5W
PO=5W
PVcc=12V
TA=25èC
RL=4W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
D30042
20
100
1k
Frequency (Hz)
10k 20k
D03025
Hybrid Modulation PO = 1 W,2.5W,5W
FSW = 384 kHz
BTL Mode
Load = 6 Ω
Hybrid Modulation
PO = 1W
FSW = 384 kHz
BTL Mode
Load = 4 Ω
图7-5. THD+N vs Frequency-BTL
图7-6. THD+N vs Frequency-BTL
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7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted). Measurements were made using TAS5825MEVM board and
Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio
frequency set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter used was 10 μH / 0.68 μF, unless otherwise
noted.
10
5
10
5
PVcc=18V
TA=25èC
RL=8W
PVcc=18V
TA=25èC
RL=6W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D30062
D03027
Hybrid Modulation PO = 1W,2.5W,5W
BTL Mode
Hybrid Modulation PO = 1W,2.5W,5W
BTL Mode
FSW = 384 kHz
图7-7. THD+N vs Frequency-BTL
FSW = 384 kHz
图7-8. THD+N vs Frequency-BTL
Load = 8 Ω
Load = 6 Ω
10
5
10
5
PVcc=18V
TA=25èC
RL=4W
PVcc=24V
TA=25èC
RL=8W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D30082
D03029
Hybrid Modulation PO = 1W,2.5W,5W
BTL Mode
Hybrid Modulation PO = 1W,2.5W,5W
BTL Mode
FSW = 384 kHz
图7-9. THD+N vs Frequency-BTL
FSW = 384 kHz
图7-10. THD+N vs Frequency-BTL
Load = 4 Ω
Load = 8 Ω
10
5
10
5
PVcc=24V
TA=25èC
RL=6W
PVcc=24V
TA=25èC
RL=4W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D301002
D030121
Hybrid Modulation PO = 1W,2.5W,5W
Hybrid Modulation PO = 1W,2.5W,5W
BTL Mode
FSW = 384 kHz
BTL Mode
FSW = 384 kHz
图7-12. THD+N vs Frequency-BTL
Load = 6 Ω
Load = 4 Ω
图7-11. THD+N vs Frequency-BTL
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted). Measurements were made using TAS5825MEVM board and
Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio
frequency set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter used was 10 μH / 0.68 μF, unless otherwise
noted.
10
5
10
5
PVCC=7.4V
TA=25èC
Fin=1kHz
PVCC=12V
TA=25èC
Fin=1kHz
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Load= 4W
Load= 6W
Load= 8W
Load=4W
Load=6W
Load=8W
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
10
0.01
0.1
1
Output Power (W)
10
Output Power (W)
D101017
D010172
Hybrid Modulation
Load = 4 Ω/6 Ω/8
Ω
Fin = 1 kHz
BTL Mode
Hybrid Modulation
Load = 4 Ω/6 Ω/8
Ω
Fin = 1 kHz
BTL Mode
FSW = 384 kHz
FSW = 384 kHz
图7-13. THD+N vs Output Power-BTL
图7-14. THD+N vs Output Power-BTL
10
10
PVCC=18V
TA=25èC
Fin=1kHz
PVCC=24V
TA=25èC
Fin=1kHz
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Load=4W
Load=6W
Load=8W
Load=4W
Load=6W
Load=8W
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D101037
D010174
One channel run Hybrid Modulation
Fin = 1 kHz
BTL Mode
One Channel run Hybrid Modulation
Fin = 1 kHz
BTL Mode
FSW = 384 kHz
FSW = 384 kHz
Load = 4 Ω/6 Ω/8
Load = 4 Ω/6 Ω/8
Ω
Ω
图7-15. THD+N vs Output Power-BTL
图7-16. THD+N vs Output Power-BTL
60
40
20
0
0
-20
Fsw=384kHz, Hybrid Modulation
PVDD=12V, Fsw=384kHz, LC filter=10uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-40
-60
-80
-100
-120
5
10
15 18 20
Supply Voltage (V)
25
20
100
1k
Frequency (Hz)
10k 20k
D01031705
D090310
Hybrid Modulation
PVDD=12V Hybrid Modulation
FSW = 384 kHz
FSW = 384 kHz
BTL Mode
BTL Mode
Load = 6 Ω
Load = 6 Ω
图7-18. Crosstalk
图7-17. Idle Channel Noise vs Supply Voltage
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted). Measurements were made using TAS5825MEVM board and
Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio
frequency set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter used was 10 μH / 0.68 μF, unless otherwise
noted.
0
100
90
80
70
60
50
40
30
20
10
0
PVDD=24V, Fsw=384kHz, LC filter=10uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-40
-60
-80
TA=25èC
RL=4W
BTL Mode
PVDD = 7.4V
PVDD = 12 V
PVDD = 18 V
-100
-120
20
100
1k
Frequency (Hz)
10k 20k
0
10
20
30 40
Output Power (W)
50
60
70
D09031
D012146
PVDD=24V Hybrid Modulation
FSW = 384 kHz
Hybrid Modulation
BTL Mode
FSW = 384 kHz
BTL Mode
Load = 6 Ω
图7-19. Crosstalk
Load = 4 Ω
图7-20. Efficiency vs Output Power
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PVDD = 7.4V
PVDD = 7.4V
PVDD = 12 V
PVDD = 18 V
PVDD = 24V
TA=25èC
RL=6W
BTL Mode
TA=25èC
RL=8W
BTL Mode
PVDD = 12 V
PVDD = 18 V
PVDD = 24 V
0
10
20
30
40
Output Power (W)
50
60
70
80
90 100
0
10
20
30
40
Output Power (W)
50
60
70
80
90 100
TDA01S21457
D012148
Hybrid Modulation
Hybrid Modulation
FSW = 384 kHz
BTL Mode
FSW = 384 kHz
BTL Mode
Load = 6 Ω
Load = 8 Ω
图7-21. Efficiency vs Output Power
图7-22. Efficiency vs Output Power
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7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter used was 10 μH / 0.68 μF （Pre-Filter PBTL, the
merging of the two output channels in this device can be done before the inductor portion of the output filter, see connect
method in 节10.2.5）, unless otherwise noted.
10
5
10
5
PVcc=12V
TA=25èC
RL=4W
PVcc=12V
TA=25èC
RL=3W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D40002
D04021
Hybrid Modulation PO = 1W,2.5W,5W
PBTL Mode
Hybrid Modulation PO = 1W,2.5W,5W
PBTL Mode
FSW = 384 kHz
图7-23. THD+N vs Frequency-PBTL
FSW = 384 kHz
图7-24. THD+N vs Frequency-PBTL
Load = 4 Ω
Load = 3 Ω
10
5
10
5
PVcc=18V
TA=25èC
RL=4W
PVcc=18V
TA=25èC
RL=3W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D4002
D04023
Hybrid Modulation PO = 1W,2.5W,5W
PBTL Mode
Hybrid Modulation PO = 1W, 2.5W, 5W
PBTL Mode
FSW = 384 kHz
图7-25. THD+N vs Frequency-PBTL
FSW = 384 kHz
图7-26. THD+N vs Frequency-PBTL
Load = 4 Ω
Load = 3 Ω
10
5
10
5
PVcc=24V
TA=25èC
RL=4W
PVcc=24V
TA=25èC
RL=3W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D40042
D04025
Hybrid Modulation PO = 1W,2.5W,5W
PBTL Mode
Hybrid Modulation PO = 1W,2.5W,5W
PBTL Mode
FSW = 384 kHz
图7-27. THD+N vs Frequency-PBTL
FSW = 384 kHz
图7-28. THD+N vs Frequency-PBTL
Load = 4 Ω
Load = 3 Ω
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter used was 10 μH / 0.68 μF （Pre-Filter PBTL, the
merging of the two output channels in this device can be done before the inductor portion of the output filter, see connect
method in 节10.2.5）, unless otherwise noted.
10
5
10
5
PVCC=12V
TA=25èC
PBTL Mode
PVCC=18V
TA=25èC
PBTL Mode
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
Load=4W
Load=3W
Load=4W
Load=3W
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D40067
D0407
Hybrid Modulation
Hybrid Modulation
FSW = 384 kHz
PBTL Mode
FSW = 384 kHz
PBTL Mode
Load = 4 Ω, 3 Ω
Load = 4 Ω, 3 Ω
图7-29. THD+N vs Output Power-PBTL
图7-30. THD+N vs Output Power-PBTL
10
100
PVCC=24V
TA=25èC
PBTL Mode
5
90
80
70
60
50
40
30
20
10
0
2
1
0.5
0.2
0.1
0.05
0.02
0.01
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
0.005
TA=25èC
RL=4W
Load=4W
Load=3W
0.002
0.001
0.1
1
10
20
100
0
10
20
30
40
Output Power (W)
50
60
70
80
Output Power (W)
D40087
D01240
Hybrid Modulation
Hybrid Modulation
FSW = 384 kHz
PBTL Mode
FSW = 384 kHz
PBTL Mode
Load = 4 Ω, 3 Ω
Load = 4- Ω
图7-31. THD+N vs Output Power-PBTL
图7-32. Efficiency vs Output Power
100
60
40
20
0
Fsw=384kHz, Hybrid Modulation, PBTL Mode
90
80
70
60
50
40
30
20
10
0
TA=25èC
RL=3W
PBTL Mode
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
0
10
20
30
40
50
60
Output Power (W)
70
80
90 100
5
10
15
Supply Voltage (V)
18
20
D101294
D01032701
Hybrid Modulation
Hybrid Modulation
FSW = 384 kHz
PBTL Mode
FSW = 384 kHz
PBTL Mode
Load = 3 Ω
Load = 6 Ω
图7-33. Efficiency vs Output Power
图7-34. Idle Channel Noise vs Supply Voltage
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 384 kHz, the LC filter used was 10 μH / 0.68 μF （Pre-Filter PBTL, the
merging of the two output channels in this device can be done before the inductor portion of the output filter, see connect
method in 节10.2.5）, unless otherwise noted.
100
THD+N=1%, R L=4W
THD+N=10%, R L=4W
90
THD+N=1%, R L=3W
THD+N=10%, R L=3W
80
70
60
50
40
30
20
10
0
4
6
8
10
12
14
16
Supply Voltage (V)
18
20
22
24
D122
Hybrid Modulation
FSW = 384 kHz
PBTL Mode
Load = 3 Ω, 4 Ω
图7-35. Output Power vs Supply Voltage
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7μH / 0.68 μF, unless otherwise noted.
10
5
10
5
PVcc=5V
TA=25èC
BTL Mode
Pout=1W
PVcc=7.4V
TA=25èC
RL=4W
Load=2W
Load=4W
P O=1W
PO =2.5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D20002
D02021
BD Modulation
PO = 1W
BD Modulation
PO = 1W, 2.5W
BTL Mode
FSW = 768 kHz
BTL Mode
FSW = 768 kHz
Load = 2 Ω, 4 Ω
Load = 4 Ω
图7-36. THD+N vs Frequency-BTL
图7-37. THD+N vs Frequency-BTL
10
5
10
5
PVcc=7.4V
TA=25èC
RL=6W
PVcc=7.4V
TA=25èC
RL=8W
P O=1W
PO =2.5W
P O=1W
PO =2.5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D2002
D020432
BD Modulation
PO = 1W, 2.5W
BTL Mode
BD Modulation
PO = 1W, 2.5W
BTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 6 Ω
Load = 8 Ω
图7-38. THD+N vs Frequency-BTL
图7-39. THD+N vs Frequency-BTL
10
5
10
5
PVcc=12V
TA=25èC
RL=4W
PVcc=12V
TA=25èC
RL=6W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D20042
D02025
BD Modulation
PO = 1W,2.5W,5W
BTL Mode
BD Modulation
PO = 1W,2.5W,5W
BTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 4 Ω
Load = 6 Ω
图7-40. THD+N vs Frequency-BTL
图7-41. THD+N vs Frequency-BTL
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7μH / 0.68 μF, unless otherwise noted.
10
5
10
5
PVcc=12V
TA=25èC
RL=8W
PVcc=18V
TA=25èC
RL=4W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D20062
D02027
BD Modulation
PO = 1W,2.5W,5W
BTL Mode
BD Modulation
PO = 1W,2.5W,5W
BTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 8 Ω
Load = 4 Ω
图7-42. THD+N vs Frequency-BTL
图7-43. THD+N vs Frequency-BTL
10
5
10
5
PVcc=18V
TA=25èC
RL=6W
PVcc=18V
TA=25èC
RL=8W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D20082
D02029
BD Modulation
PO = 1W,2.5W 5W
BTL Mode
BD Modulation
PO = 1W,2.5W,5W
BTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 6 Ω
Load = 8 Ω
图7-44. THD+N vs Frequency-BTL
图7-45. THD+N vs Frequency-BTL
10
5
10
5
PVcc=24V
A=25èC
RL=6W
PVcc=24V
TA=25èC
RL=4W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
T
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D201002
D020121
BD Modulation
PO = 1W,2.5W,5W
BTL Mode
BD Modulation
PO = 1W,2.5W,5W
BTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 4 Ω
Load = 6 Ω
图7-46. THD+N vs Frequency-BTL
图7-47. THD+N vs Frequency-BTL
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7μH / 0.68 μF, unless otherwise noted.
10
5
10
5
PVcc=24V
TA=25èC
RL=8W
PVCC=7.4V
TA=25èC
BTL Mode
P O=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Load=4W
0.005
0.005
Load=6W
Load=8W
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
0.01
0.1
1
10
Output Power (W)
D20102
D020273
BD Modulation
PO = 1W,2.5W,5W
BTL Mode
BD Modulation
Load = 4 Ω, 6 Ω, 8
Ω
FSW = 768 kHz
FSW = 768 kHz
BTL Mode
Load = 8 Ω
图7-48. THD+N vs Frequency-BTL
图7-49. THD+N vs Output Power-BTL
10
5
10
PVCC=12V
TA=25èC
BTL Mode
PVCC=18V
TA=25èC
BTL Mode
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Load=4W
Load=6W
Load=8W
Load=4W
Load=6W
Load=8W
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10
0.01
0.1
1
Output Power (W)
10 20
D202027
D020271
BD Modulation
BD Modulation
Two Channel Run
BTL Mode
FSW = 768 kHz
BTL Mode
FSW = 768 kHz
Load = 4 Ω, 6 Ω, 8
Load = 4 Ω, 6 Ω, 8
Ω
Ω
图7-50. THD+N vs Output Power-BTL
图7-51. THD+N vs Output Power-BTL
10
10
PVCC=18V
TA=25èC
BTL Mode, 1CH Run
PVCC=24V
TA=25èC
BTL Mode
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Load=4W
Load=6W
Load=8W
0.005
0.005
Load=6W
Load=4W
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D021304017
D020373
BD Modulation
1 Channel Run
BTL Mode
BD Modulation
2 Channel Run
BTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 4 Ω, 6 Ω, 8
Load = 4 Ω, 6 Ω
Ω
图7-52. THD+N vs Output Power-BTL
图7-53. THD+N vs Output Power-BTL
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7μH / 0.68 μF, unless otherwise noted.
10
5
45
40
35
30
25
20
15
10
5
PVCC=24V
TA=25èC
BTL Mode
THD+N=1%, R L=4W
THD+N=10%, R L=4W
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
BTL Mode
TA=25èC
Load=6W
Load=4W
0.002
0.001
0
0.01
0.1
1
Output Power (W)
10 20
4
6
8
10 12
Supply Voltage (V)
14
16
18 19
D014
D023274
D203027
BD Modulation
1 Channel Run
BTL Mode
Dashed lines represent thermally limited region.
BD Modulation
FSW = 768 kHz
Load = 4 Ω, 6 Ω
FSW = 768 kHz
BTL Mode
Load = 4 Ω
图7-54. THD+N vs Output Power-BTL
图7-55. Output Power vs Supply Voltage
50
45
40
35
30
25
20
15
10
5
45
THD+N=1%, R L=6W
THD+N=10%, R L=6W
THD+N=1%, R L=8W
THD+N=10%, R L=8W
40
35
30
25
20
15
10
5
BTL Mode
TA=25èC
BTL Mode
TA=25èC
0
0
4
6
8
10
12
14
16
Supply Voltage (V)
18
20
22
24
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
D014
D2030257
D014
D023276
Dashed lines represent thermally limited region.
BD Modulation
Dashed lines represent thermally limited region.
BD Modulation
FSW = 768 kHz
BTL Mode
FSW = 768 kHz
BTL Mode
Load = 6 Ω
Load = 8 Ω
图7-56. Output Power vs Supply Voltage
图7-57. Output Power vs Supply Voltage
72
0
PVDD=12V, Fsw=768kHz, LC filter=4.7uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
48
24
0
-40
-60
-80
-100
A Channel
B Channel
-120
20
5
10
15 18 20
Supply Voltage (V)
25
100
1k
Frequency (Hz)
10k 20k
D0203270
D090312
BD Modulation
PVDD=12V
BD Modulation
FSW = 768 kHz
BTL Mode
FSW = 768 kHz
BTL Mode
Load = 6 Ω
Load = 6 Ω
图7-58. Idle Channel Noise vs Supply Voltage
图7-59. Crosstalk
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7μH / 0.68 μF, unless otherwise noted.
0
100
90
80
70
60
50
40
30
20
10
0
PVDD=24V, Fsw=768kHz, LC filter=4.7uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-40
-60
-80
PVDD = 4.5V
PVDD = 7.4 V
PVDD = 12 V
PVDD = 18V
TA=25èC
RL=4W
BTL Mode
-100
-120
20
100
1k
Frequency (Hz)
10k 20k
0
10
20
Output Power (W)
30
40
D09013
D02248
PVDD=12V
BD Modulation
BD Modulation
FSW = 768 kHz
BTL Mode
FSW = 768 kHz
BTL Mode
Load = 6 Ω
Load = 4 Ω
图7-60. Crosstalk
图7-61. Efficiency vs Output Power
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PVDD = 7.4V
PVDD = 7.4V
PVDD = 12V
PVDD = 18V
PVDD = 24V
TA=25èC
RL=6W
BTL Mode
TA=25èC
RL=8W
BTL Mode
PVDD = 12V
PVDD = 18V
PVDD = 24V
0
10
20
30 40
Output Power (W)
50
60
70
0
10
20
30
Output Power (W)
40
50
60
D20294
D022340
BD Modulation
BD Modulation
FSW = 768 kHz
BTL Mode
FSW = 768 kHz
BTL Mode
Load = 6 Ω
Load = 8 Ω
图7-62. Efficiency vs Output Power
图7-63. Efficiency vs Output Power
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7 μH / 0.68 μF （Pre-Filter PBTL, the
merging of the two output channels in this device can be done before the inductor portion of the output filter, see details in 节
10.2.5）, unless otherwise noted.
10
5
10
5
PVcc=12V
TA=25èC
RL=3W
PVcc=12V
TA=25èC
RL=4W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D203052
D020326
BD Modulation
PO = 1W,2.5W,5W
PBTL Mode
BD Modulation
PO = 1W,2.5W,5W
PBTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 3 Ω
Load = 4 Ω
图7-64. THD+N vs Frequency-PBTL
图7-65. THD+N vs Frequency-PBTL
10
5
10
5
PVcc=18V
TA=25èC
Load=3W
PBTL Mode
PVcc=18V
TA=25èC
RL=4W
P O=1W
PO=2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
PBTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D203072
D020328
BD Modulation
PO = 1W,2.5W,5W
PBTL Mode
BD Modulation
PO = 1W, 2.5W, 5W
PBTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 3 Ω
Load = 4 Ω
图7-66. THD+N vs Frequency-PBTL
图7-67. THD+N vs Frequency-PBTL
10
5
10
5
P O=1W
PO =2.5W
PO=5W
PVcc=24V
TA=25èC
RL=3W
PVcc=24V
TA=25èC
RL=4W
P O=1W
PO =2.5W
PO=5W
2
1
2
1
PBTL Mode
PBTL Mode
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D203092
D020420
BD Modulation
PO = 1W,2.5W,5W
PBTL Mode
BD Modulation
PO = 1W,2.5W,5W
PBTL Mode
FSW = 768 kHz
FSW = 768 kHz
Load = 3 Ω
Load = 4 Ω
图7-68. THD+N vs Frequency-PBTL
图7-69. THD+N vs Frequency-PBTL
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ZHCSIC2H –OCTOBER 2019 –REVISED JANUARY 2023
7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7 μH / 0.68 μF （Pre-Filter PBTL, the
merging of the two output channels in this device can be done before the inductor portion of the output filter, see details in 节
10.2.5）, unless otherwise noted.
10
5
10
5
PVCC=12V
TA=25èC
PBTL Mode
PVCC=18V
TA=25èC
PBTL Mode
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
Load=3W
Load=4W
Load=3W
Load=4W
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10 20
0.01
0.1
1
Output Power (W)
10 20
D204017
D020472
BD Modulation
BD Modulation
FSW = 768 kHz
PBTL Mode
FSW = 768 kHz
PBTL Mode
Load = 3 Ω, 4 Ω
Load = 3 Ω, 4 Ω
图7-70. THD+N vs Output Power-PBTL
图7-71. THD+N vs Output Power-PBTL
10
70
65
60
55
50
45
40
35
30
25
20
15
10
5
PVCC=24V
TA=25èC
PBTL Mode
THD+N=1%, R L=3W
THD+N=10%, R L=3W
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
PBTL Mode
TA=25èC
Load=4W
Load=3W
0.002
0.001
0
0.01
0.1
1
Output Power (W)
10 20
100
4
6
8
10
12
Supply Voltage (V)
14
16
18
20
D014
D023474
D204037
BD Modulation
BD Modulation
FSW = 768 kHz
PBTL Mode
FSW = 768 kHz
PBTL Mode
Load = 3 Ω, 4 Ω
Load = 3 Ω
图7-72. THD+N vs Output Power-PBTL
图7-73. Output Power vs Supply Voltage
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
100
THD+N=1%, R L=4W
THD+N=10%, R L=4W
90
80
70
60
50
40
30
20
10
0
TA=25èC
RL=3W
PBTL Mode
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
PBTL Mode
TA=25èC
0
4
6
8
10
12
Supply Voltage (V)
14
16
18
20
22
24
0
10
20
30
Output Power (W)
40
50
60
D014
D023475
D022446
BD Modulation
BD Modulation
FSW = 768 kHz
PBTL Mode
FSW = 768 kHz
PBTL Mode
Load = 4 Ω
Load = 3 Ω
图7-74. Output Power vs Supply Voltage
图7-75. Efficiency vs Output Power
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7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825MEVM board and Audio
Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency
set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7 μH / 0.68 μF （Pre-Filter PBTL, the
merging of the two output channels in this device can be done before the inductor portion of the output filter, see details in 节
10.2.5）, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
80
60
40
20
0
TA=25èC
RL=4W
PBTL Mode
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
Fsw=768kHz, PBTL Mode
18 20 25
0
10
20 30
Output Power (W)
40
50
5
10
15
Supply Voltage (V)
D204274
D02034780
BD Modulation
BD Modulation
FSW = 768 kHz
PBTL Mode
FSW = 768 kHz
PBTL Mode
Load = 4 Ω
Load =4Ω
图7-76. Efficiency vs Output Power
图7-77. Idle Channel Noise vs Supply Voltage
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8 Parameter Measurement Information
LRCK/FS
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
SCLKL
SCLKH
t
LS
SCLK
(Input)
t
t
SL
SCLK
DATA
(Input)
0.5 × DVDD
0.5 × DVDD
STOP
t
t
DH
SU
t
DFS
DATA
(Output)
图8-1. Serial Audio Port Timing in Target Mode
Repeated
START
START
t
t
t
t
P-SU
t
D-SU
D-HD
SDA-F
SDA-R
t
BUF.
SDA
t
t
t
SP
SCL-R.
RS-HD
t
LOW.
SCL
t
HI.
t
RS-SU
t
t
SCL-F.
S-HD.
图8-2. I2C Communication Port Timing Diagram
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9 Detailed Description
9.1 Overview
The TAS5825M device combines 4 main building blocks into a single cohesive device that maximizes sound
quality, flexibility, and ease of use. The 4 main building blocks are listed as follows:
• A stereo digital to PWM modulator.
• An Audio DSP subsystem.
• A flexible close-loop amplifier capable of operating in stereo or mono, at several different switching
frequencies, and with a variety of output voltages and loads.
• An I2C control port for communication with the device
The device requires only two power supplies for proper operation. A DVDD supply is required to power the low
voltage digital circuitry. Another supply, called PVDD, is required to provide power to the output stage of the
audio amplifier. Two internal LDOs convert PVDD to 5 V for GVDD and AVDD and to 1.5V for DVDD
respectively.
9.2 Functional Block Diagram
4.5-24V
3.3/1.8V
DVDD
VR_DIG
AVDD
PVDD1/2/3/4
LDO 1.5V
LDO 5V
BST_A+
Close Loop Feedback
ADR
IO
OUT_A+
PDN
I2S/TDM
OUT_A-
BST_A-
GPIO0
GPIO1
GPIO2
H Bridge
Audio DSP
Subsystem
&
Digital to PWM
Conversion
Gate Driver
&
OC/DC Protect
SDA
SCL
BST_B-
PDM
OUT_B-
Modulator
SDIN
OUT_B+
BST_B+
LRCLK
SCLK
PLL & OSC
LDO 5V
(PVDD to GVDD)
Close Loop Feedback
GVDD
PGND 1/2/3/4
AGND
DGND
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9.3 Feature Description
9.3.1 Power Supplies
For system design, TAS5825M needs a 3.3-V or 1.8-V supply in addition to the (typical) 12 V or 24 V power-
stage supply. Two internal voltage regulators provide good voltage levels for the gate drive circuitry and internal
circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to filter the
supply. Connecting external circuitry to these regulator outputs can result in reduced performance and damage
to the device. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only a few external capacitors. To provide good electrical
and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent
half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x). The gate drive voltages
(GVDD) are derived from the PVDD voltage. Special attention needs to be paid to placing all decoupling
capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins
and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic
capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the
power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the
gate-drive regulator output pin (GVDD) and the bootstrap pin. When the power-stage output is high, the
bootstrap capacitor potential is shifted above the output potential and thus provides a good voltage supply for
the high-side gate driver.
9.3.2 Device Clocking
The TAS5825M devices have flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface.
DACCLK
LRCLK/FS
DSPCLK
OSRCLK
DSP
(Including
interpolator)
Serial Audio
Interface (Input)
Delta Sigma
Modulator
Audio In
DAC
图9-1. Audio Flow with Respective Clocks
图9-1 shows the basic data flow and clock Distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
• SCLK (Bit Clock)
• LRCLK/FS (Left/Right Word Clock or Frame Sync)
• SDIN (Input Data)
The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP
and the DAC clock.
The TAS5825M device has an audio sampling rate detection circuit that automatically senses which frequency
the sampling rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz –
96 kHz, 176.4 kHz – 192 kHz are supported. The sampling frequency detector sets the clock for DAC and DSP
automatically.
If the input LRCLK/SCLK stopped during music playing, the TAS5825M DSP switches to sleep state and waiting
for the clock recovery (Class D output switches to Hiz automatically ), once LRCLK/SCLK recovered, TAS5825M
auto recovers to the play mode. There is no need to reload the DSP code.
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9.3.3 Serial Audio Port –Clock Rates
The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK , and SDIN. SCLK is the
serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio
interface. Serial data is clocked into the TAS5825M device with SCLK. The LRCLK/FS pin is the serial audio left/
right word clock or frame sync when the device is operated in TDM Mode.
表9-1. Audio Data Formats, Bit Depths and Clock Rates
MAXIMUM LRCLK/FS FREQUENCY
FORMAT
DATA BITS
SCLK RATE (fS)
(kHz)
32 to 192
32
I2S/LJ/RJ
32, 24, 20, 16
64, 32
128
44.1,48
96
128,256,512
128,256
128
TDM
32, 24, 20, 16
192
When Clock halt, non-supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in
Register 113 (Register Address 0x71).
9.3.4 Clock Halt Auto-Recovery
Some of host processor halts the I2S clock when there is no audio playing. When Clock halt, the device puts all
channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After the audio
clock recovery, the device automatically returns to the previous state.
9.3.5 Sample Rate on the Fly Change
TAS5825M supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32kHz to 48kHz or
96kHz or 192kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 100us before
changing to the new sample rate.
9.3.6 Serial Audio Port - Data Formats and Bit Depths
The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and
TDM/DSP data. Data formats are selected via Register (Register Address 0x33h -D[5:4]). If the high width of
LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, then the register (Register Address 0x33h -D[3:2])
sets to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is
accepted. All the data formats, word length and clock rate supported by this device are shown in Table 1. The
data formats are detailed in 图 9-2 through 图 9-6. The word length are selected via Register (Register Address
0x33h -D[1:0]). The offsets of data are selected via Register (Register Address 0x33h -D[7]) and Register
(Register Address 0x34h -D[7:0]). Default setting is I2S and 24 bit word length.
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1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
2
2
2
15 16
MSB
LSB
MSB
MSB
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
1
23 24
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
1
31 32
MSB
LSB
LSB
图9-2. Left Justified Audio Data Format
1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
1
1
2
2
2
15 16
MSB LSB
MSB LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
23 24
MSB
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
31 32
MSB
MSB
LSB
LSB
I2S Data Format; L-channel = LOW, R-channel = HIGH
I2S Data Format; L-channel = LOW, R-channel = HIGH
图9-3. I2S Audio Data Format
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1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
2
15 16
MSB LSB
MSB LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
1
2
23 24
MSB
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
1
2
31 32
MSB
MSB
LSB
LSB
Right-Justified Data Format; L-channel = HIGH, R-channel = LOW
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
图9-4. Right Justified Audio Data Format
1 /fS .
LRCK/FS
SCLK
…
…
…
…
…
…
Audio data word = 16-bit, Offset = 0
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
Data Slot 2
LSB
MSB
LSB
MSB
Audio data word = 24-bit, Offset = 0
,
-
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 0
…
…
1
2
31 32
LSB
1
2
31 32
LSB
DATA
MSB
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS must be 1x SCLK at minimum. Rising edge is considered frame start.
图9-5. TDM 1 Audio Data Format
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1 /fS .
OFFSET = 1
LRCK/FS
…
…
…
…
…
SCLK
Audio data word = 16-bit, Offset = 1
…
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
LSB
Data Slot 2
LSB
MSB
MSB
Audio data word = 24-bit, Offset = 1
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
Data Slot 2
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 1
…
…
1
2
31 32
LSB
1
2
31 32
DATA
Data Slot 1
Data Slot 2
LSB
MSB
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS must be 1x SCLK at minimum. Rising edge is considered frame start.
图9-6. TDM 2 Audio Data Format
9.3.7 Digital Audio Processing
TAS5825M DSP has flexible process flows which support Multi-Band DRC, Post AGL,FIR filter, 2*15 BQs,
Spatializer (stereo widening),Dynamic Biquad, Smart Speaker Excursion control, Smart Thermal and Smart
Bass Control for different applications, refer to application note: TAS5825M Process Flows for details.
Based on integrated PVDD sense ADC and 4 level temperature sensor, TAS5825M DSP also support PVDD
tracking(Dynamic Headroom tracking),advanced thermal foldback and Hybrid modulation(Low power dissipation
to extend battery life time), refer to application note:TAS5825M Advanced Features.
9.3.8 Class D Audio Amplifier
Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, and
the first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into
two pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the
speaker amplifier. Feedback loops around the DPC provide for constant gain across supply voltages, reduce
distortion, and increase immunity to power supply injected noise and distortion. The analog gain is also applied
in the Class-D amplifier section of the device. The gain structures are discussed in detail below for both 图 9-7
and 表9-2. The switching rate of the amplifier is configurable by register (Register Address 0x02h -D[6:4])
9.3.8.1 Speaker Amplifier Gain Select
A combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. As
seen in 图 9-7, the audio path of the TAS5825M consists of a digital audio input port, a digital audio path, a
digital to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds
the output information back into the DPC block to correct for distortion sensed on the output pins. The total
amplifier gain is comprised of digital gain, shown in the digital audio path and the analog gain from the input of
the analog modulator to the output of the speaker amplifier power stage.
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Analog Gain
Analog Gain
Digital Gain
Digital Gain
Closed Loop Class D Amplifier
Closed Loop Class D Amplifier
SPK_OUTA+
SPK_OUTA+
Full Bridge Power
Full Bridge Power
Stage
A
A
Stage
Gate
Gate
Drivers
Drivers
SPK_OUTA-
SPK_OUTA-
Serial
Serial
Audio Processing
Audio Processing
(Flexible Audio Process Flows)
(Flexible Audio Process Flows)
Serial
Serial
Audio In
Audio In
Digital to PWM
Digital to PWM
Conversion
Conversion
Audio
Audio
Port
Port
SPK_OUTB+
SPK_OUTB+
Gate
Gate
Drivers
Drivers
Full Bridge Power
Full Bridge Power
Stage
Stage
B
B
SPK_OUTB-
SPK_OUTB-
SCL
I2C Interface
I2C Interface
Control Register
Control Register
Closed Loop Class D Amplifier
Closed Loop Class D Amplifier
SDA
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
图9-7. Speaker Amplifier Gain
As shown in 图9-7, the first gain stage for the speaker amplifier is present in the digital audio path. The first gain
stage consists of the volume control and the digital boost block. The volume control is set to 0 dB by default and
does not change. For all settings of the register 0x54, AGAIN[4:0], the digital boost block remains at 0 dB. These
gain settings make sure that the output signal is not clipping at different PVDD levels. 0dBFS output is 29.5-V
peak output voltage
表9-2. Analog Gain Setting
AGAIN <4:0>
00000
GAIN (dBFS)
AMPLIFIER OUTPUT PEAK VOLTAGE (V)
0
29.5
27.85
…….
4.95
00001
-0.5
…….
……..
-15.5
11111
9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
TAS5825M closed loop structure provides Loop bandwidth setting option (Setting by register 83 -Register
address 0x53h-D[6-5]) to co-work with different switching frequency (Setting by register 2 -Register address
0x02h-D[6-4] ). 表9-3 shows recommended settings for the Loop Bandwidth and Switching Frequency selection.
Same Fsw, Better THD+N performance with higher BW.
表9-3. Loop Bandwidth and Switching Frequency Setting
Modulation
Scheme
Fsw
BW (Loop Band Width)
Notes
384 kHz
480 kHz
576 kHz
768 kHz
384 kHz
480 kHz
576 kHz
768 kHz
80 kHz
80 kHz, 100 kHz
Principle: Fsw (Switching Frequency) ≥4.2 × Loop
Hybrid, 1SPW
Bandwidth
80 kHz, 100 kHz, 120 kHz
80 kHz, 100 kHz, 120 kHz, 175 kHz
80 kHz, 100 kHz, 120 kHz
80 kHz, 100 kHz, 120 kHz
80 kHz, 100 kHz, 120 kHz, 175 kHz
80 kHz, 100 kHz, 120 kHz, 175 kHz
Principle: Fsw (Switching Frequency) ≥3 × Loop
BD
Bandwidth
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9.4 Device Functional Modes
9.4.1 Software Control
The TAS5825M device is configured via an I2 C communication port.
The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements
are described in the I2C Bus Timing –Standard and I2C Bus Timing –Fast sections.
There are two methods to program TAS5825M DSP memory.
• Loading with I2C Communication Port by host processor. This method is recommend for most of applications.
• Fast loading from external EEPROM with SPI communication Port. This method can be used in some
applications which need fast loading to save initialization time or release the Host Controller's loading.
TAS5825M supports to load the DSP memory data from external EEPROM via SPI. The GPIOs can be
configured as SI,SO and SCK for EEPROM via Register (0x60,0x61,0x62,0x63,0x64). The chip selection CS
of EEPROM is controlled by the Host Processor. See AppNote: Load TAS5825M Configurations from
EEPROM via SPI.
9.4.2 Speaker Amplifier Operating Modes
The TAS5825M device can be used with two different amplifier configurations, can be configured by Register
0x02h -D[2]:
• BTL Mode
• PBTL Mode
9.4.2.1 BTL Mode
In BTL mode, the TAS5825M amplifies two independent signals, which represent the left and right portions of a
stereo signal. The amplified left signal is presented on differential output pair shown as OUT_A+ and OUT_A-,
the amplified right signal is presented on differential output pair shown as OUT_B+ and OUT_B-.
9.4.2.2 PBTL Mode
The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in
parallel with one another to increase the power sourcing capabilities of the device. On the output side of the
TAS5825M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter
Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the inductor
portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive
inductors to be used because the current is divided between the two inductors. The process is called Post-Filter
PBTL. On the input side of the TAS5825M device, the input signal to the PBTL amplifier is left frame of I2S or
TDM data.
9.4.3 Low EMI Modes
TAS5825M employs several modes to minimize EMI during playing audio, and can be used based on different
applications.
9.4.3.1 Spread Spectrum
Spread spectrum is used in some inductor free cases to minimize EMI noise. The TAS5825M supports Spread
Spectrum with triangle mode.
User needs to configure register SS_CTRL0 (0x6B) to enable triangle mode and enable spread spectrum, select
spread spectrum frequency and range with SS_CTRL1 (0x6C). For 384 kHz FSW, which is configured by
DEVICE_CTRL1 (0x02), the spread spectrum frequency and range are described in 表9-4.
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表9-4. Triangle Mode Spread Spectrum Frequency and Range Selection
SS_TRI_CTRL[3:0]
0
1
2
3
4
5
6
7
Triangle Freq
24k
48k
Spread Spectrum
Range
5%
10%
20%
25%
5%
10%
20%
25%
User Application example: Central Switching Frequency is 384 kHz, Triangle Frequency is 24 kHz.
Register 0x6b = 0x03 // Enable Spread Spectrum
Register 0x6c = 0x03 // SS_CTRL[3:0]=0011, Triangle Frequency = 24 kHz, Spread Spectrum Range must be
25% (336 kHz through 432 kHz)
9.4.3.2 Channel to Channel Phase Shift
This device supports channel to channel 180-degree PWM phase shift to minimize the EMI. Bit 0 of Register
0x53 can be used to disable or enable the phase shift.
9.4.3.3 Multi-Devices PWM Phase Synchronization
TAS5825M support up to 4 phases selection for the multi devices application system. For example, when a
system integrated 4 TAS5825MM devices, user can select phase0/1/2/3 for each device by register
PHASE_CTRL(0x6A), which means there is a 45 degree phase shift between each device to minimize the EMI.
There are two methods for Multi-Device PWM phase synchronization. Phase Synchronization With I2S Clock In
Startup Phase or Phase Synchronization With GPIO.
9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
1. Step 1: Halt I2S clock.
2. Step 2: Configure each device phase selection and enable the phase synchronization. For example:
Register 0x6A=0x03 for device 0; Register 0x6A=0x07 for device 1; Register 0x6A=0x0B for device 2;
Register 0x6A=0x0F for device 3.
3. Step 3: Configure each device into HIZ mode.
4. Step 4: Provide I2S to each device. Phase synchronization for all 4 devices is automatically done by internal
sequence.
5. Step 5: Initialize the DSP code (This step can be skipped if only need to do the Phase Synchronization).
6. Step 6: Device to Device PWM phase shift must be fixed with 45 degree.
9.4.3.3.2 Phase Synchronization With GPIO
1. Step 1: Connect GPIOx pin of each device to SOC's GPIO pin on PCB.
2. Step 2: Configure each device GPIOx as phase sync input usage by registers GPIO_CTRL (0X60) and
GPIO_INPUT_SEL (0x64).
3. Step 3: Select different phase for each device and enable phase synchronization by register PHASE_CTRL
(0x6A).
4. Step 4: Configure each device into PLAY mode by register DEVICE_CTRL2 (0x03) and monitor the
POWER_STATE register (0x68) until device changed to HIZ state.
5. Step 5: Give a 0 to 1 toggle on SOC GPIO. Then all 4 devices enter into PLAY mode and device to Device
PWM phase shift must be fixed with 45 degrees.
6. Step 6: Phase Synchronization has been finished. Configure the GPIOx pin to other function based on the
application.
9.4.4 Thermal Foldback
The Thermal Foldback (TFB), is designed to protect TAS5825M from excessive die temperature increases, in
case the device operates beyond the recommended temperature/power limit, or with a weaker thermal system
design than recommended. The TFB allows the TAS5825M to play as loud as possible without triggering
unexpected thermal shutdown. When the die temperature triggers the over-temperature warning (OTW) level,
(TAS5825M has four different temperature threshold, each threshold is indicated in I2C register 0x73 bits 0,1,2
and 3 ), an internal AGL (Automatic Gain Limiter) reduces the digital gain gradually, lower value of OTW, smaller
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attenuation added, with the OTW warning goes higher, more attenuation added. Once the die temperature drops
below the OTW, the device’s digital gain gradually returns to the former setting. Both the attenuation gain and
adjustable rate are programmable. The TFB gain regulation speed (attack rate and release rate) settings are the
same as a regular AGL, which is also configurable with TAS5825M App in PurePathTM Console3.
9.4.5 Device State Control
Except Shutdown Mode, TAS5825M has other 4 states for different power dissipation which listed in 节7.5.
• Deep Sleep Mode. Register 0x03h -D[1:0]=00, Device stays in Deep Sleep Mode. In this mode, I2 C block
keep works. This mode can be used to extend the battery life time in some portable speaker application case,
once the host processor stopped playing audio for a long time, TAS5825M can be set to Deep Sleep Mode to
minimize power dissipation until host processor start playing audio again. Device returns back to Play Mode
by setting Register 0x03h -D[1:0] to 11. Compare with Shutdown Mode (Pull PDN Low), enter or exit Deep
Sleep Mode, DSP keeps active.
• Sleep Mode. Register 0x03h -D[1:0]=01, Device stays in Sleep Mode. In this mode, I2 C block, Digital core,
DSP Memory, 5 V Analog LDO keep works. Compare with Shutdown Mode (Pull PDN Low), enter or exit
Sleep Mode, DSP keeps active.
• Output Hiz Mode. Register 0x03h -D[1:0]=10, Device stays in Hiz Mode. In this mode, Only output driver set
to be Hiz state, all other block work normally.
• Play Mode. Register 0x03h -D[1:0]=11, Device stays in Play Mode.
9.4.6 Device Modulation
TAS5825M has 3 modulation schemes: BD modulation, 1SPW modulation and Hybrid modulation. Select
modulation schemes for TAS5825M with Register 0x02 [1:0]-DAMP_MOD.
9.4.6.1 BD Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
0V
-
OUTP OUTN
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
图9-8. BD Mode Modulation
9.4.6.2 1SPW Modulation
The 1SPW mode alters the normal modulation scheme to achieve higher efficiency with a slight penalty in THD
degradation and more attention required in the output filter selection. In Low Idle Current mode, the outputs
operate at approximately 17% modulation during idle conditions. When an audio signal is applied, one output
decreases and one increases. The decreasing output signal rails to GND. At this point all the audio modulation
takes place through the rising output. The result is that only one output is switching during a majority of the audio
cycle. Efficiency is improved in this mode due to the reduction of switching losses.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
图9-9. 1SPW Mode Modulation
9.4.6.3 Hybrid Modulation
Hybrid Modulation is designed for minimized power loss without compromising the THD+N performance, and is
optimized for battery-powered applications. With Hybrid modulation, TAS5825M detects the input signal level
and adjust PWM duty cycle dynamically based on PVDD. Hybrid modulation achieves ultra low idle current and
maintains the same audio performance level as the BD Modulation.
备注
As Hybrid Modulation need the internal DSP to detect the input signal level and adjust PWM duty
cycle dynamically. To use the Hybrid Modulation, users need to select the corresponding process
flows which support Hybrid Modulation in TAS5825M PPC3 App. Look intoTAS5825M PPC3 App for
more information about TAS5825M flexible audio process flows.
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9.5 Programming and Control
9.5.1 I2 C Serial Communication Bus
The device has a bidirectional serial control interface that is compatible with I2C bus protocol and supports 100
and 400-kHz data transfer rates for random and sequential write and read operations as a target device.
Because the TAS5825M register map and DSP memory spans multi pages, the user must change from page to
page before writing individual register or DSP memory. Changing from page to page is accomplished via register
0 on each page. This register value selects the page address, from 0 to 255. All registers are listed in the
TAS5825M data sheet and is in Page 0.
9.5.2 I2 C Target Address
The TAS5825M device has 7 bits for the target address. The first five bits (MSBs) of the target address are
factory preset to 10011(0x9x). The next two bits of address byte are the device select bits which can be user-
defined by ADR pin in 表9-5.
表9-5. I2 C Target Address Configuration
ADR PIN Configuration
0 Ω to GND
MSBs
User Define
LSB
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
R/ W
R/ W
R/ W
R/ W
1 kΩ to GND
4.7 kΩ to GND
15 kΩ to GND
9.5.2.1 Random Write
As shown in 图 9-10, a single-byte data-write transfer begins with the controller device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the controller transmits the address
byte corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the controller device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the controller device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图9-10. Random Write Transfer
9.5.2.2 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the controller to the device as shown in 图 9-11. After receiving each data byte, the device
responds with an acknowledge bit and the I2 subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
R/W ACK
A4 A3
A0
ACK
ACK
ACK
ACK
D0
A6
A1
A7
A6
A5
A1
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
图9-11. Sequential Write Transfer
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9.5.2.3 Random Read
As shown in 图 9-12, a single-byte data-read transfer begins with the controller device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the
device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the
controller device transmits another start condition followed by the address and the read/write bit again. This time
the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device
again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address
being read. After receiving the data byte, the controller device transmits a not-acknowledge followed by a stop
condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
Subaddress
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Data Byte
图9-12. Random Read Transfer
9.5.2.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the controller device as shown in 图9-13. Except for the last data byte, the controller
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
sub address by one. After receiving the last data byte, the controller device transmits a not-acknowledge
followed by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
图9-13. Sequential Read Transfer
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9.5.2.5 DSP Memory Book, Page and BQ update
On Page 0x00 of each book, Register 0x7f is used to change the book. Register 0x00 of each page is used to
change the page. To change a Page first write 0x00 to Register 0x00 to switch to Page 0 then write the book
number to Register 0x7f on Page 0. To switch between pages in a book, simply write the page number to
register 0x00.
All the Biquad Filters coefficients are addressed in book 0xAA. The five coefficients of every Biquad Filter must
be written entirely and sequentially from the lowest address to the highest address. The address of all Biquad
Filters can be found in 节9.6.
All DSP/Audio Process Flow Related Register are listed in Application Note, TAS5825M Process Flows.
9.5.2.6 Checksum
This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum, and an
Exclusive (XOR) checksum. Register reads do not change checksum, but writes so that even nonexistent
registers change the checksum. Both checksums are 8-bit checksums and both are available together
simultaneously. The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00) to their respective
4-byte register locations.
9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell
delineation, (1 + x1 + x2 + x8)). A major advantage of the CRC checksum is that the input order is sensitive. The
CRC supports all I2C transactions, excluding book and page switching. The CRC checksum is read from register
0x7E on page0 of any book (B_x, Page_0, Reg_126). The CRC checksum can be reset by writing 0x00 to the
same register locations where the CRC checksum is valid.
9.5.2.6.2 Exclusive or (XOR) Checksum
The XOR Checksum is a simpler checksum scheme. The scheme performs sequential XOR of each register
byte write with the previous 8-bit checksum register value. XOR supports only Book 0x8C, and excludes page
switching and all registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on
page 0x00 of book 0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the
same register location where the XOR Checksum is read.
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9.5.3 Control via Software
• Startup Procedures
• Shutdown Procedures
9.5.3.1 Startup Procedures
1. Configure ADR pin with proper setting for I2C device address.
2. Bring up power supplies (it does not matter if PVDD or DVDD comes up first).
3. Once power supplies are stable, bring up PDN to High and wait 5 ms at least, then start SCLK, LRCLK.
4. Once I2S clock are stable, set the device into HiZ state and enable DSP via the I2C control port.
5. Wait 5 ms at least. Then initialize the DSP Coefficient, then set the device to Play state.
6. The device is now in normal operation.
Initialization
Normal Op
eration
DVDD
PVDD
PDN
0 ns
0 ns
0 ns
5ms
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2C
Set to HiZ state
(Enable DSP)
DSP Coeff
Play
Deep sleep
5 ms for device settle down
图9-14. Start-Up Sequence
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9.5.3.2 Shutdown Procedures
1. The device is in normal operation.
2. Configure the Register 0x03h -D[1:0]=10 (Hiz) via the I2C control port or Pull PDN low.
3. Wait at least 6 ms (this time depends on the LRCLK rate ,digital volume and digital volume ramp down rate).
4. Bring down power supplies.
5. The device is now fully shutdown and powered off.
PDN
6ms
4.5V
PVDD
0ms
DVDD
6ms
I2C
I2C
I2C
I2C
Output Hiz
ñ
ñ
Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I2C.
At least 6ms delay needed based on LRCLK (Fs) = 48kHz,Digital volume ramp down update every sample period,
decreased by 0.5dB for each update, digital volume =24dB. Change the value of register 0x4C and 0x4E or change
the LRCLK rate, the delay changes.
图9-15. Power-Down Sequence
9.5.3.3 Protection and Monitoring
9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
The CBC current-limiting circuit terminates each PWM pulse limit the output current flow to the average current
limit (ILIM) threshold. The overall effect on the audio in the case of a current overload is quite similar a voltage-
clipping event, temporarily limiting power at the peaks of the music signal and normal operation continues
without disruption on removal of the overload.
备注
CBC (Cycle-By-Cycle) current-limiting only allows in BTL mode, not allowed under PBTL.
9.5.3.3.2 Overcurrent Shutdown (OCSD)
Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector,
and the affected channel shuts down in < 100 ns if the peak current are enough. The shutdown speed depends
on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. The
user can restart the affected channel via I2C. An OCSD event activates the fault pin, and the I2 fault register
saves a record. If the supply or ground short is strong enough to exceed the peak current threshold but not
severe enough to trigger the OCSD, the peak current limiter prevents excess current from damaging the output
FETs, and operation returns to normal after the short is removed.
9.5.3.3.3 DC Detect
If the TAS5825M device measures a DC offset in the output voltage, the FAULTZ line is pulled low and the
OUTxx outputs transition to high impedance, signifying a fault.
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9.6 Register Maps
9.6.1 CONTROL PORT Registers
表 9-6 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in 表
9-6 must be considered as reserved locations and the register contents must not be modified.
表9-6. CONTROL PORT Registers
Offset
1h
Acronym
Register Name
Section
RESET_CTRL
Register 1
节9.6.1.2
节9.6.1.3
节9.6.1.4
节9.6.1.5
节9.6.1.6
节9.6.1.7
节9.6.1.8
节9.6.1.9
节9.6.1.10
节9.6.1.11
节9.6.1.12
节9.6.1.13
节9.6.1.14
节9.6.1.15
节9.6.1.16
节9.6.1.17
节9.6.1.18
节9.6.1.19
节9.6.1.20
节9.6.1.21
节9.6.1.22
节9.6.1.23
节9.6.1.24
节9.6.1.25
节9.6.1.26
节9.6.1.27
节9.6.1.28
节9.6.1.29
节9.6.1.30
节9.6.1.31
节9.6.1.32
节9.6.1.33
节9.6.1.34
节9.6.1.35
节9.6.1.36
节9.6.1.37
节9.6.1.38
节9.6.1.39
2h
DEVICE_CTRL_1
DEVICE_CTRL2
I2C_PAGE_AUTO_INC
SIG_CH_CTRL
CLOCK_DET_CTRL
SDOUT_SEL
Register 2
3h
Register 3
Fh
Register 15
Register 40
Register 41
Register 48
Register 49
Register 51
Register 52
Register 53
Register 55
Register 56
Register 57
Register 64
Register 70
Register 76
Register 78
Register 79
Register 80
Register 81
Register 83
Register 84
Register 85
Register 86
Register 87
Register 88
Register 89
Register 90
Register 91
Register 92
Register 94
Register 96
Register 97
Register 98
Register 99
Register 100
Register 101
28h
29h
30h
31h
33h
34h
35h
37h
38h
39h
40h
46h
4Ch
4Eh
4Fh
50h
51h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Eh
60h
61h
62h
63h
64h
65h
I2S_CTRL
SAP_CTRL1
SAP_CTRL2
SAP_CTRL3
FS_MON
BCK (SCLK)_MON
CLKDET_STATUS
DSP_PGM_MODE
DSP_CTRL
DIG_VOL
DIG_VOL_CTRL1
DIG_VOL_CTRL2
AUTO_MUTE_CTRL
AUTO_MUTE_TIME
ANA_CTRL
AGAIN
SPI_CLK
EEPROM_CTRL0
EEPROM_RD_CMD
EEPROM_ADDR_START0
EEPROM_ADDR_START1
EEPROM_ADDR_START2
EEPROM_BOOT_STATUS
BQ_WR_CTRL1
PVDD_ADC
GPIO_CTRL
GPIO0_SEL
GPIO1_SEL
GPIO2_SEL
GPIO_INPUT_SEL
GPIO_OUT
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表9-6. CONTROL PORT Registers (continued)
Offset
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
Acronym
Register Name
Register 102
Register 103
Register 104
Register 105
Register 106
Register 107
Register 108
Register 109
Register 110
Register 111
Register 112
Register 113
Register 114
Register 115
Register 116
Register 117
Register 118
Register 119
Register 120
Section
GPIO_OUT_INV
DIE_ID
节9.6.1.40
节9.6.1.41
节9.6.1.42
节9.6.1.43
节9.6.1.44
节9.6.1.45
节9.6.1.46
节9.6.1.47
节9.6.1.48
节9.6.1.49
节9.6.1.50
节9.6.1.51
节9.6.1.52
节9.6.1.53
节9.6.1.54
节9.6.1.55
节9.6.1.56
节9.6.1.57
节9.6.1.58
POWER_STATE
AUTOMUTE_STATE
PHASE_CTRL
SS_CTRL0
SS_CTRL1
SS_CTRL2
SS_CTRL3
SS_CTRL4
CHAN_FAULT
GLOBAL_FAULT1
GLOBAL_FAULT2
WARNING
PIN_CONTROL1
PIN_CONTROL2
MISC_CONTROL
CBC_CONTROL
FAULT_CLEAR
Complex bit access types are encoded to fit into small table cells. 表 9-7 shows the codes that are used for
access types in this section.
表9-7. CONTROL PORT Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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9.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]
RESET_CTRL is shown in 图9-12 and described in 表9-8.
Return to 表9-6.
图9-16. RESET_CTRL Register
7
6
5
4
RST_MOD
W
3
2
RESERVED
R
1
0
RST_REG
W
RESERVED
R/W
表9-8. RESET_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
R/W
000
This bit is reserved
RST_DIG_CORE
W
0
WRITE CLEAR BIT
Reset DIG_CORE
WRITE CLEAR BIT Reset Full Digital Core. This bit resets the Full
Digital Signal Path (Include DSP coefficient RAM and I2C Control
Port Registers), Since the DSP is also reset, the coefficient RAM
content is also cleared by the DSP.
0: Normal
1: Reset Full Digital Signal Path
3-1
0
RESERVED
RST_REG
R
000
0
This bit is reserved
W
WRITE CLEAR BIT
Reset Registers
This bit resets the mode registers back to their initial values. Only
reset Control Port Registers, The RAM content is not cleared.
0: Normal
1: Reset I2C Control Port Registers
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9.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
DEVICE_CTRL_1 is shown in 图9-13 and described in 表9-9.
Return to 表9-6.
图9-17. DEVICE_CTRL_1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
FSW_SEL
R/W
RESERVED
R/W
DAMP_PBTL
R/W
DAMP_MOD
R/W
表9-9. DEVICE_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
FSW_SEL
R/W
0
This bit is reserved
6-4
R/W
000
SELECT FSW
000:384K
010:480K
011:576K
100:768K
001:Reserved
101:Reserved
110:Reserved
111:Reserved
3
2
RESERVED
DAMP_PBTL
R/W
R/W
0
0
This bit is reserved
0: SET DAMP TO BTL MODE
1:SET DAMP TO PBTL MODE
1-0
DAMP_MOD
R/W
00
00:BD MODE 01:1SPW MODE 10:HYBRID MODE
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9.6.1.3 DEVICE_CTRL2 Register (Offset = 3h) [reset = 00x10]
DEVICE_CTRL2 is shown in 图9-14 and described in 表9-10.
Return to 表9-6.
图9-18. DEVICE_CTRL2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DIS_DSP
R/W
MUTE_LEFT
R/W
RESERVED
R/W
CTRL_STATE
R/W
表9-10. DEVICE_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
DIS_DSP
R/W
000
This bit is reserved
DSP reset
R/W
1
When the bit is made 0, DSP starts powering up and send out data.
This needs to be made 0 only after all the input clocks are settled so
that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3
MUTE
R/W
0
Mute both Left and Right Channel
This bit issues soft mute request for both left and right channel. The
volume is smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2
RESERVED
R/W
R/W
0
This bit is reserved
1-0
CTRL_STATE
00
device state control register
00: Deep Sleep
01: Sleep
10: Hiz,
11: PLAY
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9.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
I2C_PAGE_AUTO_INC is shown in 图9-15 and described in 表9-11.
Return to 表9-6.
图9-19. I2C_PAGE_AUTO_INC Register
7
6
5
4
3
2
1
0
RESERVED
R/W
PAGE_AUTOIN
C_REG
RESERVED
R/W
R/W
表9-11. I2C_PAGE_AUTO_INC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
R/W
0000
This bit is reserved
Page auto increment disable
PAGE_AUTOINC_REG
R/W
0
Disable page auto increment mode for non -zero books. When end
of page is reached, the page goes back to 8th address location of
next page when this bit is 0. When this bit is 1 the page goes to the
0th location of current page itself.
0: Enable Page auto increment
1: Disable Page auto increment
2-0
RESERVED
R/W
000
This bit is reserved
9.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
SIG_CH_CTRL is shown in 图9-16 and described in 表9-12.
Return to 表9-6.
图9-20. SIG_CH_CTRL Register
7
6
5
4
3
2
1
0
SCLK_RATIO_CONFIGURE
R/W
FSMODE
R/W
RESERVED
R/W
表9-12. SIG_CH_CTRL Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
SCLK_RATIO_CONFIGU R/W
RE
0000
These bits indicate the configured SCLK ratio, the number of SCLK
clocks in one audio frame. Device sets this ratio automatically.
4'b0011:32FS
4'b0101:64FS
4'b0111:128FS
4'b1001:256FS
4'b1011:512FS
3
FSMODE
R/W
0
FS Speed Mode: These bits select the FS operation mode, which
must be set according to the current audio sampling rate and is set
manually. If the input Fs is 44.1 kHz/88.2 kHz/176.4 kHz.
4 'b0000 Auto detection
4 'b0100 Reserved
4 'b0110 32 KHz
4 'b1000 44.1 KHz
4 'b1001 48 KHz
4'b1010 88.2 KHz
4 'b1011 96 KHz
4 'b1100 176.4 KHz
4 'b1101 192 KHz
Others Reserved
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表9-12. SIG_CH_CTRL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
RESERVED
R/W
000
This bit is reserved
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9.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
CLOCK_DET_CTRL is shown in 图9-17 and described in 表9-13.
Return to 表9-6.
图9-21. CLOCK_DET_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
DIS_DET_PLL DIS_DET_SCL DIS_DET_FS DIS_DET_SCL DIS_DET_MISS RESERVED
RESERVED
K_RANGE
K
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表9-13. CLOCK_DET_CTRL Register Field Descriptions
Bit
Field
RESERVED
DIS_DET_PLL
Type
Reset
Description
7
R/W
0
This bit is reserved
Ignore PLL overate Detection
6
R/W
0
This bit controls whether to ignore the PLL overrate detection. The
PLL must be slow than 150 MHz or an error is reported. When
ignored, a PLL overrate error does not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5
DIS_DET_SCLK_RANGE R/W
0
Ignore BCK Range Detection
This bit controls whether to ignore the SCLK range detection. The
SCLK must be stable between 256 KHz and 50 MHz or an error is
reported. When ignored, a SCLK range error does not cause a clock
error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4
3
DIS_DET_FS
R/W
R/W
0
0
Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When
ignored, FS error does not cause a clock error. But
CLKDET_STATUS reports fs error.
0: Regard FS detection
1: Ignore FS detection
DIS_DET_SCLK
Ignore SCLK Detection
This bit controls whether to ignore the SCLK detection against
LRCK. The SCLK must be stable between 32 FS and 512 FS
inclusive or an error is reported. When ignored, a SCLK error does
not cause a clock error.
0: Regard SCLK detection
1: Ignore SCLK detection
2
DIS_DET_MISS
R/W
0
Ignore SCLK Missing Detection
This bit controls whether to ignore the SCLK missing detection.
When ignored an SCLK missing does not cause a clock error.
0: Regard SCLK missing detection
1: Ignore SCLK missing detection
1
0
RESERVED
RESERVED
R/W
R/W
0
0
This bit is reserved
This bit is reserved
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9.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0x00]
SDOUT_SEL is shown in 图9-19 and described in 表9-14.
Return to 表9-6.
图9-22. SDOUT_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
RESERVED
R/W
SDOUT_SEL
R/W
表9-14. SDOUT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
SDOUT_SEL
R/W
0000000
These bits are reserved
R/W
0
SDOUT Select. This bit selects what is being output as SDOUT pin.
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
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9.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in 图9-19 and described in 表9-15.
Return to 表9-6.
图9-23. I2S_CTRL Register
7
6
5
4
3
RESERVED
R
2
1
0
RESERVED
R/W
SCLK_INV
R/W
RESERVED
R/W
RESERVED
R
RESERVED
R/W
表9-15. I2S_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
SCLK_INV
R/W
00
This bit is reserved
SCLK Polarity
R/W
0
This bit sets the inverted SCLK mode. In inverted SCLK mode, the
DAC assumes that the LRCK and DIN edges are aligned to the rising
edge of the SCLK. Normally the edges are assumed to be aligned to
the falling edge of the SCLK
0: Normal SCLK mode
1: Inverted SCLK mode
4
3
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R
0
This bit is reserved
This bit is reserved
These bits are reserved
This bit is reserved
0
2-1
0
R
00
0
R/W
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9.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
SAP_CTRL1 is shown in 图9-20 and described in 表9-16.
Return to 表9-6.
图9-24. SAP_CTRL1 Register
7
6
5
4
3
2
1
0
I2S_SHIFT_MS
B
RESERVED
DATA_FORMAT
R/W
I2S_LRCLK_PULSE
R/W
WORD_LENGTH
R/W
R/W
R/W
表9-16. SAP_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
I2S_SHIFT_MSB
RESERVED
R/W
0
I2S Shift MSB
6
R/W
R/W
0
This bit is reserved
I2S Data Format
5-4
DATA_FORMAT
00
These bits control both input and output audio interface formats for
DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2
1-0
I2S_LRCLK_PULSE
WORD_LENGTH
R/W
R/W
00
10
01: LRCLK pulse < 8 SCLK
I2S Word Length
These bits control both input and output audio interface sample word
lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
SAP_CTRL2 is shown in 图9-21 and described in 表9-17.
Return to 表9-6.
图9-25. SAP_CTRL2 Register
7
6
5
4
3
2
1
0
I2S_SHIFT
R/W
表9-17. SAP_CTRL2 Register Field Descriptions
Bit
7-0
Field
I2S_SHIFT
Type
Reset
Description
R/W
00000000
I2S Shift LSB
These bits control the offset of audio data in the audio frame for both
input and output. The offset is defined as the number of SCLK from
the starting (MSB) of audio frame to the starting of the desired audio
sample. MSB [8] locates in 节9.6.1.10
000000000: offset = 0 SCLK (no offset)
000000001: offset = 1 SCLK
000000010: offset = 2 SCLKs
and
111111111: offset = 512 SCLKs
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9.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
SAP_CTRL3 is shown in 图9-22 and described in 表9-18.
Return to 表9-6.
图9-26. SAP_CTRL3 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
LEFT_DAC_DPATH
R/W
RESERVED
R/W
RIGHT_DAC_DPATH
R/W
表9-18. SAP_CTRL3 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5-4
RESERVED
00
These bits are reserved
LEFT_DAC_DPATH
01
Left DAC Data Path. These bits control the left channel audio data
path connection.
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
3-2
1-0
RESERVED
R/W
R/W
00
01
These bits are reserved
RIGHT_DAC_DPATH
Right DAC Data Path. These bits control the right channel audio data
path connection.
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)
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9.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
FS_MON is shown in 图9-23 and described in 表9-19.
Return to 表9-6.
图9-27. FS_MON Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SCLK_RATIO_HIGH
R
FS
R
表9-19. FS_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-4
3-0
RESERVED
SCLK_RATIO_HIGH
FS
R/W
00
This bit is reserved
2 msbs of detected SCLK ratio
R
R
00
0000
These bits indicate the currently detected audio sampling rate.
4 'b0000 FS Error
4 'b0100 16 KHz
4 'b0110 32 KHz
4 'b1000 Reserved
4 'b1001 48 KHz
4 'b1011 96 KHz
4 'b1101 192 KHz
Others Reserved
9.6.1.13 BCK (SCLK)_MON Register (Offset = 38h) [reset = 0x00]
BCK_MON is shown in 图9-24 and described in 表9-20.
Return to 表9-6.
图9-28. BCK (SCLK)_MON Register
7
6
5
4
3
2
1
0
BCLK (SCLK)_RATIO_LOW
R
表9-20. BCK_MON Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
BCLK
(SCLK)_RATIO_LOW
R
00000000
These bits indicate the currently detected BCK (SCLK) ratio, the
number of BCK (SCLK) clocks in one audio frame.
BCK (SCLK) = 32 FS - 512 FS
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9.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
CLKDET_STATUS is shown in 图9-25 and described in 表9-21.
Return to 表9-6.
图9-29. CLKDET_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DET_STATUS
R
表9-21. CLKDET_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
R/W
00
This bit is reserved
DET_STATUS
R
000000
bit0: In auto detection mode(reg_fsmode=0),this bit indicated
whether the audio sampling rate is valid or not. In non auto detection
mode(reg_fsmode!=0), Fs error indicates that configured fs is
different with detected fs. Even FS Error Detection Ignore is set, this
flag is also asserted.
bit1: This bit indicates whether the SCLK is valid or not. The SCLK
ratio must be stable and in the range of 32-512FS to be valid.
bit2: This bit indicates whether the SCLK is missing or not.
bit3:This bit indicates whether the PLL is locked or not. The PLL is
reported as unlocked when the PLL is disabled.
bits4:This bit indicates whether the PLL is overrate
bits5:This bit indicates whether the SCLK is overrate or underrate
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9.6.1.15 DSP_PGM_MODE Register (Offset = 40h) [reset = 0x01]
DSP_PGM_MODE is shown in 图9-26 and described in 表9-22.
Return to 表9-6.
图9-30. DSP_PGM_MODE Register
7
6
5
4
3
2
1
0
RESERVED
R/W
MODE_SEL
R/W
表9-22. DSP_PGM_MODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
2-0
RESERVED
MODE_SEL
R/W
000
This bit is reserved
DSP Program Selection
R/W
00001
These bits select the DSP program to use for audio processing.
00000 => ram mode
00001 => rom mode 1
00010 => rom mode 2
00011 => rom mode 3
9.6.1.16 DSP_CTRL Register (Offset = 46h) [reset = 0x01]
DSP_CTRL is shown in 图9-27 and described in 表9-23.
Return to 表9-6.
图9-31. DSP_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
USER_DEFINED_PROCESSING RESERVED BOOT_FROM_I USE_DEFAULT
_RATE
RAM
_COEFFS
R/W
R/W
R
R/W
R/W
表9-23. DSP_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7-5
4-3
R/W
000
This bit is reserved
USER_DEFINED_PROCE R/W
SSING_RATE
00
00:input
01:48k
10:96k
11:192k
2
1
0
RESERVED
RESERVED
R
R
0
0
1
This bit is reserved
This bit is reserved
USE_DEFAULT_COEFFS R/W
Use default coefficients from ZROM this bit controls whether to use
default coefficients from ZROM or use the non-default coefficients
downloaded to device by the Host
0 : don't use default coefficients from ZROM
1 : use default coefficients from ZROM
9.6.1.17 DIG_VOL Register (Offset = 4Ch) [reset = 30h]
DIG_VOL is shown in 图9-28 and described in 表9-24.
Return to 表9-6.
图9-32. DIG_VOL Register
7
6
5
4
3
2
1
0
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图9-32. DIG_VOL Register (continued)
PGA_LEFT
R/W
表9-24. DIG_VOL Register Field Descriptions
Bit
Field
PGA
Type
Reset
Description
7-0
R/W
00110000
Digital Volume
These bits control both left and right channel digital volume. The
digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute
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9.6.1.18 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]
DIG_VOL_CTRL1 is shown in 图9-29 and described in 表9-25.
Return to 表9-6.
图9-33. DIG_VOL_CTRL1 Register
7
6
5
4
3
2
1
0
PGA_RAMP_DOWN_SPEED
R/W
PGA_RAMP_DOWN_STEP
R/W
PGA_RAMP_UP_SPEED
R/W
PGA_RAMP_UP_STEP
R/W
表9-25. DIG_VOL_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PGA_RAMP_DOWN_SPE R/W
ED
00
Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
3-2
1-0
PGA_RAMP_DOWN_STE R/W
P
11
00
11
Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
PGA_RAMP_UP_SPEED R/W
Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
PGA_RAMP_UP_STEP
R/W
Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the
volume is ramping up.
00: Increment by 4 dB for each update
01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update
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9.6.1.19 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL2 is shown in 图9-30 and described in 表9-26.
Return to 表9-6.
图9-34. DIG_VOL_CTRL2 Register
7
6
5
4
3
2
1
0
FAST_RAMP_DOWN_SPEED
R/W
FAST_RAMP_DOWN_STEP
R/W
RESERVED
R/W
表9-26. DIG_VOL_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
FAST_RAMP_DOWN_SP R/W
EED
00
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down due to clock error or power outage,
which usually needs faster ramp down compared to normal soft
mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
FAST_RAMP_DOWN_ST R/W
EP
11
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down due to clock error or power outage, which
usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0
RESERVED
R/W
0000
This bit is reserved
9.6.1.20 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
AUTO_MUTE_CTRL is shown in 图9-31 and described in 表9-27.
Return to 表9-6.
图9-35. AUTO_MUTE_CTRL Register
7
6
5
4
3
2
1
REG_AUTO_MUTE_CTRL
R/W
0
RESERVED
R/W
表9-27. AUTO_MUTE_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7-3
2-0
R/W
00000
This bit is reserved
REG_AUTO_MUTE_CTR R/W
L
111
bit0:
0: Disable left channel auto mute
1: Enable left channel auto mute
bit1:
0: Disable right channel auto mute
1: Enable right channel auto mute
bit2: 0:
Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are
about to be auto muted.
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9.6.1.21 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
AUTO_MUTE_TIME is shown in 图9-32 and described in 表9-28.
Return to 表9-6.
图9-36. AUTO_MUTE_TIME Register
7
6
5
AUTOMUTE_TIME_LEFT
R/W
4
3
2
1
0
RESERVED
R/W
RESERVED
R/W
AUTOMUTE_TIME_RIGHT
R/W
表9-28. AUTO_MUTE_TIME Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-4
AUTOMUTE_TIME_LEFT R/W
000
Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
3
RESERVED
R/W
0
This bit is reserved
2-0
AUTOMUTE_TIME_RIGH R/W
T
000
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
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9.6.1.22 ANA_CTRL Register (Offset = 53h) [reset = 0h]
ANA_CTRL is shown in 图9-33 and described in 表9-29
Return to 表9-6
图9-37. ANA_CTRL Register
7
6
5
4
3
2
1
0
AMUTE_DLY
R/W
表9-29. ANA_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R/W
0
This bit is reserved
6-5
Class D bandwidth control R/W
00
00: 100 kHz
01: 80 kHz
10: 120 kHz
11:175 kHz
With Fsw = 384 kHz, 100 kHz bandwidth is selected for high audio
performance. With Fsw = 768 kHz, 175 kHz bandwidth is selected for
high audio performance.
4-1
0
RESERVED
R/W
R/W
0000
0
These bits are reserved
L and R PWM output
phase control
0: out of phase
1: in phase
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9.6.1.23 AGAIN Register (Offset = 54h) [reset = 0x00]
AGAIN is shown in 图9-34 and described in 表9-30.
Return to 表9-6.
图9-38. AGAIN Register
7
6
5
4
3
2
1
0
RESERVED
R/W
ANA_GAIN
R/W
表9-30. AGAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4-0
RESERVED
ANA_GAIN
R/W
000
This bit is reserved
R/W
00000
Analog Gain Control
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001:-0.5db 11111: -15.5 dB
9.6.1.24 SPI_CLK Register (Offset = 55h) [reset = 0x00]
SPI_CLK is shown in 图9-35 and described in 表9-31.
Return to 表9-6.
图9-39. SPI_CLK Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SPI_CLK_SEL
R/W
表9-31. SPI_CLK Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R/W
0000
This bit is reserved
SPI_CLK_SEL
R/W
0000
00:1.25M
01:2.5M
10:5M
11:10M
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9.6.1.25 EEPROM_CTRL0 Register (Offset = 56h) [reset = 0x00]
EEPROM_CTRL0 is shown in 图9-36 and described in 表9-32.
Return to 表9-6.
图9-40. EEPROM_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
EEPROM_ADD
R_24BITS_ENA
BLE
SPI_CLK_RATE
SPI_INV_POLA SPI_MST_LSB LOAD_EEPRO
R
M_START
R/W
R/W
R/W
R/W
R/W
表9-32. EEPROM_CTRL0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R/W
00
This bit is reserved
EEPROM_ADDR_24BITS R/W
_ENABLE
0
enable 24 bits mode for EEPROM address
4-3
SPI_CLK_RATE
R/W
00
0: spi clock rate = 1.25 MHz
1: spi clock rate = 2.5 MHz
2: spi clock rate = 5 MHz
3: spi clock rate = 10 MHz
2
SPI_INV_POLAR
SPI_MST_LSB
R/W
R/W
0
0: spi serial data change at post edge SCK
1: spi serial data change at neg edge SCK
1
0
0
0
0: msb first 1: lsb first
LOAD_EEPROM_START R/W
0: dsp coefficients read from host
1: dsp coefficients read from EEPROM
9.6.1.26 EEPROM_RD_CMD Register (Offset = 57h) [reset = 0x03]
EEPROM_RD_CMD is shown in 图9-37 and described in 表9-33.
Return to 表9-6.
图9-41. EEPROM_RD_CMD Register
7
6
5
4
3
2
1
0
EEPROM_RD_CMD
R/W-00000011
表9-33. EEPROM_RD_CMD Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPROM_RD_CMD
R/W
00000011
EEPROM read command
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9.6.1.27 EEPROM_ADDR_START0 Register (Offset = 58h) [reset = 0x00]
EEPROM_ADDR_START0 is shown in 图9-38 and described in 表9-34.
Return to 表9-6.
图9-42. EEPROM_ADDR_START0 Register
7
6
5
4
3
2
1
0
EEPROM_ADDR_START_HIGH
R/W
表9-34. EEPROM_ADDR_START0 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPROM_ADDR_START R/W
_HIGH
00000000
8 msb of EEPROM read starting address for coefficient
9.6.1.28 EEPROM_ADDR_START1 Register (Offset = 59h) [reset = 0x00]
EEPROM_ADDR_START1 is shown in 图9-39 and described in 表9-35.
Return to 表9-6.
图9-43. EEPROM_ADDR_START1 Register
7
6
5
4
3
2
1
0
EEPROM_ADDR_START_MIDDLE
R/W
表9-35. EEPROM_ADDR_START1 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPROM_ADDR_START R/W
_MIDDLE
00000000
8 middle of EEPROM read starting address for coefficients
9.6.1.29 EEPROM_ADDR_START2 Register (Offset = 5Ah) [reset = 0h]
EEPROM_ADDR_START2 is shown in 图9-40 and described in 表9-36.
Return to 表9-6.
图9-44. EEPROM_ADDR_START2 Register
7
6
5
4
3
2
1
0
EEPROM_ADDR_START_LOW
R/W
表9-36. EEPROM_ADDR_START2 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPROM_ADDR_START R/W
_LOW
00000000
8 lsb of EEPROM read starting address for coefficients
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9.6.1.30 EEPROM_BOOT_STATUS Register (Offset = 5Bh) [reset = 0x00]
EEPROM_BOOT_STATUS is shown in 图9-41 and described in 表9-37.
Return to 表9-6.
图9-45. EEPROM_BOOT_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R
LOAD_EEPRO LOAD_EEPRO
M_CRC_ERRO
R
M_DONE
R
R
表9-37. EEPROM_BOOT_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
1
RESERVED
R
000000
This bit is reserved
LOAD_EEPROM_CRC_E
RROR
R
R
0
0
0: CRC pass for EEPROM boot load
1: CRC don't pass for EEPROM boot load.
0
LOAD_EEPROM_DONE
Indicate that the EEPROM boot load has been finished.
9.6.1.31 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x000]
BQ_WR_CTRL1 is shown in 图9-42 and described in 表9-38.
Return to 表9-6.
图9-46. BQ_WR_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
BQ_WR_FIRST
_COEF
R/W
R/W
表9-38. BQ_WR_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
R/W
0000000
This bit is reserved
BQ_WR_FIRST_COEF
R/W
0
Indicate the first coefficient of a BQ is starting to write.
9.6.1.32 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]
PVDD_ADC is shown in 图9-43 and described in 表9-39.
Return to 表9-6.
图9-47. PVDD_ADC Register
7
6
5
4
3
2
1
0
ADC_DATA_OUT
R
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表9-39. PVDD_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PVDD_ADC[7:0]
R
00000000
PVDD Voltage = PVDD_ADC[7:0] / 8.428 (V)
223: 26.45V
222: 26.34V
221:26.22V
...
39: 4.63V
38: 4.51V
37: 4.39V
9.6.1.33 GPIO_CTRL Register (Offset = 60h) [reset = 0x00]
GPIO_CTRL is shown in 图9-44 and described in 表9-40.
Return to 表9-6.
图9-48. GPIO_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO2_OE
R/W
GPIO1_OE
R/W
GPIO0_OE
R/W
表9-40. GPIO_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
GPIO2_OE
R/W
0000
This bit is reserved
R/W
R/W
R/W
0
0
0
GPIO2 Output Enable. This bit sets the direction of the GPIO2 pin
0: GPIO2 is input
1: GPIO2 is output
1
0
GPIO1_OE
GPIO0_OE
GPIO1 Output Enable This bit sets the direction of the GPIO1 pin
0: GPIO1 is input
1: GPIO1 is output
GPIO0 Output Enable This bit sets the direction of the GPIO0 pin
0: GPIO0 is input
1: GPIO0 is output
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9.6.1.34 GPIO0_SEL Register (Offset = 61h) [reset = 0x00]
GPIO0_SEL is shown in 图9-45 and described in 表9-41.
Return to 表9-6.
图9-49. GPIO0_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO0_SEL
R/W
表9-41. GPIO0_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
GPIO0_SEL
R/W
0000
This bit is reserved
R/W
0000
0000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in 节9.6.1.39
0011: Auto mute flag (asserted when both L and R channels are auto
muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO0 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO0 as FAULTZ output
1100: GPIO0 as SPI CLK
1101: GPIO0 as SPI_PICO
1110: Reserved
1111: Reserved
9.6.1.35 GPIO1_SEL Register (Offset = 62h) [reset = 0x00]
GPIO1_SEL is shown in 图9-46 and described in 表9-42.
Return to 表9-6.
图9-50. GPIO1_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO1_SEL
R/W
表9-42. GPIO1_SEL Register Field Descriptions
Bit
7-4
Field
RESERVED
Type
Reset
Description
R/W
0000
This bit is reserved
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表9-42. GPIO1_SEL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
GPIO1_SEL
R/W
0000
0000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in 节9.6.1.39
0011: Auto mute flag (asserted when both L and R channels are auto
muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO1 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO1 as FAULTZ output
1100: GPIO1 as SPI CLK
1101: GPIO1 as SPI_PICO
1110: Reserved
1111: Reserved
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9.6.1.36 GPIO2_SEL Register (Offset = 63h) [reset = 0x00]
GPIO2_SEL is shown in 图9-47 and described in 表9-43.
Return to 表9-6.
图9-51. GPIO2_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO2_SEL
R/W
表9-43. GPIO2_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
GPIO2_SEL
R/W
0000
This bit is reserved
R/W
0000
0000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in 节9.6.1.39
0011: Auto mute flag (asserted when both L and R channels are auto
muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO2 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO2 as FAULTZ output
1100: GPIO2 as SPI CLK
1101: GPIO2 as SPI_PICO
1110: Reserved
1111: Reserved
9.6.1.37 GPIO_INPUT_SEL Register (Offset = 64h) [reset = 0x00]
GPIO_INPUT_SEL is shown in 图9-48 and described in 表9-44.
Return to 表9-6.
图9-52. GPIO_INPUT_SEL Register
7
6
5
4
3
2
1
0
GPIO_SPI_POCI_SEL
R/W
GPIO_PHASE_SYNC_SEL
R/W
GPIO_RESETZ_SEL
R/W
GPIO_MUTEZ_SEL
R/W
表9-44. GPIO_INPUT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
GPIO_SPI_POCI_SEL
R/W
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
5-4
3-2
GPIO_PHASE_SYNC_SE R/W
L
00
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
GPIO_RESETZ_SEL
R/W
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2 cannot be reset by GPIO reset
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表9-44. GPIO_INPUT_SEL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
GPIO_MUTEZ_SEL
R/W
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
MUTEZ pin active-low, output driver sets to HiZ state, the output stop
switching of the Class D amplifier.
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9.6.1.38 GPIO_OUT Register (Offset = 65h) [reset = 0x00]
GPIO_OUT is shown in 图9-49 and described in 表9-45.
Return to 表9-6.
图9-53. GPIO_OUT Register
7
6
5
4
3
2
1
0
0
0
RESERVED
R/W
GPIO_OUT
R/W
表9-45. GPIO_OUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2-0
RESERVED
GPIO_OUT
R/W
00000
This bit is reserved
R/W
000
bit0: GPIO0 output
bit1: GPIO1 output
bit2: GPIO2 output
9.6.1.39 GPIO_OUT_INV Register (Offset = 66h) [reset = 0x00]
GPIO_OUT_INV is shown in 图9-50 and described in 表9-46.
Return to 表9-6.
图9-54. GPIO_OUT_INV Register
7
6
5
4
3
2
1
RESERVED
R/W
GPIO_OUT
R/W
表9-46. GPIO_OUT_INV Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2-0
RESERVED
GPIO_OUT
R/W
00000
This bit is reserved
R/W
000
bit0: GPIO0 output invert
bit1: GPIO1 output invert
bit2: GPIO2 output invert
9.6.1.40 DIE_ID Register (Offset = 67h) [reset = 95h]
DIE_ID is shown in 图9-51 and described in 表9-47.
Return to 表9-6.
图9-55. DIE_ID Register
7
6
5
4
3
2
1
DIE_ID
R
表9-47. DIE_ID Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIE_ID
R
10010101
DIE ID
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9.6.1.41 POWER_STATE Register (Offset = 68h) [reset = 0x00]
POWER_STATE is shown in 图9-52 and described in 表9-48.
Return to 表9-6.
图9-56. POWER_STATE Register
7
6
5
4
3
2
1
0
STATE_RPT
R
表9-48. POWER_STATE Register Field Descriptions
Bit
7-0
Field
STATE_RPT
Type
Reset
Description
R
00000000
0: Deep sleep
1: Seep
2: HIZ
3: Play
Others: reserved
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9.6.1.42 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
AUTOMUTE_STATE is shown in 图9-53 and described in 表9-49.
Return to 表9-6.
图9-57. AUTOMUTE_STATE Register
7
6
5
4
3
2
1
0
RESERVED
R
ZERO_RIGHT_ ZERO_LEFT_M
MON
ON
R
R
表9-49. AUTOMUTE_STATE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
1
RESERVED
R
000000
This bit is reserved
ZERO_RIGHT_MON
R
R
0
0
This bit indicates the auto mute status for right channel.
0: Not auto muted
1: Auto muted
0
ZERO_LEFT_MON
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
9.6.1.43 PHASE_CTRL Register (Offset = 6Ah) [reset = 0]
PHASE_CTRL is shown in 图9-54 and described in 表9-50.
Return to 表9-6.
图9-58. PHASE_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
RAMP_PHASE_SEL
R/W
PHASE_SYNC PHASE_SYNC
_SEL
_EN
R/W
R/W
表9-50. PHASE_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-2
RESERVED
R/W
0000
This bit is reserved
RAMP_PHASE_SEL
R/W
00
Select ramp clock phase when multi devices integrated in one
system to reduce EMI and peak supply peak current. TI recommends
set all devices the same RAMP frequency and same spread
spectrum and must be set before driving device into PLAY mode if
this feature is needed.
2'b00: phase 0
2'b01: phase 1
2'b10: phase 2
2'b11: phase 3 all of above have a 45 degree of phase shift
1
0
PHASE_SYNC_SEL
PHASE_SYNC_EN
R/W
R/W
0
0
ramp phase sync sel,
0: is GPIO sync;
1: internal sync
ramp phase sync enable
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9.6.1.44 RAMP_SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
RAMP_SS_CTRL0 is shown in 图9-55 and described in 表9-51.
Return to 表9-6.
图9-59. SS_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
SS_PRE_DIV_ SS_MANUAL_
RESERVED
R/W
SS_RDM_EN
SS_TRI_EN
SEL
MODE
R/W
R/W
R/W
R/W
R/W
R/W
表9-51. RAMP_SS_CTRL0 Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R/W
0
This bit is reserved
This bit is reserved
6
5
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
0
SS_PRE_DIV_SEL
SS_MANUAL_MODE
RESERVED
0
Select pll clock divide 2 as source clock in manual mode
Set ramp ss controller to manual mode
This bit is reserved
4
0
3-2
1
00
0
SS_RDM_EN
Random SS enable
0
SS_TRI_EN
0
Triangle SS enable
9.6.1.45 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in 图9-56 and described in 表9-52.
Return to 表9-6.
图9-60. SS_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SS_RDM_CTRL
R/W
SS_TRI_CTRL
R/W
表9-52. SS_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
Add Dither
6-4
3-0
SS_RDM_CTRL
SS_TRI_CTRL
R/W
R/W
000
0000
Triangle SS frequency and range control
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9.6.1.46 SS_CTRL2 Register (Offset = 6Dh) [reset = 0xA0]
SS_CTRL2 is shown in 图9-57 and described in 表9-53.
Return to 表9-6.
图9-61. SS_CTRL2 Register
7
6
5
4
3
2
1
0
TM_FREQ_CTRL
R/W
表9-53. SS_CTRL2 Register Field Descriptions
Bit
7-0
Field
TM_FREQ_CTRL
Type
Reset
Description
R/W
10100000
Control ramp frequency in manual mode, F=61440000/N
9.6.1.47 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
SS_CTRL3 is shown in 图9-58 and described in 表9-54.
Return to 表9-6.
图9-62. SS_CTRL3 Register
7
6
5
4
3
2
1
0
TM_DSTEP_CTRL
R/W
TM_USTEP_CTRL
R/W
表9-54. SS_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SS_TM_DSTEP_CTRL
R/W
0001
Control triangle mode spread spectrum fall step in ramp ss manual
mode
3-0
SS_TM_USTEP_CTRL
R/W
0001
Control triangle mode spread spectrum rise step in ramp ss manual
mode
9.6.1.48 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
SS_CTRL4 is shown in 图9-59 and described in 表9-55.
Return to 表9-6.
图9-63. SS_CTRL4 Register
7
6
5
4
3
2
SS_TM_PERIOD_BOUNDRY
R/W
1
0
RESERVED
R/W
TM_AMP_CTRL
R/W
表9-55. SS_CTRL4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-5
4-0
TM_AMP_CTRL
R/W
01
Control ramp amp ctrl in ramp ss manual model
SS_TM_PERIOD_BOUND R/W
RY
00100
Control triangle mode spread spectrum boundary in ramp ss manual
mode
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9.6.1.49 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
CHAN_FAULT is shown in 图9-60 and described in 表9-56.
Return to 表9-6.
图9-64. CHAN_FAULT Register
7
6
5
4
3
CH1_DC_1
R
2
CH2_DC_1
R
1
CH1_OC_I
R
0
CH2_OC_I
R
RESERVED
R
表9-56. CHAN_FAULT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
CH1_DC_1
R
0000
This bit is reserved
R
R
R
0
0
0
Left channel DC fault. Once there is a DC fault, this bit sets to be 1.
Class D output sets to Hi-Z. Report by FAULT pin (GPIO). Clear this
fault by setting bit 7 of 节9.6.1.58 to 1 or this bit keeps 1.
2
1
CH2_DC_1
CH1_OC_I
Right channel DC fault. Once there is a DC fault, this bit sets to be 1.
Class D output sets to Hi-Z. Report by FAULT pin (GPIO). Clear this
fault by setting bit 7 of 节9.6.1.58 to 1 or this bit keeps 1.
Left channel over current fault. Once there is an OC fault, this bit
sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin
(GPIO). Clear this fault by setting bit 7 of 节9.6.1.58 to 1 or this bit
keeps 1.
0
CH2_OC_I
R
0
Right channel over current fault. Once there is an OC fault, this bit
sets to be 1. Class D output sets to Hi-Z. Report by FAULT pin
(GPIO). Clear this fault by setting bit 7 of 节9.6.1.58 to 1 or this bit
keeps 1.
9.6.1.50 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
GLOBAL_FAULT1 is shown in 图9-61 and described in 表9-57.
Return to 表9-6.
图9-65. GLOBAL_FAULT1 Register
7
6
5
4
3
2
1
0
OTP_CRC_ER BQ_WR_ERRO LOAD_EEPRO
RESERVED
RESERVED
CLK_FAULT_I
R
PVDD_OV_I
PVDD_UV_I
ROR
R
M_ERROR
R
R
R
R
R
R
R
表9-57. GLOBAL_FAULT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
OTP_CRC_ERROR
BQ_WR_ERROR
R
0
Indicate OTP CRC check error.
R
0
0
The recent BQ is written failed
LOAD_EEPROM_ERROR R
0: EEPROM boot load was done successfully
1: EEPROM boot load was done unsuccessfully
4
3
RESERVED
RESERVED
R
R
0
0
This bit is reserved
This bit is reserved
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表9-57. GLOBAL_FAULT1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
CLK_FAULT_I
PVDD_OV_I
PVDD_UV_I
R
0
Clock fault. Once there is a Clock fault, this bit sets to be 1. Class D
output sets to Hi-Z. Report by FAULT pin (GPIO). Clock fault works
with an auto-recovery mode, once the clock error removes, device
automatically returns to the previous state.
Clear this fault by setting bit 7 of 节9.6.1.58 to 1 or this bit keeps 1.
1
0
R
R
0
0
PVDD OV fault. Once there is an OV fault, this bit sets to be 1. Class
D output sets to Hi-Z. Report by FAULT pin (GPIO). OV fault works
with an auto-recovery mode, once the OV error removes, device
automatically returns to the previous state.
Clear this fault by setting bit 7 of 节9.6.1.58 to 1 or this bit keeps 1.
PVDD UV fault. Once there is an UV fault, this bit sets to be 1. Class
D output sets to Hi-Z. Report by FAULT pin (GPIO). OV fault works
with an auto-recovery mode, once the OV error removes, device
automatically returns to the previous state.
Clear this fault by setting bit 7 of 节9.6.1.58 to 1 or this bit keeps 1.
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9.6.1.51 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
GLOBAL_FAULT2 is shown in 图9-62 and described in 表9-58.
Return to 表9-6.
图9-66. GLOBAL_FAULT2 Register
7
6
5
4
3
2
1
0
RESERVED
R
CBC_FAULT_C CBC_FAULT_C
OTSD_I
H2_I
H1_I
R
R
R
表9-58. GLOBAL_FAULT2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
R
0000
This bit is reserved
CBC_FAULT_CH2_I
CBC_FAULT_CH1_I
OTSD_I
R
R
R
0
0
0
Right channel cycle by cycle over current fault
Left channel cycle by cycle over current fault
Over temperature shut down fault.
1
0
Once there is a OT fault, this bit sets to be 1. Class D output sets to
Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-
recovery mode, once the OV error removes, device automatically
returns to the previous state.
Clear this fault by setting bit 7 of 节9.6.1.58 to 1 or this bit keeps 1.
9.6.1.52 WARNING Register (Offset = 73h) [reset = 0x00]
WARNING is shown in 图9-63 and described in 表9-59.
Return to 表9-6.
图9-67. WARNING Register
7
6
5
4
3
2
1
0
RESERVED
R
CBCW_CH1_I CBCW_CH2_I OTW_LEVEL4_ OTW_LEVEL3_ OTW_LEVEL2_ OTW_LEVEL1_
I
I
I
I
R
R
R
R
R
R
表9-59. WARNING Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0
This bit is reserved
CBCW_CH1_I
CBCW_CH2_I
OTW_LEVEL4_I
OTW_LEVEL3_I
OTW_LEVEL2_I
OTW_LEVEL1_I
R
R
R
R
R
R
0
0
0
0
0
0
Left channel cycle by cycle over current warning
Right channel cycle by cycle over current warning
Over temperature warning leve4, 146C
Over temperature warning leve3, 134C
Over temperature warning leve2, 122C
Over temperature warning leve1, 112C
4
3
2
1
0
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9.6.1.53 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
PIN_CONTROL1 is shown in 图9-64 and described in 表9-60.
Return to 表9-6.
图9-68. PIN_CONTROL1 Register
7
6
5
4
3
2
1
0
MASK_OTSD MASK_DVDD_ MASK_DVDD_ MASK_CLK_FA RESERVED
MASK_PVDD_
UV
MASK_DC
MASK_OC
UV
OV
ULT
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
表9-60. PIN_CONTROL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
2
1
0
MASK_OTSD
R/W
0
Mask OTSD fault report
Mask DVDD UV fault report
Mask DVDD OV fault report
Mask clock fault report
This bit is reserved
MASK_DVDD_UV
MASK_DVDD_OV
MASK_CLK_FAULT
RESERVED
R/W
R/W
R/W
R
0
0
0
0
0
0
0
MASK_PVDD_UV
MASK_DC
R/W
R/W
R/W
Mask PVDD UV fault report mask PVDD OV fault report
Mask DC fault report
MASK_OC
Mask OC fault report
9.6.1.54 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
PIN_CONTROL2 is shown in 图9-65 and described in 表9-61.
Return to 表9-6.
图9-69. PIN_CONTROL2 Register
7
6
5
4
3
2
1
0
CBC_FAULT_L CBC_WARN_L CLKFLT_LATC OTSD_LATCH_ OTW_LATCH_
MASK_OTW
MASK_CBCW MASK_CBC_F
AULT
ATCH_EN
ATCH_EN
H_EN
EN
EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表9-61. PIN_CONTROL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CBC_FAULT_LATCH_EN R/W
CBC_WARN_LATCH_EN R/W
1
Enable CBC fault latch by setting this bit to 1
Enable CBC warning latch by setting this bit to 1
Enable clock fault latch by setting this bit to 1
Enable OTSD fault latch by setting this bit to 1
Enable OT warning latch by setting this bit to 1
Mask OT warning report by setting this bit to 1
Mask CBC warning report by setting this bit to 1
Mask CBC fault report by setting this bit to 1
6
5
4
3
2
1
0
1
1
1
1
0
0
0
CLKFLT_LATCH_EN
OTSD_LATCH_EN
OTW_LATCH_EN
MASK_OTW
R/W
R/W
R/W
R/W
R/W
R/W
MASK_CBCW
MASK_CBC_FAULT
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9.6.1.55 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
MISC_CONTROL is shown in 图9-66 and described in 表9-62.
Return to 表9-6.
图9-70. MISC_CONTROL Register
7
6
5
4
3
2
1
0
DET_STATUS_
LATCH
RESERVED
R/W
OTSD_AUTO_
REC_EN
RESERVED
R/W
R/W
R/W
表9-62. MISC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DET_STATUS_LATCH
R/W
0
1:Latch clock detection status
0:Don't latch clock detection status
6-5
4
RESERVED
R/W
R/W
R/W
00
These bits are reserved
OTSD auto recovery enable
This bit is reserved
OTSD_AUTO_REC_EN
RESERVED
0
3-0
0000
9.6.1.56 CBC_CONTROL Register (Offset = 77h) [reset = 0x00]
CBC_CONTROL is shown in 图9-67 and described in 表9-63.
Return to 表9-6.
图9-71. CBC_CONTROL Register
7
6
5
4
3
2
1
0
RESERVED
CBC_EN
CBC_WARN_E CBC_FAULT_E
N
N
R/W
R/W
R/W
R/W
表9-63. CBC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
R/W
00000
These bits are reserved
CBC_EN
R/W
R/W
R/W
0
0
0
Enable CBC function
Enable CBC warning
Enable CBC fault
1
CBC_WARN_EN
CBC_FAULT_EN
0
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9.6.1.57 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
FAULT_CLEAR is shown in 图9-68 and described in 表9-64.
Return to 表9-6.
图9-72. FAULT_CLEAR Register
7
6
5
4
3
2
1
0
ANALOG_FAUL
T_CLEAR
RESERVED
R/W
W
表9-64. FAULT_CLEAR Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ANALOG_FAULT_CLEAR
RESERVED
W
0
WRITE CLEAR BIT once write this bit to 1, device clears analog fault
This bit is reserved
6-0
R/W
0000000
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
This section details the information required to configure the device for several popular configurations and
provides guidance on integrating the TAS5825M device into the larger system.
10.1.1 Inductor Selections
TI requires that the peak current is smaller than the OCP (Over Current Protection) value which is 7.5 A, there
are 3 cases which cause high peak current flow through inductor.
1. During power up (idle state, no audio input), the duty cycle increases from 0 to θ.
Ipeak _ power _up ö PVDD ì C / L ìsin(1/ LìC ì
q
/ Fsw )
(1)
备注
θ=0.5 (BD Modulation), 0.14 (1SPW Modulation), 0.14 (Hybrid Modulation)
2. During music playing, some audio burst signal (high frequency) with very hard PVDD clipping causes PWM
duty cycle increase dramatically. This is the worst case and rarely happens.
Ipeak _clipping ö PVDDì(1-q)/(F ì L)
sw
(2)
3. Peak current due to Max output power. Ignore the ripple current flow through capacitor here.
Ipeak _ output _ power ö 2ì Max _Output _ Power / Rspea ker_ Load
(3)
TI suggests that inductor saturation current Isat, is larger than the amplifier peak current during power-up and
play audio.
ISAT í max(Ipeak_ power_up,I peak_clipping,Ipeak_output_ power
)
(4)
表10-1. Inductor Requirements
PVDD (V)
≤12
Switching Frequency (kHz)
Minimum Inductance (L) (µH)
384
384
4.7
10
> 12
For higher switching frequencies (Fsw), select the inductors with minimum inductance to be 384 kHz / Fsw × L.
Same PVDD and switching frequency, larger inductance means smaller idle current for lower power dissipation.
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10.1.2 Bootstrap Capacitors
The output stage of the TAS5825M uses a high-side NMOS driver, rather than a PMOS driver. To generate the
gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating
power supply for the switching cycle. Use 0.47-µF capacitors to connect the appropriate output pin (OUT_X) to
the bootstrap pin (BST_X). For example, connect a 0.47-µF capacitor between OUT_A and BST_A for
bootstrapping the A channel. Similarly, connect another 0.47-µF capacitor between the OUT_B and BST_B pins
for the B channel inverting output.
10.1.3 Power Supply Decoupling
To make sure of high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise
transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. The power supply input must be decoupled with some
good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to
the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the
PVDD pins of the device.
10.1.4 Output EMI Filtering
The TAS5825M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that
are commonly used. In other high-power applications, large toroid inductors are required for maximum power
and film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter
Design (SLOA119) for a detailed description on the proper component selection and design of an L-C filter
based upon the desired load and response.
For EMI performance and EMI Design consideration, reference to application report: TAS5825M Design
Considerations for EMC.
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10.2 Typical Applications
10.2.1 2.0 (Stereo BTL) System
In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels
are amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated
based upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered
2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
图10-1 shows the 2.0 (Stereo BTL) system application.
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图10-1. 2.0 (Stereo BTL) System Application Schematic
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10.2.2 Design Requirements
• Power supplies:
– 3.3-V supply
– 5-V to 24-V supply
• Communication: host processor serving as I2C compliant controller
• External memory (such as EEPROM and FLASH) used for coefficients.
The requirements for the supporting components for the TAS5825M device in a Stereo 2.0 (BTL) system is
provide in 表10-2.
表10-2. Supporting Component Requirements for Stereo 2.0 (BTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C1, C16
0.1 µF
22 µF
0402
0805
0603
0603
0603
0603
0805
CAP, CERM, 0.1 µF, 50 V, ±10%, X7R, 0402
CAP, CERM, 22 µF, 35 V, ±20%, JB, 0805
CAP, CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 1 µF, 16 V, ±10%, X5R, 0603
CAP, CERM, 0.47 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 0.68 µF, 50 V, ±10%, X7R, 0805
C2, C17, C37, C38
C3
4.7 µF
0.1 µF
1 µF
C4
C5, C14, C15
C6, C9, C10, C13
C41, C42, C43, C44
0.47 µF
0.68 µF
Inductor, Shielded, Ferrite, 10 µH, 4.4 A, 0.0304 Ω,
L1, L2, L3, L4
10 µH
SMD 1274AS-H-100M=P3
R1
0402
0402
RES, 0, 5%, 0.063 W, 0402
0 Ω
R20, R21, R22, R23
RES, 10.0 k, 1%, 0.063 W, 0402
10 kΩ
10.2.3 Detailed Design procedures
This Design procedures can be used for both Stereo 2.0, Advanced 2.1 and Mono Mode.
10.2.3.1 Step One: Hardware Integration
• Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
• Following the recommended component placement, board layout, and routing given in the example layout
above, integrate the device and the supporting components into the system PCB file.
– The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the
high-frequency signals, all of which go to the serial audio port. Constructing these signals to make sure
the signals are given precedent as design trade-offs are made is recommended.
– For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
10.2.3.2 Step Two: Hardware Integration
Using the TAS5825MEVM evaluation module and the PPC3 app to configure the desired device settings.
10.2.3.3 Step Three: Software Integration
• Using the End System Integration feature of the PPC3 app to generate a baseline configuration file.
• Generate additional configuration files based upon operating modes of the end-equipment and integrate
static configuration information into initialization files.
• Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
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10.2.4 Application Curves
45
10
5
PVcc=12V
TA=25èC
RL=8W
THD+N=1%, R L=8W
THD+N=10%, R L=8W
P O=1W
PO =2.5W
PO=5W
40
2
1
35
30
25
20
15
10
0.5
0.2
0.1
0.05
0.02
0.01
0.005
BTL Mode
TA=25èC
5
0
0.002
0.001
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
20
100
1k
Frequency (Hz)
10k 20k
D014
D023276
D03023
Hybrid Modulation Fsw=384kHz
PVDD=12V Hybrid Modulation Fsw=384kHz
Load=8Ω
图10-3. THD+N vs Frequency
图10-2. Output Power vs PVDD
10
10
PVcc=18V
TA=25èC
RL=8W
PVcc=24V
TA=25èC
RL=8W
P O=1W
PO =2.5W
PO=5W
P O=1W
PO =2.5W
PO=5W
5
5
2
1
2
1
0.5
0.5
0.2
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0.02
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0.02
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0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
D30062
D03029
PVDD=18V Hybrid Modulation Fsw=384kHz
PVDD=24V Hybrid Modulation Fsw=384kHz
图10-4. THD+N vs Frequency
图10-5. THD+N vs Frequency
10
10
PVCC=18V
TA=25èC
Fin=1kHz
PVCC=12V
TA=25èC
Fin=1kHz
5
5
2
1
2
1
0.5
0.5
0.2
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0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Load=4W
Load=6W
Load=8W
Load=4W
Load=6W
Load=8W
0.005
0.005
0.002
0.001
0.002
0.001
0.01
0.1
1
Output Power (W)
10
0.01
0.1
1
Output Power (W)
10 20
D101027
D010173
PVDD=12V Hybrid Modulation Fsw=384kHz
PVDD=18V Hybrid Modulation Fsw=384kHz
图10-6. THD+N vs Power
图10-7. THD+N vs Power
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10.2.5 MONO (PBTL) Systems
In MONO mode, TAS5825M can be used as PBTL mode to drive sub-woofer with more output power.
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图10-8. Sub-woofer (PBTL) Application Schematic
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表10-3. Supporting Component Requirements for Sub-woofer (PBTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C1, C2
390uF
0.1 µF
22 µF
10mmx10mm
0402
CAP, AL, 390 μF, 35 V, +/- 20%, 0.08 ohm, SMD
CAP, CERM, 0.1 µF, 50 V, ±10%, X7R, 0402
CAP, CERM, 22 µF, 35 V, ±20%, JB, 0805
CAP, CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 1 µF, 16 V, ±10%, X5R, 0603
CAP, CERM, 0.47 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 0.68 µF, 50 V, ±10%, X7R, 0805
Inductor, Shielded, 4.7 μH, 8.7 A
C4, C5
C3, C6
0805
C7
4.7 µF
0.1 µF
1 µF
0603
C8
0603
C9,C10,C11
C12,C13,C16,C17
C14,C15
L1,L2
0603
0.47 µF
0.68 µF
4.7 µH
0603
0805
R2
0402
0402
RES, 0, 5%, 0.063 W, 0402
1 kΩ
R3,R4,R5,R6
RES, 10.0 k, 1%, 0.063 W, 0402
10 kΩ
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10.2.6 Advanced 2.1 System (Two TAS5825M Devices)
In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was
done in the high-frequency channels. To accomplish this, two TAS5825M devices are used - one for the high
frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can
be sent from the TAS5825M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept
the same digital input as the stereo, which might come from a central systems processor. 图 10-9 shows the 2.1
(Stereo BTL with Two TAS5825M devices) system application.
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图10-9. 2.1 (2.1 CH with Two TAS5825M Devices) Application Schematic
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10.2.7 Application Curves
10
100
90
80
70
60
50
40
30
20
10
0
PVCC=24V
TA=25èC
PBTL Mode
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
PVDD = 12V
PVDD = 18 V
PVDD = 24 V
0.005
TA=25èC
RL=4W
Load=4W
Load=3W
0.002
0.001
0.1
1
10
20
100
0
10
20
30
40
Output Power (W)
50
60
70
80
Output Power (W)
D40087
D01240
PVDD = 18 V Hybrid Modulation Fsw = 384 kHz
Hybrid Modulation Fsw = 384 kHz
Load = 4Ω
图10-10. THD+N vs Output Power
图10-11. Efficiency vs Output Power
10.3 Power Supply Recommendations
The TAS5825M device requires two power supplies for proper operation. A high-voltage supply calls PVDD is
required to power the output stage of the speaker amplifier and the associated circuitry. Additionally, one low-
voltage power supply which is calls DVDD is required to power the various low-power portions of the device. The
allowable voltage range for both PVDD and DVDD supply are listed in the Recommended Operating Conditions
table. The two power supplies do not have a required powerup sequence. The power supplies can be powered
on in any order.
Internal Digital
Circuitry
Digital IO
DVDD
VR_DIG
1.5V
1.8V/3.3V'
LDO
External Filtering/Decoupling
DVDD
Output Stage
Power Supply
Gate Drive
Voltage
PVDD
4.5V~26.4V
GVDD
5V
LDO
LDO
External Filtering/Decoupling
Internal Analog
Circuitry
PVDD
AVDD
5V
External Filtering/Decoupling
Copyright © 2017, Texas Instruments Incorporated
图10-12. Power Supply Function Block Diagram
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10.3.1 DVDD Supply
The DVDD supply that is required from the system is used to power several portions of the device. As shown in
图 10-12, the DVDD supply provides power to the DVDD pin. Proper connection, routing and decoupling
techniques are highlighted in 节 10 and 节 10.4.2 and must be followed as closely as possible for proper
operation and performance.
Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.
To simplify the power supply requirements for the system, the TAS5825M device includes an integrated low
dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and the output is presented on the DVDD_REG pin, providing a connection point for an external bypass
capacitor. Note that the linear regulator integrated in the device has only been designed to support the current
requirements of the internal circuitry, and must not be used to power any additional external circuity. Additional
loading on this pin can cause the voltage to sag, negatively affecting the performance and operation of the
device.
10.3.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques
are highlighted in the TAS5825MEVM and must be followed as closely as possible for proper operation and
performance. Due to the high-voltage switching of the output stage, properly decoupling the output power stages
in the manner described in the TAS5825M device 节 10 is important. Lack of proper decoupling, like that shown
in the 节10, results in voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is
provided for the attachment of decoupling capacitor for the gate drive voltage regulator. Note that the linear
regulator integrated in the device has only been designed to support the current requirements of the internal
circuitry, and must not be used to power any additional external circuitry. Additional loading on this pin can cause
the voltage to sag, negatively affecting the performance and operation of the device.
Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.
AVDD pin is provided for the attachment of decoupling capacitor for the TAS5825M internal circuitry. Note that
the linear regulator integrated in the device has only been designed to support the current requirements of the
internal circuitry, and must not be used to power any additional external circuitry. Additional loading on this pin
can cause the voltage to sag, negatively affecting the performance and operation of the device.
10.4 Layout
10.4.1 Layout Guidelines
10.4.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
The guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in 节 10.4.2. These examples represent exemplary
baseline balance of the engineering trade-offs involved with lying out the device. These designs can be modified
slightly as needed to meet the needs of a given application. In some applications, for instance, solution size can
be compromised to improve thermal performance through the use of additional contiguous copper neat the
device. Conversely, EMI performance can be prioritized over thermal performance by routing on internal traces
and incorporating a via picket-fence and additional filtering components. In all cases, TI recommends to start
from the guidance shown in 节10.4.2 and work with TI field application engineers or through the E2E community
to modify the example based upon the application specific goals.
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10.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This
applies to DVDD, AVDD, GVDD and PVDD. However, the capacitors on the PVDD net for the TAS5825M device
deserve special attention.
The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as
possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in
the system, but doing so can also negatively affect the reliability of the device. Placement of these components
too far from the TAS5825M device can cause ringing on the output pins that can cause the voltage on the output
pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the
deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD
pins than what is shown in the example layouts in the 节10.4.2 section.
10.4.1.3 Optimizing Thermal Performance
Follow the layout example shown in the 图 10-13 to achieve the best balance of solution size, thermal, audio,
and electromagnetic performance. In some cases, deviation from this guidance can be required due to design
constraints which cannot be avoided. In these instances, the system designer must make sure that the heat can
get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device
naturally travels away from the device and into the lower temperature structures around the device.
10.4.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips must be followed to achieve that goal:
• Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5825M device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
• Place the TAS5825M device away from the edge of the PCB when possible to make sure that the heat can
travel away from the device on all four sides.
• Avoid cutting off the flow of heat from the TAS5825M device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
• Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient the pads so that the narrow end of the passive component is facing the
TAS5825M device.
• Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
10.4.1.3.2 Stencil Pattern
The recommended drawings for the TAS5825M device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to be an excellent choice for the majority of manufacturing capabilities in the industry and prioritizes
manufacturability over all other performance criteria. In elevated ambient temperature or under high-power
dissipation use-cases, this guidance can be too conservative and advanced PCB design techniques can be used
to improve thermal performance of the system.
备注
The customer must verify that deviation from the guidance shown in the package addendum, including
the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability
goals.
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10.4.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5825M device is soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. TI recommends to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5825M
device, be made no smaller than what is specified in the package addendum. This method makes sure that the
TAS5825M device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in 节
10.4.2, this interface can benefit from improved thermal performance.
备注
Vias can obstruct heat flow if the vias are not constructed properly.
More notes on the construction and placement of vias are as follows:
• Remove thermal reliefs on thermal vias, because the thermal reliefs impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
• The diameter of the drill must be 8 mm or less. Also, the distance between the via barrel and the surrounding
planes must be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing must be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
• Vias must be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in 节10.4.2.
• Make sure that vias do not cut off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias that are farthest from the TAS5825M device to open up the current path
to and from the device.
10.4.1.3.2.2 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the
thermal pad on the PCB is large and depositing a large, single deposition of solder paste leads to manufacturing
issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste to outgas during
the assembly process and reduce the risk of solder bridging under the device. This structure is called an
aperture array, and is shown in the 节 10.4.2 section. Make sure that the total area of the aperture array (the
area of all of the small apertures combined) covers between 70% and 80% of the area of the thermal pad itself.
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10.4.2 Layout Example
2
11cm
From
System
Processor
图10-13. 2.0 (Stereo BTL) 3-D View
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图10-14. 2.0 (Stereo BTL) Top Copper View
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
The glossary listed in 节 11 and is a general glossary with commonly used acronyms and words which are
defined in accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE,
and others. The glossary provided in this section defines words, phrases, and acronyms that are unique to this
product and documentation, collateral, or support tools and software used with this product. For any additional
questions regarding definitions and terminology, please see the e2e Audio Amplifier Forum.
Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one half-
bridge and the other terminal is connected to another half-bridge.
DUT refers to a device under test to differentiate one device from another.
Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing
the output signal to the input signal and attempts to correct for non-linearities in the output.
Dynamic controls are those which are changed during normal use by either the system or the end-user.
GPIO is a general purpose input/output pin and is a highly configurable, bi-directional digital pin, which can
perform many functions as required by the system.
Host processor (also known as System Processor, Scalar, Host, or System Controller) refers to a device,
which serves as a central system controller, providing control information to devices connected as well as
gathering audio source data from devices upstream and distributing to other devices. This device often
configures the controls of the audio processing devices (like the TAS5825M) in the audio path to optimize the
audio output of a loudspeaker based on frequency response, time alignment, target sound pressure level, safe
operating area of the system, and user preference.
Hybrid Flow uses components which are built in RAM and components which are built in ROM to make a
configurable device that is easier to use than a fully-programmable device while remaining flexible enough to be
used in several applications
Maximum continuous output power refers to the maximum output power that the amplifier can continuously
deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period
of time required that their temperatures reach thermal equilibrium and are no longer increasing
Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to
two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half
bridges placed in parallel
RDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.
Static controls/Static configurations are controls which do not change while the system is in normal use.
Vias are copper-plated through-hole in a PCB.
11.1.2 Development Support
For RDGUI software, please consult your local field support engineer.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
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链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5825MRHBR
TAS5825MRHBT
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-25 to 85
-25 to 85
5825M
5825M
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5825MRHBR
TAS5825MRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TAS5825MRHBR
TAS5825MRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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