TAS5828M [TI]
具有集成音频处理器的 50W 立体声、数字输入、高性能、闭环、D 类音频放大器;
| 型号： | TAS5828M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成音频处理器的 50W 立体声、数字输入、高性能、闭环、D 类音频放大器 放大器 音频放大器 |
| 文件： | 总91页 (文件大小：2767K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5828M
ZHCSO77A –JUNE 2021 –REVISED DECEMBER 2021
采用Hybrid-Pro 算法的TAS5828M 50W 立体声、数字输入、高效闭环D 类放大
器
1 特性
2 应用
• 灵活的音频I/O：
• 电池供电扬声器
• 无线、蓝牙扬声器
• 条形音箱和低音炮
• 散热或效率敏感型音频系统
– 支持32kHz、44.1kHz、48kHz、88.2kHz、
96kHz 和192kHz 采样速率
– 用于音频监控、子通道或回声消除的I2S、LJ、
RJ、TDM 和SDOUT
3 说明
– 支持三线制数字音频接口（无需MCLK）
• 高效D 类调制
TAS5828M 是一款立体声、高性能闭环 D 类放大器，
具有集成的音频处理器和高达192kHz 的架构。
– 电源效率高于90%，RDSon 为90mΩ
• 支持多路输出配置
软件控制模式启动后，TAS5828M 不仅实现了经典的
BQ、3 频带DRC 和AGL，还实现了Hybrid-Pro 专有
算法。Hybrid-Pro 算法可检测即将发生的音频功率需
求，并通过Hybrid-Pro 反馈引脚(HPFB) 为前直流/直
流转换器提供PWM 格式控制信号。TAS5828M 支持
用于可预测的包络跟踪、高达4ms 的音频信号延迟缓
冲器，这有助于防止因直流/直流电压调整而导致的音
频削波。
– 2 × 50W，2.0 模式(4Ω, 23 V, THD + N = 1%)
– 2 × 40W，2.0 模式(6Ω, 24V, THD + N = 1%)
– 1 × 100W，1.0 模式(2Ω, 23 V, THD + N = 1%)
– 1 × 80W，1.0 模式(3Ω, 24V, THD + N = 1%)
• 优异的音频性能：
– 1W、1kHz、PVDD = 12V 的条件下，THD + N
≤0.03%
– SNR ≥110dB（A 加权），ICN ≤40µVRMS
• 灵活处理特性
在设置为硬件控制模式时，TAS5828M 通过引脚配置
支持开关频率、模拟增益、BTL/PBTL 模式和逐周期电
流限制阈值。此模式专为免去终端系统软件驱动程序集
成工作而设计。
– 3 频带高级DRC + 2 个BQ + AGL + 2 个BQ
– 每通道12 个BQ、电平计
– 96kHz、192kHz 处理器采样
器件信息
封装(1)
– 混合器、音量、动态EQ、输出交叉开关
– PVDD 检测和Hybrid-Pro 算法音频信号跟踪
• 灵活的电源配置
封装尺寸（标称值）
器件型号
TAS5828M
TSSOP (32) DAD 11.00mm × 6.20mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– PVDD：4.5V 至26.4V
– DVDD 和I/O：1.8V 或3.3V
• 出色的集成式自保护功能：
Speaker
Channel
Speaker
Channel
L
R
– 过流错误(OCE)
– 逐周期电流限制
– 过热警告(OTW)
– 过热错误(OTE)
– 欠压和过压锁定(UVLO/OVLO)
– PVDD 压降检测
• 可轻松进行系统集成
– I2C 软件或硬件控制模式
– 与开环器件相比，所需的无源器件更少
Digital
Audio
Source
System
Processor
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEX7
TAS5828M
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ZHCSO77A –JUNE 2021 –REVISED DECEMBER 2021
Table of Contents
8.6 Register Maps...........................................................48
9 Application and Implementation..................................76
9.1 Application Information............................................. 76
9.2 Typical Applications.................................................. 78
10 Power Supply Recommendations..............................82
10.1 DVDD Supply..........................................................82
10.2 PVDD Supply..........................................................82
11 Layout...........................................................................84
11.1 Layout Guidelines................................................... 84
11.2 Layout Example...................................................... 86
12 Device and Documentation Support..........................88
12.1 Device Support....................................................... 88
12.2 Receiving Notification of Documentation Updates..88
12.3 Support Resources................................................. 88
12.4 Trademarks.............................................................89
12.5 Electrostatic Discharge Caution..............................89
12.6 Glossary..................................................................89
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings .............................................................. 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................8
6.6 Timing Requirements ...............................................12
6.7 Typical Characteristics..............................................13
7 Parameter Measurement Information..........................27
8 Detailed Description......................................................28
8.1 Overview...................................................................28
8.2 Functional Block Diagram.........................................28
8.3 Feature Description...................................................28
8.4 Device Functional Modes..........................................35
8.5 Programming and Control.........................................40
Information.................................................................... 89
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (June 2021) to Revision A (December 2021)
Page
• 将文档状态从：预告信息更改为量产数据.........................................................................................................1
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5 Pin Configuration and Functions
AGND
AVDD
GVDD
PDN
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVDD
2
PVDD
3
OUT_B+
BST_B+
PGND
4
SCL
5
SDA
6
PGND
SDIN
7
OUT_B-
BST_B-
BST_A-
OUT_A-
PGND
BCLK
LRCLK
GPIO2
GPIO1
GPIO0
ADR
8
Thermal
Pad
9
10
11
12
13
14
15
16
PGND
BST_A+
OUT_A+
PVDD
VR_DIG
DVDD
DGND
PVDD
Not to scale
图5-1. DAD (TSSOP) Package, 32-Pin PadUp, Software Mode, Top View
表5-1. Pin Functions - Software Mode
PIN
TYPE(1)
DESCRIPTION
NAME
AGND
AVDD
GVDD
PDN
NO.
1
G
P
Analog ground.
2
Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices.
Gate drive internal regulator output. This pin must not be used to drive external devices.
Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
I2C serial control clock input.
3
P
4
DI
SCL
5
DI
SDA
6
DI/O
DI
I2C serial control data interface input/output.
SDIN
BCLK
7
Data line to the serial data port.
8
DI
Bit clock for the digital signal that is active on the input data line of the serial data port.
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this
corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync
boundary.
LRCLK
9
DI
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x62h). Can be configured to be open drain output or push-pull output.
GPIO2
GPIO1
GPIO0
10
11
12
DI/O
DI/O
DI/O
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x61h). Can be configured to be open drain output or push-pull output.
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x63h). Can be configured to be open drain output or push-pull output.
ADR
13
14
AI
P
A table of resistor value (Pull down to GND) decides the device I2C address. See 表8-7.
VR_DIG
Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices.
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表5-1. Pin Functions - Software Mode (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
DVDD
DGND
NO.
15
16
17
18
31
32
21
22
27
28
19
P
G
P
P
P
P
G
G
G
G
O
3.3-V or 1.8-V digital power supply.
Digital ground.
PVDD
PGND
PVDD voltage input.
Ground reference for power device circuitry. Connect this pin to system ground.
Positive pin for differential speaker amplifier output A.
OUT_A+
BST_A+
OUT_A-
BST_A-
Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_A+.
20
23
24
P
O
P
Negative pin for differential speaker amplifier output A.
Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_A-.
Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_B-.
BST_B-
OUT_B-
BST_B+
OUT_B+
25
26
29
30
P
O
P
Negative pin for differential speaker amplifier output B.
Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_B+.
O
P
Positive pin for differential speaker amplifier output B.
PowerPAD™
Ground, connect to grounded heat sink for best system performance.
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =
Power, G = Ground (0 V)
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AGND
AVDD
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVDD
2
PVDD
GVDD
3
OUT_B+
BST_B+
PGND
PDN
4
HW_SEL0
HW_SEL1
SDIN
5
6
PGND
7
OUT_B-
BST_B-
BST_A-
OUT_A-
PGND
BCLK
8
Thermal
Pad
LRCLK
MUTE
9
10
11
12
13
14
15
16
FAULT
PD_DET
HW_MODE
VR_DIG
DVDD
PGND
BST_A+
OUT_A+
PVDD
DGND
PVDD
Not to scale
图5-2. DAD (TSSOP) Package, 32-Pin PadUp, Hardware Mode,Top View
表5-2. Pin Functions - Hardware Mode
PIN
NAME
TYPE1
DESCRIPTION
NO.
1
AGND
G
P
Analog ground.
AVDD
2
Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices.
Gate drive internal regulator output. This pin must not be used to drive external devices.
Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
GVDD
3
P
PDN
4
DI
Analog gain and BTL/PBTL mode selection in Hardware Mode . Pull up to DVDD or Pull down to ground with
different resistor. See 表8-6.
HW_SEL0
HW_SEL1
5
6
DI
DI
PWM Switching Frequency and Spread Spectrum Enable/Disable selection in Hardware Mode. Pull up to DVDD
or Pull down to ground with different resistor. See 表8-5.
SDIN
BCLK
7
8
DI
DI
Data line to the serial data port.
Bit clock for the digital signal that is active on the input data line of the serial data port.
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this
corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync
boundary.
LRCLK
MUTE
9
DI
DI
Speaker amplifier Mute. Which must be pulled low (connect to DGND) to MUTE the device and pulled high
(connected to DVDD) to exit MUTE state. In Mute state, device output keep in Hi-Z state.
10
FAULT
11
12
13
14
15
DO
DO
AI
Fault terminal,which is pulled LOW when an internal fault occurs.
PVDD Drop detection, which is pulled LOW when the PVDD drop below 8V.
Connect to DVDD directly to ensure device enter into Hardware Control Mode.
Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices.
3.3-V or 1.8-V digital power supply.
PD_DET
HW_MODE
VR_DIG
DVDD
P
P
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表5-2. Pin Functions - Hardware Mode (continued)
PIN
TYPE1
DESCRIPTION
NAME
NO.
16
17
18
31
32
21
22
27
28
19
DGND
G
P
P
P
P
G
G
G
G
O
Digital ground.
PVDD
PGND
PVDD voltage input.
Ground reference for power device circuitry. Connect this pin to system ground.
Positive pin for differential speaker amplifier output A.
OUT_A+
BST_A+
OUT_A-
BST_A-
Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_A+.
20
23
24
P
O
P
Negative pin for differential speaker amplifier output A.
Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_A-.
Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_B-.
BST_B-
OUT_B-
BST_B+
OUT_B+
25
26
29
30
P
O
P
Negative pin for differential speaker amplifier output B.
Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_B+.
O
P
Positive pin for differential speaker amplifier output B.
PowerPAD™
Ground, connect to grounded heat sink for best system performance.
1. AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional
(input and output), P = Power, G = Ground (0 V)
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6 Specifications
6.1 Absolute Maximum Ratings
Free-air room temperature 25°C (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.5
–0.3
–40
-40
MAX
UNIT
V
DVDD
PVDD
VI(DigIn)
VI(SPK_OUTxx)
TA
Low-voltage digital supply
PVDD supply
3.9
30
V
DVDD referenced digital inputs(2)
Voltage at speaker output pins
Ambient operating temperature
Operating junction temperature
Storage temperature
VDVDD + 0.5
V
32
85
V
°C
°C
°C
TJ
150
125
Tstg
–40
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) DVDD referenced digital pins include: ADR/FAULT, LRCLK, SCLK, SDIN, SDOUT, SCL, SDA, PDN
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002.(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
26.4
3.63
UNIT
V
PVDD
DVDD
V(POWER)
Power supply inputs
1.62
V
4.5V-24V Operating PVDD Range,
BTL Mode
3.2
Ω
Ω
RSPK
Minimum Speaker Load
4.5V-24V Operating PVDD Range,
PBTL Mode
1.6
VIH(DigIn)
VIL(DigIn)
LOUT
Input logic high for DVDD referenced digital inputs
Input logic low for DVDD referenced digital inputs
Minimum inductor value in LC filter under short-circuit condition
0.9 × VDVDD
DVDD
V
V
0.1 × VDVDD
1
µH
6.4 Thermal Information
TAS5828M - TSSOP32 (DAD) - 32 PINS
THERMAL METRIC(1)
UNIT
JEDEC STANDARD 4-LAYER PCB
RθJA(top)
ψJT
Junction-to-case (top) thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.2
1.2
21
°C/W
°C/W
°C/W
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Free-air room temperature 25°C, 1SPW Mode, LC filter=10uH+0.68uF, Fsw=384kHz, Class D Bandwidth=80kHz, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital I/O
Input logic high current level
for DVDD referenced digital
input pins
|IIH|
VIN(DigIn) = VDVDD
10
uA
uA
Input logic low current level
for DVDD referenced digital
input pins
|IIL|
VIN(DigIn) = 0 V
–10
Input logic high threshold for
DVDD referenced digital
inputs
VIH(Digin)
70%
80%
VDVDD
Input logic low threshold for
DVDD referenced digital
inputs
VIL(Digin)
30%
VDVDD
Output logic high voltage
level
VOH(Digin)
IOH = 4 mA
VDVDD
VDVDD
VOL(Digin)
Output logic low voltage level
20%
400
IOH = –4 mA
I2C CONTROL PORT
Allowable load capacitance
CL(I2C)
pF
for each I2C Line
fSCL(fast)
fSCL(slow)
SERIAL AUDIO PORT
Support SCL frequency
No wait states, fast mode
No wait states, slow mode
400
100
kHz
kHz
Support SCL frequency
Required LRCLK/FS to SCLK
rising edge delay
tDLY
5
ns
DSCLK
fS
fSCLK
fSCLK
Allowable SCLK duty cycle
Supported input sample rates
Supported SCLK frequencies
SCLK frequency
40%
32
60%
192
kHz
fS
32
64
24.576
MHz
AMPLIFIER OPERATING MODE AND DC PRAMETERS
Quiescent supply current of
DVDD
PDN = 2 V, DVDD = 3.3 V, Play mode,
General Audio Process flow with full DSP running
ICC
ICC
ICC
ICC
23
1
mA
mA
mA
uA
Quiescent supply current of
DVDD
PDN = 2 V, DVDD = 3.3 V,Sleep mode
Quiescent supply current of
DVDD
PDN = 2 V, DVDD = 3.3 V,Deep Sleep mode
PDN = 0.8 V, DVDD = 3.3 V,Shutdown mode
1
Quiescent supply current of
DVDD
16
PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, 1SPW
Modulation, Play Mode
Quiescent supply current of
PVDD
ICC
39
mA
PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Output Hiz
Mode
Quiescent supply current of
PVDD
ICC
ICC
ICC
11
7.5
10
mA
mA
uA
PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Sleep Mode
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Deep Sleep
Mode
Quiescent supply current of
PVDD
PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Shutdown
Mode
Quiescent supply current of
PVDD
ICC
10
uA
Value represents the "peak voltage" disregarding
clipping due to lower PVDD
Measured at 0 dB input(1FS)
AV(SPK_AMP)
Programmable Gain
Amplifier gain error
13.75
29.4
dBV
dB
Gain = 26.4dBV
0.5
ΔAV(SPK_AMP)
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C, 1SPW Mode, LC filter=10uH+0.68uF, Fsw=384kHz, Class D Bandwidth=80kHz, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
384
480
768
480
768
MAX
UNIT
kHz
kHz
kHz
kHz
kHz
Software Mode
Hardware Mode
Switching frequency of the
speaker amplifier.
fSPK_AMP
Drain-to-source on resistance
of the individual output
MOSFETs
FET + Metallization. VPVDD=24V, I(OUT)=500mA,
TJ=25℃
RDS(on)
90
mΩ
PROTECTION
Over-Current Error Threshold Speaker Output Current (Post LC filter), Speaker
OCETHRES
7.5
3.7
27
8
4
8.5
4.2
A
V
(Speaker current)
current, LC Filter=10uH+0.68uF, BTL Mode
PVDD under voltage error
threshold
UVETHRES(PVDD)
OVETHRES(PVDD)
DCETHRES
PVDD over voltage error
threshold
28.1
1.7
29.2
V
Output DC Error protection
threshold
Class D Amplifier's output DC voltage cross
speaker load to trigger Output DC Fault protection
V
Class D Amplifier's output remain at or above
DCETHRES
TDCDET
Output DC Detect time
570
165
10
ms
Over temperature error
threshold
OTETHRES
℃
℃
°C
°C
°C
°C
Over temperature error
hysteresis
OTEHystersis
OTWTHRES
OTWTHRES
OTWTHRES
OTWTHRES
Over temperature warning
level
Read by register 0x73 bit0
Read by register 0x73 bit1
Read by register 0x73 bit2
Read by register 0x73 bit3
112
122
134
146
Over temperature warning
level
Over temperature warning
level
Over temperature warning
level
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C, 1SPW Mode, LC filter=10uH+0.68uF, Fsw=384kHz, Class D Bandwidth=80kHz, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMACNE (STEREO BTL)
Measured differentially with zero input data,
programmable gain configured with 29.4dBV
analog gain, VPVDD range:12V~24V
|VOS
|
Amplifier offset voltage
5
mV
W
W
W
W
W
W
W
W
–5
VPVDD = 18 V, LC Filter=10uH+0.68uF, RSPK = 4
Ω, f = 1 KHz, THD+N =
10%
43
35
31
25
55
44
54
43
VPVDD = 18 V, LC Filter=10uH+0.68uF, RSPK = 4
Ω, f = 1 KHz, THD+N =
1%
VPVDD = 18 V, LC Filter=10uH+0.68uF, RSPK = 6
Ω, f = 1 KHz, THD+N =
10%
VPVDD = 18 V, LC Filter=10uH+0.68uF, RSPK = 6
Ω, f = 1 KHz, THD+N =
1%
PO(SPK)
Output Power (Per Channel)
VPVDD = 21 V, LC Filter=10uH+0.68uF, RSPK = 4
Ω, f = 1 KHz, THD+N =
10%
VPVDD = 21 V, LC Filter=10uH+0.68uF, RSPK = 4
Ω, f = 1 KHz, THD+N =
1%
VPVDD = 24 V, LC Filter=10uH+0.68uF, RSPK = 6 Ω,
f = 1 KHz, THD+N =
10%
VPVDD = 24 V, LC Filter=10uH+0.68uF, RSPK = 6 Ω,
f = 1 KHz, THD+N =
1%
Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz)
0.08
0.06
%
%
VPVDD = 18 V,LC Filter=10uH+0.68uF, Load=4Ω
VPVDD = 24 V,LC Filter=10uH+0.68uF,Load=6Ω
THD+NSPK
VPVDD = 18 V, LC Filter=10uH+0.68uF, Load=4 Ω,
Fsw=768kHz, BD Modulation
40
35
35
35
µVrms
µVrms
µVrms
µVrms
VPVDD = 18 V, LC Filter=10uH+0.68uF,Load=4 Ω,
Fsw=384kHz, 1SPW Modulation
Idle channel noise(Aweighted,
AES17)
ICN(SPK)
VPVDD = 24 V, LC Filter=10uH+0.68uF,,Load=6 Ω,
Fsw=768kHz, BD Modulation
VPVDD = 24 V, LC Filter=10uH+0.68uF,Load=6 Ω,
Fsw=384kHz, 1SPW Modulation
A-Weighted, -60 dBFS method. VPVDD = 24
V,Load=6Ω
Analog Gain = 29.4dBV
DR
Dynamic range
111
dB
A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=24V, load=6Ω
111
106
72
dB
dB
dB
SNR
Signal-to-noise ratio
A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=18V, Load=4Ω
Injected Noise = 1 KHz, 1 Vrms, VPVDD = 24 V,
input audio signal = digital zero
PSRR
Power supply rejection ratio
Cross-talk (worst case
between left-to-right and
right-to-left coupling)
f = 1 KHz, based on Inductor (DFEG7030D-4R7)
from Murata
X-talkSPK
100
dB
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C, 1SPW Mode, LC filter=10uH+0.68uF, Fsw=384kHz, Class D Bandwidth=80kHz, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE (MONO PBTL)
Measured differentially with zero input data,
programmable gain configured with 29.4dBV
Analog gain, VPVDD = 12V-24V range, 1SPW
mode
|VOS
|
Amplifier offset voltage
5
mV
–5
VPVDD = 24 V, RSPK = 3 Ω, f = 1KHz, THD+N =
1%
84
104
67
W
W
W
W
VPVDD = 24 V, RSPK = 3 Ω, f = 1KHz, THD+N =
10%
PO(SPK)
Output Power
VPVDD = 18 V, RSPK = 2 Ω, f = 1KHz, THD+N =
1%
VPVDD = 18 V, RSPK = 2 Ω, f = 1KHz, THD+N =
10%
80
Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz)
0.07
0.05
%
%
VPVDD = 18 V, LC-filter=10uH+0.68uF, RSPK = 2 Ω
VPVDD = 24 V, LC-filter=10uH+0.68uF, RSPK = 3 Ω
THD+NSPK
DR
A-Weighted, -60 dBFS method, VPVDD=24V, RSPK
= 3 Ω.
Dynamic range
111
108
106
72
dB
dB
dB
dB
A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=24V, RSPK = 3 Ω
SNR
Signal-to-noise ratio
Power supply rejection ratio
A-Weighted,referenced to 1% THD+N Output
Level, VPVDD=18V, RSPK = 2 Ω
Injected Noise = 1 KHz, 1 Vrms,VPVDD = 18 V,
input audio signal = digital zero
PSRR
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UNIT
ZHCSO77A –JUNE 2021 –REVISED DECEMBER 2021
6.6 Timing Requirements
MIN
NOM
MAX
Serial Audio Port Timing - Target Mode
fSCLK
tSCLK
tSCLKL
tSCLKH
tSL
SCLK frequency
1.024
40
16
16
8
MHz
ns
SCLK period
SCLK pulse width, low
ns
SCLK pulse width, high
ns
SCLK rising to LRCLK/FS edge
LRCK/FS Edge to SCLK rising edge
Data setup time, before SCLK rising edge
Data hold time, after SCLK rising edge
Data delay time from SCLK falling edge
ns
tLS
8
ns
tSU
8
ns
tDH
8
ns
tDFS
15
ns
I2C Bus Timing –Standard
fSCL
SCL clock frequency
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
4.7
tLOW
tHI
4.7
High period of the SCL clock
Setup time for (repeated) START condition
Hold time for (repeated) START condition
Data setup time
4
tRS-SU
tS-HD
tD-SU
tD-HD
tSCL-R
4.7
4
250
Data hold time
0
3450
1000
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
tSCL-R1
20 + 0.1CB
1000
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
Cb
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
4
1000
1000
1000
ns
ns
ns
µs
pf
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Capacitive load for each bus line
400
400
I2C Bus Timing –Fast
fSCL
SCL clock frequency
kHz
µs
µs
ns
ns
ns
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for (repeated)START condition
Hold time for (repeated)START condition
Data setup time
1.3
tLOW
tHI
1.3
600
tRS-SU
tRS-HD
tD-SU
tD-HD
tSCL-R
600
600
100
Data hold time
0
900
300
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
tSCL-R1
20 + 0.1CB
300
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
tSP
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
600
300
300
300
ns
ns
ns
ns
ns
pf
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Pulse width of spike suppressed
Capacitive load for each bus line
50
Cb
400
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ZHCSO77A –JUNE 2021 –REVISED DECEMBER 2021
6.7 Typical Characteristics
6.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
Free-air room temperature 25°C (unless otherwise noted). Measurements were made using Audio Precision
System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio
frequency set to 1 kHz and device PWM frequency set to 384kHz, 80 kHz Class D Amplifier Loop Bandwidth, LC
filter with 10μH / 0.68 μF, unless otherwise noted.
10
5
10
5
PVCC=12V
TA=25°C
RL=4
PVCC=12V
TA=25°C
RL=8
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
BD Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
BTL Mode
BD Modulation
FSW=384kHz Load = 8
PO=1W,2.5W,5W
BTL Mode
图6-1. THD+N vs Frequency-BTL
图6-2. THD+N vs Frequency-BTL
10
5
10
5
PVCC=18V
TA=25°C
RL=4
PVCC=18V
TA=25°C
RL=8
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
BD Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
BTL Mode
BD Modulation
FSW=384kHz Load = 8
PO=1W,2.5W,5W
BTL Mode
图6-3. THD+N vs Frequency-BTL
图6-4. THD+N vs Frequency-BTL
10
5
10
5
PVCC=24V
TA=25°C
RL=4
PVCC=24V
TA=25°C
RL=8
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
BD Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
BTL Mode
BD Modulation
FSW=384kHz Load = 8
PO=1W,2.5W,5W
BTL Mode
图6-5. THD+N vs Frequency-BTL
图6-6. THD+N vs Frequency-BTL
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20
10
5
20
10
5
PVCC=12V
TA=25C
PVCC=18V
TA=25C
BTL Mode
BTL Mode
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
Load=4
Load=6
Load=8
Load=4
Load=6
Load=8
0.002
0.001
0.0005
0.002
0.001
0.0005
0.01
0.1
1
10 20
0.01
0.1
1
10 20
Output Power (W)
Output Power (W)
BD Modulation
Load = 4, 6, 8
BD Modulation
Load = 4, 6, 8
FSW = 384 kHz
BTL Mode
FSW = 384 kHz
BTL Mode
图6-7. THD+N vs Output Power-BTL
图6-8. THD+N vs Output Power-BTL
20
10
5
100
90
80
70
60
50
40
30
20
10
0
PVCC=24V
TA=25C
BTL Mode
THD+N=1%, RL=4
THD+N=10%, RL=4
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
Load=4
Load=6
Load=8
0.002
0.001
0.0005
BTL Mode
TA=25C
0.01
0.1
1
10 20
100
Output Power (W)
4.5
8.5
12.5
16.5
20.5
24.5
28
Supply Voltage (V)
BD Modulation
FSW = 384 kHz
Load = 4, 6, 8
BTL Mode
BD Modulation
FSW=384kHz
Load = 4
BTL Mode
图6-9. THD+N vs Output Power-BTL
图6-10. Output Power vs Supply Voltage
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
THD+N=1%, RL=6
THD+N=10%, RL=6
THD+N=1%, RL=8
THD+N=10%, RL=8
BTL Mode
TA=25C
BTL Mode
TA=25C
0
0
4.5
8.5
12.5
16.5
20.5
24.5
28
4.5
8.5
12.5
16.5
20.5
24.5
28
Supply Voltage (V)
Supply Voltage (V)
BD Modulation
Load = 6
BD Modulation
Load = 8
FSW=384kHz
BTL Mode
FSW=384kHz
BTL Mode
图6-11. Output Power vs Supply Voltage
图6-12. Output Power vs Supply Voltage
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100
100
80
60
40
20
0
80
60
40
20
FSW=384k, BD Modulation
18 20 25
FSW=384k, BD Modulation
0
5
10
15
5
10
15
18 20
25
Supply Voltage (V)
Supply Voltage (V)
D03007
D00370
BD Modulation
BD Modulation
FSW=384kHz
Load = 8
BTL Mode
FSW=384kHz
Load = 4
BTL Mode
图6-14. Idle Channel Noise vs Supply Voltage
图6-13. Idle Channel Noise vs Supply Voltage
0
0
PVDD=12V. 384kHz, LC filter=10uH+0.68uF
Ch 1 to Ch 2
PVDD=24V. 384kHz, LC filter=10uH+0.68uF
Ch 1 to Ch 2
-20
-40
Ch 2 to Ch 1
-20
-40
Ch 2 to Ch 1
-60
-60
-80
-80
-100
-120
-100
-120
20
100
1k
10k
20k
Frequency (Hz)
D001
PVDD=12V
BD Modulation
20
100
1k
10k 20k
FSW=384kHz
Load = 4
BTL Mode
Frequency (Hz)
D001
图6-15. Crosstalk
PVDD=24V
BD Modulation
FSW=384kHz
Load = 4
BTL Mode
图6-16. Crosstalk
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Gain=29.5dB
TA=25C
RL=4
Gain=29.5dB
TA=25C
RL=6
PVCC = 12 V
PVCC = 16 V
PVCC = 24 V
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
D024
D024
BD Modulation
BD Modulation
FSW=384kHz
Load = 4
BTL Mode
FSW=384kHz
Load = 6
BTL Mode
图6-17. Efficiency vs Output Power
图6-18. Efficiency vs Output Power
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100
90
80
70
60
50
40
30
20
Gain=29.5dB
TA=25C
RL=8
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
10
0
0
10
20
30
40
50
60
70
80
90 100
Output Power (W)
D024
BD Modulation
FSW=384kHz
Load = 8
BTL Mode
图6-19. Efficiency vs Output Power
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6.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
Free-air room temperature 25°C (unless otherwise noted). Measurements were made using Audio Precision
System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio
frequency set to 1 kHz and device PWM frequency set to 384 kHz, 80 kHz Class D Loop Bandwidth, the LC filter
used was 10μH / 0.68 μF, unless otherwise noted.
20
20
10 PVCC=12V
10 PVCC=12V
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
TA=25°C
TA=25°C
5
5
RL=4
RL=8
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
1SPW Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
BTL Mode
1SPW Modulation
FSW=384kHz Load = 8
PO=1W,2.5W,5W
BTL Mode
图6-20. THD+N vs Frequency-BTL
图6-21. THD+N vs Frequency-BTL
20
20
10 PVCC=18V
10 PVCC=18V
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
TA=25°C
TA=25°C
5
5
RL=4
RL=8
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
1SPW Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
BTL Mode
1SPW Modulation
FSW=384kHz Load = 8
PO=1W,2.5W,5W
BTL Mode
图6-22. THD+N vs Frequency-BTL
图6-23. THD+N vs Frequency-BTL
20
20
10 PVCC=24V
10 PVCC=24V
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
TA=25°C
TA=25°C
5
5
RL=4
RL=8
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
1SPW Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
BTL Mode
1SPW Modulation
FSW=384kHz Load = 8
PO=1W,2.5W,5W
BTL Mode
图6-24. THD+N vs Frequency-BTL
图6-25. THD+N vs Frequency-BTL
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20
10
5
20
10
5
PVCC=12V
TA=25C
PVCC=18V
TA=25C
BTL Mode
BTL Mode
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
Load=4
Load=6
Load=8
Load=4
Load=6
Load=8
0.002
0.001
0.0005
0.002
0.001
0.0005
10m
100m
1
10 20
0.01
0.1
1
10 20
Output Power (W)
Output Power (W)
1SPW Modulation
Load = 4, 6, 8
1SPW Modulation
Load = 4, 6, 8
FSW = 384 kHz
BTL Mode
FSW = 384 kHz
BTL Mode
图6-26. THD+N vs Output Power-BTL
图6-27. THD+N vs Output Power-BTL
20
10
5
100
90
80
70
60
50
40
30
20
10
0
PVCC=24V
TA=25C
BTL Mode
THD+N=1%, RL=4
THD+N=10%, RL=4
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
Load=4
Load=6
Load=8
0.002
0.001
0.0005
BTL Mode
TA=25C
0.01
0.1
1
10 20
100
4.5
8.5
12.5
16.5
20.5
24.5
28
Output Power (W)
Supply Voltage (V)
1SPW Modulation
1SPW Modulation
Load = 4
FSW = 384 kHz
Load = 4, 6, 8
BTL Mode
FSW=384kHz
BTL Mode
图6-28. THD+N vs Output Power-BTL
图6-29. Output Power vs Supply Voltage
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
THD+N=1%, RL=6
THD+N=10%, RL=6
THD+N=1%, RL=8
THD+N=10%, RL=8
BTL Mode
TA=25C
BTL Mode
TA=25C
0
0
4.5
8.5
12.5
16.5
20.5
24.5
28
4.5
8.5
12.5
16.5
20.5
24.5
28
Supply Voltage (V)
Supply Voltage (V)
1SPW Modulation
Load = 6
1SPW Modulation
Load = 8
FSW=384kHz
BTL Mode
FSW=384kHz
BTL Mode
图6-30. Output Power vs Supply Voltage
图6-31. Output Power vs Supply Voltage
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100
100
80
60
40
20
0
80
60
40
20
FSW=384k, 1SPW Modulation
18 20 25
FSW=384k, 1SPW Modulation
0
5
10
15
5
10
15
18 20
25
Supply Voltage (V)
Supply Voltage (V)
D03007
D00370
1SPW Modulation
1SPW Modulation
FSW=384kHz
Load = 4
BTL Mode
FSW=384kHz
Load = 8
BTL Mode
图6-32. Idle Channel Noise vs Supply Voltage
图6-33. Idle Channel Noise vs Supply Voltage
0
0
PVDD=12V 384kHz, LC filter=10uH+0.68uF
Ch 1 to Ch 2
PVDD=24V. 384kHz, LC filter=10uH+0.68uF
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-40
-20
-40
Ch 2 to Ch 1
-60
-60
-80
-80
-100
-100
-120
20
100
1k
10k
20k
Frequency (Hz)
D001
-120
PVDD=12V
FSW=384kHz
1SPW Modulation
Load = 4
20
100
1k
10k 20k
BTL Mode
Frequency (Hz)
D001
图6-34. Crosstalk
PVDD=24V
FSW=384kHz
1SPW Modulation
Load = 4
BTL Mode
图6-35. Crosstalk - old
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Gain=29.5dB
TA=25C
RL=4
Gain=29.5dB
TA=25C
RL=6
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Output Power (W)
Output Power (W)
D024
D024
1SPW Modulation
1SPW Modulation
FSW=384kHz
Load = 4
BTL Mode
FSW=384kHz
Load = 6
BTL Mode
图6-36. Efficiency vs Output Power
图6-37. Efficiency vs Output Power
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100
90
80
70
60
50
40
30
20
Gain=29.5dB
TA=25C
RL=8
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
10
0
0
10
20
30
40
50
60
70
80
90 100
Output Power (W)
D024
1SPW Modulation
FSW=384kHz
Load = 8
BTL Mode
图6-38. Efficiency vs Output Power
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6.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
Free-air room temperature 25°C (unless otherwise noted). Measurements were made using Audio Precision
System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio
frequency set to 1 kHz and device PWM frequency set to 384 kHz, 80 kHz Class D Amplifier Loop Bandwidth,
LC filter with 10 μH / 0.68 μF （Post-Filter PBTL, the merging of the two output channels after the inductor
portion of the output filter, see details in 节9.2.4）, unless otherwise noted.
10
5
10
5
PVCC=12V
TA=25°C
RL=2
PVCC=12V
TA=25°C
RL=4
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
BD Modulation
FSW=384kHz Load = 2
PO=1W,2.5W,5W
PBTL Mode
BD Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
PBTL Mode
图6-39. THD+N vs Frequency-PBTL
图6-40. THD+N vs Frequency-PBTL
10
5
10
5
PVCC=18V
TA=25°C
RL=2
PVCC=18V
TA=25°C
RL=4
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
BD Modulation
FSW=384kHz Load = 2
PO=1W,2.5W,5W
PBTL Mode
BD Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
PBTL Mode
图6-41. THD+N vs Frequency-PBTL
图6-42. THD+N vs Frequency-PBTL
10
5
10
5
PVCC=24V
TA=25°C
RL=2
PVCC=24V
TA=25°C
RL=4
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
BD Modulation
FSW=384kHz Load = 2
PO=1W,2.5W,5W
PBTL Mode
BD Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
PBTL Mode
图6-43. THD+N vs Frequency-PBTL
图6-44. THD+N vs Frequency-PBTL
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15
15
10
5
10
PVCC=18V
TA=25C
PBTL Mode
PVCC=12V
TA=25C
PBTL Mode
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.005
0.02
0.01
0.005
Load=2
Load=3
Load=4
Load=2
Load=3
Load=4
0.002
0.001
0.002
0.001
0.01
0.1
1
10 20
100
0.01
0.1
1
10 20
Output Power (W)
Output Power (W)
BD Modulation
Load = 2, 3, 4
BD Modulation
Load = 2, 3, 4
FSW = 384 kHz
PBTL Mode
FSW = 384 kHz
PBTL Mode
图6-46. THD+N vs Output Power-PBTL
图6-45. THD+N vs Output Power-PBTL
15
195
10
THD+N=1%, RL=2
THD+N=10%, RL=2
PVCC=24V
TA=25C
PBTL Mode
180
165
150
135
120
105
90
5
2
1
0.5
0.2
0.1
0.05
75
0.02
0.01
60
45
Load=2
Load=3
Load=4
0.005
30
PBTL Mode
TA=25C
15
0.002
0.001
0
4.5
8.5
12.5
16.5
20.5
24.5
28
0.01
0.1
1
10 20
100
Supply Voltage (V)
Output Power (W)
BD Modulation
Load = 2
BD Modulation
Load = 2, 3, 4
FSW=384kHz
PBTL Mode
FSW = 384 kHz
PBTL Mode
图6-48. Output Power vs Supply Voltage
图6-47. THD+N vs Output Power-PBTL
130
100
THD+N=1%, RL=3
THD+N=10%, RL=3
THD+N=1%, RL=4
THD+N=10%, RL=4
120
110
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
PBTL Mode
TA=25C
PBTL Mode
TA=25C
4.5
8.5
12.5
16.5
20.5
24.5
28
4.5
8.5
12.5
16.5
20.5
24.5
28
Supply Voltage (V)
Supply Voltage (V)
BD Modulation
Load = 3
BD Modulation
Load = 4
FSW=384kHz
PBTL Mode
FSW=384kHz
PBTL Mode
图6-49. Output Power vs Supply Voltage
图6-50. Output Power vs Supply Voltage
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100
100
80
60
40
20
0
80
60
40
20
FSW=384k, BD Modulation
18 20 25
FSW=384k, BD Modulation
0
5
10
15
5
10
15
18 20
25
Supply Voltage (V)
Supply Voltage (V)
D03007
D00370
BD Modulation
BD Modulation
FSW=384kHz
Load = 2
PBTL Mode
FSW=384kHz
Load = 4
PBTL Mode
图6-51. Idle Channel Noise vs Supply Voltage
图6-52. Idle Channel Noise vs Supply Voltage
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
Gain=29.5dB
TA=25C
RL=2
Gain=29.5dB
TA=25C
RL=3
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
10
0
10
0
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
D024
D024
BD Modulation
BD Modulation
FSW=384kHz
Load = 2
PBTL Mode
FSW=384kHz
Load = 3
PBTL Mode
图6-53. Efficiency vs Output Power
图6-54. Efficiency vs Output Power
100
90
80
70
60
50
40
30
20
Gain=29.5dB
TA=25C
RL=4
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
10
0
0
10
20
30
40
50
60
70
80
90 100
Output Power (W)
D024
BD Modulation
FSW=384kHz
Load = 4
PBTL Mode
图6-55. Efficiency vs Output Power
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6.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
Free-air room temperature 25°C (unless otherwise noted). Measurements were made using Audio Precision
System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio
frequency set to 1 kHz and device PWM frequency set to 384 kHz, 80 kHz Class D Amplifier Loop Bandwidth,
the LC filter used was 10 μH / 0.68 μF （Post-Filter PBTL, the merging of the two output channels after the
inductor portion of the output filter, see connect method in 节9.2.4）, unless otherwise noted.
10
5
10
5
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
PVCC=12V
TA=25°C
RL=2
PVCC=12V
TA=25°C
RL=4
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
1SPW Modulation
FSW=384kHz Load = 2
PO=1W,2.5W,5W
PBTL Mode
1SPW Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
PBTL Mode
图6-56. THD+N vs Frequency-PBTL
图6-57. THD+N vs Frequency-PBTL
10
5
10
5
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
PVCC=18V
TA=25°C
RL=2
PVCC=18V
TA=25°C
RL=4
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
1SPW Modulation
FSW=384kHz Load = 2
PO=1W,2.5W,5W
PBTL Mode
1SPW Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
PBTL Mode
图6-58. THD+N vs Frequency-PBTL
图6-59. THD+N vs Frequency-PBTL
10
5
10
5
PO=1W
PO=2.5W
PO=5W
PO=1W
PO=2.5W
PO=5W
PVCC=24V
TA=25°C
RL=2
PVCC=24V
TA=25°C
RL=4
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
1SPW Modulation
FSW=384kHz Load = 2
PO=1W,2.5W,5W
PBTL Mode
1SPW Modulation
FSW=384kHz Load = 4
PO=1W,2.5W,5W
PBTL Mode
图6-60. THD+N vs Frequency-PBTL
图6-61. THD+N vs Frequency-PBTL
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15
10
5
15
10
5
PVCC=18V
TA=25C
PBTL Mode
PVCC=12V
TA=25C
PBTL Mode
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.005
0.02
0.01
0.005
Load=2
Load=3
Load=4
Load=2
Load=3
Load=4
0.002
0.001
0.002
0.001
10m
100m
1
10 20
100
0.01
0.1
1
10 20
Output Power (W)
Output Power (W)
1SPW Modulation
Load = 2, 3, 4
1SPW Modulation
Load = 2, 3, 4
FSW = 384 kHz
PBTL Mode
FSW = 384 kHz
PBTL Mode
图6-63. THD+N vs Output Power-PBTL
图6-62. THD+N vs Output Power-PBTL
15
195
10
THD+N=1%, RL=2
THD+N=10%, RL=2
PVCC=24V
TA=25C
PBTL Mode
180
165
150
135
120
105
90
5
2
1
0.5
0.2
0.1
0.05
75
0.02
0.01
60
45
Load=2
Load=3
Load=4
0.005
30
PBTL Mode
TA=25C
15
0.002
0.001
0
4.5
8.5
12.5
16.5
20.5
24.5
28
0.01
0.1
1
10 20
100
Supply Voltage (V)
Output Power (W)
1SPW Modulation
1SPW Modulation
Load = 2, 3, 4
FSW=384kHz
Load = 2
PBTL Mode
FSW = 384 kHz
PBTL Mode
图6-65. Output Power vs Supply Voltage
图6-64. THD+N vs Output Power-PBTL
195
195
THD+N=1%, RL=3
THD+N=10%, RL=3
THD+N=1%, RL=4
THD+N=10%, RL=4
180
165
150
135
120
105
90
180
165
150
135
120
105
90
75
75
60
60
45
45
30
30
PBTL Mode
TA=25C
PBTL Mode
TA=25C
15
15
0
0
4.5
8.5
12.5
16.5
20.5
24.5
28
4.5
8.5
12.5
16.5
20.5
24.5
28
Supply Voltage (V)
Supply Voltage (V)
1SPW Modulation
1SPW Modulation
FSW=384kHz
Load = 3
PBTL Mode
FSW=384kHz
Load = 4
PBTL Mode
图6-66. Output Power vs Supply Voltage
图6-67. Output Power vs Supply Voltage
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100
80
60
40
20
100
80
60
40
20
0
FSW=384k, 1SPW Modulation
15 18 20 25
FSW=384k, 1SPW Modulation
15 18 20 25
0
5
10
5
10
Supply Voltage (V)
Supply Voltage (V)
D00370
D03007
1SPW Modulation
1SPW Modulation
FSW=384kHz
Load = 4
PBTL Mode
FSW=384kHz
Load = 2
PBTL Mode
图6-69. Idle Channel Noise vs Supply Voltage
图6-68. Idle Channel Noise vs Supply Voltage
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
20
Gain=29.5dB
PVCC = 12 V
Gain=29.5dB
PVCC = 12V
TA=25C
PVCC = 18 V
10
TA=25C
PVCC = 18 V
10
RL=3
RL=2
PVCC = 24 V
PVCC = 24 V
0
0
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
D024
D024
1SPW Modulation
1SPW Modulation
FSW=384kHz
Load = 3
PBTL Mode
FSW=384kHz
Load = 2
PBTL Mode
图6-71. Efficiency vs Output Power
图6-70. Efficiency vs Output Power
100
90
80
70
60
50
40
30
20
Gain=29.5dB
TA=25C
RL=4
PVCC = 12 V
PVCC = 18 V
PVCC = 24 V
10
0
0
10
20
30
40
50
60
70
80
90 100
Output Power (W)
D024
1SPW Modulation
FSW=384kHz
Load = 4
PBTL Mode
图6-72. Efficiency vs Output Power
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7 Parameter Measurement Information
LRCK/FS
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
SCLKL
SCLKH
t
LS
SCLK
(Input)
t
t
SL
SCLK
DATA
(Input)
0.5 × DVDD
t
t
DH
SU
t
DFS
DATA
(Output)
0.5 × DVDD
图7-1. Serial Audio Port Timing in Target Mode
Repeated
START
START
STOP
t
t
t
t
P-SU
t
D-SU
D-HD
SDA-F
SDA-R
t
BUF.
SDA
t
t
t
SP
SCL-R.
RS-HD
t
LOW.
SCL
t
HI.
t
RS-SU
t
t
SCL-F.
S-HD.
图7-2. I2C Communication Port Timing Diagram
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8 Detailed Description
8.1 Overview
The TAS5828M device combines 4 main building blocks into a single cohesive device that maximizes sound
quality, flexibility, and ease of use. The 4 main building blocks are listed as follows:
• A stereo digital to PWM modulator.
• An Audio DSP subsystem.
• A flexible close-loop amplifier capable of operating in stereo or mono, at several different switching
frequencies, and with a variety of output voltages and loads.
• An I2C control port for communication with the device
The device requires only two power supplies for proper operation. A DVDD supply is required to power the low
voltage digital circuitry. Another supply, called PVDD, is required to provide power to the output stage of the
audio amplifier. Two internal LDOs convert PVDD to 5 V for GVDD and AVDD and to 1.5 V for DVDD
respectively.
8.2 Functional Block Diagram
1.5V Regulator
5V Regulator
5V Regulator
(For Digital Core)
( Analog Power Supply )
(Internal Gate Drive
Internal Voltage Supplies
I -> V
Closed Loop Class D Amplifier
Analog Gain Setting
…CDSP
Full Bridge
Power
Stage A
+
Gate
Drives
OUT_A+
OUT_A-
DAC
œ
Analog
to
Output
Current
Flexible
Monitoring
(OC protection)
Process Flow
PWM
Modulator
SCLK
LRCLK
SDIN
OUT_B+
OUT_B-
Full Bridge
Power
Stage B
Serial
Audio
Port
+
Gate
Drives
DAC
œ
Die Temperature Monitoring
and UV/OV/OT Protection
Clock Monitoring
and Error Protection
Error Reporting
SDOUT
Internal Control Registers and State Machines
GPIO0/FAULT
ADR/HW_MODE
GPIO1/PWM_CTRL
GPIO2/SDOUT
SDOUT
SCL/HW_SEL0
SDA/HW_SEL1
PDN
8.3 Feature Description
8.3.1 Power Supplies
For system design, TAS5828M needs a 3.3-V or 1.8-V supply in addition to the (typical) 12 V or 24 V power-
stage supply. Two internal voltage regulators provide suitable voltage levels for the gate drive circuitry and
internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to filter
the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and
damage to the device. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate
drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. To provide good
electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical,
independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x). The gate drive
voltages (GVDD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling
capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins
and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic
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capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the
power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the
gate-drive regulator output pin (GVDD) and the bootstrap pin. When the power-stage output is high, the
bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for
the high-side gate driver.
8.3.2 Device Clocking
The TAS5828M devices have flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface.
DACCLK
LRCLK/FS
DSPCLK
OSRCLK
DSP
(Including
interpolator)
Serial Audio
Interface (Input)
Delta Sigma
Modulator
Audio In
DAC
图8-1. Audio Flow with Respective Clocks
图8-1 shows the basic data flow and clock Distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
• SCLK (Bit Clock)
• LRCLK/FS (Left/Right Word Clock or Frame Sync)
• SDIN (Input Data)
The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP
and the DAC clock.
The TAS5828M device has an audio sampling rate detection circuit that automatically senses which frequency
the sampling rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz –
96 kHz, 176.4 kHz – 192 kHz are supported. The sampling frequency detector sets the clock for DAC and DSP
automatically.
If the input LRCLK/SCLK stopped during music playing, the TAS5828M DSP switches to sleep state and waiting
for the clock recovery (Class D output switches to Hiz automatically ), once LRCLK/SCLK recovered, TAS5828M
auto recovers to the play mode. There is no need to reload the DSP code.
8.3.3 Serial Audio Port –Clock Rates
The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK , and SDIN. SCLK is the
serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio
interface. Serial data is clocked into the TAS5828M device with SCLK. The LRCLK/FS pin is the serial audio left/
right word clock or frame sync when the device is operated in TDM Mode.
表8-1. Audio Data Formats, Bit Depths and Clock Rates
MAXIMUM LRCLK/FS FREQUENCY
FORMAT
DATA BITS
SCLK RATE (fS)
(kHz)
32 to 192
32
I2S/LJ/RJ
32, 24, 20, 16
64, 32
128
44.1,48
96
128,256,512
128,256
128
TDM
32, 24, 20, 16
192
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When Clock halt, non-supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in
Register 113 (Register Address 0x71).
8.3.4 Clock Halt Auto-recovery
As some of host processor will Halt the I2S clock when there is no audio playing. When Clock halt, the device
puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After audio
clocks recovery, the device automatically returns to the previous state.
8.3.5 Sample Rate on the Fly Change
TAS5828M supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32kHz to 48kHz or
96kHz or 192kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 100us before
changing to the new sample rate.
8.3.6 Serial Audio Port - Data Formats and Bit Depths
The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and
TDM/DSP data. Data formats are selected via Register (Register Address 0x33h -D[5:4]). If the high width of
LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, the register (Register Address 0x33h -D[3:2]) should
set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted.
All the data formats, word length and clock rate supported by this device are shown in Table 1. The data formats
are detailed in 图 8-2 through 图 8-6. The word length are selected via Register (Register Address 0x33h -
D[1:0]). The offsets of data are selected via Register (Register Address 0x33h -D[7]) and Register (Register
Address 0x34h -D[7:0]). Default setting is I2S and 24 bit word length.
1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
1
1
2
2
2
15 16
MSB
LSB
MSB
MSB
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
23 24
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
31 32
MSB
LSB
LSB
图8-2. Left Justified Audio Data Format
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1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
1
1
2
2
2
15 16
MSB LSB
MSB LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
23 24
MSB
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
31 32
MSB
MSB
LSB
LSB
I2S Data Format; L-channel = LOW, R-channel = HIGH
I2S Data Format; L-channel = LOW, R-channel = HIGH
图8-3. I2S Audio Data Format
1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
2
15 16
MSB LSB
MSB LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
1
2
23 24
MSB
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
1
2
31 32
MSB
MSB
LSB
LSB
Right-Justified Data Format; L-channel = HIGH, R-channel = LOW
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
图8-4. Right Justified Audio Data Format
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1 /fS .
LRCK/FS
…
…
…
…
…
…
SCLK
Audio data word = 16-bit, Offset = 0
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
Data Slot 2
LSB
MSB
LSB
MSB
Audio data word = 24-bit, Offset = 0
,
-
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 0
…
…
1
2
31 32
LSB
1
2
31 32
LSB
DATA
MSB
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
图8-5. TDM 1 Audio Data Format
1 /fS .
OFFSET = 1
LRCK/FS
…
…
…
…
…
SCLK
Audio data word = 16-bit, Offset = 1
…
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
LSB
Data Slot 2
LSB
MSB
MSB
Audio data word = 24-bit, Offset = 1
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
Data Slot 2
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 1
…
…
1
2
31 32
LSB
1
2
31 32
DATA
Data Slot 1
Data Slot 2
LSB
MSB
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
图8-6. TDM 2 Audio Data Format
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8.3.7 Digital Audio Processing
TAS5828M digital audio processing includes three main functions: basic audio tuning blocks, Hybrid-Pro
algorithm and advanced features.
Basic audio tuning blocks are SRC (sample rate converter), stereo channel Input Mixer, 15 BQs for each
channel, pop click free Volume, multi-bands DRC, and AGL. Detailed introduction of each block can be found
with TAS5825M Process Flows.
Hybrid-Pro can be used in conjunction with Hybrid Modulation, which is an innovative Class-D internal PWM
modulation scheme to improve efficiency even more without compromising THD+N performance. Hybrid-Pro
goes beyond Hybrid PWM modulation from system efficiency perspective, by tracking audio signal envelope with
advanced look-ahead DSP structure, controlling the external PVDD supply voltage rail, and maintaining just
enough margin to provide high dynamic range without clipping distortion to save as much power as possible.
Refer TAS5828M User Guide for more configurable options:
• Optional 8 steps 384 kHz PWM format or 16 steps 192 kHz PWM format Hybrid-Pro control waveform for
external DC-DC converter.
• Configurable max 4 ms look-ahead audio signal delay buffer, which provides capability to fit various
applications systems' DC-DC bandwidth and power supply coupling capacitance.
• Max 512 samples audio signal peak hold to optimize power supply voltage rail transition from large audio
input to small level, which is useful to avoid clipping distortion.
• Hybrid-Pro Margin automatically adjusts audio signal trigger level and each step level. Fine tune it to achieve
the balance between efficiency and envelope tracking speed.
Advanced features include PVDD Sensing (Dynamic Headroom Tracking), Thermal Foldback and Hybrid PWM
modulation. They are implemented based on integrated 8-bit PVDD sense ADC and 4 level temperature sensor.
Refer to application note:TAS5825M Advanced Features.
8.3.8 Class D Audio Amplifier
Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose
first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two
pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker
amplifier. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and
increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D
amplifier section of the device. The gain structures are discussed in detail below for both 图 8-7 and 表 8-2. The
switching rate of the amplifier is configurable by register (Register Address 0x02h -D[6:4])
8.3.8.1 Speaker Amplifier Gain Select
A combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. As
seen in 图 8-7, the audio path of the TAS5828M consists of a digital audio input port, a digital audio path, a
digital to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds
the output information back into the DPC block to correct for distortion sensed on the output pins. The total
amplifier gain is comprised of digital gain, shown in the digital audio path and the analog gain from the input of
the analog modulator to the output of the speaker amplifier power stage.
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DSP Volume
DAC Volume
Analog Gain
Book 0x78, Page 0x2A
Register 0x24/0x28/0x30
Book 0x00, Page 0x00
Register 0x4C
Book 0x00, Page 0x00
Register 0x54
I -> V
Closed Loop Class D Amplifier
Analog Gain Setting
…DSP
Full Bridge
Power
Stage A
+
Gate
Drives
OUT_A+
OUT_A-
DAC
œ
Analog
Output
Current
Monitoring
(OC protection)
SCLK
LRCLK
SDIN
Serial
Audio
Port
ROM Fixed
Process Flow
to
PWM
Modulator
OUT_B+
OUT_B-
Full Bridge
Power
Stage B
+
Gate
Drives
DAC
œ
图8-7. Speaker Amplifier Gain
As shown in 图 8-7, the first gain stage for the speaker amplifier is present in the digital audio path. It consists of
the volume control and the digital boost block. The volume control is set to 0 dB by default, it does not change.
For all settings of the register 0x54, AGAIN[4:0], the digital boost block remains at 0 dB. These gain settings
ensure that the output signal is not clipping at different PVDD levels. 0dBFS output is 29.5-V peak output voltage
表8-2. Analog Gain Setting
AMPLIFIER OUTPUT PEAK
VOLTAGE (VP/FS)
AMPLIFIER OUTPUT PEAK
VOLTAGE (dBVP/FS)
AGAIN <4:0>
GAIN (dBFS)
00000
00001
00010
00011
…….
0
29.5
27.85
26.29
24.82
…….
4.95
29.4
28.9
28.4
27.9
…….
13.9
-0.5
-1.0
-1.5
……..
-15.5
11111
8.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
TAS5828M closed loop structure provides Loop bandwidth setting option (Setting by register 83 -Register
address 0x53h-D[6-5]) to co-work with different switching frequency (Setting by register 2 -Register address
0x02h-D[6-4] ). 表8-3 shows recommended settings for the Loop Bandwidth and Switching Frequency selection.
Same Fsw, Better THD+N performance with higher BW.
表8-3. Loop Bandwidth and Switching Frequency Setting
Modulation
Scheme
Fsw
BW (Loop Band Width)
Notes
384kHz
480kHz
576kHz
768kHz
384kHz
480kHz
576kHz
768kHz
80kHz
80kHz, 100kHz
Principle: Fsw (Switching Frequency) ≥4.2 × Loop
Hybrid, 1SPW
Bandwidth
80kHz, 100kHz, 120kHz
80kHz, 100kHz, 120kHz, 175kHz
80kHz, 100kHz, 120kHz
80kHz, 100kHz, 120kHz
80kHz, 100kHz, 120kHz, 175kHz
80kHz, 100kHz, 120kHz, 175kHz
Principle: Fsw (Switching Frequency) ≥3 × Loop
BD
Bandwidth
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8.4 Device Functional Modes
8.4.1 Software Control
The TAS5828M device is configured via an I2 C communication port.
The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements
are described in the .Timing Requirements - I2C Bus Timing.
8.4.2 Speaker Amplifier Operating Modes
The TAS5828M device can be configured as two different amplifier configurations through Register 0x02h -D[2]:
• BTL Mode
• PBTL Mode
8.4.2.1 BTL Mode
In BTL mode, the TAS5828M amplifies two independent signals, which represent the left and right portions of a
stereo signal. The amplified left signal is presented on differential output pair shown as OUT_A+ and OUT_A-,
the amplified right signal is presented on differential output pair shown as OUT_B+ and OUT_B-.
8.4.2.2 PBTL Mode
The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in
parallel with one another to increase the power sourcing capabilities of the device. On the output side of the
TAS5828M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter
Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the inductor
portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive
inductors to be used because the current is divided between the two inductors. The process is called Post-Filter
PBTL. On the input side of the TAS5828M device, the input signal to the PBTL amplifier is left frame of I2S or
TDM data.
8.4.3 Low EMI Modes
TAS5828M employs several modes to minimize EMI during playing audio, and they can be used based on
different applications.
8.4.3.1 Spread Spectrum
Spread spectrum is used in some inductor free or inductor less case to minimize EMI noise. The TAS5828M
supports Spread Spectrum with triangle mode.
User need configure register SS_CTRL0 (0x6B) to Enable triangle mode and enable spread spectrum, select
spread spectrum frequency and range with SS_CTRL1 (0x6C). For 768kHz FSW which configured by
DEVICE_CTRL1 (0x02), the spread spectrum frequency and range are described in 表8-4.
表8-4. Triangle Mode Spread Spectrum Frequency and Range Selection
SS_TRI_CTRL[3:0]
0
1
2
3
4
5
6
7
Triangle Freq
24k
48k
Spread Spectrum
Range
5%
10%
20%
25%
5%
10%
20%
25%
User Application example: Central Switching Frequency is 768kHz, Triangle Frequency is 48kHz.
Register 0x02 = 0x41 // 768kHz Fsw, BTL Mode, 1SPW mode.
Register 0x6b = 0x03 // Enable Spread Spectrum
Register 0x6c = 0x03 // SS_CTRL[3:0]=0011, Triangle Frequency = 48kHz, Spread Spectrum Range should be
10% (729kHz~807kHz)
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8.4.3.2 Channel to Channel Phase Shift
This device supports channel to channel 180-degree PWM phase shift to minimize the EMI. Bit 0 of Register
0x53 can be used to disable or enable the phase shift.
8.4.3.3 Multi-Devices PWM Phase Synchronization
TAS5828M support up to 4 phases selection for the multi devices application system. For example, when a
system integrated 4 TAS5828M devices, user can select phase0/1/2/3 for each device by register
PHASE_CTRL(0x6A), which means there is a 45 degree phase shift between each device to minimize the EMI.
There are two methods for Multi-Device PWM phase synchronization. Phase Synchronization With I2S Clock In
Startup Phase or Phase Synchronization With GPIO.
8.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
1. Step 1, Halt I2S clock.
2. Step 2, Configure each device phase selection and enable the phase synchronization. For example:
Register 0x6A=0x03 for device 0; Register 0x6A=0x07 for device 1; Register 0x6A=0x0B for device 2;
Register 0x6A=0x0F for device 3.
3. Step 3, Configure each device into HIZ mode.
4. Step 4, Provide I2S to each device. Phase synchronization for all 4 devices is automatically done by internal
sequence.
5. Step 5, Initialize the DSP code (This step can be skipped if only need to do the Phase Synchronization).
6. Step 6, Device to Device PWM phase shift should be fixed with 45 degree.
8.4.3.3.2 Phase Synchronization With GPIO
1. Step 1, Connect GPIOx pin of each device to the SOC GPIO pin on PCB.
2. Step 2, Configure each device GPIOx as phase sync input usage by registers GPIO_CTRL (0X60) and
GPIO_INPUT_SEL (0x64).
3. Step 3, Select different phase for each device and enable phase synchronization by register PHASE_CTRL
(0x6A).
4. Step 4, Configure each device into PLAY mode by register DEVICE_CTRL2 (0x03) and monitor the
POWER_STATE register (0x68) until device changed to HIZ state.
5. Step 5, Give a 0 to 1 toggle on SOC GPIO. Then all 4 devices nter into PLAY mode, and device-to-device
PWM phase shift should be fixed with 45 degree.
6. Step 6, Phase Synchronization has been finished. Configure the GPIOx pin to other function based on the
application.
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8.4.4 Thermal Foldback
The Thermal Foldback (TFB) is designed to protect TAS5828M from excessive die temperature increases, in
case the device operates beyond the recommended temperature/power limit, or with a weaker thermal system
design than recommended. It allows the TAS5828M to play as loud as possible without triggering unexpected
thermal shutdown. When the die temperature triggers the over-temperature warning (OTW) level (TAS5828M
has four different temperature threshold, each threshold is indicated in I2C register 0x73 bits 0,1,2 and 3 ), an
internal AGL (Automatic Gain Limiter) reduces the digital gain gradually, lower value of OTW, smaller attenuation
added, with the OTW waring goes higher, more attenuation added. Once the die temperature drops below the
OTW, the device’s digital gain gradually returns to the former setting. Both the attenuation gain and adjustable
rate are programmable. The TFB gain regulation speed (attack rate and release rate) settings are the same as a
regular AGL, which is also configurable with TAS5828M App in PurePathTM Console3.
8.4.5 Device State Control
Except Shutdown Mode, TAS5828M has other 4 states for different power dissipation which listed in the
Electrical Characteristics Table.
• Deep Sleep Mode. Register 0x03h -D[1:0]=00, Device stays in Deep Sleep Mode. In this mode, I2 C block
keep works. This mode can be used to extend the battery life time in some portable speaker application case,
once the host processor stopped playing audio for a long time, TAS5828M can be set to Deep Sleep Mode to
minimize power dissipation until host processor start playing audio again. Device returns back to Play Mode
by setting Register 0x03h -D[1:0] to 11. Compare with Shutdown Mode (Pull PDN Low), enter or exit Deep
Sleep Mode, DSP keeps active.
• Sleep Mode. Register 0x03h -D[1:0]=01, Device stays in Sleep Mode. In this mode, I2 C block, Digital core,
DSP Memory , 5 V Analog LDO keep works. Compare with Shutdown Mode (Pull PDN Low), enter or exit
Sleep Mode, DSP keeps active.
• Output Hiz Mode. Register 0x03h -D[1:0]=10, Device stays in Hiz Mode. In this mode, Only output driver set
to be Hiz state, all other block work normally.
• Play Mode. Register 0x03h -D[1:0]=11, Device stays in Play Mode.
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8.4.6 Device Modulation
TAS5828M has 3 modulation schemes: BD modulation, 1SPW modulation and Hybrid modulation. Select
modulation schemes for TAS5828M with Register 0x02 [1:0]-DAMP_MOD.
8.4.6.1 BD Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
图8-8. BD Mode Modulation
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8.4.6.2 1SPW Modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In Low Idle Current mode the
outputs operate at ~17% modulation during idle conditions. When an audio signal is applied, one output
decreases and one increases. The decreasing output signal rails to GND. At this point all the audio modulation
takes place through the rising output. The result is that only one output is switching during a majority of the audio
cycle. Efficiency is improved in this mode due to the reduction of switching losses.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
图8-9. 1SPW Mode Modulation
8.4.6.3 Hybrid Modulation
Hybrid Modulation is designed for minimized power loss without compromising the THD+N performance, and is
optimized for battery-powered applications. With Hybrid modulation, TAS5828M detects the input signal level
and adjust PWM duty cycle dynamically based on PVDD. Hybrid modulation achieves ultra low idle current and
maintains the same audio performance level as the BD Modulation.
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备注
As Hybrid Modulation need the internal DSP to detect the input signal level and adjust PWM duty
cycle dynamically. To use the Hybrid Modulation, users need to select the corresponding process
flows which support Hybrid Modulation in TAS5828M PPC3 App. Look into TAS5828M PPC3 App for
more information about TAS5828M flexible audio process flows.
8.5 Programming and Control
8.5.1 I2 C Serial Communication Bus
The device has a bidirectional serial control interface that is compatible with I2C bus protocol and supports 100
and 400-kHz data transfer rates for random and sequential write and read operations as a target device.
Because the TAS5828M register map and DSP memory spans multi pages, the user should change from page
to page before writing individual register or DSP memory. Changing from page to page is accomplished via
register 0 on each page. This register value selects the page address, from 0 to 255. All registers listed in
TAS5828M Datasheet belongs to Page 0
8.5.2 Hardware Control Mode
For the system which does not require the advanced flexiblity of the I2C registers control or does not have an
avaliable I2C host controller, the TAS5828M can be used in Hardware Control Mode. Then the device operates
in Hardware mode default configurations and any change is accomplished via the Hardware control pins. The
audio performance between Hardware and Software Control mode with same configuration is identical, however
more features are accessible under Software Control Mode through registers.
Several I/O's on the TAS5828M need to be took into consideration during schematic design for desired startup
settings. The method going into Hardware Control Mode is to pull high HW_MODE pin13 to DVDD.
The TAS5828M default Hardware configuration with optimized audio, thermal and BOM is BTL mode, 768-kHz
switching frequency, 1 SPW mode, 175 kHz Class D amplifier loop bandwidth, 29.5 Vp/FS analog gain, CBC
threshold with 80% of OCP threshold. It requires the HW_SEL0 pin 5 and HW_SEL1 pin 6 directly tied low GND.
表8-5. Hardware Control - HW_SEL0 Pin5
Pin Configuration
0 Ωto GND
Analog Gain
29.5 VP/FS
20.9 VP/FS
14.7 VP/FS
7.4 VP/FS
H-Bridge Output Configuration
BTL
BTL
1 kΩto GND
BTL
4.7 kΩto GND
15 kΩto GND
33 kΩto DVDD
6.8 kΩto DVDD
1.5 kΩto DVDD
0 Ωto DVDD
BTL
7.4 VP/FS
PBTL
PBTL
PBTL
PBTL
14.7 VP/FS
20.9 VP/FS
29.5 VP/FS
表8-6. Hardware Control - HW_SEL1 Pin6
Pin Configuration
FSW&Class D Loop
Bandwidth
Cycle By Cycle Current
Limit Threshold
Spread Spectrum
Modulation
768 kHz FSW, 175 kHz BW CBC Threshold = 80%
OCP
Disable
1SPW
0 Ωto GND
768 kHz FSW, 175 kHz BW CBC Disable
Disable
Disable
1SPW
1SPW
1 kΩto GND
768 kHz FSW, 175 kHz BW CBC Threshold = 40%
OCP
4.7 kΩto GND
768 kHz FSW, 175 kHz BW CBC Threshold = 60%
OCP
Disable
Enable
1SPW
BD
15 kΩto GND
33 kΩto DVDD
480 kHz FSW, 100 kHz BW CBC Disable
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表8-6. Hardware Control - HW_SEL1 Pin6 (continued)
Pin Configuration
FSW&Class D Loop
Bandwidth
Cycle By Cycle Current
Limit Threshold
Spread Spectrum
Modulation
480 kHz FSW, 100 kHz BW CBC Threshold = 80%
OCP
Enable
BD
BD
BD
6.8 kΩto DVDD
1.5 kΩto DVDD
0 Ωto DVDD
480 kHz FSW, 100 kHz BW CBC Threshold = 40%
OCP
Enable
480 kHz FSW, 100 kHz BW CBC Threshold = 60%
OCP
Enable
Example 1:
BTL Mode, FSW = 768 kHz, 1 SPW Modulation, 175 kHz Loop Bandwidth, CBC Threshold = 80% OCP, Analog
Gain = 29.5 VP/FS, Spread spectrum disable.
图8-10. Typical Hardware Control Mode Application Schematic-BTL Mode
0.1
F
22
F
390 F
32-Pin I TSSOP I PadUp
Top View
1
F
1 F
PVDD
PVDD
AGND
AVDD
PDN
DVDD
DVDD
DVDD
10 ꢀ
GVDD
PDN
OUT_B+
BST_B+
0.68
F
R2
R1
R4
R3
HW_SEL0
HW_SEL1
SDIN
PGND
PGND
SDIN
SCLK
10 ꢀ
OUT_B-
BST_B-
BST_A-
0.68
0.68
F
F
SCLK
LRCLK
DVDD DVDD
DVDD
LRCLK
10 ꢀ
OUT_A-
MUTE
FAULT
MUTE
FAULT
PGND
PGND
BST_A+
PD_DET
PD_DET
DVDD
HW_MODE
10 ꢀ
F
0.47
VR_DIG
DVDD
OUT_A+
PVDD
0.68
F
DVDD
1
F
DGND
PVDD
0.1
F
4.7
F
390
F
22
F
0.1
F
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Example 2:
PBTL Mode, FSW = 768 kHz, 1 SPW Modulation, 175 kHz Loop Bandwidth, CBC Threshold = 80% OCP,
Analog Gain = 29.5 VP/FS, Spread spectrum disable.
图8-11. Typical Hardware Control Mode Application Schematic-PBTL Mode
0.1
F
22
F
390 F
32-Pin I TSSOP I PadUp
Top View
1
F
1 F
PVDD
PVDD
AGND
AVDD
PDN
DVDD
DVDD
DVDD
10 ꢀ
GVDD
PDN
OUT_B+
BST_B+
0.68
F
R2
R1
R4
R3
HW_SEL0
HW_SEL1
SDIN
PGND
PGND
SDIN
SCLK
10 ꢀ
OUT_B-
BST_B-
BST_A-
0.68
0.68
F
F
SCLK
LRCLK
DVDD DVDD
DVDD
LRCLK
10 ꢀ
OUT_A-
MUTE
FAULT
MUTE
FAULT
PGND
PGND
BST_A+
PD_DET
PD_DET
DVDD
HW_MODE
F
0.47
VR_DIG
DVDD
OUT_A+
PVDD
0.68
F
DVDD
1
F
DGND
PVDD
0.1
F
4.7
F
390
F
22
F
0.1
F
8.5.3 I2 C Target Address
The TAS5828M device has 7 bits for the target address. The user-defined address through ADR pin is listed in
表8-7.
表8-7. I2 C Target Address Configuration
ADR PIN Configuration
0 Ω to GND
MSBs
User Define
LSB
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
1kΩ to GND
4.7kΩ to GND
15kΩ to GND
33kΩ to DVDD
6.8kΩ to DVDD
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8.5.3.1 Random Write
As shown in 图 8-12, a single-byte data-write transfer begins with the controller device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the controller transmits the address
byte corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the controller device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the controller device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图8-12. Random Write Transfer
8.5.3.2 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the controller to the device as shown in 图 8-13. After receiving each data byte, the device
responds with an acknowledge bit and the I2 subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
R/W ACK
A4 A3
A0
ACK
ACK
ACK
ACK
D0
A6
A1
A7
A6
A5
A1
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
图8-13. Sequential Write Transfer
8.5.3.3 Random Read
As shown in 图 8-14, a single-byte data-read transfer begins with the controller device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the
device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the
controller device transmits another start condition followed by the address and the read/write bit again. This time
the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device
again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address
being read. After receiving the data byte, the controller device transmits a not-acknowledge followed by a stop
condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
Subaddress
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Data Byte
图8-14. Random Read Transfer
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8.5.3.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the controller device as shown in 图8-15. Except for the last data byte, the controller
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
sub address by one. After receiving the last data byte, the controller device transmits a not-acknowledge
followed by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
图8-15. Sequential Read Transfer
8.5.3.5 DSP Memory Book, Page and BQ update
On Page 0x00 of each book, Register 0x7f is used to change the book. Register 0x00 of each page is used to
change the page. To change a Page first write 0x00 to Register 0x00 to switch to Page 0 then write the book
number to Register 0x7f on Page 0. To switch between pages in a book, simply write the page number to
register 0x00.
All the Biquad Filters coefficients are addressed in book 0xAA. The five coefficients of every Biquad Filter should
be written entirely and sequentially from the lowest address to the highest address. The address of all Biquad
Filters can be found in Register Maps
All DSP/Audio Process Flow Related Register are listed in Application Note, TAS5825M Process Flows
8.5.3.6 Checksum
This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an
Exclusive (XOR) checksum. Register reads do not change checksum, but writes to even nonexistent registers
changes the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.
The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00) to their respective 4-byte register
locations.
8.5.3.6.1 Cyclic Redundancy Check (CRC) Checksum
The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell
delineation, (1 + x1 + x2 + x8)). A major advantage of the CRC checksum is that it is input order sensitive. The
CRC supports all I2C transactions, excluding book and page switching. The CRC checksum is read from register
0x7E on page0 of any book (B_x, Page_0, Reg_126). The CRC checksum can be reset by writing 0x00 to the
same register locations where the CRC checksum is valid.
8.5.3.6.2 Exclusive or (XOR) Checksum
The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with
the previous 8-bit checksum register value. XOR supports only Book 0x8C, and excludes page switching and all
registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book
0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the same register
location where it is read.
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8.5.4 Control via Software
• Startup Procedures
• Shutdown Procedures
8.5.4.1 Startup Procedures
1. Configure ADR pin with proper setting for I2C device address or Hardware Mode with proper HW_SEL0 and
HW_SEL1 settings.
2. Bring up power supplies (it does not matter if PVDD or DVDD comes up first).
3. Once power supplies are stable, wait at least 100 μs, bring up PDN to High to enable internal LDO.
4. I2C control port to configure desired settings. This process includes Deep Sleep to Hiz, register map
configurations, DSP coefficients, and set into Play mode. Hardware Mode does not need this step I2C
writing.
5. Once I2S clocks are stable, TAS5828M is going to normal operation music playing.
Ini aliza on
Normal Opera on
DVDD
PVDD
0 ns
100 ns
PDNz
I2C
0 ns
Deep sleep
(Page-0)
HiZ - DSP enable
(Page-0)
DSP ready to con gure
Play
I2S
I2S
I2S
I2S
I2S
I2S
I2S
No special sequence requirement for I2S, but it’s necessary to be ready before Play mode.
Otherwise, TAS5828M will go into Clock Fault Status.
图8-16. TAS5828M Startup Sequence
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8.5.4.2 Shutdown Procedures
1. The device is in normal operation.
2. Configure the Register 0x03h -D[1:0]=10 (Hiz) via the I2C control port or Pull PDN low.
3. Wait at least 6ms (this time depends on the LRCLK rate ,digital volume and digital volume ramp down rate).
4. Bring down power supplies.
5. The device is now fully shutdown and powered off.
PDN
6ms
4.5V
PVDD
0ms
DVDD
6ms
I2C
I2C
I2C
I2C
Output Hiz
ñ
ñ
Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I2C.
At least 6ms delay needed based on LRCLK (Fs) = 48kHz,Digital volume ramp down update every sample period,
decreased by 0.5dB for each update, digital volume =24dB. Change the value of register 0x4C and 0x4E or change
the LRCLK rate, the delay changes.
图8-17. Power-Down Sequence
8.5.5 Protection and Monitoring
8.5.5.1 Overcurrent Limit (Cycle-By-Cycle)
In stead of direct Overcurrent Shutdown to mute audio output, TAS5828M also provides CBC current limiting
protection. The purpose is to reduce output current ahead of Overcurrent Shutdown level by insert pulse into
PWM switching, and the thredhold (list in Electrical Characteristics - OCETHRES) is configurable through Register
0x77h -D[4:3] Reg_CBC_Level_Sel.
The overall effect on the audio is quite similar a voltage-clipping, which temporarily limits music signal peak
power to maintain continues music playing without disruption on removal of the overload.
8.5.5.2 Overcurrent Shutdown (OCSD)
If there is severe short-circuit event, such as output short to PVDD or ground, the TAS5828M starts shutdown
process less than 100ns once peak-current detector is over Overcurrent Threshold (list in Electrical
Characteristics - OCETHRES ). The shutdown speed depends on a number of factors, such as the impedance of
the short circuit, supply voltage, and switching frequency.
If an OCSD event occurs, the fault GPIO is pulled low and I2C fault register fault status is reported, then outputs
transfer to high impedance Hiz status, signifying a fault. This is a latched error, and the user needs to restart
output via I2C clear fault operation.
8.5.5.3 DC Detect Error
If the TAS5828M detects a DC offset in the output voltage cross speaker over DC error protection threshold
DCRTHRES, and this status period is over TDCDET (list in Electrical Characteristics - Protection), the FAULTZ line
is pulled low and the OUTxx outputs transition to high impedance, signifying a fault. This latched DC Protection
error requires I2C clear fault operation to restart audio output.
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8.5.5.4 Overtemperature Shutdown (OTSD)
The TAS5828M device continuesly monitors die temperature to ensure it does not exceed the over temperature
threshold specified in Electrical Characteristics - OCETHRES. If an OTE event occurs, the fault GPIO is pulled low
and I2C fault status is reported, then audio output trasfers to high empedance Hiz mode, signifying a fault. This is
a latched error, and it requires I2C clear fault operation to restart audio playing.
8.5.5.5 PVDD Overvoltage and Undervoltage Error
If the voltage presented on the PVDD supply rises over the OVETHRES(PVDD) or drops below the UVETHRES(PVDD)
listed in Electrical Characteristics - Protection, the fault GPIO is pulled to low and I2C fault status is reported,
then audio output transfers to high impedance Hiz mode. These are self-clearing error, which means that once
PVDD level is back to normal operation, the device resumes audio playing.
8.5.5.6 PVDD Drop Detection
TAS5828M not only provides PVDD Undervoltage Shutdown protection, but also optional PVDD drop detection.
Based on internal PVDD real-time sensing voltage, TAS5828M is able to be configured to expected behavior,
which could toggle pin10 PD_DET from high to low to indicate PVDD drops below specific level (default 8 V),
and whether TAS5828M automatically goes into Hiz mode to shutdown audio output. All these settings is
accessible through Register 0x04h and 0x05h.
The purpose is to feedback PVDD voltage drop information through GPIO to user product control system, which
is able to implement flexible protection strategy. For example, SOC could starts audio volume fade out process
once PD_DET pin goes to low. This process could provide effective pop-click free control shutdown.
8.5.5.7 Clock Fault
When a clock error is detected on incoming data clock, the TAS5828M device switches to an internal oscillator
and continues to the driving DAC, whicl attenuating the data from the last known value. Once this process is
completed, the DAC output is hard muted to ground and audio output stops. This non-latched clock fault status
is reported I2C fault status, and device audomatically returns to play mode once correct clock is back.
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8.6 Register Maps
8.6.1 CONTROL PORT Registers
表 8-8 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in 表
8-8 should be considered as reserved locations and the register contents should not be modified.
表8-8. CONTROL PORT Registers
Offset
1h
Acronym
Register Name
Section
RESET_CTRL
DEVICE_CTRL1
DEVICE_CTRL2
PVDD_DROP_DETECTION_CTRL1
PVDD_DROP_DETECTION_CTRL2
I2C_PAGE_AUTO_INC
SIG_CH_CTRL
CLOCK_DET_CTRL
SDOUT_SEL
Register 1
节8.6.1.2
节8.6.1.3
节8.6.1.4
节8.6.1.5
节8.6.1.6
节8.6.1.7
节8.6.1.8
节8.6.1.9
节8.6.1.10
节8.6.1.11
节8.6.1.12
节8.6.1.13
节8.6.1.14
节8.6.1.15
节8.6.1.16
节8.6.1.17
节8.6.1.18
节8.6.1.19
节8.6.1.20
节8.6.1.21
节8.6.1.22
节8.6.1.23
节8.6.1.24
节8.6.1.25
节8.6.1.26
节8.6.1.27
节8.6.1.28
节8.6.1.29
节8.6.1.30
节8.6.1.31
节8.6.1.32
节8.6.1.33
节8.6.1.34
节8.6.1.35
节8.6.1.36
节8.6.1.37
节8.6.1.38
节8.6.1.39
2h
Register 2
3h
Register 3
4h
Register 4
5h
Register 5
Fh
Register 15
Register 40
Register 41
Register 48
Register 49
Register 51
Register 52
Register 53
Register 55
Register 56
Register 57
Register 64
Register 70
Register 76
Register 78
Register 79
Register 80
Register 81
Register 83
Register 84
Register 94
Register 96
Register 97
Register 98
Register 99
Register 100
Register 101
Register 102
Register 103
Register 104
Register 105
Register 106
Register 107
28h
29h
30h
31h
33h
34h
35h
37h
38h
39h
40h
46h
4Ch
4Eh
4Fh
50h
51h
53h
54h
5Eh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
I2S_CTRL
SAP_CTRL1
SAP_CTRL2
SAP_CTRL3
FS_MON
BCK (SCLK)_MON
CLKDET_STATUS
DSP_PGM_MODE
DSP_CTRL
DIG_VOL
DIG_VOL_CTRL1
DIG_VOL_CTRL2
AUTO_MUTE_CTRL
AUTO_MUTE_TIME
ANA_CTRL
AGAIN
PVDD_ADC
GPIO_CTRL
GPIO1_SEL
GPIO2_SEL
GPIO0_SEL
GPIO_INPUT_SEL
GPIO_OUT
GPIO_OUT_INV
DIE_ID
POWER_STATE
AUTOMUTE_STATE
PHASE_CTRL
SS_CTRL0
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表8-8. CONTROL PORT Registers (continued)
Offset
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
Acronym
Register Name
Register 108
Register 109
Register 110
Register 111
Register 112
Register 113
Register 114
Register 115
Register 116
Register 117
Register 118
Register 119
Register 120
Section
SS_CTRL1
节8.6.1.40
节8.6.1.41
节8.6.1.42
节8.6.1.43
节8.6.1.44
节8.6.1.45
节8.6.1.46
节8.6.1.47
节8.6.1.48
节8.6.1.49
节8.6.1.50
节8.6.1.51
节8.6.1.52
SS_CTRL2
SS_CTRL3
SS_CTRL4
CHAN_FAULT
GLOBAL_FAULT1
GLOBAL_FAULT2
WARNING
PIN_CONTROL1
PIN_CONTROL2
MISC_CONTROL
CBC_CONTROL
FAULT_CLEAR
Complex bit access types are encoded to fit into small table cells. 表 8-9 shows the codes that are used for
access types in this section.
表8-9. CONTROL PORT Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
][l.,
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8.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]
RESET_CTRL is shown in 图8-14 and described in 表8-10.
Return to 表8-8.
图8-14. RESET_CTRL Register
7
6
5
4
RST_MOD
W
3
2
RESERVED
R
1
0
RST_REG
W
RESERVED
R/W
表8-10. RESET_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
R/W
000
This bit is reserved
RST_DIG_CORE
W
0
WRITE CLEAR BIT
Reset DIG_CORE
WRITE CLEAR BIT Reset Full Digital Core. This bit resets the Full
Digital Signal Path (Include DSP coefficient RAM and I2C Control
Port Registers), Since the DSP is also reset, the coeffient RAM
content is also cleared by the DSP.
0: Normal
1: Reset Full Digital Signal Path
3-1
0
RESERVED
RST_REG
R
000
0
This bit is reserved
W
WRITE CLEAR BIT
Reset Registers
This bit resets the mode registers back to their initial values. Only
reset Control Port Registers, The RAM content is not cleared.
0: Normal
1: Reset I2C Control Port Registers
8.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
DEVICE_CTRL_1 is shown in 图8-15 and described in 表8-11.
Return to 表8-8.
图8-15. DEVICE_CTRL_1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
FSW_SEL
R/W
RESERVED
R/W
DAMP_PBTL
R/W
DAMP_MOD
R/W
表8-11. DEVICE_CTRL_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
FSW_SEL
R/W
0
This bit is reserved
6-4
R/W
000
SELECT FSW
000:384K
010:480K
011:576K
100:768K
001:Reserved
101:Reserved
110:Reserved
111:Reserved
3
RESERVED
R/W
0
This bit is reserved
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表8-11. DEVICE_CTRL_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
DAMP_PBTL
DAMP_MOD
R/W
0
0: SET DAMP TO BTL MODE
1:SET DAMP TO PBTL MODE
1-0
R/W
00
00:BD MODE 01:1SPW MODE 10:HYBRID MODE
8.6.1.3 DEVICE_CTRL2 Register (Offset = 3h) [reset = 0x10]
DEVICE_CTRL2 is shown in 图8-16 and described in 表8-12.
Return to 表8-8.
图8-16. DEVICE_CTRL2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DIS_DSP
R/W
MUTE_LEFT
R/W
RESERVED
R/W
CTRL_STATE
R/W
表8-12. DEVICE_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
DIS_DSP
R/W
000
This bit is reserved
R/W
1
DSP reset
When the bit is made 0, DSP starts powering up and send out data.
This needs to be made 0 only after all the input clocks are settled so
that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3
MUTE
R/W
0
Mute both Left and Right Channel
This bit issues soft mute request for both left and right channel. The
volume is smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2
RESERVED
R/W
R/W
0
This bit is reserved
1-0
CTRL_STATE
00
device state control register
00: Deep Sleep
01: Sleep
10: Hiz,
11: PLAY
8.6.1.4 PVDD_DROP_DETECTION_CTRL1 Register (Offset = 4h) [reset = 0x00]
PVDD_DROP_DETECTION_CTRL1 is shown in 图8-17 and described in 表8-13.
Return to 表8-8.
图8-17. PVDD_DROP_DETECTION_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
PVDD_DROP_ PVDD_DROP_DET_AVE_SAMP PVDD_DROP_
DET_SEQUEN
CE
LES
DET_BYPASS
R/W
R/W
R/W
表8-13. PVDD_DROP_DETECTION_CTRL1 Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
RESERVED
R/W
000
This bit is reserved
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表8-13. PVDD_DROP_DETECTION_CTRL1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
PVDD_DROP_DET_State R/W
_Control
0
This bit controls whether device automatically set into Hiz or still play
once PVDD drop detection happens.
0: The device keeps in play mode even PVDD drops configured
threshold
1: The device goes into Hiz once PVDD drops configured threshold
2-1
PVDD_DROP_DET_AVE_ R/W
SAMPLES
00
PVDD sense average samples for drop detection
This bit is used to set PVDD voltage sense average samples for drop
detection.
00: 1 sample - cycle by cycle, no average
01: 16 samples
10: 32 samples
11: 64 samples
0
PVDD_DROP_DET_Enabl R/W
e
0
PVDD drop detection Enable
This bit controls enable or bypass PVDD drop detection.
0: Bypass PVDD drop detection
1: Enable PVDD drop detection
8.6.1.5 PVDD_DROP_DETECTION_CTRL2 Register (Offset = 5h) [reset = 0x44]
PVDD_DROP_DETECTION_CTRL2 is shown in 图8-18 and described in 表8-14.
Return to 表8-8.
图8-18. PVDD_DROP_DETECTION_CTRL2 Register
7
6
5
4
3
2
1
0
PVDD Drop Detection Voltage Threshold
R/W
表8-14. PVDD_DROP_DETECTION_CTRL2 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
PVDD Drop Detection
Voltage Threshold
R/W
00000000
This bit is used to set PVDD Drop Detection Threshold. The radio to
0xFFh equals to full scale voltage 30V. For example, 8V threshold:
8V/30V = 0x44h/0xFFh. PVDD Drop Threshold is configured as:
00: 0V
01: 0.117V
...
44: 8V
...
FF: 30V
8.6.1.6 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
I2C_PAGE_AUTO_INC is shown in 图8-19 and described in 表8-15.
Return to 表8-8.
图8-19. I2C_PAGE_AUTO_INC Register
7
6
5
4
3
2
1
0
RESERVED
R/W
PAGE_AUTOIN
C_REG
RESERVED
R/W
R/W
表8-15. I2C_PAGE_AUTO_INC Register Field Descriptions
Bit
7-4
Field
RESERVED
Type
Reset
Description
R/W
0000
This bit is reserved
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表8-15. I2C_PAGE_AUTO_INC Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
PAGE_AUTOINC_REG
R/W
0
Page auto increment disable
Disable page auto increment mode. for non -zero books. When end
of page is reached it goes back to 8th address location of next page
when this bit is 0. When this bit is 1 it goes to 0 th location of current
page itself like in older part.
0: Enable Page auto increment
1: Disable Page auto increment
2-0
RESERVED
R/W
000
This bit is reserved
8.6.1.7 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
SIG_CH_CTRL is shown in 图8-20 and described in 表8-16.
Return to 表8-8.
图8-20. SIG_CH_CTRL Register
7
6
5
4
3
2
1
0
SCLK_RATIO_CONFIGURE
R/W
FSMODE
R/W
RESERVED
R/W
表8-16. SIG_CH_CTRL Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
SCLK_RATIO_CONFIGU R/W
RE
0000
These bits indicate the configured SCLK ratio, the number of SCLK
clocks in one audio frame. Device sets this ratio automatically.
4'b0011:32FS
4'b0101:64FS
4'b0111:128FS
4'b1001:256FS
4'b1011:512FS
3
FSMODE
R/W
0
FS Speed Mode These bits select the FS operation mode, which
must be set according to the current audio sampling rate. Need set it
manually If the input Fs is 44.1kHz/88.2kHz/176.4kHz.
4 'b0000 Auto detection
4 'b0100 Reserved
4 'b0110 32KHz
4 'b1000 44.1KHz
4 'b1001 48KHz
4'b1010 88.2KHz
4 'b1011 96KHz
4 'b1100 176.4KHz
4 'b1101 192KHz
Others Reserved
2-0
RESERVED
R/W
000
This bit is reserved
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8.6.1.8 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
CLOCK_DET_CTRL is shown in 图8-21 and described in 表8-17.
Return to 表8-8.
图8-21. CLOCK_DET_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
DIS_DET_PLL DIS_DET_SCL DIS_DET_FS DIS_DET_SCL DIS_DET_MISS RESERVED
RESERVED
K_RANGE
K
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表8-17. CLOCK_DET_CTRL Register Field Descriptions
Bit
Field
RESERVED
DIS_DET_PLL
Type
Reset
Description
7
R/W
0
This bit is reserved
Ignore PLL overate Detection
6
R/W
0
This bit controls whether to ignore the PLL overrate detection. The
PLL must be slow than 150MHz or an error is reported. When
ignored, a PLL overrate error does not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5
DIS_DET_SCLK_RANGE R/W
0
Ignore BCK Range Detection
This bit controls whether to ignore the SCLK range detection. The
SCLK must be stable between 256 KHz and 50 MHz or an error is
reported. When ignored, a SCLK range error does not cause a clock
error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4
3
DIS_DET_FS
R/W
R/W
0
0
Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When
ignored, FS error does not cause a clock error.But
CLKDET_STATUS reports fs error.
0: Regard FS detection
1: Ignore FS detection
DIS_DET_SCLK
Ignore SCLK Detection
This bit controls whether to ignore the SCLK detection against
LRCK. The SCLK must be stable between 32FS and 512FS
inclusive or an error is reported. When ignored, a SCLK error does
not cause a clock error.
0: Regard SCLK detection
1: Ignore SCLK detection
2
DIS_DET_MISS
R/W
0
Ignore SCLK Missing Detection
This bit controls whether to ignore the SCLK missing detection.
When ignored, an SCLK missing does not cause a clock error.
0: Regard SCLK missing detection
1: Ignore SCLKmissing detection
1
0
RESERVED
RESERVED
R/W
R/W
0
0
This bit is reserved
This bit is reserved
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8.6.1.9 SDOUT_SEL Register (Offset = 30h) [reset = 0x00]
SDOUT_SEL is shown in 图8-23 and described in 表8-18.
Return to 表8-8.
图8-22. SDOUT_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
RESERVED
R/W
SDOUT_SEL
R/W
表8-18. SDOUT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
SDOUT_SEL
R/W
0000000
These bits are reserved
R/W
0
SDOUT Select. This bit selects what is being output as SDOUT pin.
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
8.6.1.10 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in 图8-23 and described in 表8-19.
Return to 表8-8.
图8-23. I2S_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SCLK_INV
R/W
RESERVED
R/W
RESERVED
RESERVED
R
RESERVED
R/W
R
表8-19. I2S_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
SCLK_INV
R/W
00
This bit is reserved
R/W
0
SCLK Polarity
This bit sets the inverted SCLK mode. In inverted SCLK mode, the
DAC assumes that the LRCK and DIN edges are aligned to the rising
edge of the SCLK. Normally they are assumed to be aligned to the
falling edge of theSCLK
0: Normal SCLKmode
1: Inverted SCLK mode
4
3
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R
0
This bit is reserved
This bit is reserved
These bits are reserved
This bit is reserved
0
2-1
0
R
00
0
R/W
8.6.1.11 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
SAP_CTRL1 is shown in 图8-24 and described in 表8-20.
Return to 表8-8.
图8-24. SAP_CTRL1 Register
7
6
5
4
3
2
1
0
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图8-24. SAP_CTRL1 Register (continued)
I2S_SHIFT_MS
B
RESERVED
R/W
DATA_FORMAT
I2S_LRCLK_PULSE
WORD_LENGTH
R/W
R/W
R/W
R/W
表8-20. SAP_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
I2S_SHIFT_MSB
RESERVED
R/W
0
I2S Shift MSB
6
R/W
R/W
0
This bit is reserved
I2S Data Format
5-4
DATA_FORMAT
00
These bits control both input and output audio interface formats for
DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2
1-0
I2S_LRCLK_PULSE
WORD_LENGTH
R/W
R/W
00
10
01: LRCLK pulse < 8 SCLK
I2S Word Length
These bits control both input and output audio interface sample word
lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
8.6.1.12 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
SAP_CTRL2 is shown in 图8-25 and described in 表8-21.
Return to 表8-8.
图8-25. SAP_CTRL2 Register
7
6
5
4
3
2
1
0
I2S_SHIFT
R/W
表8-21. SAP_CTRL2 Register Field Descriptions
Bit
7-0
Field
I2S_SHIFT
Type
Reset
Description
R/W
00000000
I2S Shift LSB
These bits control the offset of audio data in the audio frame for both
input and output. The offset is defined as the number of SCLK from
the starting (MSB) of audio frame to the starting of the desired audio
sample. MSB [8] locates in 节8.6.1.12
000000000: offset = 0 SCLK (no offset)
000000001: ofsset = 1 SCLK
000000010: offset = 2 SCLKs
and
111111111: offset = 512 SCLKs
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8.6.1.13 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
SAP_CTRL3 is shown in 图8-26 and described in 表8-22.
Return to 表8-8.
图8-26. SAP_CTRL3 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
LEFT_DAC_DPATH
R/W
RESERVED
R/W
RIGHT_DAC_DPATH
R/W
表8-22. SAP_CTRL3 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5-4
RESERVED
00
These bits are reserved
LEFT_DAC_DPATH
01
Left DAC Data Path. These bits control the left channel audio data
path connection.
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
3-2
1-0
RESERVED
R/W
R/W
00
01
These bits are reserved
RIGHT_DAC_DPATH
Right DAC Data Path. These bits control the right channel audio data
path connection.
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)
8.6.1.14 FS_MON Register (Offset = 37h) [reset = 0x00]
FS_MON is shown in 图8-27 and described in 表8-23.
Return to 表8-8.
图8-27. FS_MON Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SCLK_RATIO_HIGH
R
FS
R
表8-23. FS_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-4
3-0
RESERVED
SCLK_RATIO_HIGH
FS
R/W
00
This bit is reserved
R
R
00
2 msbs of detected SCLK ratio
0000
These bits indicate the currently detected audio sampling rate.
4 'b0000 FS Error
4 'b0100 16KHz
4 'b0110 32KHz
4 'b1000 Reserved
4 'b1001 48KHz
4 'b1011 96KHz
4 'b1101 192KHz
Others Reserved
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8.6.1.15 BCK (SCLK)_MON Register (Offset = 38h) [reset = 0x00]
BCK_MON is shown in 图8-28 and described in 表8-24.
Return to 表8-8.
图8-28. BCK (SCLK)_MON Register
7
6
5
4
3
2
1
0
BCLK (SCLK)_RATIO_LOW
R
表8-24. BCK_MON Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
BCLK
(SCLK)_RATIO_LOW
R
00000000
These bits indicate the currently detected BCK (SCLK) ratio, the
number of BCK (SCLK) clocks in one audio frame.
BCK (SCLK) = 32 FS~512 FS
8.6.1.16 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
CLKDET_STATUS is shown in 图8-29 and described in 表8-25.
Return to 表8-8.
图8-29. CLKDET_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DET_STATUS
R
表8-25. CLKDET_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
R/W
00
This bit is reserved
DET_STATUS
R
000000
bit0: In auto detection mode(reg_fsmode=0),this bit indicated
whether the audio sampling rate is valid or not. In non auto detection
mode(reg_fsmode!=0), Fs error indicates that configured fs is
different with detected fs. Even FS Error Detection Ignore is set, this
flag is also asserted.
bit1: This bit indicates whether the SCLK is valid or not. The SCLK
ratio must be stable and in the range of 32-512FS to be valid.
bit2: This bit indicates whether the SCLK is missing or not.
bit3:This bit indicates whether the PLL is locked or not. The PLL is
reported as unlocked when it is disabled.
bits4:This bit indicates whether the PLL is overrate
bits5:This bit indicates whether the SCLK is overrate or underrate
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8.6.1.17 DSP_PGM_MODE Register (Offset = 40h) [reset = 0x01]
DSP_PGM_MODE is shown in 图8-30 and described in 表8-26.
Return to 表8-8.
图8-30. DSP_PGM_MODE Register
7
6
5
4
3
2
1
0
RESERVED
R/W
CH1_HIZ
CH2_HIZ
MODE_SEL
R/W
表8-26. DSP_PGM_MODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
CH1_HIZ
R/W
000
This bit is reserved
Hi-Z Mode Channel-1
Stops output switching and sets channel-1 to Hi-Z mode.
0: Normal Operation
R/W
R/W
R/W
0
1: Hi-Z state
3
CH2_HIZ
0
Hi-Z Mode Channel-2
Stops output switching and sets channel-2 to Hi-Z mode.
0: Normal Operation
1: Hi-Z state
2-0
MODE_SEL
00001
DSP Program Selection
These bits select the DSP program to use for audio processing.
000 => ram mode
001 => rom mode 1
8.6.1.18 DSP_CTRL Register (Offset = 46h) [reset = 0x01]
DSP_CTRL is shown in 图8-31 and described in 表8-27.
Return to 表8-8.
图8-31. DSP_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
USER_DEFINED_PROCESSING RESERVED BOOT_FROM_I USE_DEFAULT
_RATE
RAM
_COEFFS
R/W
R/W
R
R/W
R/W
表8-27. DSP_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7-5
4-3
R/W
000
This bit is reserved
USER_DEFINED_PROCE R/W
SSING_RATE
00
00:input
01:48k
10:96k
11:192k
2
1
0
RESERVED
RESERVED
RESERVED
R
0
0
1
This bit is reserved
This bit is reserved
This bit is reserved
R
R/W
8.6.1.19 DIG_VOL Register (Offset = 4Ch) [reset = 30h]
DIG_VOL is shown in 图8-32 and described in 表8-28.
Return to 表8-8.
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图8-32. DIG_VOL Register
7
6
5
4
3
2
1
0
PGA_LEFT
R/W
表8-28. DIG_VOL Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
PGA
R/W
00110000
Digital Volume
These bits control both left and right channel digital volume. The
digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute
8.6.1.20 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]
DIG_VOL_CTRL1 is shown in 图8-33 and described in 表8-29.
Return to 表8-8.
图8-33. DIG_VOL_CTRL1 Register
7
6
5
4
3
2
1
0
PGA_RAMP_DOWN_SPEED
R/W
PGA_RAMP_DOWN_STEP
R/W
PGA_RAMP_UP_SPEED
R/W
PGA_RAMP_UP_STEP
R/W
表8-29. DIG_VOL_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PGA_RAMP_DOWN_SPE R/W
ED
00
Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
3-2
PGA_RAMP_DOWN_STE R/W
P
11
00
Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
PGA_RAMP_UP_SPEED R/W
Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
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表8-29. DIG_VOL_CTRL1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
PGA_RAMP_UP_STEP
R/W
11
Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the
volume is ramping up.
00: Increment by 4 dB for each updat
e 01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update
8.6.1.21 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL2 is shown in 图8-34 and described in 表8-30.
Return to 表8-8.
图8-34. DIG_VOL_CTRL2 Register
7
6
5
4
3
2
1
0
FAST_RAMP_DOWN_SPEED
R/W
FAST_RAMP_DOWN_STEP
R/W
RESERVED
R/W
表8-30. DIG_VOL_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
FAST_RAMP_DOWN_SP R/W
EED
00
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down due to clock error or power outage,
which usually needs faster ramp down compared to normal soft
mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
FAST_RAMP_DOWN_ST R/W
EP
11
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down due to clock error or power outage, which
usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0
RESERVED
R/W
0000
This bit is reserved
8.6.1.22 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x00]
AUTO_MUTE_CTRL is shown in 图8-35 and described in 表8-31.
Return to 表8-8.
图8-35. AUTO_MUTE_CTRL Register
7
6
5
4
3
2
1
REG_AUTO_MUTE_CTRL
R/W
0
RESERVED
R/W
表8-31. AUTO_MUTE_CTRL Register Field Descriptions
Bit
7-3
Field
RESERVED
Type
Reset
Description
R/W
00000
This bit is reserved
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表8-31. AUTO_MUTE_CTRL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
REG_AUTO_MUTE_CTR R/W
L
000
bit0:
0: Disable left channel auto mute
1: Enable left channel auto mute
bit1:
0: Disable right channel auto mute
1: Enable right channel auto mute
bit2:
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are
about to be auto muted.
8.6.1.23 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
AUTO_MUTE_TIME is shown in 图8-36 and described in 表8-32.
Return to 表8-8.
图8-36. AUTO_MUTE_TIME Register
7
6
5
AUTOMUTE_TIME_LEFT
R/W
4
3
2
1
AUTOMUTE_TIME_RIGHT
R/W
0
RESERVED
R/W
RESERVED
R/W
表8-32. AUTO_MUTE_TIME Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-4
AUTOMUTE_TIME_LEFT R/W
000
Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and scales with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
3
RESERVED
R/W
0
This bit is reserved
2-0
AUTOMUTE_TIME_RIGH R/W
T
000
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and scales with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
8.6.1.24 ANA_CTRL Register (Offset = 53h) [reset = 0h]
ANA_CTRL is shown in 图8-37 and described in 表8-33
Return to 表8-8
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图8-37. ANA_CTRL Register
7
6
5
4
3
2
1
0
AMUTE_DLY
R/W
表8-33. ANA_CTRL Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
6-5
Class D bandwidth control R/W
00
00: 100kHz
01: 80kHz
10: 120kHz
11:175kHz
With Fsw=384kHz, 100kHz bandwidth is selected for high audio
performance. With Fsw=768kHz, 175kHz bandwidth should be
selected for high audio performance.
4-1
0
RESERVED
R/W
R/W
0000
0
These bits are reserved
L and R PWM output
phase control
0: out of phase
1: in phase
8.6.1.25 AGAIN Register (Offset = 54h) [reset = 0x00]
AGAIN is shown in 图8-38 and described in 表8-34.
Return to 表8-8.
图8-38. AGAIN Register
7
6
5
4
3
2
1
0
RESERVED
R/W
ANA_GAIN
R/W
表8-34. AGAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4-0
RESERVED
ANA_GAIN
R/W
000
This bit is reserved
R/W
00000
Analog Gain Control
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001:-0.5db 11111: -15.5 dB
8.6.1.26 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]
PVDD_ADC is shown in 图8-39 and described in 表8-35.
Return to 表8-8.
图8-39. PVDD_ADC Register
7
6
5
4
3
2
1
0
ADC_DATA_OUT
R
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表8-35. PVDD_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PVDD_ADC[7:0]
R
00000000
PVDD Voltage = PVDD_ADC[7:0] / 8.428 (V)
223: 26.45V
222: 26.34V
221:26.22V
...
39: 4.63V
38: 4.51V
37: 4.39V
8.6.1.27 GPIO_CTRL Register (Offset = 60h) [reset = 0x00]
GPIO_CTRL is shown in 图8-40 and described in 表8-36.
Return to 表8-8.
图8-40. GPIO_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO0_OE
R/W
GPIO2_OE
R/W
GPIO1_OE
R/W
表8-36. GPIO_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
GPIO0_OE
R/W
0000
This bit is reserved
R/W
R/W
R/W
0
0
0
GPIO2 Output Enable. This bit sets the direction of the GPIO0 pin
0: GPIO0 is input
1: GPIO0 is output
1
0
GPIO2_OE
GPIO1_OE
GPIO2 Output Enable This bit sets the direction of the GPIO2 pin
0: GPIO2 is input
1: GPIO2 is output
GPIO1 Output Enable This bit sets the direction of the GPIO1 pin
0: GPIO1 is input
1: GPIO1 is output
8.6.1.28 GPIO1_SEL Register (Offset = 61h) [reset = 0x00]
GPIO1_SEL is shown in 图8-41 and described in 表8-37.
Return to 表8-8.
图8-41. GPIO1_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO1_SEL
R/W
表8-37. GPIO1_SEL Register Field Descriptions
Bit
7-4
Field
RESERVED
Type
Reset
Description
R/W
0000
This bit is reserved
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表8-37. GPIO1_SEL Register Field Descriptions (continued)
Bit
Field
GPIO1_SEL
Type
Reset
Description
3-0
R/W
0000
0000: off (low)
1000: GPIO1 as WARNZ output
1001: GPIO1 as Serial audio interface data output (SDOUT)
1011: GPIO1 as FAULTZ output
1100: GPIO1 as PVDD Drop Detection Flag
1101: GPIO1 as Class-H
8.6.1.29 GPIO2_SEL Register (Offset = 62h) [reset = 0x00]
GPIO2_SEL is shown in 图8-42 and described in 表8-38.
Return to 表8-8.
图8-42. GPIO2_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO2_SEL
R/W
表8-38. GPIO2_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
GPIO2_SEL
R/W
0000
This bit is reserved
R/W
0000
0000: off (low)
1000: GPIO2 as WARNZ output
1001: GPIO2 as Serial audio interface data output (SDOUT)
1011: GPIO2 as FAULTZ output
1100: GPIO2 as PVDD Drop Detection Flag
1101: GPIO2 as Class-H
8.6.1.30 GPIO0_SEL Register (Offset = 63h) [reset = 0x00]
GPIO0_SEL is shown in 图8-43 and described in 表8-39.
Return to 表8-8.
图8-43. GPIO0_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO0_SEL
R/W
表8-39. GPIO0_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
GPIO0_SEL
R/W
0000
This bit is reserved
R/W
0000
0000: off (low)
1000: GPIO0 as WARNZ output
1001: GPIO0 as Serial audio interface data output (SDOUT)
1011: GPIO0 as FAULTZ output
1100: GPIO0 as PVDD Drop Detection Flag
1101: GPIO0 as Class-H
8.6.1.31 GPIO_INPUT_SEL Register (Offset = 64h) [reset = 0x00]
GPIO_INPUT_SEL is shown in 图8-44 and described in 表8-40.
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Return to 表8-8.
图8-44. GPIO_INPUT_SEL Register
7
6
5
4
3
2
1
0
GPIO_SPI_MISO_SEL
R/W
GPIO_PHASE_SYNC_SEL
R/W
GPIO_RESETZ_SEL
R/W
GPIO_MUTEZ_SEL
R/W
表8-40. GPIO_INPUT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
GPIO_SPI_MISO_SEL
R/W
00
00: N/A
01: GPIO1
10: GPIO2
11: GPIO0
5-4
3-2
1-0
GPIO_PHASE_SYNC_SE R/W
L
00
00
00
00: N/A
01: GPIO1
10: GPIO2
11: GPIO0
GPIO_RESETZ_SEL
GPIO_MUTEZ_SEL
R/W
R/W
00: N/A
01: GPIO1
10: GPIO2
11: GPIO0 can not be reset by GPIO reset
00: N/A
01: GPIO1
10: GPIO2
11: GPIO0
MUTEZ pin active-low, output driver is set to HiZ state, Class D
amplifier's output stop switching.
8.6.1.32 GPIO_OUT Register (Offset = 65h) [reset = 0x00]
GPIO_OUT is shown in 图8-45 and described in 表8-41.
Return to 表8-8.
图8-45. GPIO_OUT Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO_OUT
R/W
表8-41. GPIO_OUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2-0
RESERVED
GPIO_OUT
R/W
00000
This bit is reserved
R/W
000
bit0: GPIO1 output
bit1: GPIO2 output
bit2: GPIO0 output
8.6.1.33 GPIO_OUT_INV Register (Offset = 66h) [reset = 0x00]
GPIO_OUT_INV is shown in 图8-46 and described in 表8-42.
Return to 表8-8.
图8-46. GPIO_OUT_INV Register
7
6
5
4
3
2
1
0
RESERVED
GPIO_OUT
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图8-46. GPIO_OUT_INV Register (continued)
R/W
R/W
表8-42. GPIO_OUT_INV Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
GPIO_OUT
R/W
00000
This bit is reserved
2-0
R/W
000
bit0: GPIO1 output invert
bit1: GPIO2 output invert
bit2: GPIO0 output invert
8.6.1.34 DIE_ID Register (Offset = 67h) [reset = 95h]
DIE_ID is shown in 图8-47 and described in 表8-43.
Return to 表8-8.
图8-47. DIE_ID Register
7
6
5
4
3
2
1
0
DIE_ID
R
表8-43. DIE_ID Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIE_ID
R
10010101
DIE ID
8.6.1.35 POWER_STATE Register (Offset = 68h) [reset = 0x00]
POWER_STATE is shown in 图8-48 and described in 表8-44.
Return to 表8-8.
图8-48. POWER_STATE Register
7
6
5
4
3
2
1
0
STATE_RPT
R
表8-44. POWER_STATE Register Field Descriptions
Bit
7-0
Field
STATE_RPT
Type
Reset
Description
R
00000000
0: Deep sleep
1: Seep
2: HIZ
3: Play
Others: reserved
8.6.1.36 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
AUTOMUTE_STATE is shown in 图8-49 and described in 表8-45.
Return to 表8-8.
图8-49. AUTOMUTE_STATE Register
7
6
5
4
3
2
1
0
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图8-49. AUTOMUTE_STATE Register (continued)
RESERVED
ZERO_RIGHT_ ZERO_LEFT_M
MON
ON
R
R
R
表8-45. AUTOMUTE_STATE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
000000
This bit is reserved
1
ZERO_RIGHT_MON
ZERO_LEFT_MON
R
R
0
0
This bit indicates the auto mute status for right channel.
0: Not auto muted
1: Auto muted
0
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
8.6.1.37 PHASE_CTRL Register (Offset = 6Ah) [reset = 0]
PHASE_CTRL is shown in 图8-50 and described in 表8-46.
Return to 表8-8.
图8-50. PHASE_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
RAMP_PHASE_SEL
R/W
PHASE_SYNC PHASE_SYNC
_SEL
_EN
R/W
R/W
表8-46. PHASE_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-2
RESERVED
R/W
0000
This bit is reserved
RAMP_PHASE_SEL
R/W
00
select ramp clock phase when multi devices integrated in one
system to reduce EMI and peak supply peak current, it is
recomended set all devices the same RAMP frequency and same
spread spectrum. it must be set before driving device into PLAY
mode if this feature is needed.
2'b00: phase 0
2'b01: phase 1
2'b10: phase 2
2'b11: phase 3 all of above have a 45 degree of phase shift
1
0
PHASE_SYNC_SEL
PHASE_SYNC_EN
R/W
R/W
0
0
ramp phase sync sel,
0: is gpio sync;
1: intenal sync
ramp phase sync enable
8.6.1.38 RAMP_SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
RAMP_SS_CTRL0 is shown in 图8-51 and described in 表8-47.
Return to 表8-8.
图8-51. SS_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
SS_PRE_DIV_ SS_MANUAL_
SEL MODE
RESERVED
SS_RDM_EN
SS_TRI_EN
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图8-51. SS_CTRL0 Register (continued)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表8-47. RAMP_SS_CTRL0 Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R/W
0
This bit is reserved
This bit is reserved
6
5
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
0
SS_PRE_DIV_SEL
SS_MANUAL_MODE
RESERVED
0
Select pll clock divide 2 as source clock in manual mode
Set ramp ss controller to manual mode
This bit is reserved
4
0
3-2
1
00
0
SS_RDM_EN
Random SS enable
0
SS_TRI_EN
0
Triangle SS enable
8.6.1.39 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in 图8-52 and described in 表8-48.
Return to 表8-8.
图8-52. SS_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SS_RDM_CTRL
R/W
SS_TRI_CTRL
R/W
表8-48. SS_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-4
3-0
SS_RDM_CTRL
SS_TRI_CTRL
R/W
R/W
000
Add Dither
0000
Triangle SS frequency and range control
8.6.1.40 SS_CTRL2 Register (Offset = 6Dh) [reset = 0xA0]
SS_CTRL2 is shown in 图8-53 and described in 表8-49.
Return to 表8-8.
图8-53. SS_CTRL2 Register
7
6
5
4
3
2
1
0
TM_FREQ_CTRL
R/W
表8-49. SS_CTRL2 Register Field Descriptions
Bit
7-0
Field
TM_FREQ_CTRL
Type
Reset
Description
R/W
10100000
Control ramp frequency in manual mode, F=61440000/N
8.6.1.41 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
SS_CTRL3 is shown in 图8-54 and described in 表8-50.
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Return to 表8-8.
图8-54. SS_CTRL3 Register
7
6
5
4
3
2
1
0
TM_DSTEP_CTRL
R/W
TM_USTEP_CTRL
R/W
表8-50. SS_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SS_TM_DSTEP_CTRL
R/W
0001
Control triangle mode spread spectrum fall step in ramp ss manual
mode
3-0
SS_TM_USTEP_CTRL
R/W
0001
Control triangle mode spread spectrum rise step in ramp ss manual
mode
8.6.1.42 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
SS_CTRL4 is shown in 图8-55 and described in 表8-51.
Return to 表8-8.
图8-55. SS_CTRL4 Register
7
6
5
4
3
2
SS_TM_PERIOD_BOUNDRY
R/W
1
0
RESERVED
R/W
TM_AMP_CTRL
R/W
表8-51. SS_CTRL4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
This bit is reserved
6-5
4-0
TM_AMP_CTRL
R/W
01
Control ramp amp ctrl in ramp ss manual model
SS_TM_PERIOD_BOUND R/W
RY
00100
Control triangle mode spread spectrum boundary in ramp ss manual
mode
8.6.1.43 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
CHAN_FAULT is shown in 图8-56 and described in 表8-52.
Return to 表8-8.
图8-56. CHAN_FAULT Register
7
6
5
4
3
CH1_DC_1
R
2
CH2_DC_1
R
1
CH1_OC_I
R
0
CH2_OC_I
R
RESERVED
R
表8-52. CHAN_FAULT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
CH1_DC_1
R
0000
This bit is reserved
R
0
Left channel DC fault. Once there is a DC fault, this bit is set to be 1.
Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this
fault by setting bit 7 of 节8.6.1.52 to 1 or this bit keeps 1.
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表8-52. CHAN_FAULT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
CH2_DC_1
CH1_OC_I
CH2_OC_I
R
0
Right channel DC fault. Once there is a DC fault, this bit is set to be
1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear
this fault by setting bit 7 of 节8.6.1.52 to 1 or this bit keeps 1.
1
0
R
R
0
0
Left channel over current fault. Once there is a OC fault, this bit is set
to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO).
Clear this fault by setting bit 7 of 节8.6.1.52 to 1 or this bit keeps 1.
Right channel over current fault. Once there is a OC fault, this bit is
set to be 1. Class D output is set to Hi-Z. Report by FAULT pin
(GPIO). Clear this fault by setting bit 7 of 节8.6.1.52 to 1 or this bit
keeps 1.
8.6.1.44 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
GLOBAL_FAULT1 is shown in 图8-57 and described in 表8-53.
Return to 表8-8.
图8-57. GLOBAL_FAULT1 Register
7
6
5
4
3
2
1
0
OTP_CRC_ER BQ_WR_ERRO LOAD_EEPRO
RESERVED
RESERVED
CLK_FAULT_I
R
PVDD_OV_I
PVDD_UV_I
ROR
R
M_ERROR
R
R
R
R
R
R
R
表8-53. GLOBAL_FAULT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
OTP_CRC_ERROR
BQ_WR_ERROR
R
0
Indicate OTP CRC check error.
R
0
0
The recent BQ is written failed
LOAD_EEPROM_ERROR R
0: EEPROM boot load was done successfully
1: EEPROM boot load was done unsuccessfully
4
3
2
RESERVED
RESERVED
CLK_FAULT_I
R
R
R
0
0
0
This bit is reserved
This bit is reserved
Clock fault. Once there is a Clock fault, this bit is set to be 1. Class D
output is set to Hi-Z. Report by FAULT pin (GPIO). Clock fault works
with an auto-recovery mode, once the clock error removes, device
automatically returns to the previous state.
Clear this fault by setting bit 7 of 节8.6.1.52 to 1 or this bit keeps 1.
1
0
PVDD_OV_I
PVDD_UV_I
R
R
0
0
PVDD OV fault. Once there is a OV fault, this bit is set to be 1. Class
D output is set to Hi-Z. Report by FAULT pin (GPIO). OV fault works
with an auto-recovery mode, once the OV error removes, device
automatically returns to the previous state.
Clear this fault by setting bit 7 of 节8.6.1.52 to 1 or this bit keeps 1.
PVDD UV fault. Once there is a UV fault, this bit is set to be 1. Class
D output is set to Hi-Z. Report by FAULT pin (GPIO). OV fault works
with an auto-recovery mode, once the OV error removes, device
automatically returns to the previous state.
Clear this fault by setting bit 7 of 节8.6.1.52 to 1 or this bit keeps 1.
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8.6.1.45 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
GLOBAL_FAULT2 is shown in 图8-58 and described in 表8-54.
Return to 表8-8.
图8-58. GLOBAL_FAULT2 Register
7
6
5
4
3
2
1
0
RESERVED
R
CBC_FAULT_C CBC_FAULT_C
OTSD_I
H2_I
H1_I
R
R
R
表8-54. GLOBAL_FAULT2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
R
0000
This bit is reserved
CBC_FAULT_CH2_I
CBC_FAULT_CH1_I
OTSD_I
R
R
R
0
0
0
Right channel cycle by cycle over current fault
Left channel cycle by cycle over current fault
Over temperature shut down fault.
1
0
Once there is a OT fault, this bit is set to be 1. Class D output is set
to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-
recovery mode, once the OV error removes, device automatically
returns to the previous state.
Clear this fault by setting bit 7 of 节8.6.1.52 to 1 or this bit keeps 1.
8.6.1.46 WARNING Register (Offset = 73h) [reset = 0x00]
WARNING is shown in 图8-59 and described in 表8-55.
Return to 表8-8.
图8-59. WARNING Register
7
6
5
4
3
2
1
0
RESERVED
R
CBCW_CH1_I CBCW_CH2_I OTW_LEVEL4_ OTW_LEVEL3_ OTW_LEVEL2_ OTW_LEVEL1_
I
I
I
I
R
R
R
R
R
R
表8-55. WARNING Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0
This bit is reserved
CBCW_CH1_I
CBCW_CH2_I
OTW_LEVEL4_I
OTW_LEVEL3_I
OTW_LEVEL2_I
OTW_LEVEL1_I
R
R
R
R
R
R
0
0
0
0
0
0
Left channel cycle by cycle over current warning
Right channel cycle by cycle over current warning
Over temperature warning leve4, 146C
Over temperature warning leve3, 134C
Over temperature warning leve2, 122C
Over temperature warning leve1, 112C
4
3
2
1
0
8.6.1.47 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
PIN_CONTROL1 is shown in 图8-60 and described in 表8-56.
Return to 表8-8.
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图8-60. PIN_CONTROL1 Register
7
6
5
4
3
2
1
0
MASK_OTSD MASK_DVDD_ MASK_DVDD_ MASK_CLK_FA RESERVED
MASK_PVDD_
UV
MASK_DC
MASK_OC
UV
OV
ULT
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
表8-56. PIN_CONTROL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
2
1
0
MASK_OTSD
R/W
0
Mask OTSD fault report
Mask DVDD UV fault report
Mask DVDD OV fault report
MASK_DVDD_UV
MASK_DVDD_OV
MASK_CLK_FAULT
RESERVED
R/W
R/W
R/W
R
0
0
0
0
0
0
0
Mask clock fault report
This bit is reserved
MASK_PVDD_UV
MASK_DC
R/W
R/W
R/W
Mask PVDD UV fault report mask PVDD OV fault report
Mask DC fault report
MASK_OC
Mask OC fault report
8.6.1.48 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
PIN_CONTROL2 is shown in 图8-61 and described in 表8-57.
Return to 表8-8.
图8-61. PIN_CONTROL2 Register
7
6
5
4
3
2
1
0
CBC_FAULT_L CBC_WARN_L CLKFLT_LATC OTSD_LATCH_ OTW_LATCH_
MASK_OTW
MASK_CBCW MASK_CBC_F
AULT
ATCH_EN
ATCH_EN
H_EN
EN
EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表8-57. PIN_CONTROL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CBC_FAULT_LATCH_EN R/W
CBC_WARN_LATCH_EN R/W
1
Enable CBC fault latch by setting this bit to 1
Enable CBC warning latch by setting this bit to 1
Enable clock fault latch by setting this bit to 1
Enable OTSD fault latch by setting this bit to 1
Enable OT warning latch by setting this bit to 1
Mask OT warning report by setting this bit to 1
Mask CBC warning report by setting this bit to 1
Mask CBC fault report by setting this bit to 1
6
5
4
3
2
1
0
1
1
1
1
0
0
0
CLKFLT_LATCH_EN
OTSD_LATCH_EN
OTW_LATCH_EN
MASK_OTW
R/W
R/W
R/W
R/W
R/W
R/W
MASK_CBCW
MASK_CBC_FAULT
8.6.1.49 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
MISC_CONTROL is shown in 图8-62 and described in 表8-58.
Return to 表8-8.
图8-62. MISC_CONTROL Register
7
6
5
4
3
2
1
0
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图8-62. MISC_CONTROL Register (continued)
DET_STATUS_
LATCH
RESERVED
OTSD_AUTO_
REC_EN
RESERVED
R/W
R/W
R/W
R/W
表8-58. MISC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DET_STATUS_LATCH
R/W
0
1:Latch clock detection status
0:Don't latch clock detection status
6-5
4
RESERVED
R/W
R/W
R/W
00
These bits are reserved
OTSD auto recovery enable
This bit is reserved
OTSD_AUTO_REC_EN
RESERVED
0
3-0
0000
8.6.1.50 CBC_CONTROL Register (Offset = 77h) [reset = 0x00]
CBC_CONTROL is shown in 图8-63 and described in 表8-59.
Return to 表8-8.
图8-63. CBC_CONTROL Register
7
6
5
4
3
2
1
0
RESERVED
CBC_LEVEL_SEL
R/W
CBC_EN
CBC_WARN_E CBC_FAULT_E
N
N
R/W
R/W
R/W
R/W
表8-59. CBC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4-3
RESERVED
R/W
000
These bits are reserved
CBC_LEVE 00
L_SEL
This bit sets CBC level, which is percentage to Over-Current
Threshold:
00: 80%
10: 60%
01: 40%
2
1
0
CBC_EN
R/W
R/W
R/W
0
0
0
Enable CBC function
Enable CBC warning
Enable CBC fault
CBC_WARN_EN
CBC_FAULT_EN
8.6.1.51 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
FAULT_CLEAR is shown in 图8-64 and described in 表8-60.
Return to 表8-8.
图8-64. FAULT_CLEAR Register
7
6
5
4
3
2
1
0
ANALOG_FAUL
T_CLEAR
RESERVED
R/W
W
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表8-60. FAULT_CLEAR Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ANALOG_FAULT_CLEAR
RESERVED
W
0
WRITE CLEAR BIT once write this bit to 1, device clears analog fault
This bit is reserved
6-0
R/W
0000000
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
This section details the information required to configure the device for several popular configurations and
provides guidance on integrating the TAS5828M device into the larger system.
9.1.1 Inductor Selections
It is required that the peak current is smaller than the OCP (Over current protection) value which is 7.5 A, there
are 3 cases which cause high peak current flow through inductor.
1. During power up (idle state, no audio input), the duty cycle increases from 0 to θ. There is a start-up current
which flow through inductor to set up the common mode voltage (PVDD×θ).
备注
θ= 0.5 (BD Modulation), 0.14 (1 SPW Modulation), 0.14 (Hybrid Modulation)
2. During music playing, some audio burst signal (high frequency) with very hard PVDD clipping causes PWM
duty cycle increase dramatically. This is the worst case and it rarely happens.
Ipeak _clipping ö PVDDì(1-q)/(F ì L)
sw
(1)
3. Peak current due to Max output power. Ignore the ripple current flow through capacitor here.
Ipeak _ output _ power ö 2ì Max _Output _ Power / Rspea ker_ Load
(2)
It is suggested that inductor saturation current Isat, is larger than the amplifier peak current during power-up and
play audio.
ISAT í max(Ipeak_ power_up,I peak_clipping,Ipeak_output_ power
)
(3)
表9-1. Inductor Requirements
PVDD (V)
≤12
Switching Frequency (kHz)
Minimum Inductance (L) (µH)
384
384
4.7
10
> 12
For higher switching frequencies (Fsw), select the inductors with minimum inductance to be 384 kHz / Fsw × L.
Same PVDD and switching frequency, larger inductance means smaller idle current for lower power dissipation.
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9.1.2 Bootstrap Capacitors
The output stage of the TAS5828M uses a high-side NMOS driver, rather than a PMOS driver. To generate the
gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating
power supply for the switching cycle. Use 0.47-µF capacitors to connect the appropriate output pin (OUT_X) to
the bootstrap pin (BST_X). For example, connect a 0.47-µF capacitor between OUT_A and BST_A for
bootstrapping the A channel. Similarly, connect another 0.47-µF capacitor between the OUT_B and BST_B pins
for the B channel inverting output.
9.1.3 Power Supply Decoupling
To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise
transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. The power supply input must be decoupled with some
good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to
the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the
PVDD pins of the device.
9.1.4 Output EMI Filtering
The device is often used with a low-pass filter, which is used to filter out the carrier frequency of the PWM
modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that
are commonly used. In other high-power applications, large toroid inductors are required for maximum power
and film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter
Design (SLOA119) for a detailed description on the proper component selection and design of an L-C filter
based upon the desired load and response.
For EMI performance and EMI Design consideration, reference to application report: TAS5825M Design
Considerations for EMC.
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9.2 Typical Applications
9.2.1 2.0 (Stereo BTL) System
In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels
are amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated
based upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered
2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
图9-1 shows the 2.0 (Stereo BTL) system application.
L1
PVDD
PVDD
Left+
10uH
C1
680nF
50V
C2
10uF
35V
C3
10uF
35V
C4
0.1uF
C8
390uF
C5
0.1uF
C6
10uF
35V
C7
10uF
35V
C9
390uF
0xC0
0xC2
0xC4
0xC6
GND
Channel L
L2
GND
GND
GND
GND
Left-
DNP
DNP
DNP
DNP
33k
6.8k
1.5k
0
0xC8
0xCA
GND
GND
GND
GND
10uH
C10
680nF
50V
DVDD
Reserved
Hardware Control Mode
U1
FROM CONTROLLER
C11
4.7uF
C12
0.1uF
GND
OUT_A+
OUT_A-
17
19
23
LRCLK
SCLK
SDIN
PVDD
OUT_A+
OUT_A-
18
31
32
L3
PVDD
PVDD
PVDD
OUT_B+
OUT_B-
Right+
GND
GND
GND
10uH
C13
680nF
50V
15
14
30
26
DVDD
OUT_B+
OUT_B-
C14
C16
C18
C20
C15
1µF
BST_A+ 470nF
BST_A-
VR_DIG
470nF
Channel R
DVDD
DVDD
R2
DVDD
R3
DVDD
R4
DVDD
1µFC17
BST_B+
BST_B-
GND
2
3
20
24
AVDD
GVDD
BST_A+
BST_A-
C19
1µF
470nF
470nF
L4
LRCLK
SCLK
SDIN
Right-
9
8
7
29
25
LRCLK
SCLK
SDIN
BST_B+
BST_B-
R1
0
R5
10.0k
10uH
C21
10.0k
1.0k
10.0k
680nF
50V
ADR
13
12
11
10
4
ADR/HW_MODE
GPIO0/FAULT
GPIO1/PWM_CTRL/MUTE
GPIO2/SDOUT/PD_DET
PDN
SCL/HW_SEL0
SDA/HW_SEL1
GPIO0_FAULT
GPIO1_Hybrid_Pro
GPIO2_WARN
PDN
AMP_SCL
AMP_SDA
1
GPIO0_FAULT
GPIO1_Hybrid_Pro
GPIO2_WARN
PDN
AGND
DGND
PGND
PGND
PGND
PGND
16
21
22
27
28
GND
5
6
AMP_SCL
AMP_SDA
TAS5828MDADR
R6
0
GND
H1
GND
1
2
HEATSINK100W_25X50X25
GND
图9-1. 2.0 (Stereo BTL) System Application Schematic
le
mb
me
li
me
le
pli
mp
is
id
in
in
it
ot
it
ion
esig
ll
ic
il
in
le
io
ic
nd
im le
io
ic
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9.2.2 Design Requirements
• Power supplies:
– 3.3-V supply
– 5-V to 24-V supply
• Communication: host processor serving as I2C compliant controller
• External memory (such as EEPROM and FLASH) used for coefficients.
The requirements for the supporting components for the TAS5828M device in a Stereo 2.0 (BTL) system is
provide in 表9-2.
表9-2. Supporting Component Requirements for Stereo 2.0 (BTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
CAP, AL, 390 uF, 35 V, ± 20%, SMD
C8, C9
390µF
0.1µF
10µF
SMD
0402
0805
0603
0603
0603
0603
0805
C4,C5
C2,C3, C6, C7
C11
CAP, CERM, 10 uF, 35 V, ± 10%, X5R, 0805
CAP,CERM, 22 µF, 35 V, ±20%, JB, 0805
CAP,CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
CAP,CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
CAP,CERM, 1 µF, 16 V, ±10%, X5R, 0603
CAP,CERM, 0.47 µF, 16 V, ±10%, X7R, 0603
CAP,CERM, 0.68 µF, 50 V, ±10%, X7R, 0805
4.7µF
0.1µF
1µF
C12
C15,C17, C19
C14,C16, C18, C20
C1,C10, C13, C21
L1,L2, L3, L4
0.47µF
0.68µF
10µH
Inductor, Shielded Drum Core, Ferrite, 10 uH, 7.1 A,
0.01294 ohm, SMD, 7447709100
R1, R6
R2,R4, R5
R3
0402
0402
0402
RES,0, 5%, 0.063 W, 0402
RES,10.0 k, 1%, 0.063 W, 0402
RES,1.0 k, 1%, 0.063 W, 0402
0Ω
10kΩ
1kΩ
9.2.3 Detailed Design procedures
This Design procedures can be used for both Stereo 2.0, Advanced 2.1 and Mono Mode.
9.2.3.1 Step One: Hardware Integration
• Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
• Following the recommended component placement, board layout, and routing given in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the
high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they
are given precedent as design trade-offs are made is recommended.
– For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
9.2.3.2 Step Two: Hardware Integration
Using the TAS5828MEVM evaluation module and the PPC3 app to configure the desired device settings.
9.2.3.3 Step Three: Software Integration
• Using the End System Integration feature of the PPC3 app to generate a baseline configuration file.
• Generate additional configuration files based upon operating modes of the end-equipment and integrate
static configuration information into initialization files.
• Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
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9.2.4 MONO (PBTL) Systems
In MONO mode, TAS5828M can be used as PBTL mode to drive sub-woofer with more output power.
L1
PVDD
PVDD
10uH
C1
680nF
50V
C2
10uF
35V
C3
10uF
35V
C4
0.1uF
C8
390uF
C5
0.1uF
C6
10uF
35V
C7
10uF
35V
C9
390uF
0xC0
0xC2
0xC4
0xC6
GND
Woofer
GND
GND
GND
GND
DNP
DNP
DNP
DNP
33k
6.8k
1.5k
0
0xC8
0xCA
GND
GND
GND
GND
DVDD
Reserved
Hardware Control Mode
U1
FROM CONTROLLER
C11
4.7uF
C12
0.1uF
17
19
23
LRCLK
SCLK
SDIN
PVDD
OUT_A+
OUT_A-
18
31
32
L3
PVDD
PVDD
PVDD
GND
GND
GND
10uH
C13
680nF
50V
15
14
30
26
DVDD
OUT_B+
OUT_B-
C14
C16
C18
C20
C15
1µF
470nF
470nF
470nF
470nF
VR_DIG
DVDD
DVDD
R2
DVDD
R3
DVDD
R4
DVDD
1µFC17
GND
2
3
20
24
AVDD
GVDD
BST_A+
BST_A-
C19
1µF
LRCLK
SCLK
SDIN
9
8
7
29
25
LRCLK
SCLK
SDIN
BST_B+
BST_B-
R1
0
R5
10.0k
10.0k
1.0k
10.0k
ADR
13
12
11
10
4
ADR/HW_MODE
GPIO0/FAULT
GPIO1/PWM_CTRL/MUTE
GPIO2/SDOUT/PD_DET
PDN
SCL/HW_SEL0
SDA/HW_SEL1
GPIO0_FAULT
GPIO1_Hybrid_Pro
GPIO2_WARN
PDN
AMP_SCL
AMP_SDA
1
GPIO0_FAULT
GPIO1_Hybrid_Pro
GPIO2_WARN
PDN
AGND
DGND
PGND
PGND
PGND
PGND
16
21
22
27
28
5
6
AMP_SCL
AMP_SDA
TAS5828MDADR
R6
0
GND
H1
GND
1
2
HEATSINK100W_25X50X25
GND
图9-2. Sub-woofer (PBTL) Application Schematic
表9-3. Supporting Component Requirements for Sub-woofer (PBTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
CAP, AL, 390 uF, 35 V, ± 20%, SMD
C8, C9
C4,C5
390µF
0.1µF
10µF
SMD
0402
0805
0603
0603
0603
0603
CAP, CERM, 10 uF, 35 V, ± 10%, X5R, 0805
CAP,CERM, 22 µF, 35 V, ±20%, JB, 0805
CAP,CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
CAP,CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
CAP,CERM, 1 µF, 16 V, ±10%, X5R, 0603
CAP,CERM, 0.47 µF, 16 V, ±10%, X7R, 0603
CAP,CERM, 0.68 µF, 50 V, ±10%, X7R, 0805 mb
C2,C3, C6, C7
C11
4.7µF
0.1µF
1µF
C12
C15,C17, C19
C14,C16, C18, C20
C1,C13
0.47µF
0.68µF
10µH
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L1,L3
Inductor, Shielded Drum Core, Ferrite, 10 uH, 7.1 A,
0.01294 ohm, SMD, 7447709100
R1, R6
0402
0402
RES,0, 5%, 0.063 W, 0402
0Ω
R2,R4, R5
RES,10.0 k, 1%, 0.063 W, 0402
10kΩ
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9.2.5 Advanced 2.1 System (Two TAS5828M Devices)
In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was
done in the high-frequency channels. To accomplish this, two TAS5828M devices are used - one for the high
frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can
be sent from the TAS5828M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept
the same digital input as the stereo, which might come from a central systems processor.图 9-3 shows the 2.1
(Stereo BTL with Two TAS5828M devices) system application.
L1
PVDD
PVDD
Left+
10uH
C1
680nF
50V
C2
10uF
35V
C3
10uF
35V
C4
0.1uF
C5
390uF
C6
0.1uF
C7
10uF
35V
C8
10uF
35V
C9
390uF
GND
Channel
L
L2
GND
GND
GND
GND
Left-
GND
GND
GND
GND
10uH
C10
680nF
50V
DVDD
U1
C11
4.7uF
C12
0.1uF
GND
17
19
23
LRCLK
SCLK
SDIN
PVDD
OUT_A+
OUT_A-
18
31
32
L3
PVDD
PVDD
PVDD
Right+
GND
GND
GND
10uH
C13
15
14
30
26
680nF
50V
DVDD
OUT_B+
OUT_B-
C14
C16
C18
C20
C15
1µF
470nF
470nF
470nF
470nF
VR_DIG
Channel
R
DVDD
R1
DVDD
R2
DVDD
1µFC17
GND
2
3
20
24
AVDD
GVDD
BST_A+
BST_A-
C19
1µF
L4
LRCLK
SCLK
SDIN
Right-
9
8
7
29
25
LRCLK
SCLK
SDIN
BST_B+
BST_B-
R3
10.0k
10uH
C21
680nF
50V
10.0k
1.0k
H1
ADR1
FAULT1
Hybrid_Pro
SDOUT
PDN1
AMP_SCL
AMP_SDA
13
12
11
10
4
ADR/HW_MODE
GPIO0/FAULT
GPIO1/PWM_CTRL/MUTE
GPIO2/SDOUT/PD_DET
PDN
SCL/HW_SEL0
SDA/HW_SEL1
1
FAULT1
Hybrid_Pro
AGND
DGND
PGND
PGND
PGND
PGND
16
21
22
27
28
GND
PDN1
5
6
1
2
AMP_SCL
AMP_SDA
HEATSINK100W_25X50X25
TAS5828MDADR
R4
0
GND
GND
L5
GND
PVDD
PVDD
10uH
C22
680nF
50V
FROM CONTROLLER
C23
10uF
35V
C24
10uF
35V
C25
0.1uF
C26
390uF
C27
0.1uF
C28
10uF
35V
C29
10uF
35V
C30
390uF
GND
Woofer
GND
GND
GND
GND
GND
GND
GND
GND
SDOUT
DVDD
U2
C31
4.7uF
C32
0.1uF
17
19
23
PVDD
OUT_A+
OUT_A-
18
31
32
L6
PVDD
PVDD
PVDD
GND
GND
GND
10uH
C33
680nF
50V
15
14
30
26
DVDD
OUT_B+
OUT_B-
C34
C36
C38
C40
C35
1µF
470nF
470nF
470nF
470nF
VR_DIG
DVDD
DVDD
DVDD
1µFC37
GND
2
3
20
24
AVDD
GVDD
BST_A+
BST_A-
C39
1µF
LRCLK
SCLK
SDIN
9
8
7
29
25
LRCLK
SCLK
SDIN
BST_B+
BST_B-
R5
10.0k
R6
1.0k
R8
10.0k
ADR2
13
12
11
10
4
H2
ADR/HW_MODE
GPIO0/FAULT
GPIO1/PWM_CTRL/MUTE
GPIO2/SDOUT/PD_DET
PDN
SCL/HW_SEL0
SDA/HW_SEL1
FAULT2
Hybrid_Pro
SDOUT2
PDN2
AMP_SCL
AMP_SDA
1
FAULT2
PDN2
AGND
DGND
PGND
PGND
PGND
PGND
16
21
22
27
28
5
6
1
2
TAS5828MDADR
HEATSINK100W_25X50X25
R9
1k
GND
GND
GND
图9-3. 2.1 (2.1 CH with Two TAS5828M Devices) Application Schematic
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10 Power Supply Recommendations
The TAS5828M device requires two power supplies for proper operation. A high-voltage supply calls PVDD is
required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low-
voltage power supply which is calls DVDD is required to power the various low-power portions of the device. The
allowable voltage range for both PVDD and DVDD supply are listed in the Recommended Operating Conditions
table. The two power supplies do not have a required powerup sequence. The power supplies can be powered
on in any order.
Internal Digital
Circuitry
Digital IO
DVDD
VR_DIG
1.5V
1.8V/3.3V'
LDO
External Filtering/Decoupling
DVDD
Output Stage
Power Supply
Gate Drive
Voltage
PVDD
4.5V~26.4V
GVDD
5V
LDO
LDO
External Filtering/Decoupling
Internal Analog
Circuitry
PVDD
AVDD
5V
External Filtering/Decoupling
Copyright © 2017, Texas Instruments Incorporated
图10-1. Power Supply Function Block Diagram
10.1 DVDD Supply
The DVDD supply that is required from the system is used to power several portions of the device. As shown in
图 10-1, it provides power to the DVDD pin. Proper connection, routing and decoupling techniques are
highlighted in the Application and Implementation section and the Layout Example section and must be followed
as closely as possible for proper operation and performance.
Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.
To simplify the power supply requirements for the system, the TAS5828M device includes an integrated low
dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuity. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
10.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques
are highlighted in the TAS5828MEVM and must be followed as closely as possible for proper operation and
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performance. Due to the high-voltage switching of the output stage, it is particularly important to properly
decouple the output power stages in the manner described in the TAS5828M device Application and
Implementation. Lack of proper decoupling, like that shown in the Application and Implementation, results in
voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is
provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note
that the linear regulator integrated in the device has only been designed to support the current requirements of
the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this
pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.
AVDD pin is provided for the attachment of decoupling capacitor for the TAS5828M internal circuitry. It is
important to note that the linear regulator integrated in the device has only been designed to support the current
requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional
loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the
device.
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11 Layout
11.1 Layout Guidelines
11.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in the Layout Example section. These examples
represent exemplary baseline balance of the engineering trade-offs involved with lying out the device. These
designs can be modified slightly as needed to meet the needs of a given application. In some applications, for
instance, solution size can be compromised to improve thermal performance through the use of additional
contiguous copper neat the device. Conversely, EMI performance can be prioritized over thermal performance
by routing on internal traces and incorporating a via picket-fence and additional filtering components. In all
cases, it is recommended to start from the guidance shown in the Layout Example section and work with TI field
application engineers or through the E2E community to modify it based upon the application specific goals.
11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This
applies to DVDD, AVDD, GVDD and PVDD. However, the capacitors on the PVDD net for the TAS5828M device
deserve special attention.
The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as
possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in
the system, but doing so can also negatively affect the reliability of the device. Placement of these components
too far from the TAS5828M device can cause ringing on the output pins that can cause the voltage on the output
pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the
deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD
pins than what is shown in the example layouts in the Layout Example section.
11.1.3 Optimizing Thermal Performance
Follow the layout example shown in the 图 11-1 to achieve the best balance of solution size, thermal, audio, and
electromagnetic performance. In some cases, deviation from this guidance can be required due to design
constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can
get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device
naturally travels away from the device and into the lower temperature structures around the device.
11.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
• Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5828M device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
• Place the TAS5828M device away from the edge of the PCB when possible to ensure that the heat can travel
away from the device on all four sides.
• Avoid cutting off the flow of heat from the TAS5828M device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
• Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5828M
device.
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• Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
11.1.3.2 Stencil Pattern
The recommended drawings for the TAS5828M device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system.
备注
The customer must verify that deviation from the guidance shown in the package addendum, including
the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability
goals.
11.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5828M device is soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5828M
device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5828M
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the
Layout Example section, this interface can benefit from improved thermal performance.
备注
Vias can obstruct heat flow if they are not constructed properly.
More notes on the construction and placement of vias are as follows:
• Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
• The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding
planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing should be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
• Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the Layout Example section.
• Ensure that vias do not cut off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias that are farthest from the TAS5828M device to open up the current path
to and from the device.
11.1.3.2.2 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the
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thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to
manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste
to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is
called an aperture array, and is shown in the Layout Example section. It is important that the total area of the
aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the
thermal pad itself.
11.2 Layout Example
2
11cm
From
System
Processor
图11-1. 2.0 (Stereo BTL) 3-D View
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图11-2. 2.0 (Stereo BTL) Top Copper View
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The glossary section is a general glossary with commonly used acronyms and words which are defined in
accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE, and others.
The glossary provided in this section defines words, phrases, and acronyms that are unique to this product and
documentation, collateral, or support tools and software used with this product. For any additional questions
regarding definitions and terminology, please see the e2e Audio Amplfier Forum.
Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one half-
bridge and the other terminal is connected to another half-bridge.
DUT refers to a device under test to differentiate one device from another.
Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing
the output signal to the input signal and attempts to correct for non-linearities in the output.
Dynamic controls are those which are changed during normal use by either the system or the end-user.
GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform
many functions as required by the system.
Host processor (also known as System Processor, Scalar, Host, or System Controller) refers to device
which serves as a central system controller, providing control information to devices connected to it as well as
gathering audio source data from devices upstream from it and distributing it to other devices. This device often
configures the controls of the audio processing devices (like the TAS5828M) in the audio path in order to
optimize the audio output of a loudspeaker based on frequency response, time alignment, target sound pressure
level, safe operating area of the system, and user preference.
Maximum continuous output power refers to the maximum output power that the amplifier can continuously
deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period
of time required that their temperatures reach thermal equilibrium and are no longer increasing
Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to
two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half
bridges placed in parallel
rDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.
Static controls/Static configurations are controls which do not change while the system is in normal use.
Vias are copper-plated through-hole in a PCB.
12.1.2 Development Support
For RDGUI software, please consult your local field support engineer.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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12.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5828MDADR
ACTIVE
HTSSOP
DAD
32
2000 RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
TAS
5828M
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
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