THS1031IPWLE_技术文档

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

28-PIN TSSOP/SOIC PACKAGE

(TOP VIEW)

10-Bit Resolution, 30 MSPS

Analog-to-Digital Converter

Configurable Input Functions:

– Single-Ended

– Single-Ended With Analog Clamp

– Single-Ended With Programmable Digital

Clamp

AGND

AV

DD

AIN

1

28

27

26

25

24

23

22

21

20

19

18

DV

2

DD

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

VREF

3

REFBS

REFBF

MODE

4

5

– Differential

6

Built-In Programmable Gain Amplifier

(PGA)

REFTF

REFTS

CLAMPIN

CLAMP

REFSENSE

7

8

Differential Nonlinearity: ±0.3 LSB

Signal-to-Noise: 56 dB

9

10

11

Spurious Free Dynamic Range: 60 dB

Adjustable Internal Voltage Reference

Straight Binary/2s Complement Output

Out-of-Range Indicator

I/O9 12

OVR 13

17 WR

16 OE

15 CLK

DGND 14

Power-Down Mode

description

The THS1031 is a CMOS, low-power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with

a supply range from 3 V to 5.5 V. The THS1031 has been designed to give circuit developers flexibility. The

analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp amplifier

whose clamp input level can be driven from an external dc source or from an internal high-precision 10-bit digital

clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR for small

signals. The THS1031 provides a wide selection of voltage references to match the user’s design requirements.

For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc

accuracy and temperature drift requirements of the application. The out-of-range output indicates any

out-of-range condition in THS1031’s input signal. The format of digital output can be coded in either unsigned

binary or 2s complement.

The speed, resolution, and single-supply operation of the THS1031 are suited to applications in set-top-box

(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function

allows dc restoration of video signal and is suitable for video applications. The speed and resolution ideally suit

charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and

camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both

imaging and communications systems.

The THS1031C is characterized for operation from 0°C to 70°C, while the THS1031I is characterized for

operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

28-TSSOP (PW)

THS1031CPW

THS1031IPW

28-SOIC (DW)

THS1031CDW

THS1031IDW

0°C to 70°C

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

functional block diagram

Power Down

10-Bit

Clamp

10

DAC

Control

WR

CLAMPIN

Register

CLAMP

Clamp

Amplifier

3

10

Core

ADC

AIN

Sample

and

Hold

Output

Buffer

I/O(0–9)

PGA

REFTS

REFBS

DAC

OVR

OE

Internal

Reference

Buffer

A

B

MODE

REFTF

REFBF

Timing

Circuit

VBG

ORG

GND

REFSENSE

VREF

CLK

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

Terminal Functions

TERMINAL

NAME

AGND

AIN

AV

I/O

DESCRIPTION

NO.

1

I

Analog ground

Analog input

27

28

19

20

15

14

2

Analog supply

DD

CLAMP

CLAMPIN

CLK

High to enable clamp mode, low to disable clamp mode

Connect to an external analog clamp reference input.

Clock input

DGND

Digital ground

DV

Digital driver supply

DD

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

3

4

5

6

7

8

9

10

11

12

Digital I/O bit 0 (LSB)

Digital I/O bit 1

Digital I/O bit 2

Digital I/O bit 3

Digital I/O bit 4

Digital I/O bit 5

Digital I/O bit 6

Digital I/O bit 7

Digital I/O bit 8

Digital I/O bit 9 (MSB)

I/O

MODE

OE

23

16

13

25

24

18

22

21

26

17

I

Mode input

High to 3-state the data bus, low to enable the data bus

Out-of-range indicator

OVR

O

I

REFBS

REFBF

REFSENSE

REFTF

REFTS

VREF

Reference bottom sense

Reference bottom decoupling

Reference sense

I

Reference top decoupling

Reference top sense

I

I/O Internal and external reference

Write strobe

WR

I

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range: AV

to AGND, DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V

AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V to 6.5 V

DD

Mode input voltage range, MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

Reference voltage input range, REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . –0.3 V to AV

Analog input voltage range, AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

Reference input voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

Reference output voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

Clock input voltage range, CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

Digital input voltage range, digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV

Digital output voltage range, digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV

+ 0.3 V

DD

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

J

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

digital inputs

MIN NOM

MAX

UNIT

Clock input

0.8 × AV

DD

High-level input voltage, V

IH

V

All other inputs

Clock input

0.8 × DV

DD

0.2 × AV

0.2 × DV

DD

Low-level input voltage, V

V

IL

All other inputs

DD

analog inputs

MIN

REFBS

1

NOM

MAX

REFTS

2

UNIT

Analog input voltage, V

I(AIN)

(PGA = 1x, top, bottom, or external reference mode)

V

Reference input voltage, V

I(VREF)

Clamp input voltage, V

0.1

AV –0.1

DD

I(CLAMPIN)

power supply

MIN NOM

MAX

5.5

UNIT

AV

DD

3

3.3

Supply voltage

Maximum sampling rate = 30 MSPS

V

DV

5.5

DD

REFTS, REFBS reference voltages (MODE = AV

)

DD

PARAMETER

MIN NOM

MAX

AV

UNIT

V

REFTS

REFBS

Reference input voltage (top)

1

DD

Reference input voltage (bottom)

0

AV –1

V

DD

Differential input voltage (REFTS – REFBS)

Switched input capacitance on REFTS or REFBS

1

2

V

0.6

pF

sampling rate and resolution

PARAMETER

MIN NOM

MAX

UNIT

MHz

Bits

f

s

Sample frequency

Resolution

5

30

10

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

electrical characteristics over recommended operating conditions, AV

= 3 V, DV

= 3 V,

DD

f = 30 MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,

s

DD

PGA = 1X, T = T

to T

(unless otherwise noted)

A

min

max

analog inputs

PARAMETER

MIN

TYP

MAX

UNIT

V

I(AIN)

Analog input voltage

REFBS

REFTS

C

Switched sampling input capacitance

Full power bandwidth (–3 dB)

1.2

150

100

pF

I

BW

MHz

µA

I

DC leakage current (input = ± FS)

lkg

VREF reference voltages

PARAMETER

Internal 1-V reference voltage (REFSENSE = VREF)

MIN

TYP

MAX

1.05

2.10

2

UNIT

V

0.95

1.90

1

2

Internal 2-V reference voltage (REFSENSE = AV

)

V

SS

)

External reference voltage (REFSENSE = AV

DD

V

Reference input resistance (REFSENSE = AV , MODE = AV /2)

DD DD

18

kΩ

REFTF, REFBF reference voltages

PARAMETER

TEST CONDITIONS

MIN

1

TYP

MAX

2

UNIT

Differential input voltage (REFTF – REFBF)

V

AV

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

1.3

2

1.5

2.5

2

1.7

3

DD

Input common mode voltage (REFTF + REFBF)/2

V

VREF = 1 V

3

REFTF voltage (MODE = AV

REFBF voltage (MODE = AV

)

DD

2.5

3.5

1

VREF = 2 V

VREF = 1 V

VREF = 2 V

2

)

DD

0.5

1.5

680

V

Input resistance between REFTF and REFBF

Ω

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

electrical characteristics over recommended operating conditions, AV

= 3 V, DV

= 3 V,

DD

f = 30 MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,

s

DD

PGA = 1X, T = T

to T

(unless otherwise noted) (continued)

A

min

max

dc accuracy

PARAMETER

MIN

TYP

±1

MAX

±2

±1

2

UNIT

LSB

INL

Integral nonlinearity (see Note 1)

DNL

Differential nonlinearity (see Note 2)

Offset error (see Note 3)

Gain error (see Note 4)

Missing code

±0.3

0.4

LSB

%FSR

1.4

3.5 %FSR

No missing code assured

NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The

deviation is measured from the center of each particular code to the true straight line between these two endpoints.

2. AnidealADCexhibitscodetransitionsthatareexactly1LSBapart. DNListhedeviationfromthisidealvalue.Thereforethismeasure

indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under

n

test (i.e., (last transition level – first transition level) ÷ (2 – 2)). Using this definition for DNL separates the effects of gain and offset

error. A minimum DNL better than –1 LSB ensures no missing codes.

3. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the

bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by

the number of ADC output levels (1024).

4. Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5

LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references

divided by the number of ADC output levels (1024).

dynamic performance (ADC and PGA)

PARAMETER

TEST CONDITIONS

MIN

TYP

9

MAX

UNIT

f = 3.5 MHz

8.2

f = 3.5 MHz, AV

f = 15 MHz

= 5 V

8.8

7.7

7.64

60

DD

ENOB

SFDR

THD

Effective number of bits

Bits

f = 15 MHz, AV

f = 3.5 MHz

DD

55

f = 3.5 MHz, AV

f = 15 MHz

63

DD

Spurious free dynamic range

Total harmonic distortion

Signal-to-noise ratio

dB

48

f = 15 MHz, AV

f = 3.5 MHz

52.4

DD

–58.2 –54.7

f = 3.5 MHz, AV

f = 15 MHz

–68.7

–47

–51.9

56

DD

f = 15 MHz, AV

f = 3.5 MHz

DD

51.2

51.1

f = 3.5 MHz, AV

f = 15 MHz

55

DD

SNR

53

f = 15 MHz, AV

f = 3.5 MHz

49.3

56

DD

f = 3.5 MHz, AV

55

DD

SINAD Signal-to-noise and distortion

f = 15 MHz

48.1

47.7

f = 15 MHz, AV

DD

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

electrical characteristics over recommended operating conditions, AV

= 3 V, DV

= 3 V,

DD

f = 30 MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,

s

DD

PGA = 1X, T = T

to T

(unless otherwise noted) (continued)

A

min

max

PGA

PARAMETER

MIN

TYP

0.5

3

MAX

UNIT

V/V

Gain range (linear scale)

Gain step size (linear scale)

Gain error from nominal

Number of control bits

0.5

4

V/V

3%

Bits

clamp amplifier and clamp DAC

PARAMETER

MIN

TYP

MAX

UNIT

Bits

V

Resolution

10

DAC output range

REFBF

REFTF

1

DAC differential nonlinearity

DAC integral nonlinearity

Clamping analog output voltage range

Clamping analog output voltage error

–1

LSB

V

±1

0.1

AV –0.1

DD

–40

40

mV

clock

PARAMETER

MIN

33

TYP

MAX

UNIT

ns

t

Clock cycle

c

Pulse duration, clock high

15

16.5

ns

w(CKH)

w(CKL)

d(o)

15

ns

Clock to data valid, delay time

Pipeline latency

25

ns

3

4

Cycles

ns

t

Aperture delay time

d(AP)

Aperture uncertainty (jitter)

2

ps

timing

PARAMETER

MIN

0

TYP

MAX

20

UNIT

ns

t

Output disable to Hi-Z output, delay time

Output enable to output valid, delay time

Output disable to write enable, delay time

Write disable to output enable, delay time

Write pulse duration

d(DZ)

d(DEN)

d(OEW)

d(WOE)

w(WP)

su

0

20

ns

12

15

5

ns

Input data setup time

ns

Input data hold time

5

ns

h

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

30.6

94

MAX

45

UNIT

I

Operating supply current

Power dissipation

Standby power

AV

= 3 V, MODE = AGND

mA

CC

DD

= DV

= 3 V

135

DD

P

D

mW

= 5 V

160

3

P

= 3 V, MODE = AGND

5

D(STBY)

7

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THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PARAMETER MEASUREMENT INFORMATION

OE

See Note A

t

w(WP)

t

d(WOE)

d(OEW)

WE

t

h

d(DZ)

t

d(DEN)

su

Hi-Z

Output

Input

Output

I/O

NOTE A: All timing measurements are based on 50% of edge transition.

Figure 1. Write Timing Diagram

Sample 2

Sample 3

Sample 1

Sample 5

Sample 4

Analog Input

t

c

t

w(CKL)

t

(CKH)

Input Clock

See

Note A

t

d(o)

Pipeline Latency

Digital Output

Sample 1

Sample 2

NOTE A: All timing measurements are based on 50% of edge transition.

Figure 2. Digital Output Timing Diagram

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

TYPICAL CHARACTERISTICS

POWER DISSIPATION

vs

SAMPLING FREQUENCY

96

94

92

90

88

86

84

82

AV

DD

= DV

= 3 V

DD

f = 3.5 MHz

i

T

= 25°C

A

5

10

15

20

25

30

f

– Sampling Frequency – MHz

s

Figure 3

EFFECTIVE NUMBER OF BITS

vs

TEMPERATURE

10.0

9.5

9.0

8.5

8.0

7.5

7

AV

DD

= DV

= 3 V

DD

f = 3.5 MHz

i

f

= 30 MSPS

s

–40

–15

10

35

60

85

T

A

– Temperature – °C

Figure 4

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

SAMPLING FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

7

AV

DD

= DV

= 3 V

DD

f = 3.5 MHz

i

T

= 25°C

A

5

10

15

20

25

30

f

– Sampling Frequency – MSPS

s

Figure 5

EFFECTIVE NUMBER OF BITS

vs

SAMPLING FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

7

AV

DD

= 5 V,

= 3 V

DV

DD

f = 3.5 MHz

i

A

T

= 25°C

5

10

15

20

25

30

f

– Sampling Frequency – MSPS

s

Figure 6

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

SAMPLING FREQUENCY

10.00

9.50

9.00

8.50

8.00

7.50

7.00

AV

DD

= DV = 5 V,

DD

f = 3.5 MHz

i

T

= 25°C

A

5

10

15

20

25

30

f

– Sampling Frequency – MSPS

s

Figure 7

DIFFERENTIAL NONLINEARITY

vs

INPUT CODE

1.0

0.8

0.6

AV

DD

s

= 3 V, DV

= 30 MSPS

= 3 V

DD

f

0.4

0.2

–0.0

–0.2

–0.4

–0.6

–0.8

–1

0

128

256

384

512

640

768

896

1024

Input Code

Figure 8

11

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THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

vs

INPUT CODE

2.0

1.5

AV

DD

= 3 V

DV

DD

f

= 30 MSPS

1.0

s

0.5

0.0

–0.5

–1.0

–1.5

–2.0

0

128

256

384

512

640

768

896

1024

Input Code

Figure 9

FFT

vs

FREQUENCY

0

–20

AV

DD

= 3 V

DV

DD

f = 3.5 MHz,

i

–40

–1 dBFS

–60

–80

–100

–120

–140

0

200

1.5

400

3

600

4.5

800

6

1000

7.5

1200

9

1400

10.5

1600

12

1800

13.5

2000

15

f – Frequency – MHz

Figure 10

12

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THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

The analog input AIN is sampled in the sample-and-hold unit, the output of which goes to a programmable gain

amplifier (PGA). The PGA feeds the ADC core, where the process of analog to digital conversion is performed

against ADC reference voltages, REFTF and REFBF.

Connecting the MODE pin to one of three voltages, AGND, AV

or AV /2 sets up operating configurations.

DD

The three settings open or close internal switches to select one of the three basic methods of ADC reference

generation.

Depending on the user’s choice of operating configuration, the ADC reference voltages may come from the

internal reference buffer (IRB) or may be fed from completely external sources. Where the reference buffer is

employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external

voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and

REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user.

The THS1031 offers a clamp function for dc restoration of ac-coupled signals. The clamp voltage may be set

digitally via the 10-bit clamp DAC or by the analog level applied to the CLAMPIN input.

The ADC core drives out through output buffers to the I/O pins I/O0 to I/O9. The output buffers can be disabled

by the OE pin. Control input data on I/O0 to I/O9 can then be written, by pulses on WR, to the control registers.

These registers control clamp operation, output format (unsigned binary or twos complement), the PGA gain

setting and the device power down function.

A single-ended, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is

sampled on the rising edge of CLK, and corresponding data is output after the following third rising edge.

The user-chosen operating configuration and reference voltages determine what input signal voltage range the

THS1031 can handle.

The following sections explain:

Theinternalsignalflowofthedevice, andhowtheinputsignalspanisrelatedtotheADCreferencevoltages;

The ways in which the ADC reference voltages can be buffered internally, or externally applied;

How to set the onboard reference generator output, if required, and several examples of complete

configurations.

Subsequent sections explain the clamp function and digital controls, followed by more detailed application

information.

signal processing chain (sample and hold, PGA, ADC)

Figure 11 shows the signal flow through the sample and hold unit and the PGA to the ADC core.

REFTF

VP+

VQ+

1

AIN

REFTS

REFBS

Sample

and

Hold

ADC

Core

–1/2

PGA

VP–

VQ–

REFBF

Figure 11. Analog Input Signal Flow

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PRINCIPLES OF OPERATION

sample-and-hold

The analog input signal A is applied to the AIN pin, either dc-coupled, ac-coupled, or ac-coupled with dc

IN

restoration using the THS1031 clamp circuit.

The differential sample and hold processes A with respect to the voltages applied to the REFTS and REFBS

IN

pins, to give a differential output VP+ – VP– = VP given by:

VP = A – VM

IN

(1)

Where:

VM

(REFTS REFBS)

2

(2)

For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However if

MODE = AV /2 then REFTS and REFBS can be connected together to operate with AIN as a complementary

DD

pair of differential inputs (see Figures 15 and 16).

programmable gain amplifier

+

–

VP is amplified by the PGA and fed into the ADC as a differential voltage VQ – VQ = VQ

VQ = Gain × VP = Gain × [A – VM]

IN

The default PGA gain at power up is 1, but can be programmed from 0.5 to 4.0 via the control register.

analog-to-digital converter

In all operating configurations, VQ is digitized against ADC reference voltages REFTF and REFBF, full-scale

values of VQ being given by

(REFTF REFBF)

VQFS

2

(3)

(REFTF REFBF)

2

VQFS

VQ voltages outside the range VQFS– to VQFS+ lie outside the conversion range of the ADC. Attempts to

convert out-of-range inputs are signalled to the application by driving the OVR output pin high. VQ voltages less

than VQFS– give ADC output code 0. VQ voltages greater than VQFS+ give output code 1023.

complete system

Combining equations 1 to 3, the analog full-scale input voltages at AIN which give VQFS+ and VQFS– at the

PGA output are:

(REFTF REFBF)

A

FS

VM

IN

(2 Gain)

(4)

and

(REFTF REFBF)

(2 Gain)

A

FS

VM

IN

(5)

(6)

The analog input span (voltage range) that lies within the ADC conversion range is:

Input span [(FS (FS )] (REFTF REFBF) Gain

)

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PRINCIPLES OF OPERATION

complete system (continued)

The REFTF and REFBF voltage difference and the gain sets the device input range. The next sections describe

in detail the various methods available for setting voltages REFTF and REFBF to obtain the desired input span

and device performance.

ADC reference generation

The THS1031 has three primary modes of ADC reference generation, selected by the voltage level applied to

the MODE pin.

Connecting the MODE pin to AGND gives full external reference mode. In this mode, the user supplies the ADC

reference voltages directly to pins REFTF and REFBF. This mode is used where there is need for minimum

power drain or where there are very tight tolerances on the ADC reference voltages. This mode also offers the

possibility of Kelvin connection of the reference inputs to the THS1031 to eliminate any voltage drops from

remote references that may occur in the system. Only single-ended input is possible in this mode.

Connecting the MODE pin to AV /2 gives differential mode. In this mode, the ADC reference voltages REFTF

DD

and REFBF are generated by the internal reference buffer from the voltage applied to the VREF pin. This mode

is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins.

A special case of differential mode is center span mode, in which user applies a single-ended signal to AIN and

applies the mid-scale input voltage (VM) to the REFTS and REFBS pins.

Connecting the MODE pin to AV

gives top/bottom mode. In this mode, the ADC reference voltages REFTF

DD

and REFBF are generated by the internal reference buffer from the voltages applied to the REFTS and REFBS

pins. Only single-ended input is possible in top/bottom mode.

Table 1. Typical Set of Reference Connections

VREF

VOLTAGE

REFERENCE MODE

MODE

REFSENSE

REFTS, REFBS

ANALOG INPUT FIGURES

Reference buffer powered

down, reference voltage pro-

vided directly by REFTS and

REFBS

External

AV

SS

AV

DD

Disabled

Single-ended

12, 13, 14

15, 16, 17

VREF

AGND

1 V

2 V

Externally connect REFTS

to REFBS. This pair then

forms AIN– to the ADC.

Differential or

center span

Internal

AV /2

DD

External

divider

1 + Ra/Rb

(see Figure 22)

External (through internal

reference buffer)

AV

DD

Disabled

REFTS = V

+ (V

–

Single-ended

MID

) × Gain/2

FS+

V

FS–

VREF

AGND

1 V

2 V

Output of VREF can be

externally tied to REFTS or

REFBS to provide one of the

reference voltages

AV

DD

18, 19

REFBS = V

MID

– (V

(top-bottom

mode)

V ) × Gain/2

FS–

External

divider

1 + Ra/Rb

(see Figure 22)

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PRINCIPLES OF OPERATION

full external reference mode (mode = AGND)

REFTF

1

AIN+

REFTS

REFBS

Sample

and

Hold

ADC

Core

–1/2

PGA

REFBF

Internal

Reference

Buffer

Figure 12. ADC Reference Generation, MODE = AGND

When MODE is connected to AGND, the internal reference buffer is powered down, its inputs and outputs

disconnected, and REFTS and REFBS internally connected to REFTF and REFBF respectively. These nodes

are connected by the user to external sources to provide the ADC reference voltages. The internal connections

are designed for use in kelvin connection mode (Figure 14). When using external reference mode as shown

in Figure 13, REFTS must be shorted to REFTF and REFBS must be shorted to REFBF externally. The mean

of REFTF and REFBF must be equal to AV /2 (see Figure 13).

DD

AV

DD

+FS

AV

DD

AIN

REFSENSE

2

–FS

AV

DD

GAIN

2

REFTS

REFBS

DC SOURCE =

+ [(FS+) – (FS–)] ×

2

AV

DD

GAIN

2

– [(FS+) – (FS–)] ×

0.1 µF

2

REFTF

REFBF

10 µF

0.1 µF

MODE

Figure 13. Full External Reference Mode

It is also possible to use REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode)

to overcome any voltage drops within the system (see Figure 14).

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PRINCIPLES OF OPERATION

full external reference mode (mode = AGND) (continued)

AV

DD

+FS

AV

DD

AIN

REFSENSE

2

–FS

REFTS

REFBS

_

+

AV

REFTF

DD

GAIN

2

REFT =

REFB =

+ [(FS+) – (FS–)] ×

– [(FS+) – (FS–)] ×

2

0.1 µF

10 µF

0.1 µF

_

+

REFBF

MODE

AV

DD

GAIN

2

Figure 14. Full External Reference With Kelvin Connections

differential mode (mode = AV /2)

DD

AV

DD

+ VREF

2

REFTF =

1

AIN+

REFTS

REFBS

Sample

and

Hold

ADC

Core

–1/2

PGA

AIN–

AV

DD

– VREF

Internal

Reference

Buffer

VREF

REFBF =

2

AGND

Figure 15. ADC Reference Generation, MODE = AV /2

DD

When MODE = AV /2, the internal reference buffer is enabled, its outputs internally switched to REFTF and

DD

REFBF and inputs internally switched to VREF and AGND as shown in Figure 15. The REFTF and REFBF

voltages are centered on AV /2 by the internal reference buffer and the voltage difference between REFTF

DD

and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are

open in this mode, allowing REFTS and REFBS to form the AIN– to the sample and hold.

Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to

an internally generated voltage of 1 V, 2 V, or an intermediate voltage (see the onboard reference generator

configuration).

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PRINCIPLES OF OPERATION

differential mode (mode = AV /2) (continued)

DD

AV

DD

+FS

2

AIN+

AIN

MODE

–FS

+FS

REFTS

AIN–

–FS

REFBS REFSENSE

0.1 µF

REFTF

REFBF

VREF

10 µF

0.1 µF

Figure 16. Differential Input Mode, 1-V Reference Span

AV

DD

2

+FS

VM

–FS

AIN

MODE

REFTS

DC SOURCE = VM

+

_

VM

REFBS

REFTF

0.1 µF

10 µF

0.1 µF

REFBF

REFSENSE

Figure 17. Center Span Mode, 2-V Reference Span

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PRINCIPLES OF OPERATION

top/bottom mode (MODE = AV

)

DD

REFTF = AV

DD

+ (REFTS – REFBS)

2

1

AIN+

REFTS

REFBS

Sample

and

Hold

ADC

Core

–1/2

PGA

REFBF = AV

– (REFTS – REFBS)

Internal

Reference

Buffer

DD

2

Figure 18. ADC Reference Generation Mode = AV

DD

ConnectingMODEtoAV enablestheinternalreferencebuffer. ItsinputsareinternallyswitchedtotheREFTS

DD

and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections

(REFTS to REFTF) and (REFBS to REFBF) are broken.

To match the signal span to the full ADC input span, the voltage difference between REFTS and REFBS should

be REFTS – REFBS = [(FS+) – (FS–)] × Gain, with the average of the REFTS and REFBS voltages being the

AIN midscale voltage, VM.

Typically, REFSENSE is tied to AV

choose to use the ORG output to VREF as either REFTS or REFBS.

to disable the ORG output to VREF (as in Figure 19), but the user can

DD

AV

DD

+FS

AIN

MODE

–FS

GAIN

DC SOURCE = VM + [(FS+) – (FS–)] ×

REFSENSE

REFTS

REFBS

2

GAIN

2

DC SOURCE =VM – [(FS+) – (FS–)] ×

0.1 µF

REFTF

REFBF

10 µF

0.1 µF

Figure 19. ADC Reference Generation Mode = AV

DD

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PRINCIPLES OF OPERATION

onboard reference generator configuration

The onboard reference generator (ORG) can supply a supply-voltage-independent and temperature-

independent voltage on pin VREF.

External connections to REFSENSE control the ORG’s output to the VREF pin as shown in Table 2.

Table 2. Effect of REFSENSE Connection on VREF Value

REFSENSE CONNECTION

VREF pin

ORG OUTPUT TO VREF

REFER TO:

Figure 20

Figure 21

Figure 22

Figure 23

1 V

2 V

AGND

External divider junction

(1 + R /R )

A B

AV

DD

Open circuit

REFSENSE = AV

powers the ORG down, saving power when the ORG function is not required.

DD

If MODE = AV /2, the voltage on VREF determines the ADC reference voltages:

DD

AV

DD

VREF

2

REFTF

REFBF

2

(7)

AV

DD VREF

2

REFTF REFBF

VREF

Internal

Reference

Buffer

Mode =

AV

DD

2

+

_

VREF = 1 V

REFSENSE

+

VBG

_

0.1 µF 1 µF

Tantalum

AGND

Figure 20. 1-V VREF Using ORG

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PRINCIPLES OF OPERATION

onboard reference generator configuration (continued)

Internal

Reference

Buffer

Mode =

AV

DD

2

+

_

VREF = 2 V

REFSENSE

+

_

VBG

0.1 µF 1 µF

Tantalum

10 kΩ

AGND

Figure 21. 2-V VREF Using ORG

Internal

Reference

Buffer

Mode =

AV

DD

2

+

_

VREF = 1 + (Ra/Rb)

+

_

VBG

0.1 µF 1 µF

Tantalum

Ra

REFSENSE

Rb

AGND

Figure 22. External Divider Mode

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PRINCIPLES OF OPERATION

onboard reference generator configuration (continued)

Internal

Reference

Buffer

Mode =

AV

DD

2

VREF = External

REFSENSE

+

_

+

VBG

_

AV

DD

AGND

Figure 23. Drive VREF Mode

operating configuration examples

This section provides examples of operating configurations.

Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF

to drive REFTS and with PGA gain = 1. Connecting the MODE pin to AV

puts the THS1031 in top/bottom

DD

mode. Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are

user-connected to VREF and AGND respectively to match the AIN pin input range to the voltage range of the

input signal.

AV

DD

2 V

1 V

0 V

AIN

MODE

VREF = 2 V

REFTS

0.1 µF

REFTF

REFBF

REFSENSE

REFBS

10 µF

0.1 µF

Figure 24. Operation Configuration in Top/Bottom Mode

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PRINCIPLES OF OPERATION

operating configuration examples (continued)

In Figure 25, the input signal is differential, soMode=AV /2(differentialmode)issettoallowtheinversesignal

DD

to be applied to REFTS and REFBS. The differential input goes from –0.8 V to 0.8 V, giving a total input signal

span of 1.6 V. Using a PGA gain of 1, REFTF–REFBF should therefore, equal 1.6 V. REFSENSE is connected

to resistors RA and RB (external divider mode) to make VREF = 1.6 V, that is R /R = 0.6 (see Figure 22).

A

B

AV

DD

2

1.4 V

1 V

AIN+

AIN

MODE

0.6 V

1.4 V

1 V

REFTS

AIN–

VREF = 1.6 V

REFSENSE

0.6 V

REFBS

REFTF

R

A

B

0.1 µF

R

10 µF

0.1 µF

REFBF

Figure 25. Differential Operation

Figure 26 shows a center span configuration for an input waveform swinging between 0.2 and 1.9 V. Pins

REFTS and REFBS are connected to a voltage source of 1.05 V, equal to the mid-scale of the input waveform.

With the PGA gain set to its default value of 1, REFTF–REFBF should be set equal to the span of the input

waveform, 1.7 V, so VREF is connected to an external source of 1.7 V. REFSENSE must be connected to AV

to disable the ORG output to VREF (see Figure 23) to allow this external source to be applied.

DD

AV

DD

AV

DD

2

1.9 V

1.05 V

0.2 V

AIN

MODE

REFSENSE

REFTS

DC SOURCE = 1.05 V

REFBS

REFTF

0.1 µF

VREF

DC SOURCE = 1.7 V

10 µF

0.1 µF

REFBF

Figure 26. Center Span Operation

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PRINCIPLES OF OPERATION

operating configuration examples (continued)

Figure 27 shows an example of top/bottom mode operation on an input span of 800 mV with mid-scale value

1.5 V. Pin REFTS is set to 2.5 V and pin REFBS to 0.5 V, making their average value equal to the mid-scale

value of A and giving the maximum specified difference of 2 V between REFTS and REFBS to maximize the

IN

full-scale range of the ADC core for best resolution. The PGA gain then has to be set to 2.5, to amplify the

800 mV input signal to 2 V at the ADC core input.

PP

AV

DD

1.9 V

1.5 V

1.1 V

AIN

MODE

REFSENSE

REFTS

DC SOURCE = 2.5 V

DC SOURCE = 0.5 V

REFBS

REFTF

0.1 µF

10 µF

0.1 µF

REFBF

Figure 27. Top/Bottom Mode, PGA Gain 2.5

clamp operation

10-Bit

DAC

CLAMPIN

CLAMP

Control Register (Bit CLINT)

(Clamp)

+

_

V

C

SW1

IN

R

IN

AIN

S/H

V

IN

Figure 28. Schematic of Clamp Circuitry

The THS1031 provides a clamp function for restoring a dc reference level to the signal at AIN which has been

lost through ac-coupling from the signal source to this pin.

Figure 29 shows an example of using the clamp to restore the black level of a composite video input ac coupled

to AIN. While the clamp pin is held high, the clamp amplifier forces the voltage at AIN to equal the clamp

reference voltage, setting the dc voltage at AIN for the video black level.

After power up, the clamp reference voltage is the voltage on the CLAMPIN pin. This reference can instead be

taken from the internal CLAMP DAC by suitably programming the THS1031 clamp and control registers.

Clamp acquisition and clamp droop design calculations are discussed later.

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PRINCIPLES OF OPERATION

clamp operation (continued)

Line Sync

Black

Level

Video at AIN

CLAMP

Figure 29. Example Waveforms for Line-Clamping to a Video Input Black Level

clamp DAC output voltage range and limits

When using the internal clamp DAC in top/bottom or center span mode, the user must ensure that the desired

dc clamp level at AIN lies within the voltage range V to V . This is because the clamp DAC voltage

REFBF

REFTF

is constrained to lie within this range V

to V

. Specifically:

REFBF

VDAC

V

(V

V

)

(0.006 0.988 (DAC code) 1024)

REFBF

REFTF

REFBF

(8)

DAC codes can range from 0 to 1023. Figure 30 graphically shows the clamp DAC output voltage versus the

DAC code.

VDAC

V

REFTF

V

+ 0.006(V )

–V

REFBF

REFTF REFBF

V

+ 0.987(V )

–V

REFBF

REFTF REFBF

V

REFBF

DAC Code

0

1023

Figure 30. Clamp DAC Output Voltage Versus DAC Register Code Value

If the desired dc level at AIN does not lie within the voltage range V to V , then either the CLAMPIN

REFTF

REFBF

pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application

to move the AIN input range into the CLAMP DAC voltage range. This is achieved in both top/bottom and center

span modes by shifting both REFTS and REFBS up or down by the voltage through which the AIN input range

is to be moved.

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PRINCIPLES OF OPERATION

power management

In power-sensitive applications (such as battery-powered systems) where the THS1031 ADC is not required

to convert continuously, power can be saved between conversion intervals by placing the THS1031 into

power-down mode. This is achieved by setting bit 3 (PWDN) of the control register to 1. In power-down mode,

the device typically consumes less than 1 mW of power in either top/bottom or center-span modes. Power-down

mode is exited by resetting control register bit 3 to 0. On power up, the THS1031 typically requires 5 ms of

wake-up time before valid conversion results are available.

In systems where the ADC must run continuously, but where the clamp is not required, setting control register

bit 6 (CLDIS to 1), which disables only the clamp circuits, can save power.

Disabling the ORG in applications where the ORG output is not required can also reduce power dissipation by

1 mA analog I . This is achieved by connecting the REFSENSE pin to AV

.

DD

output format and digital I/O

While the OE pin is held low, ADC conversion results are output at pins I/O0 (LSB) to I/O9 (MSB). The ADC input

over-range indicator is output at pin OVR. OVR is also disabled when OE is held high.

The default ADC output data format is unsigned binary (output codes 0 to 1023). The output format can be

switched to 2s complement (output codes –512 to 511) by setting control register bit 5 (TWOC) to 1.

writing to the internal registers through the digital I/O bus

Pulling pin OE high disables the I/O and OVR pin output drivers, placing the driver outputs in a high impedance

state. This allows control register data to be loaded into the THS1031 by presenting it on the I/O0 to I/O9 pins

and pulsing the WR pin high to latch the data into the chosen control or DAC register.

Figure 31 shows an example register write cycle where the clamp DAC code is set to 10F (hex) by writing to

clamp registers 1 and 2 (see the register map in Table 3). Pins I/O0 to I/O7 are driven to the clamp DAC code

lower byte (0F hex) and pins I/08 and I/O9 are both driven to 0 to select clamp register 1 as the data destination.

The clamp low-byte data is then loaded into this register by pulsing WR high. The top 2 bits of the DAC word

are then loaded by driving 01(hex) on pins I/O0 to I/O7 and by driving pin I/O8 to 1 and pin I/O9 to 0 to select

clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp

register 2. Interface timing parameters are given in Figures 1 and 2.

OE

WR

Output

Input 00F

Input 101

Output

I/O (0–9)

Load 0F Into

REGISTER 0

Load 01 Into

REGISTER 1

Figure 31. Example Register Write Cycle to Clamp DAC Register

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digital control registers

The THS1031 contains two clamp registers and a control register for user programming of THS1031 operation.

Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE pins (see the

previous section). In input mode, the two I/O bus MSBs are address bits, 00 addressing clamp register 1, 01

clamp register 2, and 10 the control register.

Table 3. Register Map

BIT

ADDRESS

I/O[9:8]

DEF

(HEX)

DESCRIPTION

B7

B6

B5

B4

B3

B2

B1

B0

00

01

10

11

Clamp Reg. 1

Clamp Reg. 2

Control Reg.

Reserved

00

01

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[9]

PGA[1]

DAC[0]

DAC[8]

PGA[0]

CLDIS

TWOC

CLINT

PDWN

PGA[2]

Table 4. Register Contents

REGISTER

BIT NO BIT NAME(S)

DEFAULT

DESCRIPTION

PGA gain:

000 = 0.5

001 = 1.0 (default value)

010 = 1.5

2:0

PGA[2:0]

0

011 = 2.0

100 = 2.5

101 = 3.0

110 = 3.5

111 = 4.0

Power down

3

4

5

PDWN

CLINT

TWOC

CLDIS

0

0 = THS1031 powered up

1 = THS1031 powered down

Control Register

I/O[9:8] = 10

Clamp voltage internal/external

0 = external analog clamp voltage from CLAMPIN pin

1 = from onboard DAC (see clamp register)

Output format

0 = unsigned binary

1 = two’s complement

Clamp amplifier disable (for power saving)

0 = Enable

1 = Disable

6

7

Unused

Clamp DAC voltage

Clamp Register 1

I/O[9:8] = 00

(DAC[0] = LSB.)

DAC[9:0] = 00h: Clamp voltage = REFBF

DAC[9:0] = 3Fh: Clamp voltage = REFTF

7:0

DAC[7:0]

DAC[9:8]

0

7:2

1:0

Unused

Clamp Register 2

I/O[9:8] = 01

Clamp DAC voltage

(DAC[9] = MSB)

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

driving the THS1301 analog inputs

driving AIN

Figure 32 shows an equivalent circuit for the THS1031 AIN pin. The load presented to the system at the AIN

pin comprises the switched input sampling capacitor, C

, and various stray capacitances, C and C

.

SAMPLE

P1

P2

AV

DD

CLK

1.2 pF

AIN

C

C1

8 pF

C2

1.2 pF

SAMPLE

AGND

CLK

+

_

V

LAST

Figure 32. Equivalent Circuit of Analog Input AIN

In any single-ended input mode, V = the average of the previously sampled voltage at AIN and the average

LAST

of the voltages on pins REFTS and REFBS. In any differential mode, V

= the common mode input voltage.

LAST

The external source driving AIN must be able to charge and settle into C

to within 0.5 LSB error while sampling (CLK pin low) to achieve full ADC resolution.

and the C and C strays

P1 P2

SAMPLE

AIN input current and input load modeling

When CLK goes low, the source driving AIN must charge the total switched capacitance C = C

S

The total charge transferred depends on the voltage at AIN and is given by

+ C

.

SAMPLE

P2

Q

(AIN

V

)

C .

CHARGING

LAST

S

(9)

do not change between samples, the maximum amount of

For a fixed voltage at AIN, so that AIN and V

charge transfer occurs at AIN = FS– (charging current flows out of THS1030) and AIN = FS+ (current flows into

LAST

THS1030). If AIN is held at the voltage FS+, VLAST = [(FS+) + VM]/2, giving a maximum transferred charge:

[(FS

)

VM]

C

(FS

)

[(FS

2

)

VM]

S

Q(FS)

C

S

2

(10)

(1 4 of the input voltage span)

C

S

If the input voltage changes between samples, then the maximum possible charge transfer is

Q(max) Q(FS)

which occurs for a full-scale input change (FS+ to FS– or FS– to FS+) between samples.

3

(11)

The charging current pulses can make the AIN source jump or ring, especially if the source is slightly inductive

at high frequencies. Inserting a small series resistor of 20 Ω or less in the input path can damp source ringing.

See Figure 33. This resistor can be made larger than 20 Ω if reduced input bandwidth or distortion performance

is acceptable.

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

AIN input current and input load modeling (continued)

R< 20 Ω

AIN

V

S

Figure 33. Damping Source Ringing Using a Small Resistor

equivalent input resistance at AIN and ac-coupling to AIN

Some applications may require ac-coupling of the input signal to the AIN pin. Such applications can use an

ac-coupling network such as shown in Figure 34.

AV

DD

R

(Bias1)

C

in

AIN

R

(Bias2)

Figure 34. AC-Coupling the Input Signal to the AIN Pin

Note that if the bias voltage is derived from the supplies, as shown in Figure 34, then additional filtering should

be used to ensure that noise from the supplies does not reach AIN.

Working with the input current pulse equations given in the previous section is awkward when designing

ac-coupling input networks. For such design, it is much simpler to model the AIN input as an equivalent

resistance, R

, from the AIN pin to a voltage source VM where

AIN

VM = (REFTS + REFBS)/2 and R

= 1 / (C x f

)

clk

AIN

S

where f is the CLK frequency.

clk

The high-pass –3 dB cutoff frequency for the circuit shown in Figure 34 is:

1

f

(

3 dB)

2

R

tot

IN

(12)

where R tot is the parallel combination of Rbias1, Rbias2, and R

. This approximation is good provided that

IN

AIN

the clock frequency, f , is much higher than f(–3 dB).

clk

Note also that the effect of the equivalent R

bias network dc level.

and VM at the AIN pin must be allowed for when designing the

AIN

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

details

The above value for R

is derived by noting that the average AIN voltage must equal the bias voltage supplied

AIN

by the ac coupling network. The average value of V

in equation 13 is thus a constant voltage

LAST

V

= V(AIN bias) – VM

LAST

(13)

For an input voltage V at the AIN pin,

in

Qin = (V – V

) × C

S

IN

LAST

(14)

Provided that f (–3 dB) is much lower than f , a constant current flowing over the clock period can approximate

clk

the input charging pulse

I

= Qin/t

clk

= (Vin – V

IN

= Qin × f

) × C × f

S clk

LAST

(15)

The ac input resistance R

is then

AIN

R

= dIin/dVin

AIN

= 1 / (dVin / dIin)

= 1 / (C x f

)

clk

S

(16)

driving the VREF pin (differential mode)

Figure 35 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin

(MODE = AV /2 and REFSENSE = AV ).

DD

AV

DD

R

IN

REFSENSE = AV

DD

,

VREF

AV

DD

2

14 kΩ

Mode =

AGND

+

AV

DD

4

+ VREF/4

4

_

Figure 35. Equivalent Circuit of VREF

The current flowing into I is given by

IN

I

(3 VREF AV

)

IN

DD

(4

R

)

IN

(17)

Note that the actual IIN may differ from this value by up to 50% due to device-to-device processing variations

and allowing for operating temperature variations.

The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground

and capable of driving I .

IN

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

driving the internal reference buffer (top/bottom mode)

Figure 36 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal

reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.

AV

DD

R

IN

REFTS

REFBS

14 kΩ

AV

DD

2

Mode =

AGND

+

_

AV

DD

+ REFTS + REFBS

4

Figure 36. Equivalent Circuit of Inputs to Internal Reference Buffer

Equations for the currents flowing into REFTS and REFBS are:

(3 REFTS AV

REFBS)

DD

)

I

TS

IN

(4

R

IN

(18)

(3 REFBS AV

REFTS)

DD

)

BS

(4

R

IN

ThesecurrentsmustbeprovidedbythesourcesonREFTSandREFBSinadditiontotherequirementsofdriving

the sample and hold. Tolerance on these currents are ±50%.

driving REFTS and REFBS

AV

DD

CLK

0.6 pF

REFTS

REFBS

C

C1

7 pF

C2

0.6 pF

SAMPLE

AGND

Mode = AV

DD

CLK

+

_

V

LAST

Internal

Reference

Buffer

Figure 37. Equivalent Circuit of REFTS and REFBS Inputs

This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also

drivingaswitchedcapacitorloadlikeAIN, butwiththesamplingcapacitorandC oneachpinnowbeing0.6 pF

P2

and about 0.6 pF respectively.

31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

driving REFTF and REFBF (full external reference mode)

AV

DD

REFTF

To REFBS

(For Kelvin Connection)

AGND

680 Ω

AV

DD

REFBF

To REFTS

(For Kelvin Connection)

AGND

Figure 38. Equivalent Circuit of REFTF and REFBF Inputs

Note the need for off-chip decoupling.

clamp operation

The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or by

programming the on-chip clamp DAC.

clamp acquisition time

Figure 39 shows the basic operation of the clamp circuit with the analog input AIN coupled via an RC circuit.

10-Bit

DAC

CLAMPIN

CLAMP

Control Register

+

V

CLAMP

_

C

SW1

IN

R

IN

AIN

S/H

V

IN

Figure 39. Schematic of Clamp Circuitry

After powerup, the clamp circuit requires SW1 to be closed to charge the coupling capacitor, C , to the voltage

IN

required to set the dc clamp level at AIN. The charging time required to set the correct clamp voltage is called

the clamp acquisition time, t

:

ACQ

Vc

Ve

t

C

R

In

ACQ

IN

(19)

Vcisthedifferencebetweenthedcbiasvoltageleveloftheinputsignal, V , andthetargetclampoutputvoltage,

IN

V

. Ve is the difference between the ideal Vc and the actual Vc obtained during the acquisition time. The

(clamp)

maximum tolerable error depends on the application requirements.

32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

clamp acquisition time (continued)

For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of

1.3 V at the THS1031 input. The voltage Vc required across the input coupling capacitor is thus 1.3 – 0.3 = 1 V.

If a 10 mV or less clamp voltage error Ve will give acceptable system operation, if the source resistance Rin is

20 Ω and the coupling capacitor C is 1 µF, then the total clamp pulse duration required to reach this error is:

IN

Vc

Ve

1

0.01

t

C

R

In

1

F

20

In

= 92 µs (approximately)

ACQ

IN

(20)

Note that SW1 does not have to be closed continuously until the desired clamp voltage is achieved. The clamp

level can be acquired over a longer interval by using a series of shorter clamp pulses with total pulse duration

at least equal to the acquisition time calculated using equation 19.

droop

The charge pulses entering or leaving AIN caused by the sample and hold switched capacitor input can charge

or discharge C , causing the voltage at AIN to drift toward VM (the average of REFTS and REFBS) during the

IN

time between clamp pulses. This effect is called clamp droop and can be seen as a slow change in the ADC

output code when the input signal is a constant dc level. Through careful clamp circuit design, this droop can

be kept below 1 LSB, giving no change in the ADC output between clamp pulses.

The clamp voltage droop is a function of the input current to the THS1031 and the time between clamp pulses,

td

I

IN

V

td (approximately)

DROOP

C

IN

(21)

Where:

I

(V

– VM)

2

R

IN

AIN

(V

CS fclk

2

AIN

R

is the input resistance given by equation 20. Cs is approximately 2.5 pF. Substituting I into the droop

IN

AIN

voltage equation gives

V

(V – VM)

CS td (2 C )

DROOP

AIN

IN

(22)

Note that I has maximum value when V

level is near either full-scale input voltage. There is no droop when the clamp level equals VM because I is

is either +FS or –FS, and so the droop rate is worst then the clamp

IN

AIN

IN

zero. Note that the actual voltage droop may be up to 50% more than given by equation 22 when allowing for

temperature variations and device to device processing variations.

For example, with C = 1 µF at f = 30 MSPS conversion rate in top/bottom mode with REFTS = 2.5 V and

IN

clk

REFBS = 0.5 V, the clamp droop over td = 63.5 ms when V

= +FS is

AIN

V

(V

– VM)

CS fclk td (2 C )

DROOP

AIN

IN

(2.5 V – 1.5 V)

2.5 pF 30 MMz 2

0.0024 mV

1.25 LSB (assuming PGA gain

1)

(23)

33

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

clamp operation (continued)

Thus if a constant voltage is applied to the clamp input that drives the ADC output to code 1023 (with no

over-range), then the ADC output code will slowly drop to code 1022, or possibly code 1021, over the period

t .

d

If the calculated droop is greater than can be tolerated in the application then increase C to slow the droop

IN

and hence reduce the voltage change between clamp pulses.

If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly

larger than calculated above due to the capacitor’s rapid rate of self-discharge. Avoid using electrolytic and

tantalum coupling capacitors as these usually exhibit much higher leakage then nonpolarized capacitor types.

Electrolytic and tantalum capacitors also tend to have higher parasitics inductance, which can cause further

problems at high input frequencies.

steady-state clamp voltage error

Under steady-state conditions, the change in the clamp voltage caused during clamping must equal the change

caused by clamp droop, otherwise the effect causing the largest voltage change would pull the clamp voltage

away until these charging and droop effects equalize.

Figure 40 shows the approximate voltage waveform at AIN resulting from clamp droop during t and clamp

d

voltage reacquisition during the clamp pulse time, t .

c

V

(Clamp)

V

COS

V

= ∆V

AIN

DROOP

V

AIN

t

d

c

VM

Figure 40. Approximate Waveforms at AIN During Droop and Clamping

The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming

that almost all of V

approximationwhenV

is then

appears across R , giving a charging current V

/Rin (this is a reasonable

COS

IN

COS

islargeenoughtobeaproblem).ThevoltagechangeatAINduringclampacquisition

COS

V

COS

V

tc

AIN

R

(24)

IN

The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the

droop voltage to the clamp acquisition voltage change gives

R

I

td

IN

tc

V

COS

(25)

Where I is the input current given by equation, thus for low offset voltage, keep R low and ensure that the

IN

ratio t /t is not unreasonably large.

d c

34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

PRINCIPLES OF OPERATION

driving the clock input

Obtaining good performance from the THS1031 requires care when driving the clock input.

Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should

ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as

possible in which to operate.

The CLK pin should be driven from a low jitter source for best dynamic performance. To maintain low jitter at

the CLK input, any clock buffers external to the THS1031 should have fast rising edges. Use a fast logic family

such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other

logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.

The CLK input threshold is nominally aroundAV /2—ensurethatanyclockbuffershaveanappropriatesupply

DD

voltage to drive above and below this level.

digital output loading and circuit board layout

The THS1031 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30 MHz clock and 3 V

digital supply. Minimizing the load on the outputs will improve THS1031 signal-to-noise performance by

reducing the switching noise coupling from the THS1031 output buffers to the internal analog circuits. The

output load capacitance can be minimized by buffering the THS1031 digital outputs with a low input capacitance

buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks

between the THS1031 and this buffer.

Noise levels at the output buffers, and hence coupling to the analog circuits within THS1031, becomes worse

as the THS1031 digital supply voltage is increased. Where possible, consider using the lowest DV

application can tolerate.

that the

DD

Use good layout practices when designing the application PCB to ensure that any off-chip return currents from

the THS1031 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any

sensitive analog circuits. The THS1031 should be soldered directly to the PCB for best performance. Socketing

the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.

user tips for obtaining best performance from the THS1031

Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails.

ORG modes offer the simplest configurations for ADC reference generation.

Choose differential input mode for best distortion performance.

Choose a 2-V ADC input span for best noise performance.

Choose a 1-V ADC input span for best distortion performance.

If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the

system. Care should be taken to ensure noise is not injected into the THS1031.

Use external voltage sources for ADC reference generation where there are stringent requirements on

accuracy and drift.

Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB

traces.

35

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

16 PINS SHOWN

0.050 (1,27)

16

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

M

9

0.419 (10,65)

0.400 (10,15)

0.010 (0,25) NOM

0.299 (7,59)

0.293 (7,45)

Gage Plane

0.010 (0,25)

1

8

0°–8°

0.050 (1,27)

0.016 (0,40)

A

Seating Plane

0.004 (0,10)

0.012 (0,30)

0.004 (0,10)

0.104 (2,65) MAX

PINS **

16

20

24

28

DIM

0.410

0.510

0.610

0.710

A MAX

A MIN

(10,41) (12,95) (15,49) (18,03)

0.400

0.500

0.600

0.700

(10,16) (12,70) (15,24) (17,78)

4040000/C 07/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-013

36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

37

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

17-Jun-2009

PACKAGING INFORMATION

Orderable Device

THS1031CDW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

DW

28

20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

THS1031CDWG4

THS1031CPW

SOIC

TSSOP

SOIC

DW

PW

DW

PW

20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

THS1031CPWG4

THS1031CPWR

THS1031CPWRG4

THS1031IDW

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

THS1031IDWG4

THS1031IPW

SOIC

20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

THS1031IPWG4

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

THS1031CPWR

TSSOP

PW

28

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 28

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 33.0

THS1031CPWR

2000

Pack Materials-Page 2

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Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

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型号：	THS1031IPWLE
厂家：	TEXAS INSTRUMENTS
描述：	10-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, PLASTIC, TSSOP-28 光电二极管转换器
文件：	总41页 (文件大小：719K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THS1031IPWLE [TI]

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