THS7530QPWPRQ1 [TI]
汽车类、300MHz、全差分、连续可变增益放大器 | PWP | 14 | -40 to 125;
| 型号： | THS7530QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类、300MHz、全差分、连续可变增益放大器 | PWP | 14 | -40 to 125 放大器 光电二极管 |
| 文件： | 总28页 (文件大小：1421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THS7530-Q1
ZHCSEH5 –DECEMBER 2015
THS7530-Q1 高速、全差分、连续
可变增益放大器
1 特性
•
•
通信中的系统增益校准
仪表中的可变增益
1
•
•
适用于汽车电子 应用
具有符合 AEC-Q100 标准的下列结果：
3 说明
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
THS7530-Q1 器件采用德州仪器 (TI) 先进的 BiCom III
SiGe 互补双极工艺制造。THS7530-Q1 是一款带有压
控增益的直流耦合高带宽放大器。该放大器具有高阻抗
差分输入和低阻抗差分输出，提供高带宽增益控制、输
出共模控制和输出电压钳位功能。
–
–
器件人体放电模式 (HBM) 分类等级 2
器件组件充电模式 (CDM) 分类等级 C6
•
•
低噪声：Vn = 1.1nV/√Hz，
噪声系数 = 9dB
低失真：
该器件在 300MHz 带宽下
–
频率为 32MHz 时：HD2 = –65dBc，HD3 =
的动态性能优异。当频率为 32MHz，同时将 1 VPP 输
出施加于 400Ω 负载，三次谐波失真为 –61dBc。
–61dBc
–
频率为 70MHz 时：IMD3 = –62dBc，OIP3 =
21dBm
增益控制（单位：dB）呈线性变化。在 0V 至 0.9V 电
压范围内，增益以 38.8dB/V 的斜率由 11.6dB 变化为
46.5dB。
•
•
300MHz 带宽
连续可变增益范围：11.6dB
至 46.5dB
输出电压限制功能用于限制输出电压摆幅并避免后续级
发生饱和。
•
•
•
•
增益斜率：38.8dB/V
全差分输入和输出
输出共模电压控制
输出电压限制
该器件可在汽车级温度范围内（–40°C 至 +125°C）额
定运行。
器件信息(1)
2 应用
器件型号
封装
封装尺寸（标称值）
•
超声波应用、声纳和雷达中的
时间增益放大器
THS7530-Q1
HTSSOP (14)
5.00mm x 4.40mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
通信和和视频中的
自动增益控制
典型应用电路
VS+ = 5 V
1 kW
1 kW
0.1 mF
24.9 W
0.1 mF
6.8 mF
33 pF
24.9 W
VCL+
VCL-
0.1 mF
0.1 mF
0.1 mF
24.9 W
VIN+
VOUT-
VOCM
THS7530
0.1 mF
PD
VOUT+
VIN-
24.9 W
VG-
0.1 mF
33 pF
VG+
VS-
VREF
AGC Detect
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS932
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 15
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: Main Amplifier.................. 5
6.6 Package Thermal Data ............................................. 6
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information ................ 10
7.1 Test Circuits ............................................................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
9
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Examples................................................... 20
12 器件和文档支持 ..................................................... 22
12.1 器件支持 ............................................................... 22
12.2 文档支持................................................................ 22
12.3 社区资源................................................................ 22
12.4 商标....................................................................... 22
12.5 静电放电警告......................................................... 22
12.6 Glossary................................................................ 22
13 机械、封装和可订购信息....................................... 22
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 12 月
*
最初发布版本。
2
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
5 Pin Configuration and Functions
PWP Package
14-Pin HTSSOP With PowerPAD™
Top View
VCL+
VCL-
VOCM
VOUT-
VOUT+
VS+
NC
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN+
VIN-
VG+
VG-
VS-
8
PD
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
1
NC
—
—
No internal connection
2
Power down, PD = logic low puts the device into low power mode; PD = logic high or open for normal
operation
PD
7
VCL–
VCL+
VG-
13
14
6
I
I
Output negative clamp voltage input
Output positive clamp voltage input
Gain setting negative input
I
VG+
5
I
Gain setting positive input
VIN–
VIN+
VOCM
VOUT–
VOUT+
VS–
4
I
Inverting amplifier input
3
I
Noninverting amplifier input
12
11
10
8
I
Output common-mode voltage input
Inverted amplifier output
O
O
I
Noninverted amplifier output
Negative amplifier power-supply input
Positive amplifier power-supply input
VS+
9
I
Copyright © 2015, Texas Instruments Incorporated
3
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted.(1)
MIN
MAX
5.5
±VS
65
UNIT
V
VS+ – VS–
Supply voltage
VI
Input voltage
V
IO
Output current
mA
V
VID
Differential input voltage
Continuous power dissipation
Maximum junction temperature
Maximum junction temperature for long term stability(2)
Storage temperature
±4
See Thermal Information
150
125
150
°C
°C
°C
TJ
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
[VS– to VS+
]
Supply voltage
4.5
5
2.5
2.5
5.5
V
V
Input common mode voltage
Output common mode voltage
Operating free-air temperature
[VS– to VS+] = 5 V
[VS– to VS+] = 5 V
V
TA
–40
125
°C
6.4 Thermal Information
THS7530
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
14 PINS
75.3
35
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
28.9
1.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
28.6
3.2
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
6.5 Electrical Characteristics: Main Amplifier
VS+ = 5 V, VS– = 0 V, VOCM = 2.5 V, VICM = 2.5 V, VG- = 0 V, VG+ = 1 V (maximum gain), TA = 25°C, AC performance measured
using the AC test circuit shown in Figure 16 (unless otherwise noted). DC performance is measured using the DC test circuit
shown in Figure 17 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Small-signal bandwidth
Slew rate(1)
Settling time to 1%(1)
All gains, PIN = –45 dBm
300
1250
11
MHz
V/µs
ns
1-VPP Step, 25% to 75%, minimum gain
1-VPP Step, minimum gain
Harmonic distortion, 2nd harmonic
Harmonic distortion, 3rd harmonic
f = 32 MHz, VO(PP) = 1 V, RL(diff)= 400 Ω
f = 32 MHz, VO(PP) = 1 V, RL(diff)= 400 Ω
–65
–61
dBc
dBc
PO = –10 dBm each tone, fC= 70 MHz,
200-kHz tone spacing
Third-order intermodulation distortion
–62
dBc
Third-order output intercept point
Noise figure (with input termination)
Total input voltage noise
fC= 70 MHz, 200-kHz tone spacing
Source impedance: 50 Ω
f > 100 kHz
21
9
dBm
dB
1.1
nV/√Hz
DC PERFORMANCE—INPUTS
TA = 25°C
20
39
40
Input bias current
µA
pA
V
TA = –40°C to +125°C
Input bias current offset
Minimum input voltage
<150
1.5
Minimum gain, TA = 25°C
Minimum gain, TA = –40°C to +125°C
Minimum gain, TA = 25°C
Minimum gain, TA = –40°C to +125°C
TA = 25°C
1.6
1.7
3.2
3.15
56
3.3
114
Maximum input voltage
V
Common-mode rejection ratio
dB
TA = –40°C to +125°C
44
Differential input impedance
8.5 || 3
±100
3.5
kΩ || pF
DC PERFORMANCE—OUTPUTS
All gains, TA = 25°C
All gains, TA = –40°C to +125°C
TA = 25°C
±410
±480
Output offset voltage
mV
V
3.25
3
Maximum output voltage high
Minimum output voltage low
TA = –40°C to +125°C
TA = 25°C
1.5
1.8
2
V
TA = –40°C to +125°C
TA = 25°C
±16
±16
±30
Output current
mA
TA = –40°C to +125°C
Output impedance
15
Ω
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Gain
32
1
MHz
V/V
TA = 25°C
4.5
12
Common-mode offset voltage
mV
TA = –40°C to +125°C
13.8
Minimum input voltage
Maximum input voltage
Input impedance
1.75
3.25
25 || 1
2.5
V
V
kΩ || pF
V
Default voltage, with no connect
Input bias current
<1
µA
GAIN CONTROL
Gain control differential voltage range
Minus gain control voltage
Minimum gain
VG+
0 to 1
–0.6 to 0.8
11.6
V
V
VG– – VS–
VG+ = 0 V
VG+ = 0.9 V
VG+ = 0 V to 0.9 V
dB
dB
dB/V
Maximum gain
46.5
Gain slope
38.8
(1) Slew rate and settling time measured at amplifier output.
Copyright © 2015, Texas Instruments Incorporated
5
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
Electrical Characteristics: Main Amplifier (continued)
VS+ = 5 V, VS– = 0 V, VOCM = 2.5 V, VICM = 2.5 V, VG- = 0 V, VG+ = 1 V (maximum gain), TA = 25°C, AC performance measured
using the AC test circuit shown in Figure 16 (unless otherwise noted). DC performance is measured using the DC test circuit
shown in Figure 17 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±1.5
±4
MAX
UNIT
Gain slope variation
VG+ = 0 V to 0.9 V
dB/V
VG+ = 0 V to 0.15 V
VG+ = 0.15 V to 0.9 V
Gain error
dB
±2.25
<1
Gain control input bias current
Gain control input resistance
Gain control bandwidth
µA
kΩ
40
Small signal –3 dB
15
MHz
VOLTAGE CLAMPING
Device In voltage limiting mode, TA = 25°C
Device In voltage limiting mode, TA = –40°C to +125°C
Device in voltage limiting mode
±25
±40
Output voltages (VOUT±) relative to clamp
mV
voltages (VCL±
)
±180
Clamp voltage (VCL±) input resistance
Clamp voltage (VCL±) limits
POWER SUPPLY
3.3
kΩ
VS– to VS+
V
TA = 25°C
5
40
77
5.5
5.5
48
Specified operating voltage
Maximum quiescent current
V
TA = –40°C to +125°C
TA = 25°C
mA
dB
TA = –40°C to +125°C
TA = 25°C
49
70
45
Power supply rejection (±PSRR)
TA = –40°C to +125°C
POWER DOWN
TTL low = shut down, TA = 25°C
1.4
1.4
Enable voltage threshold
Disable voltage threshold
V
V
TTL low = shut down,
TA = –40°C to +125°C
1
TTL high = normal operation, TA = 25°C
TTL high = normal operation,
TA = –40°C to +125°C
1.65
TA = 25°C
0.35
±9
0.4
0.55
±16
Power-down quiescent current
Input current high
mA
µA
µA
TA = –40°C to +125°C
TA = 25°C
TA = –40°C to +125°C
TA = 25°C
±19
±109
±116
±130
Input current low
TA = –40°C to +125°C
Input impedance
50 || 1
820
500
80
kΩ || pF
ns
Turnon time delay
Measured to 50% quiescent current
Measured to 50% quiescent current
Turnoff time delay
ns
Forward isolation in power down
Input resistance in power down
Output resistance in power down
dB
> 1
MΩ
kΩ
16
6.6 Package Thermal Data
PACKAGE
TA = 25°C
PCB
POWER RATING(1)
PWP (14-pin)(2)
See Layout.
3 W
(1) This data was taken using 2 oz trace and copper pad that is soldered directly to a 3 in × 3 in PCB.
(2) The THS7530-Q1 incorporates a PowerPAD on the underside of the chip. The PowerpAD acts as a heatsink and must be connected to
a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the
PowerPAD thermally enhanced package.
6
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
6.7 Typical Characteristics
Measured using the AC test circuit shown in Figure 16 (unless otherwise noted).
Table 1. Table Of Graphs
FIGURE
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 24
Figure 25
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Voltage Gain to Load
Gain and Gain Error
vs Frequency (Input at 45 dBm)
vs VG+
Noise Figure
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
Output Intercept Point
1-dB Compression Point
Total Input Voltage Noise
Intermodulation Distortion
Harmonic Distortion
S-Parameters
Differential Input Impedance of Main Amplifier
Differential Output Impedance of Main Amplifier vs Frequency
VG+ Input Impedance
vs Frequency
vs Frequency
vs Frequency
vs Time
VOCM Input Impedance
Common-Mode Rejection Ratio
Step Response: 2 VPP
Step Response: Rising Edge
Step Response: Falling Edge
vs Time
vs Time
50
45
40
35
30
25
20
15
10
5
0.4
0.2
0
Gain
Gain Error
Maximum Gain
40
30
20
10
Gain
-0.2
-0.4
Gain Error
Minimum Gain
0
-0.6
-0.8
-10
0
1
10
100
Frequency (MHz)
1000
0
200
400
600
800
1000
VG+ Voltage (mV)
Gain is taken at load.
PIN = –45 dBm
Add 6 dB to refer to amplifier output
Figure 1. Voltage Gain to Load vs Frequency
Figure 2. Gain and Gain Error vs VG+
Copyright © 2015, Texas Instruments Incorporated
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THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
35
60
55
50
45
40
35
30
25
20
15
10
Gain = 20 dB
OIP2
OIP3
Gain = 30 dB
Gain = 40 dB
30
25
20
15
10
5
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Frequency (MHz)
Frequency (MHz)
Terminated input
Figure 3. Noise Figure vs Frequency
Taken at load.
Add 3 dB to refer to amplifier output.
Figure 4. Output Intercept Point vs Frequency
15
14
13
12
11
10
9
100
8
10
7
6
5
4
3
2
1
0
1
0
50
100
150
200
250
300
10
100
1 k
10 k
100 k
1 M
10 M 100 M
Frequency (Hz)
Frequency (MHz)
Taken at load.
Add 3 dB to refer to amplifier output.
Figure 6. Total Input Voltage Noise vs Frequency
Figure 5. 1-dB Compression Point vs Frequency
-50
-45
HD2
IMD2
HD3
-52
IMD3
-50
-54
-56
-58
-60
-62
-64
-66
-68
-70
-55
-60
-65
-70
-75
-80
0
10
20
30
40
50
60
70
0
50
100
150
200
Frequency (MHz)
Frequency (MHz)
VG+ = 1 V
VO = 1 VPP
RL = 400 Ω
VG+ = 1 V
VO = 1 VPP (composite)
RL = 400 Ω
Figure 8. Harmonic Distortion vs Frequency
Figure 7. Intermodulation Distortion vs Frequency
8
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
50
45
40
35
30
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
0
1
10
100
Frequency (MHz)
1000
0.1
1
10
Frequency (MHz)
Figure 9. Differential Output Impedance of Main Amplifier
Figure 10. VG+ Input Impedance vs Frequency
vs Frequency
25
-10
-20
-30
-40
-50
-60
20
15
10
5
0
0.1
1
10
100
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Figure 11. VOCM Input Impedance vs Frequency
Figure 12. Common-Mode Rejection Ratio vs Frequency
1.5
1.5
1.0
0.5
0
1.0
0.5
0
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
0
2
4
6
8
10
12
0
200
400
600
800
1000
Time (ns)
Time (ns)
RL = 400 Ω
At amplifier output and minimum gain
RL = 400 Ω
At amplifier output and minimum gain
Figure 13. Step Response
Figure 14. Step Response: Rising Edge
Copyright © 2015, Texas Instruments Incorporated
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THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
0
2
4
6
8
10
12
Time (ns)
RL = 400 Ω
At amplifier output and minimum gain
Figure 15. Step Response: Falling Edge
7 Parameter Measurement Information
7.1 Test Circuits
VS+ = 5 V
1 kW
1 kW
0.1 mF
0.1 mF
6.8 mF
VCL+
VCL-
33 pF
50 W
Coax
Coax
VIN
VOUT
1:1
1:1
50-W
50-W
24.9 W
Source
Load
VOCM
THS7530
PD
24.9 W
VG-
VG+
0.1 mF
33 pF
VS-
Figure 16. AC Test Circuit
VS+ = 5 V
VCL+
VCL-
0.1 mF
800 W
6.8 mF
VOUT-
VOUT+
VIN+
VOCM
VIN-
THS7530
PD
VG-
0.1 mF
VS-
VG+
Figure 17. DC Test Circuit
10
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
8 Detailed Description
8.1 Overview
The THS7530-Q1 device is a fully-differential amplifier with 300-MHz bandwidth and with continually-variable
gain from 11.6 dB to 46.5 dB. This amplifier together with an automatic gain control (AGC) circuit will precisely
established a desired amplitude at its output.
The input architecture is a modified Gilbert cell. The output from the Gilbert cell is converted to a voltage and
buffered to the output as a fully-differential signal. A summing node between the outputs is used to compare the
output common-mode voltage to the VOCM input. The VOCM error amplifier then servos the output common-mode
voltage to maintain it equal to the VOCM input. Left unterminated, VOCM is set to midsupply by internal resistors.
The gain control input is conditioned to give linear-in-dB gain control (block H). The gain control input is a
differential signal from 0 V to 0.9 V which varies the gain from 11.6 dB to 46.5 dB.
VCL+ and VCL– provide inputs that limit the output voltage swing of the amplifier.
8.2 Functional Block Diagram
VCL+
VCL-
VS+
VOUT+
Output
Buffer
x1
VOCM Error
Amplifier
VOUT-
VOCM
VIN+
VIN-
Power
Control
PD
VS-
VG+
VG-
H
THS7530
8.3 Feature Description
The main features of the THS7530-Q1 device are continually-variable gain control, common-mode voltage
control, output voltage clamps, and power-down mode.
8.3.1 Continually-Variable Gain Control
The amplifier gain in dB is a linear function of the gain control voltage, which has a range of 0 V to 0.9 V. The
slope of the gain control input is 38.8 dB/V with a gain range of 11.6 dB to 46.5 dB, which is 3.8 to 211.3 V/V,
respectively. The bandwidth of the gain control is 15 MHz, typically.
The gain control is a differential input to reduce noise due to ground bounce, coupling, and so forth. The negative
gain-control input VG– can be below the negative supply by as much as 600 mV.
8.3.2 Common-Mode Voltage Control
The common-mode voltage control sets the common-mode voltage of the differential output. The gain of the
control voltage is 1 V/V with a range of 1.75 V to 3.25 V above the negative supply. If unconnected, the common-
mode voltage control is at mid-supply, typically 2.5 V above the negative supply. The bandwidth of the common-
mode voltage control is an impressive 32 MHz.
Copyright © 2015, Texas Instruments Incorporated
11
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
Feature Description (continued)
8.3.3 Output Voltage Clamps
Separate inputs, VCL– and VCL+, establish the minimum and maximum output voltages, respectively. The typical
error of the output voltage compared to the clamp voltage is only 25 mV. This feature can be used to avoid
saturating the inputs of a receiving device, thereby precluding long recovery times in the signal path.
8.3.4 Power-Down Mode
To minimize power consumption when idle, the THS7530-Q1 device has an active-low power-down control that
reduces the quiescent current from 40 mA to 350 µA. The turnon delay is only 820 ns.
When in power-down mode, the THS7530-Q1 device has a 80-dB forward isolation to allow other devices to
drive the same signal path with minimal interference from the idle THS7530-Q1 device.
8.4 Device Functional Modes
The THS7530-Q1 device has two functional modes: full-power mode and power-down mode. The power-down
mode reduces the quiescent current of the device to 350 µA from a typical value of 40 mA.
With a turnon time of only 820 ns and a turnoff time of 500 ns, the power-down mode can be used to greatly
reduce the average power consumption of the device without sacrificing system performance.
12
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The THS7530-Q1 device is designed to work in a wide variety of applications requiring continuously variable gain
and a fully-differential signal path. The common-mode voltage control and the output voltage clamps enable the
THS7530-Q1 device to drive a diverse array of receiving circuits.
VS+ = 5 V
1 kW
1 kW
0.1 mF
0.1 mF
6.8 mF
33 pF
50 W
VCL+
VCL-
24.9 W
1:1
1:1
VIN
VOUT
VOCM
THS7530
PD
24.9 W
0.1 mF
VG-
33 pF
VS-
VG+
Figure 18. EVM Schematic: Designed for Use With Typical 50-Ω RF Test Equipment
VS+ = 5 V
1 kW
1 kW
0.1 mF
49.9 W
0.1 mF
6.8 mF
33 pF
49.9 W
VCL+
VCL-
0.1 mF
0.1 mF
24.9 W
VIN
VOUT-
VOCM
THS7530
0.1 mF
PD
VOUT+
24.9 W
VG-
0.1 mF
33 pF
VS-
VG+
Figure 19. AC-Coupled Single-Ended Input With AC-Coupled Differential Output
Copyright © 2015, Texas Instruments Incorporated
13
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
Application Information (continued)
VS+ = 5 V
1 kW
1 kW
0.1 mF
0.1 mF
6.8 mF
33 pF
24.9 W
24.9 W
VCL+
VCL-
0.1 mF
0.1 mF
0.1 mF
24.9 W
VIN+
VOUT-
VOCM
THS7530
0.1 mF
PD
VOUT+
VIN-
24.9 W
VG-
0.1 mF
33 pF
VS-
VG+
Figure 20. AC-Coupled Differential Input With AC-Coupled Differential Output
VS+ = 5 V
1 kW
1 kW
0.1 mF
49.9 W
0.1 mF
6.8 mF
33 pF
49.9 W
VCL+
VCL-
0.1 mF
24.9 W
VIN
VOUT-
VOCM
THS7530
PD
VOUT+
24.9 W
VG-
0.1 mF
33 pF
VS-
VG+
Figure 21. DC-Coupled Single-Ended Input With DC-Coupled Differential Output
VS+ = 5 V
1 kW
1 kW
0.1 mF
24.9 W
0.1 mF
6.8 mF
33 pF
24.9 W
VCL+
VCL-
24.9 W
VIN+
VOUT-
VOCM
THS7530
PD
VOUT+
VIN-
24.9 W
VG-
0.1 mF
33 pF
VS-
VG+
Figure 22. DC-Coupled Differential Input With DC-Coupled Differential Output
14
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
9.2 Typical Application
VS+ = 5 V
1 kW
1 kW
0.1 mF
0.1 mF
6.8 mF
33 pF
24.9 W
24.9 W
VCL+
VCL-
0.1 mF
0.1 mF
0.1 mF
0.1 mF
24.9 W
VIN+
VOUT-
VOCM
THS7530
PD
VOUT+
VIN-
24.9 W
VG-
0.1 mF
33 pF
VG+
VS-
VREF
AGC Detect
Figure 23. Typical Application Circuit
9.2.1 Design Requirements
A typical application circuit is shown in Figure 23. Two noteworthy aspects of this circuit are the customer’s
automatic gain control (AGC) circuit and the THS7530-Q1 input bias circuit.
The proper design of the AGC circuit is essential for the THS7530-Q1 device to operate properly in the
customer’s application. The method of detecting the amplitude of the differential output of the THS7530-Q1
device and creating the gain-control voltage, VG+, from the detected amplitude and the reference amplitude, Vref,
are application-specific and beyond the scope of this document. The bandwidth of the amplitude of the THS7530-
Q1 amplitude control is 15 MHz, which allows for rapid corrections of amplitude errors but which also allows
noise from DC to 15 MHz to create an amplitude error. The trade-off between rapid amplitude correction and
amplitude modulation due to noise is an important design consideration.
The input bias currents of the differential inputs of the THS7530-Q1 device are typically 20 µA. When the
differential inputs are AC-coupled, the bias currents must be supplied as shown in Figure 23. In this circuit, the
DC bias voltage is mid-supply and the AC differential input impedance is 50 Ω. The 0.1-µF capacitor between the
two 24.9-Ω resistors creates an AC ground for the driving circuit.
9.2.2 Detailed Design Procedure
The THS7530-Q1 device is designed for nominal 5-V power supply from VS+ to VS–.
The amplifier has fully differential inputs, VIN+ and VIN–, and fully differential outputs, VOUT+ and VOUT– The inputs
are high impedance and outputs are low impedance. External resistors are recommended for impedance
matching and termination purposes.
The inputs and outputs can be DC-coupled, but for best performance, the input and output common-mode
voltage should be maintained at the midpoint between the two supply pins. The output common-mode voltage is
controlled by the voltage applied to VOCM. Left unterminated, VOCM is set to midsupply by internal resistors. A 0.1-
µF bypass capacitor should be placed between VOCM and ground to reduce common-mode noise. The input
common-mode voltage defaults to midrail when left unconnected. For voltages other than midrail, VOCMmust be
biased by external means. VIN+ and VIN– both require a nominal 30-µA bias current for proper operation.
Therefore, ensure equal input impedance at each input to avoid generating an offset voltage that varies with
gain.
Voltage applied from VG– to VG+ controls the gain of the part with 38.8-dB/V gain slope. The input can be
differential or single ended. VG– must be maintained within –0.6 V and 0.8 V of VS–for proper operation. The
negative gain input should typically be tied directly to the negative power supply.
Copyright © 2015, Texas Instruments Incorporated
15
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
Typical Application (continued)
VCL+ and VCL– are inputs that limit the output voltage swing of the amplifier. The voltages applied set an absolute
limit on the voltages at the output. Input voltages at VCL+ and VCL– clamp the output, ensuring that neither output
exceeds those values.
The power-down input is a TTL compatible input, referenced to the negative supply voltage. A logic low puts the
THS7530-Q1 device in power-saving mode. In power-down mode the part consumes less than 1-mA current, the
output goes high impedance, and a high amount of isolation is maintained between the input and output.
Power-supply bypass capacitors are required for proper operation. A 6.8-µF tantalum bulk capacitor is
recommended if the amplifier is located far from the power supply and may be shared among other devices. A
ceramic 0.1-µF capacitor is recommended within 0.1-in of the device power pin. The ceramic capacitors should
be located on the same layer as the amplifier to eliminate the use of vias between the capacitors and the power
pin.
Table 2. THS7530EVM Bill of Materials
ITEM
NO.
DESCRIPTION
SIZE
REFERENCE DESIGNATOR
QTY
PART NUMBER
1
Bead, ferrite, 3 A, 80 Ω
1206
D
FB1
C2
1
1
1
8
(Steward) HI1206N800R–00
(AVX) TAJD685K035R
2
Capacitor, tantalum, 6.8 mF, 35 V, 10%
Capacitor, ceramic, 0.1 mF, X7R, 16V
Capacitor, ceramic, 0.1 mF, X7R, 50 V
3
508
805
C1
(AVX) 0508YC104KAT2A
(AVX) 08055C104KAT2A
5
C3, C7, C12, C13, C14, C15,
C16, C17
6
7
Diode, Schottky, 20 V, 0.5 A
SOD-123
805
D1
1
3
(Diodes Inc.) B0520LW–7
Resistor, 10 Ω, 1/8 W, 1%
R24, R25, R26
(PHYCOMP)
9C08052A10R0FKHFT
8
Resistor, 24.9 Ω, 1/8 W, 1%
Resistor, 1 kΩ, 1.8W, 1%
Resistor, 3.92 kΩ , 1/8 W, 1%
Resistor, 0 Ω, 1/4 W
805
R9, R15
R7, R12
R1
2
2
1
2
1
(PHYCOMP)
9C08052A24R9FKHFT
9
805
(PHYCOMP)
9C08052A1001FKHFT
10
11
12
805
(PHYCOMP)
9C08052A3921FKHFT
1206
1206
C4, C5
R4
(PHYCOMP)
9C12063A0R00JLHFT
Resistor, 49.9 Ω, 1/4 W, 1%
(PHYCOMP)
9C12063A49R9FKRFT
13
14
15
16
17
18
Pot., ceramic, 1/4 inch square, 1 kΩ
Pot., ceramic, 1/4 inch square, 10 kΩ
IC, TLV2371
R2
1
3
3
2
2
2
(Bourns) 3362P–1–102
(Bourns) 3362P–1–103
(TI) TLV2371IDBVT
R21, R22, R23
U2, U3, U4
T1, T2
SOT-23
CD542
Transformer, 1:1
(Mini-Circuits) ADT1-1WT
(Johnson) 142–0701–801
(HH Smith) 101
Connector, edge, SMA PCB Jack
J3, J4
Jack, banana receptacle, 0.25-in diameter
hole
J1, J2
19
20
21
22
23
24
25
26
Header, 0.1-in Ctrs, 0.025-in square pins
Shunts
2 POS.
JP1
1
1
3
4
4
4
1
1
(Sullins) PZC36SAAN
(Sullins) SSC02SYAN
(Keystone) 5001
JP1
Test point, black
TP2, TP3, TP4
TP1, TP8, TP9, TP10
Test points, red
(Keystone) 5000
Standoff, 4–40 Hex, 0.625-in Length
Screw, Phillips, 4–40, .250-in
IC, THS7530-Q1
(Keystone) 1804
SHR–0440–016–SN
(TI) THS7530QPWPRQ1
(TI) EDGE # 6441987
U1
Board, printed circuit
16
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
9.2.3 Application Curves
Figure 24 and Figure 25 highlight the input characteristics of the THS7530-Q1 device that should be used to
design the circuit driving the THS7530-Q1 device.
0
-10
-20
-30
-40
-50
-60
-70
10
9
8
7
6
5
4
3
2
1
0
S11
S12
S22
0.1
1
10
100
300
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Figure 25. Differential Input Impedance of Main Amplifier
vs Frequency
Figure 24. S-Parameters vs Frequency
10 Power Supply Recommendations
The THS7530-Q1 device is principally intended to operate with a nominal single-supply voltage of 5 V. Supply
voltage tolerances of ±10% are supported. The absolute maximum supply is 5.5 V.
Supply decoupling is required, as described in Application and Implementation.
Split (or bipolar) supplies can be used with the THS7530-Q1 device, as long as the total value across the device
remains less than 5.5 V (absolute maximum).
Copyright © 2015, Texas Instruments Incorporated
17
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The THS7530-Q1 device is available in a thermally-enhanced PowerPAD™ package. Figure 26 shows the
recommended number of vias and thermal land size recommended for best performance. Thermal vias connect
the thermal land to internal or external copper planes and should have a drill diameter sufficiently small so that
the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent
wicking the solder away from the interface between the package body and the thermal land on the surface of the
board during solder reflow. The experiments conducted jointly with Solectron Texas indicate that a via drill
diameter of 0.33 mm (13 mils, or .013 in) or smaller works well when 1-ounce copper is plated at the surface of
the board and simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper
plating is performed, then a solder mask material should be used to cap the vias with a dimension equal to the
via diameter + 0.1 mm minimum. This prevents the solder from being wicked through the thermal via and
potentially creating a solder void in the region between the package bottom and the thermal land on the surface
of the PCB.
TSSOP
14-Pin PWP Package
2 ´ 3
3.4
5
Figure 26. Recommended Thermal Land Size and Thermal Via Patterns (Dimensions in mm)
See TI's Technical Brief titled, PowerPAD™ Thermally Enhanced Package (SLMA002) for a detailed discussion
of the PowerPAD™ package, its dimensions, and recommended use.
18
Copyright © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
Layout Guidelines (continued)
Figure 27. EVM Schematic
Copyright © 2015, Texas Instruments Incorporated
19
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
11.2 Layout Examples
Figure 28. Layout Diagram (Top)
Figure 29. Layout Diagram (Ground)
20
版权 © 2015, Texas Instruments Incorporated
THS7530-Q1
www.ti.com.cn
ZHCSEH5 –DECEMBER 2015
Layout Examples (continued)
Figure 30. Layout Diagram (Power)
Figure 31. Layout Diagram (Bottom)
版权 © 2015, Texas Instruments Incorporated
21
THS7530-Q1
ZHCSEH5 –DECEMBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 开发支持
有关 THS7530 PSPICE 模型，请参见 SLOJ139。
有关 THS7530 TINA-TI SPICE 模型，请参见 SLAM020。
有关 THS7530 TINA-TI 参考设计，请参见 SLAC091。
12.2 文档支持
12.2.1 相关文档
相关文档如下：
•
•
•
•
•
《THS7530 EVM 用户指南》，SLOU161
《高速运算放大器噪声分析》，SBOA066
《TI 模拟信号链指南》，SLYB174
《PowerPAD™ 耐热增强型封装》，SLMA002
《PowerPAD™ 速成》，SLMA004
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS7530QPWPRQ1
ACTIVE
HTSSOP
PWP
14
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
T7530Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
PWP 14
4.4 x 5.0, 0.65 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224995/A
www.ti.com
PACKAGE OUTLINE
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
12X 0.65
14
1
2X
5.1
4.9
3.9
NOTE 3
7
8
0.30
14X
0.19
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X (0.6)
NOTE 5
2X (0.4)
NOTE 5
THERMAL
PAD
7
8
0.25
1.2 MAX
GAGE PLANE
2.59
1.89
15
0.15
0.05
0.75
0.50
0 -8
A
20
1
14
DETAIL A
TYPICAL
2.6
1.9
4229706/A 06/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.6)
METAL COVERED
BY SOLDER MASK
SYMM
14X (1.5)
(1.2) TYP
14
14X (0.45)
1
(5)
NOTE 9
(R0.05) TYP
SYMM
(0.6)
15
(2.59)
12X (0.65)
7
8
(
0.2) TYP
VIA
SEE DETAILS
(1.1) TYP
SOLDER MASK
DEFINED PAD
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4229706/A 06/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.6)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
14X (1.5)
14X (0.45)
14
1
(R0.05) TYP
(2.59)
SYMM
15
BASED ON
0.125 THICK
STENCIL
12X (0.65)
7
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 12X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 2.90
2.60 X 2.59 (SHOWN)
2.37 X 2.36
0.125
0.15
0.175
2.20 X 2.19
4229706/A 06/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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