TLC1551IDW_技术文档

ꢀ

ꢁ

ꢎ

ꢂ

ꢉ

ꢔ

ꢃ

ꢀ

ꢄ

ꢍ

ꢆ

ꢄ

ꢉ

ꢀ

ꢅ

ꢏ

ꢕ

ꢆ

ꢇ

ꢆ

ꢖ

ꢀ

ꢎ

ꢋ

ꢁ

ꢂ

ꢋ

ꢃ

ꢁ

ꢄ

ꢂ

ꢁ

ꢅ

ꢍ

ꢑ

ꢈ

ꢌ

ꢁ

ꢇ

ꢀ

ꢁ

ꢒ

ꢀ

ꢂ

ꢀ

ꢖ

ꢃ

ꢑ

ꢗ

ꢄ

ꢒ

ꢄ

ꢃ

ꢆ

ꢓ

ꢃ

ꢅ

ꢉ

ꢊ

ꢆ

ꢀ

ꢋ

ꢌ

ꢋ

ꢁ

ꢍ

ꢆ

ꢀ

ꢐ

ꢑ

ꢒ

ꢍ

ꢗ

ꢀ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

†

D

Power Dissipation . . . 40 mW Max

J

OR DW PACKAGE

(TOP VIEW)

Advanced LinEPIC Single-Poly Process

Provides Close Capacitor Matching for

Better Accuracy

REF+

REF−

ANLG GND

AIN

RD

WR

CLKIN

CS

D9

1

24

23

22

21

20

19

18

17

16

15

14

13

2

D

Fast Parallel Processing for DSP and µP

Interface

3

4

Either External or Internal Clock Can Be

Used

ANLG V

5

DD

DGTL GND1

DGTL GND2

D8

6

D7

7

Conversion Time . . . 6 µs

Total Unadjusted Error . . . 1 LSB Max

CMOS Technology

DGTL V

D6

8

DD1

DGTL V

DD2

D5

9

EOC

D0

D1

D4

D3

D2

10

11

12

description

The TLC1550x and TLC1551 are data acquisition

†

Refer to the mechanical data for the JW

package.

analog-to-digital converters (ADCs) using a 10-bit,

switched-capacitor, successive-approximation net-

work. A high-speed, 3-state parallel port directly

interfaces to a digital signal processor (DSP) or

microprocessor (µP) system data bus. D0 through

D9 are the digital output terminals with D0 being

the least significant bit (LSB). Separate power

terminals for the analog and digital portions

minimize noise pickup in the supply leads.

Additionally, the digital power is divided into two

parts to separate the lower current logic from the

higher current bus drivers. An external clock can be

applied to CLKIN to override the internal system

clock if desired.

FK OR FN PACKAGE

(TOP VIEW)

4

3

2 1 28 27 26

5

6

7

8

9

AIN

ANLG V

DGTL GND1

25 CS

24 D9

DD

D8

NC

D7

D6

D5

23

22

21

20

19

NC

DGTL GND2

DGTL V

10

11

DD1

DGTL V

DD2

The TLC1550I and TLC1551I are characterized for

operation from −40°C to 85°C. The TLC1550M is

characterized over the full military range of −55°C

to 125°C.

12 13 14 15 16 17 18

NC − No internal connection

AVAILABLE OPTIONS

PACKAGE

T

A

CERAMIC CHIP CARRIER PLASTIC CHIP CARRIER

CERAMIC DIP

(J)

SOIC

(DW)

(FK)

(FN)

TLC1550IFN

TLC1551IFN

TLC1550IDW

TLC1551IDW

−40°C to 85°C

−55°C to 125°C

—

TLC1550MFK

—

TLC1550MJ

—

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These

circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,

Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated

voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device

should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,

preferably either V

CC

or ground.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Advanced LinEPIC is a trademark of Texas Instruments.

ꢖ

ꢒ

ꢍ

ꢜ

ꢏ

ꢝ

ꢤ

ꢗ

ꢂ

ꢠ

ꢀ

ꢞ

ꢪ

ꢆ

ꢛ

ꢍ

ꢘ

ꢚ

ꢌ

ꢮ

ꢏ

ꢋ

ꢀ

ꢋ

ꢣ

ꢘ

ꢨ

ꢝ

ꢮ

ꢛ

ꢞ

ꢚ

ꢡ

ꢤ

ꢘ

ꢟ

ꢣ

ꢙ

ꢛ

ꢚ

ꢘ

ꢛ

ꢣ

ꢠ

ꢙ

ꢠ

ꢞ

ꢝ

ꢟ

ꢬ

ꢚ

ꢩ

ꢚ

ꢨ

ꢘ

ꢟ

ꢤ

ꢡ

ꢠ

ꢘ

ꢛ

ꢮ

ꢙ

ꢝ

ꢯ

ꢠ

ꢢ

ꢣ

ꢞ

ꢤ

ꢠ

ꢟ

ꢣ

ꢟ

ꢭ

ꢛ

ꢚ

ꢘ

ꢝ

ꢜ

ꢤ

ꢘ

ꢜ

ꢟ

ꢨ

ꢠ

ꢨ

ꢫ

Copyright  2003, Texas Instruments Incorporated

ꢍ ꢘ ꢙ ꢚ ꢛꢜ ꢝꢞ ꢟꢠ ꢞꢛ ꢡꢙ ꢢꢣ ꢤꢘ ꢟ ꢟꢛ ꢈꢆ ꢁꢉ ꢖꢒ ꢥ ꢉꢦꢧꢄ ꢦꢄꢇ ꢤꢢꢢ ꢙꢤ ꢚ ꢤ ꢡꢨ ꢟꢨꢚ ꢠ ꢤ ꢚ ꢨ ꢟꢨ ꢠꢟꢨ ꢜ

ꢚ

ꢛ

ꢞ

ꢟ

ꢛ

ꢚ

ꢡ

ꢟ

ꢛ

ꢠ

ꢙ

ꢣ

ꢮ

ꢣ

ꢞ

ꢨ

ꢚ

ꢟ

ꢨ

ꢚ

ꢛ

ꢮ

ꢀ

ꢨ

ꢰ

ꢤ

ꢆ

ꢘ

ꢡ

ꢨ

ꢠ

ꢟ

ꢤ

ꢘ

ꢜ

ꢚ

ꢜ

ꢤ

ꢟ ꢨ ꢠ ꢟꢣ ꢘꢬ ꢛꢮ ꢤ ꢢꢢ ꢙꢤ ꢚ ꢤ ꢡ ꢨ ꢟ ꢨ ꢚ ꢠ ꢫ

ꢚ

ꢤ

ꢘ

ꢟ

ꢭ

ꢫ

ꢖ

ꢚ

ꢛ

ꢜ

ꢟ

ꢣ

ꢛ

ꢞ

ꢨ

ꢠ

ꢣ

ꢘ

ꢜ

ꢛ

ꢨ

ꢛ

ꢟ

ꢘ

ꢨ

ꢞ

ꢨ

ꢠ

ꢤ

ꢚ

ꢣ

ꢢ

ꢣ

ꢘ

ꢞ

ꢢ

ꢝ

ꢝ ꢘꢢ ꢨꢠꢠ ꢛ ꢟꢩꢨ ꢚ ꢪꢣ ꢠꢨ ꢘ ꢛꢟꢨ ꢜꢫ ꢍ ꢘ ꢤꢢ ꢢ ꢛ ꢟꢩꢨ ꢚ ꢙꢚ ꢛ ꢜꢝꢞ ꢟꢠ ꢇ ꢙꢚ ꢛ ꢜꢝꢞ ꢟꢣꢛ ꢘ

ꢟ

ꢙ

ꢚ

ꢛꢞ

ꢨ

ꢠ

ꢣ

ꢘꢬ

ꢜ

ꢛꢨ

ꢠ

ꢘ

ꢛꢟ

ꢘ

ꢨ

ꢞ

ꢨ

ꢠ

ꢤ

ꢚ

ꢣ

ꢢ

ꢭ

ꢣ

ꢘ

ꢞ

ꢢ

ꢝ

ꢜ

ꢨ

ꢟ

ꢨ

ꢠ

ꢣ

ꢘ

ꢬ

ꢛ

ꢮ

ꢤ

ꢢ

ꢙ

ꢤ

ꢚ

ꢤ

ꢡ

ꢨ

ꢟ

ꢨꢚ

ꢠ

ꢫ

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃꢄ ꢄ ꢅ ꢈꢇ ꢀꢁ ꢂꢃ ꢄ ꢄ ꢃ ꢆ

ꢃꢅ ꢉꢊꢆ ꢀ ꢋ ꢌꢋ ꢁ ꢍꢎꢉꢀꢍ ꢉꢏꢆ ꢎ ꢆꢀꢋꢁ ꢂꢍ ꢌꢐ ꢑ ꢒꢀꢑꢒ ꢓ

ꢔꢆ ꢀ ꢕ ꢖꢋ ꢒ ꢋꢁ ꢁ ꢑ ꢁ ꢍ ꢗꢀꢖ ꢗꢀ ꢓ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

functional block diagram

EOC

10

CS

WR

RD

Successive-

Approximation

Register

D0−D9

Control

Logic

10

Frequency

Divided by 2

Internal

Clock

DGTL

Comp

V

DD1

10-Bit

100 kΩ

Capacitor

NOM

DAC and S/H

Clock Detector

CLKIN

REF+

REF−

AIN

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

AIN

C = 60 pF TYP

i

(equivalent input

capacitance)

5 MΩ TYP

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢎ

ꢂ

ꢉ

ꢔ

ꢃ

ꢀ

ꢄ

ꢍ

ꢆ

ꢄ

ꢉ

ꢀ

ꢅ

ꢏ

ꢕ

ꢆ

ꢇ

ꢆ

ꢖ

ꢀ

ꢎ

ꢋ

ꢁ

ꢂ

ꢋ

ꢃ

ꢁ

ꢄ

ꢂ

ꢁ

ꢅ

ꢍ

ꢑ

ꢈ

ꢌ

ꢁ

ꢇ

ꢀ

ꢁ

ꢒ

ꢀ

ꢂ

ꢀ

ꢖ

ꢃ

ꢑ

ꢗ

ꢄ

ꢒ

ꢄ

ꢃ

ꢆ

ꢓ

ꢃ

ꢅ

ꢉ

ꢊ

ꢆ

ꢀ

ꢋ

ꢌ

ꢋ

ꢁꢍ

ꢆ

ꢀ

ꢐ

ꢑ

ꢒ

ꢍ

ꢗ

ꢀ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

Terminal Functions

TERMINAL

DESCRIPTION

†

‡

NAME

ANLG GND

AIN

NO.

4

NO.

3

Analog ground. The reference point for the voltage applied on terminals ANLG V , AIN, REF+, and REF−.

DD

5

4

Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output.

ANLG V

CLKIN

6

5

Analog positive power supply voltage. The voltage applied to this terminal is designated V .

DD3

DD

26

22

Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a

few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high

or left unconnected.

CS

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

25

13

14

16

17

18

19

20

21

23

24

7

21

11

12

13

14

15

16

17

18

19

20

6

Chip-select. CS must be low for RD or WR to be recognized by the A/D converter.

Data bus output. D0 is bit 1 (LSB).

Data bus output. D1 is bit 2.

Data bus output. D2 is bit 3.

Data bus output. D3 is bit 4.

Data bus output. D4 is bit 5.

Data bus output. D5 is bit 6.

Data bus output. D6 is bit 7.

Data bus output. D7 is bit 8.

Data bus output. D8 is bit 9.

Data bus output. D9 is bit 10 (MSB).

DGTL GND1

DGTL GND2

Digital ground 1. The ground for power supply DGTL V

Digital ground 2. The ground for power supply DGTL V

and is the substrate connection

DD1

DD2

9

7

DGTL V

EOC

10

8

Digital positive power-supply voltage 1. DGTL V

DD1

supplies the logic. The voltage applied to DGTL V is

DD1

designated V

.

DD1

11

12

28

9

10

24

Digital positive power-supply voltage 2. DGTL V supplies only the higher-current output buffers. The voltage

DD2

applied to DGTL V

is designated V .

DD2

End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferred

to the output latch. EOC can be connected to the µP- or DSP-interrupt terminal or can be continuously polled.

RD

Read input. When CS is low and RD is taken low, the data is placed on the data bus from the output latch. The

output latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RD

resets EOC to a high within the t

specifications.

d(EOC)

REF+

2

1

Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts

to 1111111111. Analog input voltages between REF+ and REF− convert to the appropriate result in a ratiometric

manner.

REF−

WR

3

2

Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF− converts

to 0000000000.

27

23

Write input. When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holds

the analog input until conversion is completed. Before and after the conversion period, which is given by t

the ADC remains in the sampling mode.

,

conv

†

‡

Terminal numbers for FK and FN packages.

Terminal numbers for J, DW, and NW packages.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃꢄ ꢄ ꢅ ꢈꢇ ꢀꢁ ꢂꢃ ꢄ ꢄ ꢃ ꢆ

ꢃꢅ ꢉꢊꢆ ꢀ ꢋ ꢌꢋ ꢁ ꢍꢎꢉꢀꢍ ꢉꢏꢆ ꢎ ꢆꢀꢋꢁ ꢂꢍ ꢌꢐ ꢑ ꢒꢀꢑꢒ ꢓ

ꢔꢆ ꢀ ꢕ ꢖꢋ ꢒ ꢋꢁ ꢁ ꢑ ꢁ ꢍ ꢗꢀꢖ ꢗꢀ ꢓ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

, V

, and V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V

DD1 DD2

DD3

Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

Output voltage range, V

+ 0.3 V

I

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

O

Peak input current (any digital input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

Operating free-air temperature range, T : TLC1550I, TLC1551I . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

A

TLC1550M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Case temperature for 10 seconds: FK or FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: J or NW package . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1:

V

is the voltage measured at DGTL V

with respect to DGND1. V

is the voltage measured at DGTL V

with respect to the

with respect to AGND. For these specifications, all ground terminals are tied

DD

DD1

DGND2. V

DD1

DD2

is the voltage measured at ANLG V

DD3

together (and represent 0 V). When V

, V

, and V

are equal, they are referred to simply as V

.

DD1 DD2 DD3

DD

recommended operating conditions

MIN

NOM MAX

UNIT

V

Supply voltage, V

, V

4.75

5

5.5

DD1 DD2 DD3

Positive reference voltage, V

(see Note 2)

V

DD3

0

V

REF+

Negative reference voltage, V

(see Note 2)

V

REF−

Differential reference voltage, V

− V

REF−

(see Note 2)

V

DD3

V

REF+

Analog input voltage range

0

2

V

DD3

V

High-level control input voltage, V

IH

V

Low-level control input voltage, V

IL

0.8

7.8

V

Input clock frequency, f

(CLKIN)

0.5

0

MHz

ns

Setup time, CS low before WR or RD goes low, t

su(CS)

Hold time, CS low after WR or RD goes high, t

h(CS)

0

WR or RD pulse duration, t

w(WR)

50

40% of

period

80% of

period

Input clock low pulse duration, t

w(L−CLKIN)

TLC155xI

−40

−55

85

Operating free-air temperature, T

°C

A

TLC1550M

125

NOTE 2: Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied to

REF− convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢎ

ꢂ

ꢉ

ꢔ

ꢃ

ꢀ

ꢄ

ꢍ

ꢆ

ꢄ

ꢉ

ꢀ

ꢅ

ꢏ

ꢕ

ꢆ

ꢇ

ꢆ

ꢖ

ꢀ

ꢎ

ꢋ

ꢁ

ꢂ

ꢋ

ꢃ

ꢁ

ꢄ

ꢂ

ꢁ

ꢅ

ꢍ

ꢑ

ꢈ

ꢌ

ꢁ

ꢇ

ꢀ

ꢁ

ꢒ

ꢀ

ꢂ

ꢀ

ꢖ

ꢃ

ꢑ

ꢗ

ꢄ

ꢒ

ꢄ

ꢃ

ꢆ

ꢓ

ꢃ

ꢅ

ꢉ

ꢊ

ꢆ

ꢀ

ꢋ

ꢌ

ꢋ

ꢁꢍ

ꢆ

ꢀ

ꢐꢑ

ꢒ

ꢍ

ꢗ

ꢀ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

electrical characteristics over recommended operating free-air temperature range,

V

= V

= 4.75 V to 5.5 V and V = 0 (unless otherwise noted)

DD

REF+

REF−

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V

High-level output voltage

V

= 4.75 V,

I

= −360 µA

= 25°C

A

2.4

V

OH

DD

OH

T

0.4

0.5

10

V

I

= 4.75 V,

= 2.4 mA

DD

OL

V

OL

Low-level output voltage

V

T

= −55°C to 125°C

A

V

= V

DD

,

CS and RD at V

O

DD

I

Off-state (high-impedance-state) output current

µA

OZ

V

= 0,

CS and RD at V

−10

2.5

I

IH

I

IL

I

IL

High-level input current

V = V

I DD

0.005

−2.5 −0.005

µA

Low-level input current (except CLKIN)

Low-level input current (CLKIN)

V = 0

I

−50

7

−50

14

−12

2

V

= 5 V,

= 0,

T

= 25°C

O

A

I

Short-circuit output current

Operating supply current

mA

pF

OS

T

−6

8

O

A

I

CS low and RD high

(DD)

Analog inputs

Input capacitance

60

5

90*

15*

C

See typical equivalent inputs TLC1550/1I

i

Digital inputs

* On products compliant to MIL-STD-883, Class B, this parameter is not production tested.

†

All typical values are at V

= 5 V, T = 25°C.

A

DD

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃꢄ ꢄ ꢅ ꢈꢇ ꢀꢁ ꢂꢃ ꢄ ꢄ ꢃ ꢆ

ꢃꢅ ꢉꢊꢆ ꢀ ꢋ ꢌꢋ ꢁ ꢍꢎꢉꢀꢍ ꢉꢏꢆ ꢎ ꢆꢀꢋꢁ ꢂꢍ ꢌꢐ ꢑ ꢒꢀꢑꢒ ꢓ

ꢔꢆ ꢀ ꢕ ꢖꢋ ꢒ ꢋꢁ ꢁ ꢑ ꢁ ꢍ ꢗꢀꢖ ꢗꢀ ꢓ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

operating characteristics over recommended operating free-air temperature range with internal

clock and minimum sampling time of 4 µs, V

noted)

= V

= 5 V and V

= 0 (unless otherwise

DD

REF+

REF−

†

‡

PARAMETER

TLC1550I

TEST CONDITIONS

T

A

MIN TYP

MAX

0.5

1

UNIT

Full range

25°C

TLC1551I

E

Linearity error

Zero-scale error

Full-scale error

See Note 3

LSB

L

0.5

1

TLC1550M

Full range

25°C

TLC1550I

TLC1551I

0.5

1

See Notes 2 and 4

LSB

ZS

FS

0.5

1

TLC1550M

Full range

25°C

TLC1550I

TLC1551I

0.5

1

See Notes 2 and 4

See Note 5

0.5

1

TLC1550M

Full range

25°C

TLC1550I

TLC1551I

TLC1550M

0.5

1

Total unadjusted error

Conversion time

LSB

1

f

= 4.2 MHz or

clock(external)

internal clock

t

c

6

µs

t

Data access time after RD goes low

Data valid time after RD goes high

35

ns

a(D)

5

v(D)

See Figure 3

Disable time, delay time from RD high to high

impedance

t

30

ns

dis(D)

Delay time, RD low to EOC high

0

15

d(EOC)

†

‡

Full range is −40°C to 85°C for the TL155xI devices and −55°C to 125°C for the TLC1550M.

All typical values are at V

= 5 V, T = 25°C.

DD

A

NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied

to REF− convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.

3. Linearity error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value

after zero-scale error and full-scale error have been removed.

4. Zero-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified zero scale.

Full-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified full scale.

5. Total unadjusted error is the difference between the actual analog value at the transition between any two adjacent steps and its

ideal value. It includes contributions from zero-scale error, full-scale error, and linearity error.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢎ

ꢂ

ꢉ

ꢔ

ꢃ

ꢀ

ꢄ

ꢍ

ꢆ

ꢄ

ꢉ

ꢀ

ꢅ

ꢏ

ꢕ

ꢆ

ꢇ

ꢆ

ꢖ

ꢀ

ꢎ

ꢋ

ꢁ

ꢂ

ꢋ

ꢃ

ꢁ

ꢄ

ꢂ

ꢁ

ꢅ

ꢍ

ꢑ

ꢈ

ꢌ

ꢁ

ꢇ

ꢀ

ꢁ

ꢒ

ꢀ

ꢂ

ꢀ

ꢖ

ꢃ

ꢑ

ꢗ

ꢄ

ꢒ

ꢄ

ꢃ

ꢆ

ꢓ

ꢃ

ꢅ

ꢉ

ꢊ

ꢆ

ꢀ

ꢋ

ꢌ

ꢋ

ꢁꢍ

ꢆ

ꢀ

ꢐꢑ

ꢒ

ꢍ

ꢗ

ꢀ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

PARAMETER MEASUREMENT INFORMATION

Source Current = 6 mA

Test Point

See Note A

Output

Under Test

V

cp

= 1 V

C

= 62 pF

L

Sink Current = 6 mA

V

cp

= voltage commutation point for switching between source and sink currents

NOTE A: Equivalent load circuit of the Teradyne A500 tester for timing parameter measurement

Figure 1. Test Load Circuit

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃꢄ ꢄ ꢅ ꢈꢇ ꢀꢁ ꢂꢃ ꢄ ꢄ ꢃ ꢆ

ꢃꢅ ꢉꢊꢆ ꢀ ꢋ ꢌꢋ ꢁ ꢍꢎꢉꢀꢍ ꢉꢏꢆ ꢎ ꢆꢀꢋꢁ ꢂꢍ ꢌꢐ ꢑ ꢒꢀꢑꢒ ꢓ

ꢔꢆ ꢀ ꢕ ꢖꢋ ꢒ ꢋꢁ ꢁ ꢑ ꢁ ꢍ ꢗꢀꢖ ꢗꢀ ꢓ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

APPLICATION INFORMATION

simplified analog input analysis

Using the circuit in Figure 2, the time required to charge the analog input capacitance from 0 to V within 1/2

S

LSB can be derived as follows:

The capacitance charging voltage is given by

–t ńR C

c

t

i

Ǔ

(1)

(2)

_Sǒ_1−e

V

+ V

C

Where:

R = R + r

i

t

s

The final voltage to 1/2 LSB is given by

V (1/2 LSB) = V − (V /1024)

C

S

Equating equation 1 to equation 2 and solving for time t gives

c

–t ńR C

c

t

i

_*ǒ_{V ń512 + V}

Ǔ

_Sǒ_1–e

Ǔ

V

(3)

(4)

S

and

t (1/2 LSB) = R × C × ln(1024)

c

t

i

Therefore, with the values given, the time for the analog input signal to settle is

t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(1024)

(5)

c

s

This time must be less than the converter sample time shown in the timing diagrams.

†

Driving Source

TLC1550/1

R

r

i

s

V

I

V

S

V

C

1 kΩ MAX

C

i

50 pF MAX

V

= Input voltage at AIN

= External driving source voltage

I

S

s

R = Source resistance

r

= Input resistance

i

C = Input capacitance

i

†

Driving source requirements:

• Noise and distortion for the source must be equivalent to the resolution of the converter.

• R must be real at the input frequency.

s

Figure 2. Input Circuit Including the Driving Source

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢎ

ꢂ

ꢉ

ꢔ

ꢃ

ꢀ

ꢄ

ꢍ

ꢆ

ꢄ

ꢉ

ꢀ

ꢅ

ꢏ

ꢕ

ꢆ

ꢇ

ꢆ

ꢖ

ꢀ

ꢎ

ꢋ

ꢁ

ꢂ

ꢋ

ꢃ

ꢁ

ꢄ

ꢂ

ꢁ

ꢅ

ꢍ

ꢑ

ꢈ

ꢌ

ꢁ

ꢇ

ꢀ

ꢁ

ꢒ

ꢀ

ꢂ

ꢀ

ꢖ

ꢃ

ꢑ

ꢗ

ꢄ

ꢒ

ꢄ

ꢃ

ꢆ

ꢓ

ꢃ

ꢅ

ꢉ

ꢊ

ꢆ

ꢀ

ꢋ

ꢌ

ꢋ

ꢁꢍ

ꢆ

ꢀ

ꢐꢑ

ꢒ

ꢍ

ꢗ

ꢀ

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

PRINCIPLES OF OPERATION

The operating sequence for complete data acquisition is shown in Figure 3. Processors can address the TLC1550

and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoder

output to CS. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when CS is low.

Once CS is low, the onboard system clock permits the conversion to begin with a simple write command and the

converted data to be presented to the data bus with a simple read command. The device remains in a sampling (track)

mode from the rising edge of EOC until conversion begins with the rising edge of WR, which initiates the hold mode.

After the hold mode begins, the clock controls the conversion automatically. When the conversion is complete, the

end-of-conversion (EOC) signal goes low indicating that the digital data has been transferred to the output latch.

Lowering CS and RD then resets EOC and transfers the data to the data bus for the processor read cycle.

t

h(CS)

su(CS)

CS

0.8 V

t

c

t

w(WR)

2 V

1.4 V

0.8 V

WR

RD

t

h(CS)

t

su(CS)

2 V

0.8 V

t

v(D)

t

a(D)

dis(D)

2 V

0.8 V

2 V

0.8 V

D0−D9

EOC

Data Valid

t

d(EOC)

2 V

0.8 V

Figure 3. TLC1550 or TLC1551 Operating Sequence

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

16-Mar-2007

PACKAGING INFORMATION

Orderable Device

TLC1550IDW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

DW

24

28

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC1550IDWG4

TLC1550IDWR

TLC1550IDWRG4

TLC1550IFN

SOIC

PLCC

DW

FN

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

37 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC1550IFNR

FN

750 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC1550INW

TLC1550MFKB

TLC1550MJ

OBSOLETE

ACTIVE

PDIP

LCCC

CDIP

SOIC

NW

FK

J

24

28

24

TBD

Call TI

TLC1550MJB

TLC1551IDW

J

DW

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC1551IDWG4

TLC1551IDWR

TLC1551IDWRG4

TLC1551IFN

ACTIVE

SOIC

PLCC

DW

FN

24

28

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

37 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC1551IFNG4

FN

37 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Mar-2007

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997

J (R-GDIP-T**)

CERAMIC DUAL-IN-LINE PACKAGE

24 PINS SHOWN

B

13

24

C

12

1

0.065 (1,65)

0.045 (1,14)

Lens Protrusion (Lens Optional)

0.010 (0.25) MAX

0.090 (2,29)

0.060 (1,53)

0.175 (4,45)

0.140 (3,56)

A

Seating Plane

0.018 (0,46) MIN

0.125 (3,18) MIN

0.022 (0,56)

0.014 (0,36)

0.100 (2,54)

0.012 (0,30)

0.008 (0,20)

24

28

32

40

PINS **

DIM

”A”

NARR

WIDE

NARR

WIDE

NARR

WIDE

NARR

WIDE

0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)

1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)

1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)

0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)

MAX

MIN

MAX

MIN

”B”

”C”

MAX

MIN

4040084/C 10/97

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).

D. This package can be hermetically sealed with a ceramic lid using glass frit.

E. Index point is provided on cap for terminal identification.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to

discontinue any product or service without notice. Customers should obtain the latest relevant information

before placing orders and should verify that such information is current and complete. All products are sold

subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent

TI deems necessary to support this warranty. Except where mandated by government requirements, testing

of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible

for their products and applications using TI components. To minimize the risks associated with customer

products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent

right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine,

or process in which TI products or services are used. Information published by TI regarding third-party

products or services does not constitute a license from TI to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or

other intellectual property of the third party, or a license from TI under the patents or other intellectual

property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices.

Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not

responsible or liable for such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for

that product or service voids all express and any implied warranties for the associated TI product or service

and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Amplifiers

Data Converters

DSP

Interface

Applications

Audio

Automotive

Broadband

Digital Control

Military

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Logic

Power Mgmt

Microcontrollers

Low Power Wireless

power.ti.com

microcontroller.ti.com

www.ti.com/lpw

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TLC1551IDW
厂家：	TEXAS INSTRUMENTS
描述：	10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS 10位模拟数字转换器具有并行输出转换器模数转换器光电二极管输出元件
文件：	总16页 (文件大小：371K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLC1551IDW [TI]

相关型号：

TLC1551IDWG4

TLC1551IDWR

TLC1551IDWRG4

TLC1551IFK

TLC1551IFN

TLC1551IFNG4

TLC1551IFNR

TLC1551IJ

TLC1551IN

TLC1551INW

TLC155D

TLC155ED