TLC5628INE4 [TI]
OCTAL, SERIAL INPUT LOADING, 10us SETTLING TIME, 8-BIT DAC, PDIP16, PLASTIC, DIP-16;
| 型号： | TLC5628INE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL, SERIAL INPUT LOADING, 10us SETTLING TIME, 8-BIT DAC, PDIP16, PLASTIC, DIP-16 输入元件 光电二极管 转换器 |
| 文件： | 总15页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
N OR DW PACKAGE
(TOP VIEW)
Eight 8-Bit Voltage Output DACs
5-V Single-Supply Operation
Serial Interface
DACC
DACD
REF1
DACB
DACA
GND
1
2
3
4
5
6
7
8
16
15
14
High-Impedance Reference Inputs
Programmable 1 or 2 Times Output Range
Simultaneous Update Facility
Internal Power-On Reset
13 LDAC
12 LOAD
DATA
CLK
11
10
9
REF2
DACH
DACG
V
DD
Low-Power Consumption
DACE
DACF
Half-Buffered Output
applications
Programmable Voltage Sources
Digitally Controlled Amplifiers/Attenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis
description
The TLC5628C and TLC5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two
times the reference voltages and GND and are monotonic. The device is simple to use, running from a single
supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLC5628C and TLC5628I are over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word
comprises eight bits of data, three DAC select bits, and a range bit, the latter allowing selection between the
times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values
tobewrittentothedevice, thenallDACoutputsareupdatedsimultaneouslythroughcontrolofLDAC. Thedigital
inputs feature Schmitt triggers for high-noise immunity.
The 16-terminal small-outline (D) package allows digital control of analog functions in space-critical
applications. The TLC5628C is characterized for operation from 0°C to 70°C. The TLC5628I is characterized
for operation from –40°C to 85°C. The TLC5628C and TLC5628I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(DW)
PLASTIC DIP
(N)
T
A
0°C to 70°C
TLC5628CDW
TLC5628IDW
TLC5628CN
TLC5628IN
–40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
functional block diagram
14
REF1
+
–
DAC
2
+
–
DACA
× 2
9
8
Latch
Latch
DAC
DAC
15
7
+
–
DACD
DACE
× 2
× 2
8
8
Latch
Latch
Latch
Latch
11
REF2
+
–
+
–
DAC
10
+
–
DACH
× 2
8
Latch
Latch
5
CLK
DATA
LOAD
Power-On
Reset
4
Serial
Interface
13
LDAC
12
Terminal Functions
TERMINAL
NAME NO.
CLK
I/O
DESCRIPTION
5
I
Serialinterface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock
applied to the CLK terminal.
DACA
DACB
DACC
DACD
DACE
DACF
DACG
DACH
DATA
2
1
O
O
O
O
O
O
O
O
I
DAC A analog output
DAC B analog output
DAC C analog output
DAC D analog output
DAC E analog output
DAC F analog output
DAC G analog output
DAC H analog output
16
15
7
8
9
10
4
Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.
GND
3
I
I
Ground return and reference terminal
LDAC
13
Load DAC. When LDAC is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when LDAC is taken from high to low.
LOAD
12
I
Serial interface load control. When LDAC is low, the falling edge of the LOAD signal latches the digital data into
the output latch and immediately produces the analog voltage at the DAC output terminal.
REF1
REF2
14
11
6
I
I
I
Reference voltage input to DAC A B C D. This voltage defines the analog output range.
Reference voltage input to DAC E F G H. This voltage defines the analog output range.
Positive supply voltage
V
DD
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
detailed description
The TLC5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance
of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance load to the
reference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2
is used by DACE through DACH.
EachDAC output is buffered by a configurable-gain output amplifier, that can be programmed to times 1 or times
2 gain.
On power up, the DACs are reset to CODE 0.
Each output voltage is given by:
CODE
V (DACA|B|C|D|E|F|G|H)
REF
(1 RNG bit value)
O
256
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.
Table 1. Ideal Output Transfer
D7
0
0
•
D6
0
0
•
D5
0
0
•
D4
0
0
•
D3
0
0
•
D2
0
0
•
D1
0
0
•
D0
0
1
•
OUTPUT VOLTAGE
GND
(1/256) × REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
0
1
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
(127/256) × REF (1+RNG)
(128/256) × REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
(255/256) × REF (1+RNG)
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have
been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When
LDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit
(MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4.
CLK
t
su(DATA-CLK)
t
su(LOAD-CLK)
D2 D1
su(CLK-LOAD)
t
v(DATA-CLK)
DATA
LOAD
A2
A1 A0
RNG
D7
D6
D5
D4
D0
t
t
w(LOAD)
DAC Update
Figure 1. LOAD-Controlled Update (LDAC = Low)
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
data interface (continued)
CLK
t
su(DATA-CLK)
t
v(DATA-CLK)
DATA
A2
A1 A0
RNG
D7
D6
D5
D4
D2
D1
D0
t
su(LOAD–LDAC)
LOAD
LDAC
t
w(LDAC)
DAC Update
Figure 2. LDAC-Controlled Update
CLK Low
CLK
A2
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
DATA
LOAD
LDAC
Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low)
CLK Low
CLK
A2
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
DATA
LOAD
LDAC
Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word
Table 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 2. Serial Input Decode
A2
0
A1
0
A0
0
DAC UPDATED
DACA
0
0
1
DACB
0
1
0
DACC
0
1
1
DACD
1
0
0
DACE
1
0
1
DACF
1
1
0
DACG
1
1
1
DACH
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
linearity, offset, and gain error using single-end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output
voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most
negative supply rail is ground, the output cannot drive below ground.
The output voltage remains at 0 V until the input code value produces a sufficient output voltage to overcome
the inherent negative offset voltage, resulting in the transfer function shown in Figure 5.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 5. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces the breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below ground.
For a DAC, linearity is measured between the zero-input code (all inputs are 0) and the full-scale code (all inputs
are 1) after offset and full scale are adjusted out or accounted for in some way. However, single-supply operation
does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the
linearity in the unipolar mode is measured between full-scale code and the lowest code that produces a positive
output voltage.
The code is calculated from the maximum specification for the negative offset voltage.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
equivalent of inputs and outputs
INPUT CIRCUIT
OUTPUT CIRCUIT
V
DD
V
DD
_
+
Input from
Decoded DAC
Register String
DAC
Voltage Output
V
ref
Input
× 1
84 kΩ
Output
Range
Select
To DAC
Resistor
String
I
× 2
SINK
60 µA
Typical
84 kΩ
GND
GND
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
Digital input voltage range, V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V
Operating free-air temperature range, T : TLC5628C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
– GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V
+ 0.3 V
+ 0.3 V
ID
DD
DD
A
TLC5628I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
V
Supply voltage, V
DD
4.75
5.25
High-level voltage, V
IH
0.8 V
V
DD
Low-level voltage, V
0.8
V
IL
Reference voltage, V [A|B|C|D|E|F|G|H]
V
DD
–1.5
V
ref
Analog full-scale output voltage, R = 10 kΩ
3.5
V
L
Load resistance, R
10
kΩ
ns
L
Setup time, data input, t
(see Figures 1 and 2)
50
50
su(DATA-CLK)
Valid time, data input valid after CLK↓, t
(see Figures 1 and 2)
ns
ns
ns
ns
ns
ns
v(DATA-CLK)
Setup time, CLK eleventh falling edge to LOAD, t
(see Figure 1)
50
su(CLK-LOAD)
(see Figure 1)
Setup time, LOAD↑ to CLK↓, t
50
su(LOAD-CLK)
Pulse duration, LOAD, t
Pulse duration, LDAC, t
(see Figure 1)
(see Figure 2)
250
250
0
w(LOAD)
w(LDAC)
Setup time, LOAD↑ to LDAC↓, t
(see Figure 2)
su(LOAD-LDAC)
CLK frequency
1
70
85
MHz
°C
TLC5628C
TLC5628I
0
Operating free-air temperature, T
A
–40
°C
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
electrical characteristics over recommended operating free-air temperature range, V = 5 V ± 5%,
DD
V
= 2 V, × 1 gain output range (unless otherwise noted)
ref
PARAMETER
High-level input current
Low-level input current
Output sink current
TEST CONDITIONS
MIN
TYP
MAX
±10
±10
UNIT
µA
I
I
I
I
V = V
I DD
IH
V = 0 V
I
µA
IL
20
2
µA
O(sink)
O(source)
Each DAC output
Output source current
mA
Input capacitance
15
15
C
pF
i
Reference input capacitance
Supply current
I
I
V
V
= 5 V
= 5 V,
= 2 V,
= 2 V,
= 2 V,
= 2 V,
= 2 V,
= 2 V,
4
±10
±1
mA
µA
DD
DD
Reference input current
Linearity error (end point corrected)
Differential-linearity error
Zero-scale error
V
= 2 V
ref
DD
ref
E
E
E
V
ref
× 2 gain (see Note 1)
× 2 gain (see Note 2)
× 2 gain (see Note 3)
× 2 gain (see Note 4)
× 2 gain (see Note 5)
× 2 gain (see Note 6)
LSB
LSB
mV
L
V
ref
±0.9
30
D
V
ref
0
ZS
Zero-scale-error temperature coefficient
Full-scale error
V
ref
10
µV/°C
mV
E
FS
V
ref
±60
Full-scale-error temperature coefficient
Power supply rejection ratio
V
ref
±25
µV/°C
mV/V
PSRR
See Notes 7 and 8
0.5
NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
2. Differentialnonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(T
) – ZSE(T
)]/V × 10 /(T
– T
).
max
min ref max
min
5. Full-scale error is the deviation from the ideal full-scale output (V – 1 LSB) with an output load of 10 kΩ.
ref
6
6. Full-scale error temperature coefficient is given by: FSETC = [FSE(T
max
) – FSE (T
)]/V × 10 /(T
– T
).
min
min
ref max
7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the V
this signal imposed on the zero-code output voltage.
from 4.5 V to 5.5 V dc and measuring the proportion of
DD
8. Full-scale-error rejection ratio (FSE RR) is measured by varying the V
this signal imposed on the full-scale output voltage.
from 4.5 V to 5.5 V dc and measuring the proportion of
DD
operating characteristics over recommended operating free-air temperature range, V = 5 V ± 5%,
DD
V
= 2 V, × 1 gain output range (unless otherwise noted)
ref
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
V/µs
µs
Output slew rate
C
= 100 pF,
R
C
= 10 kΩ
L
L
L
Output settling time
To ±0.5 LSB,
= 100 pF,
R
= 10 kΩ, See Note 9
10
L
Large signal bandwidth
Digital crosstalk
Measured at –3 dB point
100
–50
–60
–60
100
kHz
dB
CLK = 1-MHz square wave measured at DACA-DACD
Reference feedthrough
Channel-to-channel isolation
Reference input bandwidth
See Note 10
See Note 11
See Note 12
dB
dB
kHz
NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within ±0.5 LSB starting from
an initial output voltage equal to zero.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a V input = 1 V dc + 1 V at 10 kHz.
ref pp
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with V input = 1 V dc + 1 V at 10 kHz.
ref pp
12. Reference bandwidth is the –3 dB bandwidth with an input at V = 1.25 V dc + 2 V and with a full-scale digital input code.
ref
pp
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
TLC5628
DACA
DACB
•
•
•
10 kΩ
C
= 100 pF
L
DACH
Figure 6. Slew, Settling Time, and Linearity Measurements
TYPICAL CHARACTERISTICS
POSITIVE RISE AND SETTLING TIME
NEGATIVE FALL AND SETTLING TIME
LDAC
LDAC
6
4
2
6
4
2
V
T
= 5 V
DD
= 25°C
V
= 5 V
DD
= 25°C
A
T
A
Code FF to 00 Hex
Code 00 to FF Hex
Range = ×2
Range = ×2
V
= 2 V
ref
V
ref
= 2 V
0
0
0
2
4
6
8
10 12
14
16
18
0
2
4
6
8
10 12
14
16
18
t – Time – µs
t – Time – µs
Figure 7
Figure 8
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE
vs
DAC OUTPUT VOLTAGE
vs
OUTPUT LOAD
OUTPUT LOAD
4
3.5
3
5
4.8
4.6
4.4
4.2
4
2.5
2
3.8
3.6
1.5
1
V
V
= 5 V,
= 2.5 V,
DD
ref
V
= 5 V,
= 3.5 V,
3.4
3.2
3
DD
Range = 2x
V
ref
0.5
0
Range = 1x
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
R
– Output Load – kΩ
R
– Output Load – kΩ
L
L
Figure 9
Figure 10
SUPPLY CURRENT
vs
TEMPERATURE
OUTPUT SOURCE CURRENT
vs
OUTPUT VOLTAGE
1.2
1.15
1.1
8
7
6
5
4
3
2
V
= 5 V
DD
= 25°C
T
A
V
ref
= 2 V
Range = ×2
Input Code = 255
V
= 5 V
= 2V
DD
V
ref
Range = ×2
Input Code = 255
1.05
1
0.95
0.9
0.85
0.8
1
0
–50
0
50
100
0
1
2
3
4
5
t – Temperature – °C
V
O
– Output Voltage – V
Figure 11
Figure 12
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
TYPICAL CHARACTERISTICS
RELATIVE GAIN
vs
FREQUENCY
RELATIVE GAIN
vs
FREQUENCY
10
0
0
–2
–4
–10
–6
–8
–20
–30
–40
–10
–12
–14
–16
V
= 5 V
DD
= 25°C
T
A
V
= 2 Vdc + 0.5 V
ref
Input Code = 255
pp
V
= 5 V
DD
= 25°C
T
A
–50
–60
V
ref
= 1.25 Vdc + 2 V
pp
–18
–20
Input Code = 255
1
10
100
1000
10000
1
10
100
1000
f – Frequency – kHz
f – Frequency – kHz
Figure 13
Figure 14
APPLICATION INFORMATION
_
+
TLC5628
V
O
DACA
DACB
•
•
•
R
DACH
NOTE A: Resistor R
10 kΩ
Figure 15. Output Buffering Scheme
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
0.410
0.510
0.610
0.710
A MAX
(10,41) (12,95) (15,49) (18,03)
16
9
0.400
0.500
0.600
0.700
A MIN
(10,16) (12,70) (15,24) (17,78)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
4040000/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
TLC5628CDW
TLC5628CDWG4
TLC5628CDWR
TLC5628CDWRG4
TLC5628CN
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
16
16
16
16
16
16
16
16
16
16
16
16
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
N
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Pb-Free
(RoHS)
CU NIPD
N / A for Pkg Type
TLC5628CNE4
TLC5628IDW
N
Pb-Free
(RoHS)
CU NIPD
N / A for Pkg Type
DW
DW
DW
DW
N
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC5628IDWG4
TLC5628IDWR
TLC5628IDWRG4
TLC5628IN
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Pb-Free
(RoHS)
CU NIPD
N / A for Pkg Type
TLC5628INE4
N
Pb-Free
(RoHS)
CU NIPD
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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