TLC59116F_15 [TI]
16-Channel Fast-Mode Plus I2C Bus LED Driver;
| 型号： | TLC59116F_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Channel Fast-Mode Plus I2C Bus LED Driver |
| 文件： | 总31页 (文件大小：764K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC59116F
www.ti.com
SCLS714B –MARCH 2009–REVISED JULY 2011
16-CHANNEL FAST-MODE PLUS I2C BUS LED DRIVER
Check for Samples: TLC59116F
1
FEATURES
•
16 LED Drivers (Each Output Programmable at
•
•
Software Reset Feature (SWRST Call) Allows
OFF, ON, LED Brightness, and Group
Dimming/Blinking Mixed With Individual LED
Brightness)
the Device to be Reset Through the I2C Bus
Up to 14 Possible Hardware Adjustable
Individual I2C Bus Addresses Per Device so
That Each Device Can be Programmed
Output State Change Programmable on the
Acknowledge or the STOP Command to
Update Outputs Byte-by-Byte or All at the
Same Time (Default to 'Change on STOP').
•
•
16 Open-Drain Output Channels
256-Step (8-Bit) Linear Programmable
Brightness Per LED Output Varying From Fully
OFF (Default) to Maximum Brightness Using a
97-kHz PWM Signal
•
•
256-Step Group Brightness Control Allows
General Dimming (Using a 190-Hz PWM Signal
From Fully OFF to Maximum Brightness
(Default)
256-Step Group Blinking With Frequency
Programmable From 24 Hz to 10.73 s and Duty
Cycle from 0% to 99.6%
Four Hardware Address Pins Allow 14
TLC59116F Devices to be Connected to the
Same I2C Bus
Four Software-Programmable I2C Bus
Addresses (One LED Group Call Address and
Three LED Sub-Call Addresses) Allow Groups
of Devices to be Addressed Simultaneously in
Any Combination (For example, One Register
Used for 'All Call' So All the TLC59116Fs on
the I2C Bus Can be Addressed at the Same
Time and the Second register Used for three
different addresses so that 1/3 of all devices
on the bus can be addressed at the same time
in a group). Software Enable and Disable for
I2C Bus Address.
•
•
•
120-mA Maximum Output Current
17-V Maximum Output Voltage
25-MHz Internal Oscillator Requires No
External Components
1-MHz Fast-Mode Plus (FM+) Compatible I2C
Bus Interface With 30 mA High Drive
Capability on SDA Output for Driving High
Capacity Buses
Internal Power-On Reset
Noise Filter on SCL/SDA Inputs
No Glitch on Power Up
Active-Low Reset
Supports Hot Insertion
Low Standby Current
3.3-V or 5-V Supply Voltage
5.5-V Tolerant Inputs
28-Pin TSSOP (PW)
–40°C to 85°C Operation
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
TLC59116F
SCLS714B –MARCH 2009–REVISED JULY 2011
www.ti.com
PW PACKAGE
(TOP VIEW)
RHB PACKAGE
(TOP VIEW)
V
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
N.C.
A0
CC
2
SDA
A1
3
SCL
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
A2
A3
RESET
GND
A2
4
RESET
GND
A3
5
OUT0
OUT1
OUT2
OUT3
GND
OUT4
OUT15
OUT14
OUT13
OUT12
GND
OUT0
OUT1
OUT2
OUT3
GND
OUT4
OUT5
OUT6
OUT7
OUT15
OUT14
OUT13
OUT12
GND
6
Exposed
Thermal Pad
7
8
9
10
11
12
13
14
OUT11
OUT10
OUT9
OUT8
OUT11
N.C. – No internal connection
If used, the exposed thermal pad must be
connected as a secondary ground.
N.C. – No internal connection
DESCRIPTION/ORDERING INFORMATION
The TLC59116F is an I2C-bus controlled 16-channel LED driver optimized for red/green/blue/amber (RGBA)
color mixing applications. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual
PWM controller that operates at 97 kHz with a duty cycle that is adjustable from 0% to 99.6% to allow the LED to
be set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a
fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once every 10.73 seconds with a duty
cycle that is adjustable from 0% to 99.6% that is used to either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller value or at both individual
and group PWM controller values. The TLC59116F operates with a supply voltage range of 3 V to 5.5 V and the
outputs are 17 V tolerant. LEDs can be directly connected to the TLC59116F device outputs.
Software programmable LED group and three sub call I2C bus addresses allow all or defined groups of
TLC59116F devices to respond to a common I2C bus address, allowing for example, all the same color LEDs to
be turned on or off at the same time or marquee chasing effect, thus minimizing I2C bus commands.
Four hardware address pins allow up to 14 devices on the same bus.
The software reset (SWRST) call allows the master to perform a reset of the TLC59116F through the I2C bus,
identical to the power-on reset (POR) that initializes the registers to their default state causing the outputs to be
set high (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Y59116F
QFN – RHB
Tape and reel
Tape and reel
TLC59116FIRHBR
–40°C to 85°C
TSSOP – PW
TLC59116FIPWR
Y59116F
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
Copyright © 2009–2011, Texas Instruments Incorporated
TLC59116F
www.ti.com
SCLS714B –MARCH 2009–REVISED JULY 2011
BLOCK DIAGRAM
A0 A1 A2 A3
OUT0
OUT1
OUT14 OUT15
SCL
SDA
INPUT FILTER
2
I C BUS CONTROL
POWER-ON
RESET CONTROL
OUTPUT DRIVER
RESET
LED STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
GRPFREQ
REGISTER
97 kHz
24.3 kHz
GRPPWM
REGISTER
25 MHz
OSCILLATOR
190 Hz
‘0’ – Permanently OFF
‘1’ – Permanently ON
V
CC
GND
TLC59116F
Only one PWM shown for clarity.
Copyright © 2009–2011, Texas Instruments Incorporated
3
TLC59116F
SCLS714B –MARCH 2009–REVISED JULY 2011
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
QFN (RHB) TSSOP (PW)
NAME
PIN NO.
PIN NO.
A0
A1
31
2
I
I
Address input 0
Address input 1
Address input 2
Address input 3
Power ground
32
3
A2
1
2
4
5
I
A3
I
GND
7, 18, 23
10, 19, 24
–
12, 13, 28,
29, 30
N.C.
1
–
No internal connection
OUT0–OUT3
OUT4–OUT7
OUT8–OUT11
OUT12–OUT15
RESET
3–6
8–11
14–17
19–22
24
6–9
11–14
15–18
20–23
25
O
O
O
O
I
Open-drain output 0 to 3, LED ON at low
Open-drain output 4 to 7, LED ON at low
Open-drain output 8 to 11, LED ON at low
Open-drain output 12 to 15, LED ON at low
Active-low reset input
SCL
25
26
I
Serial clock input
SDA
26
27
I/O
–
Serial data input/output
VCC
27
28
Power supply
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX UNIT
VCC
VI
Supply voltage range
7
7
V
V
Input voltage range
–0.4
–0.5
VO
IO
Output voltage range
20
V
Continuous output current per channel
Power dissipation (TA = 25°C, JESD 51-7)
Junction temperature range
Storage temperature range
120
1.6
150
150
mA
W
°C
°C
PD
TJ
PW package
–40
–55
Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL IMPEDANCE
UNIT
θJA
Package thermal impedance (JESD 51-7)
61.7
°C/W
4
Copyright © 2009–2011, Texas Instruments Incorporated
TLC59116F
www.ti.com
SCLS714B –MARCH 2009–REVISED JULY 2011
RECOMMENDED OPERATING CONDITIONS(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX UNIT
VCC
VIH
VIL
Supply voltage
3
CC × 0.7
0
5.5
VCC
CC × 0.3
17
V
V
V
V
High-level input voltage
Low-level input voltage
Output voltage
SCL, SDA, RESET, A0, A1, A2, A3
SCL, SDA, RESET, A0, A1, A2, A3
OUT0–OUT15
V
V
VO
VCC = 3 V
VCC = 5 V
20
IOL
Low-level output current
SDA
mA
30
IO
Output current per channel
OUT0–OUT15
120
mA
TA
Operating free-air temperature
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
SCL, SDA,
A0, A1, A2, A3,
RESET
IL
Input/output leakage current
VI = VCC or GND
±0.3
µA
OUT0–OUT15
Output leakage current
Power-on reset voltage
VO = 17 V, TJ = 25°C
0.5
µA
VPOR
IOL
2.5
V
VCC = 3 V, VOL = 0.4 V
VCC = 5 V, VOL = 0.4 V
VCC = 3 V, IOL = 120 mA
VCC = 4.5 V, IOL = 120 mA
VCC = 3 V, IOL = 120 mA
VCC = 4.5 V, IOL = 120 mA
20
30
SDA
Low-level output current
Low-level output voltage
On resistance
mA
mV
Ω
200
175
1.67
1.46
175
15
450
400
3.75
3.3
VOL
OUT0–OUT15
OUT0–OUT15
rON
TSD
Overtemperature shutdown(2)
Restart hysteresis
150
200
°C
°C
THYS
SCL, A0, A1, A2,
A3, RESET
Ci
Input capacitance
Input/output capacitance
Supply current
VI = VCC or GND
VI = VCC or GND
VCC = 5.5 V
5
8
pF
pF
Cio
ICC
SDA
OUT0–OUT15 =
OFF
13
mA
(1) All typical values are at TJ = 25°C.
(2) Specified by design; not production tested.
Copyright © 2009–2011, Texas Instruments Incorporated
5
TLC59116F
SCLS714B –MARCH 2009–REVISED JULY 2011
www.ti.com
I2C INTERFACE BUS TIMING REQUIREMENTS
TA = –40°C to 85°C
STANDARD-MODE
FAST-MODE
I2C BUS
FAST-MODE PLUS
I2C BUS
I2C BUS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
I2C Interface
fSCL SCL clock frequency
0
100
0
400
0
1000
kHz
Bus free time between a STOP and
START condition
tBUF
tHD;STA
tSU;STA
4.7
1.3
0.5
µs
Hold time (repeated) START
condition
4
0.6
0.6
0.26
0.26
µs
µs
Set-up time for a (repeated) START
condition
1.7
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
Set-up time for STOP condition
Data hold time
Data valid acknowledge time(1)
Data valid time(2)
4
0
0.6
0
0.26
0
µs
ns
µs
µs
ns
µs
µs
0.3
0.3
250
4.7
4
3.45
3.45
0.1
0.1
100
1.3
0.6
0.9
0.9
0.05
0.05
50
0.45
0.45
Data set-up time
Low period of the SCL clock
High period of the SCL clock
Fall times of both SDA and SCL
0.5
tHIGH
0.26
(5)
tf
300
1000
50
20 + 0.1Cb
300
300
50
120
120
50
ns
ns
ns
(3) (4)
signals
Rise time of both SDA and SCL
signals
(5)
tr
20 + 0.1Cb
Pulse width of spikes that must be
suppressed by the input filter(6)
tSP
Reset
tW
Reset pulse width
Reset recovery time
Time to reset(7) (8)
10
0
10
0
10
0
ns
ns
ns
tREC
tRESET
400
400
400
(1) tVD;ACK = time for acknowledgment signal from SCL low to SDA (out) low.
(2) tVD;DAT = minimum time for SDA data out to be valid following SCL low.
(3) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCL's falling edge.
(4) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified
at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
(5) Cb = total capacitance of one bus line in pF.
(6) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
(7) Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
(8) Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.
6
Copyright © 2009–2011, Texas Instruments Incorporated
TLC59116F
www.ti.com
SCLS714B –MARCH 2009–REVISED JULY 2011
PARAMETER MEASUREMENT INFORMATION
START
ACK OR READ CYCLE
SCL
SDA
30%
30%
t
RESET
50%
50%
50%
RESET
t
W
t
REC
t
RESET
50%
OUTx
LED OFF
Figure 1. Definition of RESET Timing
SDA
t
t
SP
BUF
t
HD;STA
t
t
f
r
t
LOW
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
t
SU;DAT
t
HD;DAT
HIGH
P
S
Sr
P
Figure 2. Definition of Timing
A. Rise and fall times refer to VIL and VIH
.
START
Condition
(S)
Bit 7
MSB
(A7)
Bit 6
(A6)
Bit 7
(D1)
Bit 8
(D0)
Acknowledge
(A)
STOP Condition
(P)
Protocol
t
t
SU;STA
HIGH
t
1/f
LOW
SCL
SCL
t
r
t
f
t
BUF
SDA
t
t
t
t
t
T
HD;STA
SU;DAT
HD;DAT
VD;DAT
VD;ACK
SU;STO
Figure 3. I2C Bus Timing
Copyright © 2009–2011, Texas Instruments Incorporated
7
TLC59116F
SCLS714B –MARCH 2009–REVISED JULY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
Open
GND
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
C
R
L
T
Figure 4. Test Circuit for Switching Characteristics
A. Load resistor, RL, for SDA and SCL > 1 kΩ (3 mA or less current)
B. Load capacitance, CL, includes jig and probe capacitance
C. Termination resistance, RT, should be equal to the output impedance ZO of the pulse generators.
8
Copyright © 2009–2011, Texas Instruments Incorporated
TLC59116F
www.ti.com
SCLS714B –MARCH 2009–REVISED JULY 2011
APPLICATION INFORMATION
Device Address
Following a START condition, the bus master outputs the address of the slave it is accessing.
Regular I2C Bus Slave Address
The I2C bus slave address of the TLC59116F is shown in Figure 5. To conserve power, no internal pullup
resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low.
For buffer management purpose, a set of sector information data should be stored in a certain buffer.
Slave Address
1
1
0
A3
A2
A1
A0
R/W
Fixed
Hardware Selectable
Figure 5. Slave Address
The last bit of the address byte defines the operation to be performed. When set to logic 1, a read is selected; a
logic 0 selects a write operation.
LED All-Call I2C Bus Address
•
•
•
Default power-up value (ALLCALLADR register): D0h or 1101 000
Programmable through I2C bus (volatile programming)
At power-up, LED All Call I2C bus address is enabled. TLC59116F sends an ACK when D0h (R/W = 0) or
D1h (R/W = 1) is sent by the master.
See Register Definitions for more detail.
NOTE
The default LED all-call I2C bus address (D0h or 1101 000) must not be used as a regular
I2C bus slave address since this address is enabled at power-up. All the TLC59116Fs on
the I2C bus will acknowledge the address if sent by the I2C bus master.
LED Sub-Call I2C Bus Address
•
•
Three different I2C bus addresses can be used
Default power-up values:
–
–
–
SUBADR1 register: D2h or 1101 001
SUBADR2 register: D4h or 1101 010
SUBADR3 register: D8h or 1101 100
•
•
Programmable through I2C bus (volatile programming)
At power-up, sub-call I2C bus address is disabled. TLC59116F does not send an ACK when D2h (R/W = 0) or
D3h (R/W = 1) or D4h (R/W = 0) or D5h (R/W = 1) or D8h (R/W = 0) or D9h (R/W = 1) is sent by the master.
See Register Definitions for more detail.
Copyright © 2009–2011, Texas Instruments Incorporated
9
TLC59116F
SCLS714B –MARCH 2009–REVISED JULY 2011
www.ti.com
NOTE
The default LED Sub Call I2C bus address may be used as a regular I2C bus slave
address as long as the Sub Call addresses are disabled in MODE1 (default).
Software Reset I2C Bus Address
The address shown in Figure 6 is used when a reset of the TLC59116F needs to be performed by the master.
The Software Reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59116F does not
acknowledge the SWRST. See Register Definitions for more detail.
R/W
1
1
0
1
0
1
1
0
The software reset I2C bus address is reserved address and cannot be use as regular I2C bus slave address or as an
LED All-Call or LED Sub-Call address.
Figure 6. Software Reset Address
Control Register
Following the successful acknowledgment of the slave address, LED All Call address or LED Sub Call address,
the bus master will send a byte to the TLC59116F, which will be stored in the Control register. The lowest 5 bits
are used as a pointer to determine which register will be accessed (D[4:0]). The highest three bits are used as
Auto-Increment flag and Auto-Increment options (AI[2:0]).
Auto-Increment
Register Address
Flag
AI2 AI1 AI0 D4 D3 D2 D1 D0
Auto-Increment Options
Figure 7. Control Register
When the Auto-Increment flag is set (AI2 = logic 1), the five low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the registers sequentially. Four
different types of Auto-Increment are possible, depending on AI1 and AI0 values.
Table 1. Auto-Increment Options(1)
AI2
AI1
AI0
PIN DESCRIPTION
0
0
0
No auto-increment
Auto-increment for all registers. D[4:0] roll over to '0 0000' after the
last register (1 1011) is accessed.
1
1
1
1
0
0
1
1
0
1
0
1
Auto-increment for individual brightness registers only. D[4:0] roll over
to '0 0010' after the last register (1 0001) is accessed.
Auto-increment for global control registers only. D[4:0] roll over to '1
0010' after the last register (1 0011) is accessed.
Auto-increment for individual and global control registers only. D[4:0]
roll over to '0 0010' after the last register (1 0011) is accessed.
(1) Other combinations not shown in Table 1 (AI[2:0] = 001, 010 and 011) are reserved and must not be
used for proper device operation.
10
Copyright © 2009–2011, Texas Instruments Incorporated
TLC59116F
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SCLS714B –MARCH 2009–REVISED JULY 2011
AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C bus
communication, for example, changes the brightness of a single LED. Data is overwritten each time the register
is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the
same I2C bus communication, for example, changing color setting to another color setting.
AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same
I2C bus communication, for example, global brightness or blinking change.
AI[2:0] = 111 is used when individually and global changes must be performed during the same I2C bus
communication, for example, changing color and global brightness at the same time.
Only the five least significant bits (LSBs) D[4:0] are affected by the AI[2:0] bits.
When Control register is written, the register entry point determined by D[4:0] is the first register that will be
addressed (read or write operation), and can be anywhere between 0 0000 and 1 1011 (as defined in ). When
AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment
stops and goes to the next one is determined by AI[2:0]. See for rollover values. For example, if the Control
register = 1111 0100 (F4h), then the register addressing sequence will be (in hex):
14 → … → 1B → 00 → … → 13 → 02 → … → 13 → 02 → … as long as the master keeps sending or reading
data.
R-Green
R-Red
+5V
IN
SHDN
TPS7A4533
+3.3V
R-Blue
GND
SENSE
OUT
...
+3.3V
SCL
SDA
RESET
SCL
SDA
VDD
OUT15
OUT14
OUT13
RESET
A0-A3
TLC59116F
OUT1
OUT0
GND
Figure 8. TLC59116F RGB in a Single Device Typical Application
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TLC59116F
SCLS714B –MARCH 2009–REVISED JULY 2011
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Register Descriptions
Table 2. Register Descriptions
REGISTER
NUMBER (HEX)
NAME
ACCESS(1)
FUNCTION
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
MODE1
MODE2
PWM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode register 1
Mode register 2
Brightness control LED0
Brightness control LED1
Brightness control LED2
Brightness control LED3
Brightness control LED4
Brightness control LED5
Brightness control LED6
Brightness control LED7
Brightness control LED8
Brightness control LED9
Brightness control LED10
Brightness control LED11
Brightness control LED12
Brightness control LED13
Brightness control LED14
Brightness control LED15
Group duty cycle control
Group frequency
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
PWM14
PWM15
GRPPWM
GRPFREQ
LEDOUT0
LEDOUT1
LEDOUT2
LEDOUT3
SUBADR1
SUBADR2
SUBADR3
ALLCALLADR
LED output state 0
LED output state 1
LED output state 2
LED output state 3
I2C bus sub-address 1
I2C bus sub-address 2
I2C bus sub-address 3
LED All Call I2C bus address
(1) R = read, W = write
12
Copyright © 2009–2011, Texas Instruments Incorporated
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Mode Register 1 (MODE1)
Table 3. MODE1 – Mode Register 1 (Address 00h) Bit Description
BIT
SYMBOL
ACCESS(1)
VALUE
0(2)
1
DESCRIPTION
Register auto-increment disabled
7
AI2
R
Register auto-increment enabled
Auto-increment bit 1 = 0
Auto-increment bit 1 = 1
Auto-increment bit 0 = 0
Auto-increment bit 0 = 1
Normal mode(3)
0(2)
6
5
4
3
2
1
0
AI1
AI0
R
1
0(2)
1
R
0
SLEEP
SUB1
SUB2
SUB3
ALLCALL
R/W
R/W
R/W
R/W
R/W
1(2)
0(2)
1
Low-power mode. Oscillator off.
(4)
TLC59116F does not respond to I2C bus sub-address 1.
TLC59116F responds to I2C bus sub-address 1.
TLC59116F does not respond to I2C bus sub-address 2.
TLC59116F responds to I2C bus sub-address 2.
TLC59116F does not respond to I2C bus sub-address 3.
TLC59116F responds to I2C bus sub-address 3.
TLC59116F does not respond to LED all-call I2C bus address.
TLC59116F responds to LED all-call I2C bus address.
0(2)
1
0(2)
1
0
1(2)
(1) R = read, W = write
(2) Default value
(3) It takes 500 µs max for the oscillator to be up and running once SLEEP bit has been set from logic 1 to 0. Timings on LEDn outputs are
not guaranteed if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 500-µs window.
(4) No LED control including ON/OFF, blinking and dimming is possible when oscillator is off. Writing to the register during SLEEP mode
does not affect LED condition. It is needed to set the SLEEP bit to logic 0 when LED condition is required to change.
Mode Register 2 (MODE2)
Table 4. MODE2 – Mode Register 2 (Address 01h) Bit Description
BIT
SYMBOL
ACCESS(1)
VALUE
00(2)
0(2)
DESCRIPTION
7:6
R
Reserved
Group control = dimming
Group control = blinking
Reserved
5
4
DMBLNK
R/W
R
1
0(2)
0(2)
Outputs change on STOP command(3)
Outputs change on ACK
Reserved
3
OCH
R/W
R
1
2:0
000(2)
(1) R = read, W = write
(2) Default value
(3) Change of the outputs at the STOP command allows synchronizing outputs of more than one TLC59116F. Applicable to registers from
02h (PWM0) to 17h (LEDOUT) only.
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Individual Brightness Control (PWM0–PWM15) Registers
Table 5. PWM0–PWM15 – Individual Brightness Control Registers (Address 02h to 11h) Bit Description
ADDRESS REGISTER
BIT
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
SYMBOL
IDC0[7:0]
IDC1[7:0]
IDC2[7:0]
IDC3[7:0]
IDC4[7:0]
IDC5[7:0]
IDC6[7:0]
IDC7[7:0]
IDC8[7:0]
IDC9[7:0]
IDC10[7:0]
IDC11[7:0]
IDC12[7:0]
IDC13[7:0]
IDC14[7:0]
IDC15[7:0]
ACCESS(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE(2)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
DESCRIPTION
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
PWM14
PWM15
PWM0 individual duty cycle
PWM1 individual duty cycle
PWM2 individual duty cycle
PWM3 individual duty cycle
PWM4 individual duty cycle
PWM5 individual duty cycle
PWM6 individual duty cycle
PWM7 individual duty cycle
PWM8 individual duty cycle
PWM9 individual duty cycle
PWM10 individual duty cycle
PWM11 individual duty cycle
PWM12 individual duty cycle
PWM13 individual duty cycle
PWM14 individual duty cycle
PWM15 individual duty cycle
(1) R = read, W = write
(2) Default value
A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from
00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable
to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers).
IDCx[7:0]
Duty cycle =
256
Group Duty Cycle Control (GRPPWM) Register
Table 6. GRPPWM – Group Duty Cycle Control Register (Address 12h) Bit Description
ADDRESS REGISTER
12h GRPPWM
BIT
SYMBOL
ACCESS(1)
VALUE(2)
DESCRIPTION
7:0
GDC0[7:0]
R/W
1111 1111
GRPPWM register
(1) R = read, W = write
(2) Default value
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed frequency signal is
superimposed wit the 97 kHz individual brightness control signal. GRPPWM is then used as a global brightness
control allowing the LED outputs to be dimmed with the same value.
NOTE
The value in GRPFREQ has to be programmed to 00h when DMBLNK = 0.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED
output off) to FFh (99.6% duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx
= 11 (LEDOUT0 to LEDOUT3 registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking
pattern, where GRPFREQ contains the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle
(ON/OFF ratio in percentages).
14
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GDC[7:0]
256
Duty cycle =
Group Frequency (GRPFREQ) Register
Table 7. GRPFREQ – Group Frequency Register (Address 13h) Bit Description
ADDRESS REGISTER
13h GRPFREQ
BIT
SYMBOL
ACCESS(1)
VALUE(2)
DESCRIPTION
7:0
GFRQ[7:0]
R/W
0000 0000
GRPFREQ register
(1) R = read, W = write
(2) Default value
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1.
NOTE
The value in GRPFREQ must be programmed to 00h when DMBLNK = 0.
Applicable to LED output programmed with LDRx = 11 (LEDOUT0 to LEDOUT3 registers). Blinking period is
controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).
GFRQ[7:0] + 1
Global blinking period =
(s)
24
LED Driver Output State (LEDOUT0–LEDOUT3) Register
Table 8. LEDOUT0–LEDOUT3 – LED Driver Output State Registers (Address 14h–17h) Bit Description
ADDRESS REGISTER
BIT
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
SYMBOL
LDR3[1:0]
LDR2[1:0]
LDR1[1:0]
LDR0[1:0]
LDR7[1:0]
LDR6[1:0]
LDR5[1:0]
LDR4[1:0]
LDR11[1:0]
LDR10[1:0]
LDR9[1:0]
LDR8[1:0]
LDR15[1:0]
LDR14[1:0]
LDR13[1:0]
LDR12[1:0]
ACCESS(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE(2)
DESCRIPTION
00
LED3 output state control
LED2 output state control
LED1 output state control
LED0 output state control
LED7 output state control
LED6 output state control
LED5 output state control
LED4 output state control
LED11 output state control
LED10 output state control
LED9 output state control
LED8 output state control
LED15 output state control
LED14 output state control
LED13 output state control
LED12 output state control
00
14h
15h
16h
17h
LEDOUT0
LEDOUT1
LEDOUT2
LEDOUT3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
(1) R = read, W = write
(2) Default value
LDRx = 00 : LED driver x is off (default power-up state).
LDRx = 01 : LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx = 10 : LED driver x is individual brightness can be controlled through its PWMx register.
LDRx = 11 : LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx
register and the GRPPWM registers.
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I2C Bus Sub-Address 1 to 3 (SUBADR1–SUBADR3) Register
Table 9. SUBADR1–SUBADR3 – I2C Bus Sub-Address Registers (Address 18h–1Ah) Bit Description
ADDRESS REGISTER
BIT
7:5
4:1
0
SYMBOL
A1[7:5]
A1[4:1]
A1[0]
ACCESS(1)
VALUE(2)
110
1001
0
DESCRIPTION
R
R/W
R
18h
19h
1Ah
SUBADR1
SUBADR2
SUBADR3
I2C bus sub-address 1
7:5
4:1
0
A2[7:5]
A2[4:1]
A2[0]
R
110
1010
0
R/W
R
I2C bus sub-address 2
I2C bus sub-address 3
7:5
4:1
0
A3[7:5]
A31[4:1]
A3[0]
R
110
1100
0
R/W
R
(1) R = read, W = write
(2) Default value
Sub-addresses are programmable through the I2C bus. Default power-up values are D2h, D4h, D8h and the
device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1
register is equal to 0).
Once sub-addresses have been programmed to their right values, SUBx bits need to be set to 1 in order to have
the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I2C bus sub-address are valid. The LSB in SUBADRx register is a read-only
bit (0).
When SUBx is set to 1, the corresponding I2C bus sub-address can be used during either an I2C bus read or
write sequence.
LED All-Call I2C Bus Address (ALLCALLADR) Register
Table 10. ALLCALLADR – All-Call I2C Bus Address Register (Address 1Bh) Bit Description
ADDRESS REGISTER
BIT
7:5
4:1
0
SYMBOL
AC[7:5]
AC[4:1]
AC[0]
ACCESS(1)
VALUE(2)
DESCRIPTION
R
R/W
R
110
ALLCALLA
1Bh
DR
1000
0
ALLCALLADR I2C bus address register
(1) R = read, W = write
(2) Default value
The LED All Call I2C bus address allows all the TLC59116Fs in the bus to be programmed at the same time
(ALLCALL bit in register MODE1 must be equal to 1 (power-up default state)). This address is programmable
through the I2C bus and can be used during either an I2C bus read or write sequence. The register address can
also be programmed as a Sub Call.
Only the 7 MSBs representing the All Call I2C bus address are valid. The LSB in ALLCALLADR register is a
read-only bit (0).
If ALLCALL bit = 0 (MODE1), the device does not acknowledge the address programmed in register
ALLCALLADR.
Power-On Reset
When power is applied to VCC, an internal power-on reset holds the TLC59116F in a reset condition until VCC
reaches VPOR. At this point, the reset condition is released and the TLC59116F registers and I2C bus state
machine are initialized to their default states causing all the channels to be deselected. Thereafter, VCC must be
lowered below 0.2 V to reset the device.
16
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External Reset
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TLC59116F registers and
I2C state machine will be held in their default state until the RESET input is once again high.
This input requires a pullup resistor to VCC if no active connection is used.
Software Reset
The software reset call (SWRST Call) allows all the devices in the I2C bus to be reset to the power-up state value
through a specific formatted I2C bus command. To be performed correctly, it implies that the I2C bus is functional
and that there is no device hanging the bus.
The SWRST Call function is defined as the following:
1. A START command is sent by the I2C bus master.
2. The reserved SWRST I2C bus address '1101 011' with the R/W bit set to '0' (write) is sent by the I2C bus
master.
3. The TLC59116F device(s) acknowledge(s) after seeing the SWRST Call address '1101 0110' (D6h) only. If
the R/W bit is set to '1' (read), no acknowledge is returned to the I2C bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends 2 bytes with 2 specific
values (SWRST data byte 1 and byte 2):
(a) Byte1 = A5h: the TLC59116F acknowledges this value only. If byte 1 is not equal to A5h, the TLC59116F
does not acknowledge it.
(b) Byte 2 = 5Ah: the TLC59116F acknowledges this value only. If byte 2 is not equal to 5Ah, the
TLC59116F does not acknowledge it.
If more than 2 bytes of data are sent, the TLC59116F does not acknowledge any more.
5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged,
the master sends a STOP command to end the SWRST Call: the TLC59116F then resets to the default
value (power-up value) and is ready to be addressed again within the specified bus free time (tBUF).
The I2C bus master must interpret a non-acknowledge from the TLC59116F (at any time) as a 'SWRST Call
Abort'. The TLC59116F does not initiate a reset of its registers. This happens only when the format of the
START Call sequence is not correct.
Individual Brightness Control With Group Dimming/Blinking
A 97-kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually
the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED
outputs):
•
A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a
global brightness control.
•
A programmable frequency signal from 24 Hz to 1/10.73 s (8 bits, 256 steps) is used to provide a global
blinking control.
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508
508
510
512 508
508
510
511
512
1
2
3
4
5
6
7
8
9
10 11 12
507
511 507
1
2
3
4
5
6
7
8
9 10 11
N X 40 ns with
N = (0 to 255)
(PWMx Register)
M X 256 X 2 X 40 ns
with M = (0 to 255)
(GRPPWM Register)
256 X 40 ns = 10.24 µs
(97.6 kHz)
Group Dimming Signal
256 X 2 X 256 X 40 ns = 5.24 ms (190.7 Hz)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Resulting Brightness + Group Dimming Signal
A. Minimum pulse width for LEDn brightness control is 40 ns.
B. Minimum pulse width for group dimming is 20.48 µs.
C. When M = 1 (GRPPWM register value), the resulting LEDn brightness control and group dimming signal will have two
pulses of the LED brightness control signal (pulse width = N × 40 ns, with N defined in the PWMx register).
D. The resulting brightness plus group dimming signal shown above demonstrate a resulting control signal with M = 4 (8
pulses).
Figure 9. Brightness and Group Dimming Signals
Characteristics of the I2C Bus
The I2C bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not
busy.
Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see
Figure 10).
SDA
SCL
Data line stable;
data valid
Change of
data
allowed
Figure 10. Bit Transfer
18
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TLC59116F
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START and STOP Conditions
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the START condition (S). A low-to-high transition of the data line while the clock is
high is defined as the STOP condition (P) (see Figure 11).
SDA
SCL
SDA
SCL
P
S
START Condition
STOP Condition
Figure 11. Definition of START and STOP Conditions
System Configuration
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master and the devices controlled by the master are the slaves (see Figure 12).
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
I2C BUS
TRANSMITTER/
RECEIVER
MULTIPLEXER
SLAVE
Figure 12. System Configuration
Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver
is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put
on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and
hold time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable
the master to generate a STOP condition.
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TLC59116F
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Data Output
By Transmitter
Not Acknowledge
Data Output
By Receiver
Acknowledge
SCL From Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
Figure 13. Acknowledge on the I2C Bus
Control Register
Slave Address
S
1
1
0
A3
A2
A1
A0
0
A
X
X
X
D4
D3
D2
D1
D0
A
A
P
Auto-Increment Options
Auto-Increment Flag
STOP
Condition
START Condition
R/W
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Figure 14. Write to a Specific Register
Control Register
MODE1 Register
MODE2 Register
Slave Address
(cont.)
S
1
1
0
A3
A2
A1
A0
0
A
1
0
0
0
0
0
0
0
A
A
A
Auto-Increment on
All Registers
MODE1 Register
Selection
START Condition
R/W
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Auto-Increment On
ALLCALLADR Register
SUBADR3 Register
(cont.)
A
A
P
Acknowledge
From Slave
Acknowledge
From Slave
STOP
Condition
Figure 15. Write to All Registers Using the Auto-Increment Feature
20
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Control Register
PWM0 Register
PWM1 Register
Slave Address
(cont.)
A6
A5
A3
A0
0
1
0
0
S
A4
A2
A1
A
1
0
0
0
1
A
A
A
Auto-Increment on
Brightness Registers
Only
PWM Register
Selection
START Condition
R/W
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Auto-Increment On
PWM15 Register
PWM0 Register
PWMx Register
PWM14 Register
(cont.)
A
A
A
A
P
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
STOP
Condition
Figure 16. Multiple Writes to Individual Brightness Registers Only Using the Auto-Increment Feature
Control Register
Slave Address
Data from MODE1 Register
Slave Address
(cont.)
A6
S
A6
A5
A4
A3
A2
A1
A0
0
A
1
0
0
0
0
0
0
0
A
Sr
A5
A4
A3
A2
A1
A0
1
A
A
Auto-Increment
on All Registers
MODE1Register
Selection
Acknowledge
From Master
START Condition
R/W
Repeated Start
R/W
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Auto-Increment On
Data from PWM0 Register
Data from ALLCALLADR Register
Data from MODE1 Register
Data from MODE2 Register
(cont.)
(cont.)
A
A
A
A
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
Data from Last Read Byte
(cont.)
P
A
Not Acknowledge
From Master
STOP
Condition
Figure 17. Read All Registers With the Auto-Increment Feature
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TLC59116F
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New LED All-Call I2C Address(B)
Control Register
Slave Address
Sequence A
S
A6 A5
A4
A3 A2 A1 A0
0
A
X
X
X
1
1
0
1
1
A
1
1
0
1
1
0
1
X
A
P
ALLCALLADR
Register Selection
Acknowledge
From Slave
START Condition
R/W
Acknowledge
From Slave
Acknowledge
From Slave
STOP
Condition
Auto-Increment Flag
The 16 LEDs are ON at Acknowledge
LEDOUT0 Register (LED0–LED3 Fully ON)(C)
LED All-Call I2C Address
Control Register
Sequence B
S
1
1
0
1
1
0
1
0
A
X
X
X
1
0
1
0
0
A
0
1
0
1
0
1
0
1
A
P
LEDOUT0 Register Selection
Acknowledge
From Slave
START Condition
R/W
Acknowledge
From Slave
Acknowledge
From the 4 Devices
STOP
Condition
Auto-Increment Flag
A. In this example, four TLC59116Fs are used with the same sequence sent to each.
B. ALLCALL bit in MODE1 register is equal to 1 for this example.
C. OCH bit in MODE2 register is equal to 1 for this example.
Figure 18. LED All-Call I2C Bus Address Programming and LED All-Call Sequence Example
22
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SCLS714B –MARCH 2009–REVISED JULY 2011
REVISION HISTORY
Changes from Revision A (June 2010) to Revision B
Page
•
Changed QFN PIN NO. to fix pin assignment typo. ............................................................................................................. 4
Copyright © 2009–2011, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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8-Jul-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLC59116FIPWR
TLC59116FIRHBR
ACTIVE
ACTIVE
TSSOP
QFN
PW
28
32
2000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
RHB
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC59116FIPWR
TLC59116FIRHBR
TSSOP
QFN
PW
28
32
2000
3000
330.0
330.0
16.4
12.4
7.1
5.3
10.4
5.3
1.6
1.5
12.0
8.0
16.0
12.0
Q1
Q2
RHB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC59116FIPWR
TLC59116FIRHBR
TSSOP
QFN
PW
28
32
2000
3000
367.0
367.0
367.0
367.0
38.0
35.0
RHB
Pack Materials-Page 2
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