TLC5954 [TI]
具有全局亮度控制、LED 开路/短路检测功能和省电模式的 48 通道 LED 驱动器;
| 型号： | TLC5954 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有全局亮度控制、LED 开路/短路检测功能和省电模式的 48 通道 LED 驱动器 驱动 驱动器 |
| 文件： | 总46页 (文件大小：1843K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TLC5954
ZHCSCD0 –APRIL 2014
TLC5954 48 通道，恒定电流发光二极管 (LED) 驱动器
具有全局亮度控制，LED 开短路检测和省电模式
1 特性
2 应用范围
1
•
•
48 个恒定灌电流输出通道 具有开关控制功能
电流能力：
•
•
•
LED 视频显示屏
可变消息标志 (VMS)
照明
–
–
32 通道为 34.9mA
16 通道为 24.4mA
3 说明
•
•
•
没有针对电流设置的外部电阻器
TLC5954 是一款 48 通道，恒定灌电流 LED 驱动器。
可通过向内部寄存器写入数据来打开或关闭每条通道。
输出通道 (OUTXn) 被分为三组，每组 16 条通道。 每
个通道组（R，G 和 B）具有 128 步长全局亮度控制
(BC) 功能。 所有 48 个通道的最大电流值可由 8 步长
最大电流控制 (MC) 功能进行设置。 此器件具有两个
错误标志：LED 开路检测 (LOD) 和 LED 短路检测
(LSD)。 错误标志可由串行接口端口读取。 此器件还
有一个省电模式，此模式在所有输出关闭时将总流耗设
定为 7µA（典型值）。
最大电流控制 (MC)：3 位（8 个步长）
针对每个色彩组的全局亮度控制 (BC)：7 位（128
个步长），3 组
•
•
•
LED 电源电压：高达 10V
VCC = 3.0V 至 3.6V
恒定电流精度：
–
通道到通道 = ±1%（典型值），±3%（最大
值）
–
器件到器件 = ±2%（典型值），±4%（最大
值）
•
•
•
•
•
•
•
•
数据传输速率：30MHz
器件信息(1)
消隐脉冲持续时间：40ns（最小值）
LED 开路检测 (LOD)
器件名称
TLC5954
封装
封装尺寸
8mm x 8mm
超薄四方扁平无引线
(VQFN) (56)
LED 短路检测 (LSD)
省电模式 (PSM)：流耗 7µA，高速恢复
欠压闭锁设置缺省数据
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
空白
空白
空白
空白
延迟开关最大限度地减少涌入电流
工作温度范围：-40°C 至 +85°C
应用电路
VLED
+
x48
GND
OUTR0
SIN
OUTB15
SOUT
Input Serial Data
Output Serial Data
VCC
Shift Clock
Data Latch
SCLK
LAT
VCC
TLC5954
BLANK Signal
BLANK
GND
GND
PowerPAD
GND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBVS241
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
目录
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description ................................................ 18
8.4 Device Functional Modes........................................ 23
8.5 Register Maps......................................................... 27
Applications and Implementation ...................... 33
9.1 Application Information............................................ 33
9.2 Typical Application .................................................. 33
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 11
9
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
11.2 Layout Example .................................................... 37
12 器件和文档支持 ..................................................... 38
12.1 器件支持................................................................ 38
12.2 文档支持................................................................ 38
12.3 Trademarks........................................................... 38
12.4 Electrostatic Discharge Caution............................ 38
12.5 Glossary................................................................ 38
13 机械封装和可订购信息 .......................................... 38
7
8
7.1 Pin Equivalent Input and Output Schematic
Diagrams.................................................................. 11
7.2 Test Circuits ............................................................ 11
7.3 Timing Diagrams..................................................... 12
Detailed Description ............................................ 16
4 修订历史记录
日期
修订版本
注释
2014 年 4 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
5 Pin Configuration and Functions
RTQ Package
VQFN-56
(Top View)
56 55 54 53 52 51 50 49
48 47 46 45 44 43
42
GND
OUTR14
OUTG14
OUTB14
OUTR15
OUTG15
OUTB15
1
SOUT
2
3
4
5
6
7
41
40
39
38
37
36
OUTB9
OUTG9
OUTR9
OUTB8
OUTG8
OUTR8
Thermal Pad
(Solder Side, GND Terminal)
OUTR0
OUTG0
8
9
35
34
OUTB7
OUTG7
OUTB0
OUTR1
OUTG1
OUTB1
OUTR2
10
11
12
13
14
33
32
31
30
29
OUTR7
OUTB6
OUTG6
OUTR6
BLANK
15 16 17 18 19 20 21 22
23 24 25 26 27 28
Copyright © 2014, Texas Instruments Incorporated
3
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
Pin Functions
PIN
NAME
NO.
I/O DESCRIPTION
GND
1, 56
—
Ground. All GND pins are connected internally.
Red LED constant-current outputs (OUTRn).
2, 5, 8, 11, 14, 17, 20,
23, 30, 33, 36, 39, 44,
47, 50, 53
OUTR0 to
OUTR15
Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be
applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on
or off control data latch.
O
Green LED constant-current outputs (OUTGn).
3, 6, 9, 12, 15, 18, 21,
24, 31, 34, 37, 40, 45,
48, 51, 54
OUTG0 to
OUTG15
Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be
applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on
or off control data latch.
O
O
I
Blue LED constant-current outputs (OUTBn).
4, 7, 10, 13, 16, 19, 22,
25, 32, 35, 38, 41, 46,
49, 52, 55
OUTB0 to
OUTB15
Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be
applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on
or off control data latch.
Serial data input of the 49-bit common shift register, Schmitt buffer input.
When SIN is high, the LSB is set to 1 for only one SCLK input rising edge. If two SCLK rising edges are input
while SIN is high, then the 49-bit shift register LSB and LSB+1 are set to 1. When SIN is low, the LSB is set to
0 at the SCLK input rising edge.
SIN
26
27
28
Edge-triggered latch, Schmitt buffer input.
The LAT rising edge latches data from the common shift register either into the output on or off data latch or
the maximum current control (MC), brightness control (BC), or function control (FC) data latch. When the
common shift register data are latched into the on or off data latch, data in the common shift register are
simultaneously replaced with SID, which is selected by SIDLD. Refer to the Output On or Off Data Latch and
Status Information Data (SID) sections for more details.
LAT
I
I
Serial data shift clock, Schmitt buffer input.
Data present on SIN are shifted to the 49-bit common shift register LSB with the SCLK rising edge. Data in the
shift register are shifted towards the MSB at each SCLK rising edge. The common shift register MSB appears
on SOUT.
SCLK
Blank all outputs, Schmitt buffer input.
BLANK
29
42
I
When BLANK is high, all constant-current outputs (OUTXn) are forced off. When BLANK is low, all OUTXn are
controlled by the on or off control data in the data latch.
Serial data output of the 49-bit common shift register.
SOUT is connected to the MSB of the register. Data are clocked out at the SCLK rising edge.
SOUT
VCC
O
43
—
—
Power-supply voltage
Thermal pad
Ground. The thermal pad must be connected to GND on the printed circuit board (PCB).
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
4.0
UNIT
VCC
VIN
Supply voltage(2)
V
V
V
Input voltage range
SIN, SCLK, LAT, BLANK
SOUT
VCC + 0.3
VCC + 0.3
VOUT
Output voltage range
OUTR0 to OUTR15, OUTG0 to OUTG15,
OUTB0 to OUTB15
–0.3
11
V
TJ (max)
Operating junction temperature
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to device ground pin.
4
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–55
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
–200
–500
2000
500
V
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
At TA= –40°C to +85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS (VCC = 3 V to 3.6 V)
VCC
Supply voltage
3.0
3.6
10
V
V
OUTR0 to OUTR15, OUTG0 to
OUTG15, OUTB0 to OUTB15
VO
Voltage applied to output
VIH
VIL
IOH
IOL
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
SIN, SCLK, LAT, BLANK
SIN, SCLK, LAT, BLANK
SOUT
0.7 × VCC
GND
VCC
V
V
0.3 × VCC
–2
2
mA
mA
SOUT
Operating free-air temperature
range
TA
TJ
–40
–40
+85
°C
°C
Operating junction temperature
range
+125
AC CHARACTERISTICS (VCC = 3 V to 3.6 V)
fCLK (SCLK)
tWH0
Data shift clock frequency
SCLK
30
MHz
ns
SCLK
10
10
15
60
40
4
tWL0
SCLK
ns
tWH1
Pulse duration
LAT
ns
tWH2
BLANK
ns
tWL2
BLANK
ns
tSU0
SIN to SCLK↑
LAT↓ to SCLK↑
ns
tSU1
20
ns
SCLK↑ resumes normal mode,
BLANK↓, PSMODE bit = 01b
tSU2
12
µs
Setup time
Hold time
LAT↑ for all data latching except all
0s resumes normal mode, BLANK↓,
PSMODE bit = 10b
tSU3
12
µs
tH0
tH1
SCLK↑ to SIN
3
ns
ns
SCLK↑ to LAT↑
10
Copyright © 2014, Texas Instruments Incorporated
5
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
6.4 Thermal Information
TLC5954
RTQ (VQFN)
56 PINS
29.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
16.3
7.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
7.7
RθJCbot
2.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
At TA = –40°C to +85°C and VCC = 3.0 V to 3.6 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
Low-level output voltage
IOH = –2 mA at SOUT
VCC – 0.4
VCC
V
VOL
IOL = 2 mA at SOUT
LODVLT = 000b
0.4
V
VLOD0
VLOD1
VLOD2
VLOD3
VLOD4
VLSD0
VLSD1
VLSD2
IIN
0.15
0.25
0.35
0.45
0.55
0.20
0.30
0.40
0.50
0.60
0.25
0.35
0.45
0.55
0.65
V
LODVLT = 001b, 101b, 110b, 111b
LODVLT = 010b
V
LED open-detection threshold
V
LODVLT = 011b
V
LODVLT = 100b
V
LSDVLT = 00b
0.45 × VCC 0.50 × VCC 0.55 × VCC
0.65 × VCC 0.70 × VCC 0.75 × VCC
0.85 × VCC 0.90 × VCC 0.95 × VCC
V
LED short-detection threshold
Input current
LSDVLT = 01b
V
LSDVLT = 10b, 11b
V
VIN = VCC or GND at SIN, SCLK, LAT, and BLANK
–1
1
μA
SIN, SCLK, LAT = GND, BLANK = VCC, VOUTXn = 1 V,
BCX = 7Fh, MC = 0h (IOUTRn, IOUTGn = 2.9-mA target,
IOUTBn = 2.0-mA target)(1)
ICC0
15
19
mA
SIN, SCLK, LAT = GND, BLANK = VCC, VOUTXn = 1 V,
BCX = 7Fh, MC = 5h (IOUTRn, IOUTGn = 17.4-mA target,
IOUTBn = 12.2-mA target)
ICC1
ICC2
ICC3
ICC4
IOLC0
IOLC1
17.5
17.5
20.5
7
22
22
mA
mA
mA
µA
Supply current (VCC
)
SIN, SCLK, LAT, BLANK = GND, all OUTXn = on,
VOUTXn = 1 V, BCX = 7Fh, MC = 5h
SIN, SCLK, LAT, BLANK = GND, all OUTXn = on,
VOUTXn = 1 V, BCX = 7Fh, MC = 7h (IOUTRn, IOUTGn
34.9-mA target, IOUTBn = 24.4-mA target)
=
25.5
60
In power-save mode, SIN, SCLK, LAT = GND,
BLANK = VCC
All OUTXn = on, VOUTXn = VOUTfix = 1 V, BC = 7Fh,
MC = 7h, at OUTR0 to OUTR15 and OUTG0 to
OUTG15
32.5
22.7
34.9
24.4
37.3
26.1
mA
mA
Constant output current
Output leakage current
All OUTXn = on, VOUTXn = VOUTfix = 1 V, BC = 7Fh,
MC = 7h, at OUTB0 to OUTB15
TJ = +25°C
0.1
0.2
0.5
µA
µA
µA
BLANK = VCC, VOUTXn = VOUTfix
= 10 V, MC = 7h, at OUTXn
IOLKG
TJ = +85°C
TJ = +125°C
Constant-current error
(channel-to-channel)(2)
All OUTXn = on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,
MC = 7h, at same color group (OUTXn)
ΔIOLC0
±1%
±3%
(1) X = R, G, and B. n = 0 to 15.
(2) The deviation of each output in the same color group (OUTRn, OUTGn, OUTBn) from the average of the same OUTXn group constant-
current. Deviation is calculated by the formula:
IOUTXn
- 1
IOUTX0 + IOUTX1 + ... + IOUTX14 + IOUTX15
16
D (%) =
´ 100
, where X = R, G, or B, and n = 0 to 15.
6
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
Electrical Characteristics (continued)
At TA = –40°C to +85°C and VCC = 3.0 V to 3.6 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Constant-current error
(device-to-device)(3)
All OUTXn = on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,
MC = 7h, at same color group (OUTXn)
ΔIOLC1
ΔIOLC2
ΔIOLC3
±0.5%
±3%
All OUTXn = on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,
MC = 7h, at OUTXn
Line regulation(4)
Load regulation(5)
±0.5
±1
±1
±3
%/V
%/V
All OUTXn = on, BCX = 7Fh, VOUTXn = 1 V to 3 V,
VOUTfix = 1 V, MC = 7h, at OUTXn
(3) The deviation of the OUTXn constant-current average from the ideal constant-current value. Deviation is calculated by the formula:
IOUTX0 + IOUTX1 + ... + IOUTX15
- (Ideal Output Current)
16
D (%) =
´ 100
Ideal Output Current
Ideal current is 34.9 mA for OUTRn and OUTGn. Ideal current is 24.4 mA for OUTBn with MC data equal to 7h.
, where X = R, G, or B, and n = 0 to 15.
(4) Line regulation is calculated by the formula:
(IOUTXn at VCC = 3.6 V) - (IOUTXn at VCC = 3.0 V)
D (%/V) =
100
´
IOUTXn at VCC = 3.0 V
3.6 V - 3.0 V
X = R, G, or B. n = 0 to 15.
(5) Load regulation is calculated by the equation:
(IOUTXn at VOUTXn = 3 V) - (IOUTXn at VOUTXn = 1 V)
D (%/V) =
100
´
IOUTXn at VOUTXn = 1 V
3 V - 1 V
, where X = R, G, or B, and n = 0 to 15.
6.6 Switching Characteristics
At TA = –40°C to +85°C, VCC = 3.0 V to 3.6 V, CL = 15 pF, RL = 100 Ω for OUTRn and OUTGn, RL = 150 Ω for OUTBn,
MC = 7h, and VLED = 4.5 V, unless otherwise noted. Typical values at TA = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
2
MAX
5
UNIT
ns
tR0
tR1
tF0
tF1
tD0
tD1
tD2
SOUT
OUTXn, BCX = 7Fh(1)
Rise time
20
2
50
5
ns
SOUT
ns
Fall time
OUTXn, BCX = 7Fh
SCLK↑ to SOUT
20
13
30
30
50
23
60
60
ns
ns
LAT↑ to OUTR0 on to off or OUTR0 off to on, BCX = 7Fh
BLANK↓↑ to OUTR0 on to off or OUTR0 off to on, BCX = 7Fh
ns
ns
Propagation delay(2)
OUTRn on to OUTGn on, OUTGn on to OUTBn on, and OUTBn on to
the next OUTRn on, BCX = 7Fh
tD3
1.5
5
ns
OUTRn off to OUTGn off, OUTGn off to OUTBn off, and OUTBn off to
the next OUTRn off, BCX = 7Fh
tD4
1.5
5
300
35
ns
ns
ns
tD5
LAT↑ to power-save mode by writing data for all OUTXn off
150
OUTXn on or off data = all 1s, BCX = 7Fh, 40-ns BLANK low-level one-
shot pulse input
tON_ERR
Output on-time error(3)
–35
(1) X = R, G, or B. n = 0 to 15.
(2) tD3 (OUTRn on to OUTGn on, OUTGn on to OUTBn on, and OUTBn on to the next OUTRn on) and tD4 (OUTRn off to OUTGn off,
OUTGn off to OUTBn off, and OUTBn off to the next OUTRn off) are calculated by:
tD3 (ns) = (the propagation delay between OUTR0 on to OUTB7 on) / 47 and
tD4 (ns) = (the propagation delay between OUTR0 off to OUTB7 off) / 47.
(3) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low-level pulse duration.
tOUT_ON is the actual on-time of OUTXn.
Copyright © 2014, Texas Instruments Incorporated
7
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
6.7 Typical Characteristics
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
45
35
30
25
20
15
10
5
MC = 0
MC = 1
MC = 2
MC = 3
MC = 4
MC = 5
MC = 6
MC = 7
MC = 1
MC = 2
MC = 3
MC = 4
MC = 5
MC = 6
MC = 7
MC = 8
40
35
30
25
20
15
10
5
0
0
0
0.5
1
1.5
Output Voltage (V)
2
2.5
3
0
0.5
1
1.5
Output Voltage (V)
2
2.5
3
D001
D002
BCR, BCG = 7Fh
BCB = 7Fh
Figure 1. Output Current vs Output Voltage
Figure 2. Output Current vs Output Voltage
(OUTRn, OUTGn)
(OUTBn)
27
26
25
24
23
22
21
38
37
36
35
34
33
32
TA = 25qC
TA = ꢀ40qC
TA = 85qC
TA = 25qC
TA = ꢀ40qC
TA = 85qC
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Voltage (V)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Voltage (V)
1
D003
D004
BCR = BCG = 7Fh
MC = 7
BCB = 7Fh
MC = 7
Figure 3. Output Current vs Output Voltage
Figure 4. Output Current vs Output Voltage
(OUTRn, OUTGn)
(OUTBn)
3
2
3
2
1
1
0
0
-1
-2
-3
-1
-2
-3
Min
Max
Min
Max
0
10
20
30
40
0
10
20
30
40
Output Current (mA)
Output Current (mA)
D005
D006
BCR = 7Fh
MC = 7
BCG = 7Fh
MC = 7
Figure 5. Constant-Current Error vs Output Current
Figure 6. Constant-Current Error vs Output Current
(Channel-to-Channel, OUTRn)
(Channel-to-Channel, OUTGn)
8
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
Typical Characteristics (continued)
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
3
3
2
2
1
1
0
0
-1
-1
-2
-3
-2
Min
Max
Min
Max
-3
0
5
10
15
20
25
30
-40
-20
0
20
40
60
80
100
Output Current (mA)
Ambient Temperature (qC)
D007
D008
BCB = 7Fh
MC = 7
BCR = 7Fh
MC = 7h
Figure 7. Constant-Current Error vs Output Current
Figure 8. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel, OUTBn)
(Channel-to-Channel, OUTRn)
3
3
2
2
1
1
0
0
-1
-2
-3
-1
-2
Min
Max
Min
Max
-3
-40
-40
-20
0
20
40
60
80
100
-20
0
20
40
60
80
100
Ambient Temperature (qC)
Ambient Temperature (qC)
D009
D010
BCG = 7Fh
MC = 7h
BCB = 7Fh
MC = 7
Figure 9. Constant-Current Error vs Ambient Temperature
Figure 10. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel, OUTGn)
(Channel-to-Channel, OUTBn)
40
40
MC = 0
MC = 1
MC = 2
MC = 3
MC = 4
MC = 5
MC = 6
MC = 7
MC = 0
MC = 1
MC = 2
MC = 3
MC = 4
MC = 5
MC = 6
MC = 7
35
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
0
16
32
48
64
80
96
112
128
0
16
32
48
64
80
96
112
128
Brightness Control Data (dec)
Brightness Control Data (dec)
D011
D012
BCR = BCG = 7Fh
BCB = 7Fh
Figure 11. Global Brightness Control Linearity
Figure 12. Global Brightness Control Linearity
(OUTRn, OUTGn)
(OUTBn)
Copyright © 2014, Texas Instruments Incorporated
9
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
Typical Characteristics (continued)
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
25
20
15
10
5
25
20
15
10
5
0
0
0
5
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
100
Red, Green Output Current (mA)
SCLK = 30 MHz
All OUTXn = On
VOUT = 0.8 V
Temperature (qC)
D013
D014
SIN = 15 MHz
MC = 0h to 7h
BCX = 7Fh
BLANK = Low
SIN = 15 MHz
BCX = 7Fh
MC = 5h
All OUTXn = On
SCLK = 30 MHz
BLANK = Low
VOUT = 0.8 V
SOUT = No Load
SOUT = No Load
TA = –40°C to +85°C
Figure 13. Supply Current vs Output Current
Figure 14. Supply Current vs Ambient Temperature
Ch1: BLANK (2V/div)
Ch2: OUTR0 (2V/div)
Ch3: OUTG0 (2V/div)
Ch4: OUTB0 (2V/div)
VCC = 3.3 V
MC = 7h
BCX = 7Fh
VLED = 4.5 V
RL = 100 Ω (OUTRn, OUTGn)
RL = 150 Ω (OUTBn)
CL = 15 pF
BLANK Low Pulse Duration = 40 ns
Figure 15. Constant-Current Output Voltage Waveform
10
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
7 Parameter Measurement Information
7.1 Pin Equivalent Input and Output Schematic Diagrams
VCC
VCC
OUTPUT
INPUT
GND
GND
Figure 16. SIN, SCLK, LAT, BLANK
Figure 17. SOUT
VCC
OUTR0
VCC
(1)
OUTXn
(1)
GND
OUTB15
VOUTXn
VOUTfix
(1) X = R, G, or B. n = 0 to 15.
Figure 18. OUTXn
7.2 Test Circuits
RL
CL
VCC
VCC
VCC
(2)
OUTXn
VCC
VLED
(1)
SOUT
GND
(1)
CL
GND
(1) CL includes measurement probe and jig capacitance.
(2) X = R, G, or B. n = 0 to 15.
(1) CL includes measurement probe and jig capacitance.
Figure 20. Rise and Fall Time Test Circuit for
SOUT
Figure 19. Rise and Fall Time Test Circuit for
OUTXn
VCC
OUTR0
VCC
(1)
OUTXn
(1)
GND
OUTB15
VOUTXn
VOUTfix
(1) X = R, G, or B. n = 0 to 15.
Figure 21. Constant-Current Test Circuit for OUTXn
Copyright © 2014, Texas Instruments Incorporated
11
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
7.3 Timing Diagrams
tWH0, tWL0, tWH1, tWH2, tWL2
VCC
Input(1)
50%
GND
tWH
tWL
tSU0, tSU1, tH0, tH1
VCC
Clock Input(1)
50%
GND
VCC
tSU
tH
Data and Control Input(1)
50%
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 22. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5
:
VCC
Input(1)
50%
GND
tD
tD5
(2)
VOH or VOUTXnH
90%
50%
10%
Output
VOL or VOUTXnL
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
(2) X = R, G, or B. n = 0 to 15.
Figure 23. Output Timing
12
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
Timing Diagrams (continued)
Output on or off data write.
FC, BC, MC data write.
ON ON ON
ON
ON
ON
B15B G15B R15B B14B G14B R14B
MC
1
ON ON
B0B G0B
ON
R0B
MC
2
MC
0
ON
R0A
H
L
H
L
L
H
SIN
t
t
SU0
H0
f
t
CLK(SCLK)
t
WH0
SU1
SCLK
LAT
1
2
3
4
5
6
1
2
3
4
47
48
49
47
48
49
t
t
t
WH1
WL0
H1
t
t
WH2
WL2
SID are not loaded into the common
shift register at the LAT signal rising
time for BC, FC data writes.
BLANK
SID are loaded into the common
shift register at the LAT signal
rising time for on or off data writes.
Common Shift Register Bit 0
(Internal)
ON ON
B14B G14B
ON
ON
ON
B0B G0B R0B
SID
R0B
MC
2
MC
1
MC
0
SID
R0A
ON
ON
B15B G15B R15B
ON
L
H
H
L
L
Common Shift Register Bit 1
(Internal)
BC
R0
MC
2
ON
G0B
SID
G0B
SID
R0B
SID
R0A
ON
ON
ON
B15B G15B R15B B14B
ON
ON ON
R1B B0B
MC
1
SID
G0A
H
L
L
H
Common Shift Register Bit 47
(Internal)
SID
B15A
SID
R0B
SID
SID
G15A R15A B14A G14A
SID SID
SID
SID
ON
G0A R0A B15B
SID SID
B15B G15B
SID
G14B
SID SID
R14A B13A
SID SID
R15B B14B
H
H
On or Off Data Latch
(Internal)
New Data
(OUTBn, OUTGn = All 1s , OUTRn = All 0s)
Old Data
Old Data (B15A to R0A = All 1s)
Global BC, FC Data Latch
(Internal)
New Data
t
, t
t
R0 F0
D0
SID
G0B
SID
B15A
SID SID
G14A R14A
SID SID
G0A R0A
SID
B15B G15B R15B B14B
SID
SID
SID
SID
R0B
SID
SID
SID
G15A R15A B14A
L
t
L
H
SOUT
t
t
(Common shift register bit48)
D2
D2
t
t
R1
D1
F1
D3
t
V
OUTXnH
OFF
V
OUTR0
OUTXnL
ON
t
t
D4
Output current is changed
by BC data changes.
OFF
ON
OUTG0
OUTB0
t
D3
D4
OFF
ON
t
D4
t
D3
OFF
ON
OUTR1
OFF
ON
OUTG7
OUTB7
OFF
ON
(1) X = R, G, or B. n = 0 to 15.
Figure 24. Data Write and OUTXn On or Off Timing Diagram
Copyright © 2014, Texas Instruments Incorporated
13
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
Timing Diagrams (continued)
H
L
SIN
SCLK
1
2
3
1
2
47
48
49
48
49
LAT
t
SU2
H
L
BLANK
PSMODE Bit in
FC Data
(Internal)
01b
(Outputs are not all off.)
On or Off Control
Data Latch
(Internal)
Data are all 0
(outputs are all off).
Data are not all 0 (outputs are not all off).
Old On or Off Data
OFF
OFF
OFF
OUTR0
OUTG0
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OUTB7
Power-Save Mode
(PSM) Status
(Internal)
Normal Mode
Normal Mode
Normal Mode
Power-Save Mode
Normal Mode
t
D5
The measured point is 90% ICC.
ICC
(VCC Current)
Figure 25. Power-Save Mode Timing Diagram (PSMODE = 01b)
14
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
Timing Diagrams (continued)
H
L
SIN
SCLK
1
2
3
47
48
49
1
2
47
48
49
LAT
t
SU3
H
L
BLANK
PSMODE Bit in
FC Data
(Internal)
10b
On or Off Control
Data Latch
(Internal)
New Data Are All 0
(Outputs Are All Off)
Old On or Off Data
(Outputs Are Not All Off)
Data Are Not All 0 (Outputs Are Not All Off)
OFF
OFF
OFF
OFF
OUTR0
OUTG0
ON
ON
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
ON
OUTB7
Power-Save Mode
(PSM) Status
(Internal)
Power-Save
Mode
Normal Mode
Normal Mode
Power-Save Mode
Normal Mode
The measured point is 90% ICC.
t
D5
ICC
(VCC Current)
Figure 26. Power-Save Mode Timing Diagram (PSMODE = 10b)
Copyright © 2014, Texas Instruments Incorporated
15
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TLC5954 is 48-channel, 34.9-mA or 24.4-mA, constant-current LED driver that can control the LED on of off
settings with the BLANK signal for grayscale (GS) control. The minimum 40-ns BLANK signal pulse duration can
be input to generate very short LED on-time.
The device has a 128-step, 7-bit, output current control function termed global brightness control (BC) that can
control each color group output. The BC function can adjust the red, green, and blue LED intensity for true white
with constant-current control. The device contributes higher image quality to LED displays with fine white balance
tuning by using these BLANK pulse durations and MC, BC functions.
The display controller can locate LED lamp failures via the device because the controller can detect LED lamp
failures with the LED open detection (LOD) and LED short detection (LSD) functions. Furthermore, the reliability
of the display can be improved by the LOD and LSD function.
The device maximum constant-current output value can be set by an internal register data function referred to as
maximum current control (MC), instead of the general method of using an external resistor setting. Thus, any
failure modes that occur from the external resistor can be eliminated. One resistor can also be eliminated with
the MC function.
The device constant-current output can drive approximately 17.4 mA at a 0.32-V output voltage and a +25°C
ambient temperature. This voltage is called knee voltage. This 0.32-V, low-knee voltage can contribute to the
design of a lower-power display system.
The total number of LED drivers on one LED display panel can be reduced because 48 LED lamps can be driven
by one LED driver. Therefore, designing fine-pitch LED displays is simplified.
16
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
8.2 Functional Block Diagram
VCC
48-Bit LOD or LSDData
VCC
UVLO
RESET
LSB
MSB
SIN
SOUT
49-Bit Common Shift Register
8
48
0
SCLK
Bits 47-40
bit 48
1
48
LSB
MSB
48
ALLOFF
48-Bit Output On or Off Data Latch
0
47
40
LSB
MSB
2
8-Bit
Decoder
40-Bit MC, BC, FC Data Latch
10110010b
39
0
LAT
33
SIDLD
2
48
2
BLANK
PSMODE
Power-
Save
Control
To All
Analog
Circuits
SID
Holder
On or Off Control with
Output Delay
ALLOFF
RESET
48
21
7
BC
8
7
7
7-Bit Global
BC for OUTRn
7-Bit Global
BC for OUTGn
7-Bit Global
BC for OUTBn
2
MC
3
7
32
7
16
7
48
32-Channel
Constant-Current Sink Driver
16-Channel Constant-
Current Sink Driver
Reference
Current
Control
GND
GND
5
LODVLT, LSDVLT
Detection
Voltage
LED Open Detection (LOD)
LED Short Detection (LSD)
Thermal
Pad
GND
OUTR0
OUTG0
OUTG15
OUTB0
OUTB15
OUTR15
Copyright © 2014, Texas Instruments Incorporated
17
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
8.3 Feature Description
8.3.1 Output Current Calculation
The output current value controlled by MC and BC can be calculated by Equation 1.
BCX
IOUTn (mA) = IOLCMax (mA) ´
0.06 + 0.94 ´
127
where:
•
•
•
•
IOLCMax = the maximum constant-current value for all OUTXn for each color group programmed by MC data,
BCX = the global brightness control value (0h to 7Fh),
X = R, G, or B for the red, green, or blue color group, and
n = 0 to 15.
(1)
Each output sinks the IOLCMax current when they turn on and the global brightness control (BC) data are set to the
maximum value of 7Fh (127d).
8.3.2 Status Information Data (SID)
The status information data (SID) contains the status of the LED open detection (LOD) and LED short detection
(LSD).
When the output on-off data latch is written, the SID selected by the SIDLD bits are loaded into lower 48 bits in
the common shift register at the LAT rising edge after the original data in the common shift register are copied to
the on-off data latch. When the BC and FC data are written, SID data are not loaded to the common shift
register. After SID data are copied into the common shift register, new SID data are not loaded until new data are
written into the common shift register even if a LAT rising edge is input.
When the device resumes normal operation after the power-save mode, a BLANK rising edge must be input after
tSU2 or tSU3 elapses in order to retain correct LOD and LSD data in the SID holder because the SID analog circuit
does not function during power-save mode. The SID load configuration and SID read timing are shown in
Figure 27 and Figure 28, respectively.
Selected SID (48 bits) by SIDLD data in the function control data latch.
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUTB15 OUTG15 OUTR15 OUTB14 OUTG14
Selected
SID for
OUTB1
Selected Selected Selected Selected
SID for
OUTR0
Selected
SID for
OUTG1
SID for
OUTR1
SID for
OUTB0
SID for
OUTG0
Selected SID by FCdata
are loaded to the lower
48 bits of the common
shift register when the
LAT rising edge is input
with 0 MSB data of the
common shift register.
SIN
SCK
Bit 48
(0)
Bit 5
Bit 47
Bit 46
Bit 45
Bit 44
Bit 43
Bit4
Bit 3
SOUT
Bit 2
Bit 1
Bit 0
LSB
MSB
Common Shift Register (49 bits)
Figure 27. SID Load Configuration
18
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
Feature Description (continued)
ON
G0A
ON
R0A
ON
B15B
ON
B15C
ON
ON
G15B R15B B6B
ON
ON
ON
ON
R1B B0B G0B
ON
R0B
ON ON
G15C R15C
L
SIN
L
SCLK
LAT
47
48
49
1
2
3
---
1
2
3
4
5
46
47
48
49
Shift Register
LSB Data
(Internal)
ON
B0A
ON
G0A
ON
R0A
SID
0A
SID
0B
ON
B15B
ON ON
G15B R6B
ON
ON
R1B B0B G0B
ON
ON
B15C
L
L
ON
R0B
Shift Register
LSB +1 Data
(Internal)
SID
1A
ON
G0A
ON ON
B15B G15B
ON
G1B R1B B0B
ON
ON
SID
0A
SID
1B
SID
0B
ON
R1A
ON
B0A
L
L
ON
G0B
Shift Register
MSB-1 Data
(Internal)
ON
B15A
SID
0
SID
47A
SID
47B
SID SID
46A 45A
SID
44A
SID
43A
SID
1A
SID
0A
SID SID
46B 45B
L
L
SID data selected by the SIDLD bit of FC data are loaded into the
common shift register at the LAT rising edge except SIDLD = 00b.
ON
B15B
Shift Register
MSB Data
(Internal)
SID
1
SID
0
SID SID
47A 46A
SID
45A
SID
44A
SID
2A
SID
1A
SID
0A
SID SID
47B 46B
L
L
Output On or Off
Data Latch
(Internal)
New On or Off Data (B15A-R0A)
Old On or Off Data
New On or Off Data (B15B-R0B)
SIDLD in FC
Data Latch
(Internal)
XXb
LOD data are selected when SIDLD = 01h. LSD data are selected when SIDLD is set to 10b.
No SID data are loaded when SIDLD is 00h or 11h.
SID
1
SID
0
SID SID
47A 46A
SID
45A
SID
44A
SID
2A
SID
1A
SID
0A
SID
47B
SID
46B
L
L
SOUT
48-Bit SID Data
BLANK
Selected detector data by SIDLD are held in the SID holder when BLANK is high. The held data are loaded into the common shift register
as SID except when SIDLD is 00h.
SID Holder Data
(Internal)
Detector Data
XXXXh
Detector Data
XXXXh
LOD data go through the SID holder when BLANK is low.
48-Bit LOD or LSD
Circuit Output Data
(Internal)
Detector Data
0000h
Detector
XXXXh
Detector Data
0000h
Detector Data
XXXXh
The detector data are not stable immediately after the BLANK signal goes low.
Figure 28. SID Read Timing Diagram
Copyright © 2014, Texas Instruments Incorporated
19
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
Feature Description (continued)
8.3.3 LED Open Detection (LOD)
LOD detects a fault caused by an open circuit in the nth LED string, or a short from OUTXn to ground with low
impedance, by comparing the OUTXn voltage to the LOD detection threshold voltage level set by LODVLT in the
function control data latch (see Table 6 and Table 8). If the OUTXn voltage is lower than the programmed
voltage, the corresponding output LOD bit is set to 1 to indicate a shorted LED. Otherwise, the LOD bit is set to
0. LOD data are only valid for outputs that are set to 1 in the output on-off data latch. LOD data are always 0 for
outputs that are set to 0 in the output on-off data latch.
LOD data are stored in a 48-bit register called the SID holder (see the Functional Block Diagram) at the BLANK
rising edge when the SIDLD bits are set to 01b (see Table 7). The loaded LOD data can be read out through the
common shift register as SID data at the SOUT pin. LOD data are not valid for 1 μs after the output is turned on.
If the OUTXn controlled by the BLANK pin is less than 1 µs, the LOD data must be ignored.
When the device resumes operation from power-save mode, all OUTXn can be controlled by the internal on-off
control data and the BLANK level after the setup time (tSU2) elapses. LOD data are valid after the propagation
delay. Figure 29 illustrates an LOD and LSD circuit, Table 1 shows the SID bit settings for LOD and LSD, and
Figure 30 illustrates the LED open-detection operating timing diagram.
VLED
LED Lamp
LSD Data
OUTXn
1 = Error
VLSD
2.9 mA to 34.9 mA (for OUTRn, OUTGn)
2.0 mA to 24.4 mA (for OUTBn)
On or Off
Control
with Maximum BC Data
LOD Data
1 = Error
VLOD
GND
Figure 29. LOD, LSD Circuit
Table 1. LOD, LSD Truth Table
CORRESPONDING BIT
LOD
LSD
IN SID
LED is not open (VOUTXn > VLOD
)
LED is not shorted (VOUTXn ≤ VLSD
)
0
LED is shorted between anode and cathode, or
shorted to higher voltage side (VOUTXn > VLSD
LED is open or shorted to GND (VOUTXn ≤ VLOD
)
1
)
20
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
SIDLD in FC
Data Latch
(Internal)
01b
H
BLANK
L
2 mA to 34.9 mA (for OUTRn, OUTGn),
1.4 mA to 24.4 mA (for OUTBn)
when BC data are maximum.
OUTXn Current
for LED Lighting
0mA
0 mA
48-bit LOD data are not stable for
1 µs after BLANK goes low.
48-Bit LOD
Circuit Output Data
(Internal)
LOD = 0000h
LOD = 0000h
LOD = XXXXh
LOD data go through the SID holder
when BLANK is low.
48-bit data are held in the
SID holder when BLANK is high.
SID Holder Data
(Internal)
LOD = XXXXh
Old data
LAT
48-Bit Output
On or Off Data Latch
(Internal)
Old output on or off data.
New output on or off data.
48-Bit Common
Shift Register
(Internal)
LOD data (XXXXh) are loaded
into the shift register.
Latched in output on or off data.
Figure 30. LOD Operation Timing Diagram
8.3.4 LED Short Detection (LSD)
LSD data detect a fault caused by a shorted LED by comparing the OUTXn voltage to the LSD detection
threshold voltage level set by LSDVLT in the function control data latch (see Table 6 and Table 9). If the OUTXn
voltage is higher than the programmed voltage, the corresponding output LSD bit is set to 1 to indicate a shorted
LED. Otherwise, the LSD bit is set to 0. LSD data are only valid for outputs that are set to 1 in the output on-off
data latch. LSD data are always 0 for outputs that are set to 0 in the output on-off data latch.
LSD data are loaded into a 48-bit register called the SID holder at the BLANK rising edge when the SIDLD bits
are set to 10b (see Table 7). The loaded LSD data can be read out through the common shift register as SID
data at the SOUT pin. LSD data are not valid for 1 μs after the output is turned on. If the OUTXn controlled by
the BLANK pin is less than 1 µs, the LSD data must be ignored.
Copyright © 2014, Texas Instruments Incorporated
21
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
When the device resumes operation from power-save mode, all OUTXn can be controlled by the internal on-off
control data and the BLANK level after the setup time (tSU2) elapses. LSD data are valid after the propagation
delay. Figure 29 illustrates an LOD and LSD circuit and Figure 31 shows LED short-detection operating timing
diagram.
SIDLD in FC
Data Latch
(Internal)
10b
H
BLANK
L
2 mA to 34.9 mA (for OUTRn, OUTGn),
1.4 mA to 24.4 mA (for OUTBn)
when BC data are maximum.
OUTXn Current
for LED Lighting
0 mA
0 mA
48-bit LSD data are not stable for
1 ms after BLANK goes low.
48-Bit LSD
Circuit Output Data
(Internal)
LSD = 0000h
LSD = 0000h
Old Data
LSD = XXXXh
LOD data go through the SID holder
when BLANK is low.
48-bit data are held in the SID holder
when BLANK is high.
SID Holder Data
(Internal)
LSD = XXXXh
LAT
48-Bit Output
On or Off Data
(Internal)
Old output on or off data.
New output on or off data.
48-Bit Common
Shift Register
(Internal)
LSD data (XXXXh) are loaded
into the shift register.
Latched output on or off data.
Figure 31. LSD Operation Timing Diagram
8.3.5 Noise Reduction
Large surge currents may flow through the device and the board on which the device is mounted if all 48 LED
channels turned on simultaneously when BLANK toggles from high to low. These large current surges can
induce detrimental noise and electromagnetic interference (EMI) into other circuits. The device turns on the LED
channels in a series delay to provide a circuit soft-start feature. A small delay circuit is implemented between
each output. When all bits of the on-off data latch are set to 1, each constant-current output turns on in the
following order: OUTR0, OUTG0, OUTB0, OUTR15, OUTG15, OUTB15, OUTR1, OUTG1, OUTB1, OUTR14,
OUTG14, OUTB14, OUTR2, OUTG2, OUTB2, OUTR13, OUTG13, OUTB13, OUTR3, OUTG3, OUTB3,
OUTR12, OUTG12, OUTB12, OUTR4, OUTG4, OUTB4, OUTR11, OUTG11, OUTB11, OUTR5, OUTG5,
OUTB5, OUTR10, OUTG10, OUTB10, OUTR6, OUTG6, OUTB6, OUTR9, OUTG9, OUTB9, OUTR7, OUTG7,
OUTB7, OUTR8, OUTG8, and OUTB8 with a small delay for each OUTXn after BLANK goes low or LAT goes
high, see Figure 24. Both turn-on and turn-off times are delayed.
22
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
8.4 Device Functional Modes
8.4.1 Maximum Constant Sink Current
The maximum output current of each channel (IOLCMax) is programmed by maximum current (MC) data and can
be set by the serial interface.
IOLCMax is the highest current for each output. Each OUTXn sinks IOLCMax current when they turn on with the
global brightness control (BC) data set to the maximum value of 7Fh (127d). MC data are updated when the
same data are written to the MC bits twice. When the device is powered on, the MC data latch is set to 0.
Table 2 shows the characteristics of the constant-current sink versus the MC control data.
Table 2. Maximum Constant-Current Output versus MC
Data
MC DATA
IOLCMax (mA)
OUTRn,
OUTGn
BINARY
DECIMAL
HEX
OUTBn
000 (default)
001
0 (default)
0 (default)
2.9
2.0
3.1
1
2
3
4
5
6
7
1
2
3
4
5
6
7
4.4
010
5.8
4.1
011
8.7
6.1
100
11.6
17.4
23.2
34.9
8.1
101
12.2
16.3
24.4
110
111
8.4.2 Global Brightness Control (BC) Function: Sink Current Control
The device is capable of simultaneously adjusting the output current of each color group (OUTR0 to OUTR15,
OUTG0 to OUTG15, and OUTB0 to OUTB15). This function is called global brightness control (BC). The BC
function allows the global BC data of LEDs connected to the three color groups to be adjusted. All OUTXn can
be adjusted in 128 steps from 6% to 100% of the maximum output current, IOLCMax. The BC data are transmitted
to the device by the serial interface. When BC data change, the output current also changes immediately.
Table 3 shows the BC data versus the constant-current ratio against IOLCMax
.
Table 3. BC Data versus Current Ratio and Set Current Value
BC DATA
OUTPUT CURRENT (mA, typ)
OUTRn, OUTGn OUTBn
MC = 7h MC = 0h
(IOLCMax = 34.9 (IOLCMax = 2.9 (IOLCMax = 24.4 (IOLCMax = 2.0
OUTPUT
CURRENT
RATIO TO
IOLCMax
BINARY
MC = 7h
MC = 0h
MSB
LSB
DECIMAL
HEX
00
(%, typ)
mA)
2.09
2.35
2.61
…
mA)
0.17
0.20
0.22
…
mA)
1.47
1.65
1.83
…
mA)
0.12
0.14
0.15
…
000 0000
000 0001
000 0010
…
0
1
6.0
6.7
01
2
02
7.5
…
…
…
111 1101
111 1110
111 1111
125
126
127
7D
7E
7F
98.5
99.3
100.0
34.4
34.7
34.9
2.86
2.88
2.90
24.1
24.3
24.4
1.96
1.98
2.00
Copyright © 2014, Texas Instruments Incorporated
23
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
8.4.3 Constant-Current Output On or Off Control
When BLANK is low, each OUTXn is controlled by the data in the output on or off data latch. When data
corresponding to an output equal 1, the output turns on; when data corresponding to an output equal 0, the
output turns off. When BLANK is high, all OUTXn are forced off. When the device is powered on, the data in the
output on or off data latch are set to 0. A truth table for the on or off control data is shown in Table 4.
Table 4. On or Off Control Data Truth Table
ON OR OFF CONTROL DATA
CONSTANT-CURRENT OUTPUT STATUS
0 (default)
1
Off
On
8.4.4 Power-Save Mode
The power-save mode control bits are assigned in the BC and FC data latch. The device dissipation current
becomes 7 μA (typ) in this mode. In PSM, all analog circuits (such as the constant-current outputs and the LOD
and LSD circuit) do not function. However, logic circuits (such as the common shift register, on-off data latch, and
BC and FC data latch) do function. When the two bits in PSMODE are 01b, 10b, or 11b, the power-save mode is
enabled. When the two bits are 11b, the device is always in power-save mode. When the two bits are set to 00b,
the device is always in normal operation. If all 0s are written in the output on-off data latch, the device goes into
power-save mode when the two bits are 01b or 10b. When a rising edge is generated at SCLK with the two
PSMODE bits set to 01b, the device exits PSM and returns to normal operation. When data in the output on-off
data latch are not all 0s, and when the two PSMODE bits set to 10b, the device exits PSM and returns to normal
operation. All OUTXn are turned on after the device exits PSM. Figure 32 and Figure 33 provide power-save
mode timing diagrams for PSMODE set to 01b and 10b, respectively. The BLANK level should go low after tSU2
or tSU3 when the device exists PSM and returns to normal mode because the output current may be unstable
immediately after starting normal mode.
24
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
L
L
SIN
SCLK
LAT
49
1
2
49
1
1
2
1
2
49
When the device resumes normal mode, BLANK should be low after
the setup time (for at least t ) from the SCLK rising edge input time
su2
H
for stable output current.
L
BLANK
48-Bit Common
Shift Register
(Internal)
SID = XXXXh
SID = 0000h
SID = XXXXh
Data Are Not 0
SID holder data are loaded to the shift register at the LAT rising edge.
Data Are Not 0
48-Bit Output
On or Off Data
(Internal)
Data Are Not 0
All Data Are 0
L
L
SOUT
ON or OFF
all OFF
ON or OFF
ON or OFF
OUTXn
SIDLD Bit in
FC Data Latch
(Internal)
01b
LOD data are all0because all outputs are off.
LOD = XXXXh
LOD = 0000h
48-Bit LOD
Circuit Output Data
(Internal)
LOD = 0000h
LOD = XXXXh
LOD = XXXXh
48-bit LOD data are not stable
for 1 µs after BLANK goes low.
LOD = XXXXh
SID Holder Data
(Internal)
LOD = 0000h
LOD = XXXXh
LOD = XXXXh
PSMODE Bit in
FC Data Latch
(Internal)
01b
Power-Save
Mode Status
Normal
Mode
Power-Save
Mode
Normal Mode
Normal Mode
more than 1mA
ICC
(VCC Current)
7 µA (typ)
Figure 32. Power-Save Mode (FC Data PSMODE Bits = 01b)
Copyright © 2014, Texas Instruments Incorporated
25
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
L
L
SIN
SCLK
LAT
49
1
2
49
1
1
2
1
2
49
When the device resumes normal mode, BLANK should be low
from the SCLK rising edge
after the setup time for at least t
su3
input time for stable output current.
H
L
BLANK
48-Bit Common
Shift Register
(Internal)
SID = XXXXh
SID = 0000h
SID = XXXXh
Data Are Not 0
SID holder data are loaded to the shift register at the LAT rising edge.
All Data = 0 Data Are Not 0
48-Bit Output
On or Off Data
(Internal)
Data Are Not 0
L
L
SOUT
ON
or OFF
ON or OFF
OUTXn
All OFF
ON or OFF
SIDLD Bit in
FC Data Latch
(Internal)
01b
LOD data are all 0 because all
outputs are off.
LOD = XXXXh
48-Bit LOD
Circuit Output Data
(Internal)
LOD =
XXXXh
LOD = 0000h
LOD = XXXXh
LOD = 0000h
48-bit LOD data are not stable
for 1 ms after BLANK goes low.
LOD = XXXXh
SID Holder Data
(Internal)
LOD =
XXXXh
LOD = 0000h
LOD = XXXXh
PSMODE Bit in
FC Data Latch
(Internal)
10b
Power-Save
Mode Status
Normal Mode
Power-Save Mode
Normal Mode
More than 1 mA
ICC (VCC Current)
7 µA (typ)
Figure 33. Power-Save Mode (FC Data PSMODE Bits = 10b)
26
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
8.5 Register Maps
8.5.1 Register and Data Latch Configuration
The device has one common shift register and four control data latches. These data latches are the output on or
off data latch, the maximum current control (MC) data latch, the global brightness control (BC) data latch, and the
function control (FC) data latch.
The common shift register is 49 bits long, the output on or off data latch is 48 bits long, and another 48-bit data
latch is comprised of the 40-bit MC, BC, and FC data latches with an 8-bit write command decoder. If the
common shift register MSB is 0, the least significant 48 bits of data from the 49-bit common shift register are
latched into the output on or off data latch. If the MSB (bit 48) from the 49-bit common shift register is 1 and MSB
1 through MSB 9 (bits [47:40]) are 96h (10010110b) for the write command data, the middle 37 bits (bits [39:3])
in the common shift register are latched into the BC and FC data latch. MC data are updated when the same
data are written to the MC bits twice with the write command data (96h) and the MSB (bit 48) set to 1. Figure 34
shows the configuration of the common shift register and the four data latches.
Common Shift Register (49 Bits)
LSB
MSB
Common Common Common Common
Data bit
47
Common Common Common Common Common
Data bit
4
Common
Data bit
43
Common
Data bit
0
SIN
Data
Select bit
Data bit Data bit
46 45
Data bit
44
Data bit
5
Data bit
3
Data bit Data bit
1
SOUT
2
SCK
48
47
46 45
44
43
---
3
2
1
0
5
4
48 Bits
This latch pulse is
generated when LAT
rising edge is input
with “0” MSB data of
common shift register
(Data select bit).
48 Bits
Output On or Off Data Latch (48 Bits)
LSB
MSB
48 Bits
OUTB15
On
OUTB1
On
OUTG15 OUTR15 OUTB14 OUTG14
On
OUTG1
On
OUTR1
On
OUTB0
On
OUTG0
On
OUTR0
On
On
On
On
47
46
45
44
43
---
3
2
1
0
5
4
Lower 3 Bits
Higher 8 Bits
Middle 37 Bits
3 Bits
3 Bits
Pre-MC Data Latch
(3 Bits)
The
previous
MC data
Xlat
RESET from UVLO
Xreset
3 Bits
3 Bits
LatMC
3 Bits
MSB
LSB
MSB
LSB
LSB
MSB
MC for
All
FC for SIDLD, LODVLT,
LSDVLT, PSMODE and
7-Bit Reserved Bit
8-Bit Write
Command Decoder,
96h (10010110b)
BC for
OUTB0-15
BC for
OUTG0-15
BC for
OUTR0-15
---
3
Latch
OUTXn
39
---
---
0
47
---
40
24
---
---
9
16
23
17
10
2
BC, FC Data Latch (37 Bits)
MC Data Latch (3 Bits)
This latch pulse is generated when the LATrising edge is input
with the MSB data of thecommon shift register = 1 (data select bit).
Figure 34. Common Shift Register and Data Latch Configuration
Copyright © 2014, Texas Instruments Incorporated
27
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
Register Maps (continued)
8.5.1.1 Common Shift Register
The 49-bit common shift register is used to shift data from the SIN pin into the device. The data shifted into the
register are used for the output on or off control, MC, BC, and several FC functions, and the write command. The
LSB of the common shift register is connected to SIN and the MSB is connected to SOUT. On each SCLK rising
edge, the data on SIN are shifted into the LSB and all 49 bits are shifted towards the MSB. The register MSB is
always connected to SOUT. In addition, the status information data (SID) selected by the SIDLD bits in the FC
data latch are loaded to the lower 48 bits of the 49-bit common shift register when a rising edge is input on LAT
for the output on or off control data write operation except when SIDLD = 00b and 11b (see Table 7). When the
device is powered on, all 49 bits of the common shift register are set to 0.
8.5.1.2 Output On or Off Data Latch
The output on or off data latch is 48 bits long and sets the on or off status for each constant-current output
(OUTRn, OUTGn, OUTBn). When BLANK is low, the output corresponding to the specific bit in the output on or
off data latch is turned on if the data are 1 and remains off if the data are 0. When BLANK is high, all outputs are
forced off, but the data in the latch do not change as long as LAT does not latch in new data. When the MSB of
the common shift register is set to 0, the lower 48 bits are written to the output on or off data latch on the LAT
rising edge. When the device is powered on, all bits in the data latch are set to 0. The output on or off data latch
bit assignment is shown in Table 5. See Figure 35 for an output on or off data write timing diagram.
Table 5. On or Off Control Data Latch Bit Assignment
CONTROL
LED
CONTROL
LED
BIT
BIT
NUMBER
BIT NAME CHANNEL
DESCRIPTION
NUMBER
BIT NAME CHANNEL
DESCRIPTION
0
1
OUTR0ON
OUTG0ON
OUTB0ON
OUTR1ON
OUTG1ON
OUTB1ON
OUTR2ON
OUTG2ON
OUTB2ON
OUTR3ON
OUTG3ON
OUTB3ON
OUTR4ON
OUTG4ON
OUTB4ON
OUTR5ON
OUTG5ON
OUTB5ON
OUTR6ON
OUTG6ON
OUTB6ON
OUTR7ON
OUTG7ON
OUTB7ON
OUTR0
OUTG0
OUTB0
OUTR1
OUTG1
OUTB1
OUTR2
OUTG2
OUTB2
OUTR3
OUTG3
OUTB3
OUTR4
OUTG4
OUTB4
OUTR5
OUTG5
OUTB5
OUTR6
OUTG6
OUTB6
OUTR7
OUTG7
OUTB7
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
OUTR8ON
OUTG8ON
OUTB8ON
OUTR8
OUTG8
2
OUTB8
3
OUTR9ON
OUTG9ON
OUTB9ON
OUTR9
4
OUTG9
5
OUTB9
6
OUTR10ON
OUTG10ON
OUTB10ON
OUTR11ON
OUTG11ON
OUTB11ON
OUTR12ON
OUTG12ON
OUTB12ON
OUTR13ON
OUTG13ON
OUTB13ON
OUTR14ON
OUTG14ON
OUTB14ON
OUTR15ON
OUTG15ON
OUTB15ON
OUTR10
OUTG10
OUTB10
OUTR11
OUTG11
OUTB11
OUTR12
OUTG12
OUTB12
OUTR13
OUTG13
OUTB13
OUTR14
OUTG14
OUTB14
OUTR15
OUTG15
OUTB15
7
8
9
0 = Output off
1 = Output on with
BLANK low.
When the device is
powered on, all bits are
set to 0.
0 = Output off
1 = Output on with
BLANK low.
When the device is
powered on, all bits are
set to 0.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
28
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
Table 6. MC, BC, and FC Data Latch and Write Command Bit Description
DEFAULT
BIT
BIT
VALUE
NUMBER
NAME
(BINARY)
DESCRIPTION
Maximum current control (MC) data for all OUTXn
(data = 0h to 7h, see Table 2)
[2:0]
[9:3]
MAXCUR (MC)
BCR (BC)
000b
—
Global brightness control (BC) data for RED color group
(data = 00h to 7Fh, see Table 3)
Global brightness control (BC) data for GREEN color group
(data = 00h to 7Fh, see Table 3)
[16:10]
[23:17]
BCG (BC)
—
Global brightness control (BC) data for BLUE color group
(data = 00h to 7Fh, see Table 3)
BCB (BC)
—
SID load control. These two bits select the SID loaded to the common register
when the LAT rising edge is input for on or off data writes. Table 7 shows the
selected data truth table.
[25:24]
[28:26]
[30:29]
SIDLD (FC)
LODVLT (FC)
LSDVLT (FC)
—
—
—
LOD detection voltage select. These three bits select the detection threshold
voltage for the LED open detection (LOD). Table 8 shows the detect voltage
truth table.
LSD detection voltage select. These two bits select the detection threshold
voltage for the LED short detection (LSD). Table 9 shows the detect voltage
truth table.
Power-save mode select. These two bits select the power-save mode between
the four modes. Table 10 shows the power-save mode truth table. Figure 32
and Figure 33 illustrate the power-save mode operation timing diagrams.
[32:31]
[39:33]
[47:40]
PSMODE (FC)
RSV
11b
—
Reserved data, don’t care.
Write command. When this data are 96h (10010110b), MC, BC, and FC data
can be updated. In order to update MC data, the same data must be written
twice to the MC bit.
WRTCMD
—
Table 7. SID Load Control Truth Table
SIDLD
STATUS INFORMATION DATA (SID) LOADED TO THE COMMON SHIFT
BIT 25
BIT 24
REGISTER
0
0
1
1
0
1
0
1
No data are loaded (default value)
LED open detection (LOD) data are loaded
LED short detection (LSD) data are loaded
No data are loaded
Table 8. LOD Threshold Voltage Truth Table
LODVLT
BIT 28
BIT 27
BIT 26
LED OPEN DETECTION (LOD) THRESHOLD VOLTAGE
VLOD0 (0.20 V, typ)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VLOD1 (0.30 V, typ)
VLOD2 (0.40 V, typ)
VLOD3 (0.50 V, typ)
VLOD4 (0.60 V, typ)
VLOD1 (0.30 V, typ)
VLOD1 (0.30 V, typ)
VLOD1 (0.30 V ,typ)
Copyright © 2014, Texas Instruments Incorporated
29
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
Table 9. LSD Threshold Voltage Truth Table
LSDVLT
BIT 30
BIT 29
LED SHORT DETECTION (LSD) THRESHOLD VOLTAGE
0
0
1
1
0
1
0
1
VLSD0 (0.50 × VCC, typ)
VLSD1 (0.70 × VCC, typ)
VLSD2 (0.90 × VCC, typ)
VLSD2 (0.90 × VCC, typ)
Table 10. Power-Save Mode Truth Table
PSMODE
BIT 32
BIT 31
POWER-SAVE MODE FUNCTION
0
0
Power-save mode is disabled in every condition.
When all zeroes (0s) are written to the output on or off data latch, the device goes
to power-save mode. When an SCLK rising edge occurs, the device goes to
normal operation and starts to control the output current. However, after the setup
time (tSU2) elapses from the SCLK input timing, BLANK must go low. Otherwise,
the output current may not reach the set constant-current value. If these two bits
are set to 01b from 10b or 11b when the device is in power-save mode (PSM), the
device remains in PSM and does not resume normal mode. When an SCLK rising
edge is input after PSMODE = 01 is selected, the device returns to normal mode.
0
1
When all zeroes (0s) are written to the output on or off data latch, the device goes
to power-save mode. When the data (except all 0s) are written to the output on or
off data latch, the device goes to normal operation and starts to control the output
current. However, after the setup time (tSU3) elapses from the LAT input timing,
BLANK must go low. Otherwise, the output current may not reach the set constant-
current value. If this bit set is selected from other bit set to this bit set when the
device is in PSM, the device remains in power-save mode. When data that are not
all set to off are written to the on or off data latch after this bit set is selected, the
device goes to normal mode.
1
0
1 (default)
1 (default)
Power-save mode is enabled in every condition.
30
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
ON ON
G15B R15B
ON
B15B
ON
B14B
ON
B15C
ON
R0A
ON
R1B B0B G0B
ON
ON
ON
R0B
ON
ON
G15C R15C B14C G14C
ON
ON
L
L
SIN
SCLK
LAT
1
2
3
4
5
1
2
3
4
5
6
46
47
48
49
Common Shift
Register LSB
(Internal)
SID
0B
SID
0A
ON
R0A
ON
B15B G15B R15B
ON
ON
ON
ON
R1B B0B G0B
ON
ON
G15C
ON
ON
ON
R15C B14C G14C
ON
B15C
L
ON
R0B
Common Shift
Register LSB +1
(Internal)
SID
1A
ON
G0A
SID
0A
ON
ON
ON
G1B R1B B0B
SID
1B
SID
0B
ON ON
R15C B14C
ON ON
B15B G15B
ON
ON
B15C G15C
L
ON
G0B
Common Shift
Register MSB -1
(Internal)
ON SID
B15A 47A
SID
46A
SID
0A
SID SID
46B 45B
SID
44B
SID SID
43B 42B
SID
45A
SID
44A
SID
43A
SID
1A
SID
47B
L
ON
B15B
Common Shift
Register MSB
(Internal)
SID SID
47A 46A
SID
45A
SID
44A
SID
2A
SID
1A
SID
0A
SID SID
47B 46B
SID
45B
SID SID
44B 43B
L
L
Output On or Off
Data Latch
(Internal)
On or Off Data
(B15A-R0A)
On or Off Data (B15B-R0B)
BC data are not changed.
BC Data Latch
(Internal)
SID SID
47A 46A
SID
45A
SID
44A
SID
2A
SID
1A
SID
0A
SID
47B
SID
46B
SID
45B
SID
44B
SID
43B
L
L
SOUT
BLANK
OUTXn(1)
OFF
OFF
OFF
ON
ON
ON
OFF
OUTXn(2)
OUTXn(3)
OUTXn(4)
OFF
ON
ON
OFF
OFF
OFF
ON
OFF
ON
ON
OFF
OFF
ON
(1) On or off latched data are 1.
(2) On or off latched data change from 1 to 0 at the second LAT signal.
(3) On or off latched data change from 0 to 1 at the second LAT signal.
(4) On or off latched data are 0.
Figure 35. Output On or Off Timing Diagram: Data Write and OUTXn Control
Copyright © 2014, Texas Instruments Incorporated
31
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
8.5.1.3 Maximum Current Control (MC), Global Brightness Control (BC), and Function Control (FC) Data
Latch
The MC, BC, and FC data latch (FC contains the PSMODE, LSDVLT, LODVLT, and SIDLD bits) is 40 bits long
and is used to adjust the output current of all OUTXn (OUTRn, OUTGn, OUTBn), to select the status information
data (SID) load data, to select LED open detection (LOD) and LED short detection (LSD) voltage, and to select
the power-save mode (PSM).
Data are latched from the lower 40 bits of the 49-bit common shift register into the MC, BC, and FC data latch at
the LAT rising edge when the MSB of the common shift register is set to 1 and the MSB 1 to MSB 9 bit data (bits
[47:40]) of the common shift register MSB side is 96h (10010110b). However, MC data are only updated when
the same data as the previous written data are written. Table 6 lists the MC, BC, and FC data latch bit
assignment. The MC, BC, and FC data write timing diagram is shown in Figure 36. When the device is powered
on, the MC data latch is set to 000b and the PSMODE bits in the FC data latch are set to 11b.
MC
0A
BC
R0B
MC
2B
MC
1B
MC
0B
L
H
L
L
H
H
L
H
H
L
H
SIN
MC, BC, FC data writes are selected when MSB -1 to MSB-9 bits are 96h (HLLHLHHL).
MC, BC, FC are selected when
the MSB is high.
SCLK
1
2
3
4
5
1
2
3
4
5
6
46
47
48
49
LAT
Common Shift
Register LSB
(Internal)
BC
R0B
MC
2B
MC
1B
MC
0B
MC
0A
H
L
H
H
L
L
L
H
H
L
L
H
L
H
Common Shift
Register LSB +1
(Internal)
MC
1B
MC
1A
MC
0A
MC
0B
BC BC
R1B R0B
MC
2B
H
H
Common Shift
Register MSB-1
(Internal)
MC
1A
MC
0A
H
L
L
H
L
L
L
H
L
L
H
H
H
L
L
L
L
H
H
Common Shift
Register MSB
(Internal)
MC
2A
MC
1A
MC
0A
H
H
H
H
Output On or Off
Data latch
(Internal)
On or off control data are not changed.
MC data in the data latch are updated to new data only when the
same data are written twice with write command.
(MC0B to MC2B data must be the same as MC0A to MC2A).
New MC data
Old MC Data
MC Data Latch
(Internal)
New BC data
Old BC Data
Old FC Data
BC Data Latch
(Internal)
BC and FC data in the data latch are updated to new data when the
MSB of the common shift resistor is 1 and write command bit
(MSB-1 ~ MSB9) is 96h (10010110b).
New FC data
FC Data Latch
(Internal)
MC
2A
MC
1A
MC
0A
H
L
L
H
L
SOUT
H
L
L
H
H
H
Figure 36. Maximum Current Control (MC), Global Brightness Control (BC), and Function Control (FC)
Data Write Timing Diagram
32
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
9 Applications and Implementation
9.1 Application Information
The device is a 48-channel, constant sink current, LED driver. This device is typically connected in series to drive
many LED lamps with only a few controller ports. Output current control data and on or off control data can be
written from the SIN input pin. The on or off timing can be controlled by the BLANK signal. Also, the LED open
and short error flag can be read out from the SOUT output pin.
9.2 Typical Application
In this application, the device VCC and LED lamp anode voltages are supplied from different power supplies.
VLED
¼
¼
¼
¼
¼
¼
¼
¼
OUTR0
SIN
OUTB15
OUTR0
SIN
OUTB15
DATA
SCLK
LAT
SOUT
SOUT
VCC
VCC
SCLK
LAT
SCLK
LAT
Device 1
Device n
VCC
GND
VCC
GND
BLANK
BLANK
BLANK
Controller
PowerPAD
PowerPAD
GND
GND
3
SID Read
Figure 37. Typical Application Circuit (Multiple Daisy-Chained Devices)
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 11. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VCC input voltage range
3.0 V to 3.6 V
LED lamp (VLED) input voltage range
Maximum LED forward voltage (VF) + 0.4 V (knee voltage)
Low level = GND, high level = VCC
SIN, SCLK, LAT, and BLANK voltage range
Copyright © 2014, Texas Instruments Incorporated
33
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
9.2.2 Detailed Design Procedure
9.2.2.1 Step-by-Step Design Procedure
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
•
•
•
•
Maximum output constant-current value for all colors of the LED ramp.
Maximum LED forward voltage (VF).
Current ratio of red, green, and blue LED lamps for the best white balance.
Is the LED open detect (LOD) function used? If so, which detection level (0.20 V, 0.30 V, 0.40 V, 0.50 V, or
0.60 V) is used?
•
Is the LED short detect (LSD) function used? If so, which detection level (50% VCC, 70% VCC, or 90% VCC)
is used?
9.2.2.2 Maximum Current (MC) Data
There are a total of three bits of MC data that set the output current of all constant-current outputs (OUTXn).
Select the MC data to be greater than the target LED ramp current if the output current is reduced white
balanced by the global brightness control data and write the data with other control data.
9.2.2.3 Global Brightness Control (BC) Data
There are a total of three sets of 7-bit BC data for the red, green, and blue LED ramp. Select the BC data for the
best white balance of the red, green, and blue LED ramp and write the data with other control data.
9.2.2.4 On or Off Data
There are a total of 48 bits of on or off data for the on or off control of each output. Select the on or off data of
the LED lamp on or off status control and write the data.
9.2.2.5 Other Control Data
There are a total of 8 bits of control data to set the function mode for the status information data (SID) load
control, LOD voltage setting, LSD voltage setting, and power save mode (PSM) explained in the Device
Functional Modes section. Write the 8-bit control data for the appropriate operation of the display system with MC
and BC data as the control data.
9.2.2.6 Grayscale Control
All constant-current outputs are controlled by the BLANK pin logic level. When BLANK is GND, all constant-
current outputs are turned on except that the output is set to 0 in the 48-bit output on-off data latch. When
BLANK is VCC, all outputs are forced off. The LED lamp grayscale can be controlled by the BLANK low pulse
duration.
34
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
9.2.3 Application Curves
One LED connected to each output. BLANK low pulse duration = 40 ns.
Ch1: VCC (2V/div)
Ch1: VCC (2V/div)
Ch2: VLED (2V/div)
Ch2: VLED (2V/div)
Ch3: Output current of VOUTR0 (10mA/div, RED LED
Ch3: Output current of VOUTG0 (10mA/div, GREEN LED
Ch4: BLANK (2V/div)
Ch4: BLANK (2V/div)
MCX = 5
BCX = 7Fh
VLED = 4.2 V
MCX = 5
BCX = 7Fh
VLED = 4.2 V
VCC = 3.3 V
SIDLD = LODVLT = LSDVLT = PSMODE = 0
VCC = 3.3 V
SIDLD = LODVLT = LSDVLT = PSMODE = 0
Figure 38. OUTR0 Output Current Waveform
Figure 39. OUTG0 Output Current Waveform
Ch1: VCC (2V/div)
Ch2: VLED (2V/div)
Ch3: Output current of VOUTB0 (10mA/div, BLUE LED
Ch4: BLANK (2V/div)
MCX = 5
BCX = 7Fh
VLED = 4.2 V
VCC = 3.3 V
SIDLD = LODVLT = LSDVLT = PSMODE = 0
Figure 40. OUTB0 Output Current Waveform
Copyright © 2014, Texas Instruments Incorporated
35
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
10 Power Supply Recommendations
The VCC power-supply voltage should be well regulated. An electrolytic capacitor must be used to reduce the
voltage ripple to less than 5% of the input voltage. Furthermore, the VLED voltage should be set to the voltage
calculated by Equation 2:
VLED ≥ LED Maximum VF × Number of LED Lamps Connected in Series + 0.4 V (5 mA for MC Data Example)
where:
•
VF = Forward voltage
(2)
Because the total current of the constant-current output is large, some electrolytic capacitors must be used to
prevent the OUTXn pin voltage from dropping lower than the calculated voltage from Equation 2.
11 Layout
11.1 Layout Guidelines
1. The decoupling capacitor should be placed near the VCC and GND pin.
2. The GND pattern should be routed as widely as possible for large GND currents. Maximum GND current is
approximately 1.52 A.
3. The routing between the LED cathode side and the device OUTXn should be routed to be as short and
straight as possible to reduce wire inductance.
4. The PowerPAD should be connected to the GND layer because the pad is connected to GND internally. The
PowerPAD also should be connected to the heat sink layer to reduce device temperature.
36
Copyright © 2014, Texas Instruments Incorporated
TLC5954
www.ti.com.cn
ZHCSCD0 –APRIL 2014
11.2 Layout Example
VIA
Top-Side PCB Pattern
Bottom-Side PCB Pattern
To
To
To
To
PowerPAD
Next Next Next Next
SIN SCLK BLANK LAT
To Next GND
To Next VCC
To Next VLED
SOUT
OUTB9
OUTG9
GND
POWER
OUTR14
OUTG14
OUTB14
OUTR9
OUTB8
OUTG8
OUTR15
OUTG15
OUTB15
OUTR0
OUTR8
OUTB7
OUTG7
OUTG0
OUTB0
OUTR1
OUTR7
OUTB6
OUTG6
OUTR6
OUTG1
OUTB1
OUTR2
BLANK
VLED
SIN
BLANK
GND
VCC
SCLK
LAT
Figure 41. Layout Example
Copyright © 2014, Texas Instruments Incorporated
37
TLC5954
ZHCSCD0 –APRIL 2014
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
要获得 LED 驱动器解决方案，请访问 http://www.ti.com.cn/solution/cn/lighting_signage。
12.2 文档支持
12.2.1 相关文档ꢀ
相关文档如下：
•
《PowerPAD™ 耐热增强型封装应用报告》，SLMA002
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
38
Copyright © 2014, Texas Instruments Incorporated
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
www.ti.com.cn/telecom
数字音频
www.ti.com.cn/audio
www.ti.com.cn/amplifiers
www.ti.com.cn/dataconverters
www.dlp.com
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP® 产品
DSP - 数字信号处理器
时钟和计时器
接口
www.ti.com.cn/computer
www.ti.com/consumer-apps
www.ti.com/energy
www.ti.com.cn/dsp
工业应用
医疗电子
安防应用
汽车电子
视频和影像
www.ti.com.cn/industrial
www.ti.com.cn/medical
www.ti.com.cn/security
www.ti.com.cn/automotive
www.ti.com.cn/video
www.ti.com.cn/clockandtimers
www.ti.com.cn/interface
www.ti.com.cn/logic
逻辑
电源管理
www.ti.com.cn/power
www.ti.com.cn/microcontrollers
www.ti.com.cn/rfidsys
www.ti.com/omap
微控制器 (MCU)
RFID 系统
OMAP应用处理器
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC5954RTQR
TLC5954RTQT
ACTIVE
ACTIVE
QFN
QFN
RTQ
RTQ
56
56
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
TLC5954
TLC5954
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RTQ 56
8 x 8, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224653/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
8.15
7.85
A
B
8.15
7.85
PIN 1 INDEX AREA
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
5.6±0.1
(0.2) TYP
15
28
52X 0.5
14
29
57
4X
6.5
SYMM
5.6±0.1
1
42
0.30
0.18
56X
PIN 1 ID
(OPTIONAL)
43
56
0.1
C A B
C
0.5
0.3
56X
SYMM
0.05
4225369 / A 10/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
(0.78)
(5.6)
8X (1.33)
6X (1.22)
43
56X (0.6)
56
1
42
56X (0.24)
6X (1.22)
8X (1.33)
52X (0.5)
SYMM
(7.8)
(5.6)
57
(R0.05)
TYP
14
29
(Ø0.2) TYP
VIA
15
28
SYMM
LAND PATTERN EXAMPLE
SCALE: 10X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225369 / A 10/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their
locations shown on this view. it is recommended thar vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
(7.8)
8X (0.665)
8X (1.33)
43
56X (0.6)
56
56X (0.24)
1
42
57
8X (1.33)
52X (0.5)
SYMM
(7.8)
8X (0.665)
(R0.05) TYP
16X
(
1.13)
14
29
METAL
TYP
15
28
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
66% PRINTED COVERAGE BY AREA
SCALE: 10X
4225369 / A 10/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
TLC5957RTQR
具有预充电 FET、LED 开路检测和 Caterpillar 消除功能的 48 通道、16 位 ES-PWM LED 驱动器 | RTQ | 56 | -40 to 85
TI
TLC5957RTQT
具有预充电 FET、LED 开路检测和 Caterpillar 消除功能的 48 通道、16 位 ES-PWM LED 驱动器 | RTQ | 56 | -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明