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TLC6C5712-Q1

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

TLC6C5712-Q1 具有 8 位点校正功能的 12 通道全套诊断、恒定灌电流

LED 驱动器

1 特性

3 说明

1

•

适用于汽车电子应用

在汽车仪表板及其他安全性能至关重要的 LED 驱动器

应用中，为了确保 LED 亮度与色温的一致性，针对多

通道 LED 的性能需求日益提升。系统级安全考量因素

要求检测各种故障情况，因此会加深系统的复杂程度。

•

符合 AEC-Q100 标准

–

器件温度等级 1：环境运行温度范围为 -40°C

至 125°C

器件人体放电模式 (HBM) 静电放电 (ESD) 分类

等级 H3A

TLC6C5712-Q1 器件是一款 12 通道恒定灌电流 LED

驱动器。凭借 8 位点校正功能和高精度输出电

流，TLC6C5712-Q1 器件成为校正 LED 亮度和色温变

化的理想解决方案。该器件针对每个组件提供高级保护

和诊断功能，可提升系统级稳定性并简化面向安全的设

计。六个具有可编程映射功能的 PWM 输入支持多种

LED 颜色调光配置并提供高调光比率。具有诊断功能

的 16 位串行外设接口 (SPI) 支持以菊花链方式连接多

个器件并简化系统级设计。

器件组件充电模式 (CDM) ESD 分类等级 C4B

•

12 条功率双扩散金属氧化物半导体 (DMOS) 晶体

管输出通道

–

最大恒定电流高达 75mA，可通过外部电阻进行

编程

–

最高输出电压高达 7V

最高压降电压：

–

50mA 时为 0.75V/通道

75mA 时为 1.2V/通道

器件信息⁽¹⁾

•

出色的输出恒流精度：

器件型号

封装

封装尺寸（标称值）

–

通道间的差异：< ±3%（最大值）

器件间的差异：< ±3%（最大值）

每通道 8 位、256 步长线性点校正

TLC6C5712-Q1

HTSSOP (28)

4.40mm x 9.70mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

典型应用电路原理图

•

支持灵活的外部脉宽调制 (PWM) 调光

3-V to 5.5-V

Supply Voltage

–

6 个具有频率监控功能的 PWM 输入

V_(SUPPLY)

V_CC

通过串行外设接口 (SPI) 实现可编程通道映射

ERR

LATCH

SCK

SENSE

保护和诊断

–

相邻引脚短路检测

OUT0

OUT1

在激活和禁用状态下可检测开路负载、短接至地

以及发光二极管 (LED) 短路

SDI

SDO

–

热预警与热关断

开漏错误报告

V_F

TLC6C5712-Q1

LED 弱电源诊断

PWM0

OUT9

参考电阻开路或短路检测与保护

通过 SPI 寄存器锁定实现内容保护

SPI 完整性诊断的强制错误

OUT10

OUT11

PWM5

IREF

R_(IREF)

•

小型热有效的 28 引脚散热薄型小外形尺寸

(HTSSOP) 封装 PowerPAD™封装

GND

2 应用范围

•

仪表板信号装置指示灯

面板及按钮背光照明

条形图 LED

变速器 PRNDL 档位指示灯

连续转向指示灯

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCO9

TLC6C5712-Q1

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

www.ti.com.cn

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 21

7.5 Register Maps......................................................... 22

Application and Implementation ........................ 55

8.1 Application Information............................................ 55

8.2 Typical Applications ................................................ 55

Power Supply Recommendations...................... 58

1

2

3

4

5

6

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 7

6.7 Switching Characteristics.......................................... 7

6.8 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

8

9

10 Layout................................................................... 58

10.1 Layout Guidelines ................................................. 58

10.2 Layout Example .................................................... 59

11 器件和文档支持 ..................................................... 60

11.1 文档支持................................................................ 60

11.2 社区资源................................................................ 60

11.3 商标....................................................................... 60

11.4 静电放电警告......................................................... 60

11.5 Glossary................................................................ 60

12 机械、封装和可订购信息....................................... 60

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (December 2014) to Revision A

Page

•

已发布完整版数据表 ............................................................................................................................................................... 1

2

TLC6C5712-Q1

www.ti.com.cn

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

5 Pin Configuration and Functions

PWP Package

28-Pin HTSSOP PowerPAD Package

Top View

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

SCK

SDI

GND

V_CC

2

3

LATCH

SDO

IREF

4

PGND

SENSE

OUT11

OUT10

OUT9

5

ERR

6

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

PWM0

PWM1

PWM2

7

Thermal

Pad

8

9

OUT8

10

11

12

13

14

OUT7

OUT6

PWM5

PWM4

PWM3

Pin Functions

I/O

DESCRIPTION

NAME

ERR

NO.

5

O

—

I

Error output, open-drain output, active-low

Device ground

GND

28

26

3

IREF

Connect an external resistor to GND for setting the full-scale current.

Latch enable

LATCH

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

PGND

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

SCK

I

6

O

—

I

Open-drain output

7

Open-drain output

8

Open-drain output

9

Open-drain output

10

11

18

19

20

21

22

23

25

12

13

14

15

16

17

1

Open-drain output

Ground for output power

PWM dimming input 0

PWM dimming input 1

PWM dimming input 2

PWM dimming input 3

PWM dimming input 4

PWM dimming input 5

SPI clock

I

SDI

2

I

Serial-data input

SDO

4

O

I

Serial-data output

SENSE

V_CC

24

27

Sense input (LED supply-voltage monitor)

Power supply

I

3

TLC6C5712-Q1

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range. Voltages referenced with respect to GND (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

–40

MAX

7

UNIT

V_CC

Input voltage

IREF, LATCH, PWMx, SCK, SDI

V_CC

10

V

SENSE

ERR open-drain output

7

Output voltage

Ground

OUTx power DMOS drain-to-source voltage

10

V

SDO

V_CC

0.3

125

150

PGND

V

Operating ambient temperature, T_A

Operating junction temperature, T_J

Storage temperature range, T_stg

°C

–40

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured relative to GND.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011

V

Electrostatic

discharge

V_(ESD)

All pins

V

Corner pins (1, 14, 15, and 28)

±750

(1) AEC Q100-002 indicates HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

V_CC

V_I

Supply input voltage

Input voltage

3

0

5.5

7

V

LATCH, PWMx, SCK, SDI, SDO

ERR, SENSE

V

0

V_O

V_IL

V_IH

T_A

T_J

Output voltage

OUTx for x = 0 to 11

0.5

7

V

Input logic-low voltage

Input logic-high voltage

Ambient operating temperature

Junction operating temperature

LATCH, PWMx, SCK, SDI

0.28 V_CC

0.38 V_CC

–40

0.3 V_CC

0.4 V_CC

0.33 V_CC

0.43 V_CC

125

V

ºC

–40

150

4

TLC6C5712-Q1

www.ti.com.cn

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

6.4 Thermal Information

TLC6C5712-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

28 PINS

39

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

19.5

16.1

0.5

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

15.9

1.7

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

T_A= 25°C, over recommended operating conditions (unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLIES (V_CC, PGND, GND)

V_CC= 5 V, PWM = H, R_REF= 20.5 kΩ

V_CC= 3.3 V

3

2.5

2.6

2.4

4.5

4

I_CC

Supply current

mA

V_(POR-rising)

V_{(POR-falling)}

V_(POR-hyst)

Power-on reset voltage, rising

Power-on reset voltage, falling

POR threshold hysteresis

Rising threshold

2.7

2.5

0.2

2.8

2.6

V

Falling threshold

LOGIC INPUTS (PWMx, SDI, LATCH, SCK)

V_(HYS)

I_lkg

Input logic hysterisis

Input leakage current

PWM pullup resistance

V_CC= 5 V or 3.3 V

V_I= V_CC

0.1 V_CC

150

V

–1

1

µA

kΩ

R_PU

105

230

CONTROL OUTPUTS (ERR, IREF, SDO)

V_(ERR)

ERR pin open-drain voltage drop

I_(ERR)= 4 mA, V_CC= 3.3 V–5 V

V_(ERR)= 5 V

0.1 V_CC

3

V

µA

V

I_lkg(ERR)

V_(IREF)

V_OH(SDO)

V_OL(SDO)

ERR leakage current

IREF voltage

R_(IREF)= 20.5 kΩ

I_(SDO)= –4 mA

1.204

1.229

1.254

SDO output-high voltage

SDO output-low voltage

0.9 V_CC

V

I_(SDO)= 4 mA

0.1 V_CC

V

OUTPUT STAGE (OUTx)

V_(OUTx)= 0.75 V, R_(IREF)= 12.2 kΩ,

Dot correction = 255

50

75

I_(OUTx,max)

Constant output current

mA

V_(OUTx)= 1.2 V, R_(IREF)= 8.13 kΩ,

Dot correction = 255

V_(OUTx)= 0.75 V, R_REF= 12.2 kΩ,

dot correction = 255

I_(OUTx,min)

Minimum current-sink capability

Constant output current

0.15

7.5

0.165

10

0.18

14

mA

V_(OUTx)= 0.75 V, reference fault detected,

Dot correction = 255

I_{(OUTx,default)}

V_CC= 3.3 V, R_(IREF)= 12.2 kΩ, dot correction = 255

V_CC= 5 V, R_(IREF)= 12.2 kΩ, dot correction = 255

V_CC= 5 V, R_(IREF)= 8.13 kΩ, dot correction = 255

0.75

0.5

V_(OUT,min)

Minimum output voltage

V

1.2

V_CC= 5 V, R_(IREF)= 12.2 kΩ, (50-mA maximum output

current)

–0.6

–0.08

–3%

0.6

0.08

3%

Output-current dot-correction

differential nonlinearity

DNL

mA

V_CC= 5 V, R_(IREF)= 61 kΩ, (10-mA maximum output

current)

V_(OUTx)= 0.75 V, R_(IREF)= 12.2 kΩ (50 mA), dot

correction = 255

V_(OUTx)= 0.75 V, R_(IREF)= 20.5 kΩ (30 mA), dot

correction = 255

–3%

3%

Output current absolute error

percentage

ΔI_(OUTx)

V_(OUTx)= 0.75 V, R_(IREF)= 61 kΩ (10 mA), dot

correction = 255

–7.5%

–3%

7.5%

3%

V_(OUTx)= 1.2 V, R_(IREF)= 8.13 kΩ (75 mA), dot

correction = 255

5

TLC6C5712-Q1

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

www.ti.com.cn

Electrical Characteristics (continued)

T_A= 25°C, over recommended operating conditions (unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output current dependency on OUTx V_(OUTx)= 0.75 V, R_(IREF)= 12.2 kΩ (50 mA),

ΔI_{(OUT_VOUT)}

–0.5%

0.5%

voltage

ΔI_{(OUT_VOUT)}= (I_{(OUT_7V)}– I_{(OUT_1V)}/ I_(IDEAL)) × 100

Ratio of output current to IREF

current, K = I_(OUTx)/ I_(IREF)

K_(OUT)

Dot correction = 255

500

mA/mA

[CH_EN_MASKx] = 1, [DIS_OFF_FAULT_DIAG] = 1,

V_(OUTx)= 6.7 V, V_(SENSE)= 7 V, T_A= 125°C

I_lkg(OUTx)

Output leakage current

0.5

10

15

µA

I_lkg(SENSE)

I_{(IREF_octh)}

I_{(IREF_octh,hyst)}

I_{(IREF_scth)}

I_{(IREF_scth,hyst)}

I_{(OUT_PULLUP)}

Leakage current at SENSE pin

V_CC= 0, V_(SENSE)= 5 V

V_CC= 5 V

IREF resistor open-circuit detection

threshold

4.5

IREF resistor open-circuit detection-

threshold hysteresis

V_CC= 5 V

2

µA

IREF resistor short-circuit detection

threshold

V_CC= 5 V

160

260

IREF resistor short-circuit detection-

threshold hysteresis

V_CC= 5 V

20

50

Channel pullup current during

deactivated state

V_CC= 5 V, V_(OUTx)= 1 V

PROTECTION CIRCUITS

Weak LED supply-detection threshold

voltage

V_(WLS)

[WLS_TH] = 0

[WLS_TH] = 1

4.1

2.7

4.2

0.1

4.3

V

V_{(WLS_hyst)}

V_{(WLS_OPT)}

V_{(WLS_hyst_OPT)}

Weak LED supply hysteresis

Weak LED supply detection-threshold

voltage

2.77

0.1

2.85

Weak LED supply hysteresis

Short circuit-to-V_(SENSE)detection

threshold, voltage difference between

V(SENSE) and V(OUTx)

V_{(SC_th)}

0.5

0.7

0.1

0.9

0.3

V

Short circuit-to-V_(SENSE)detection

hysteresis

V_{(SC_hyst)}

V_{(OC_th)}

Open-circuit detection threshold

Open-circuit-detection hysteresis

0.1

0.2

V

V_{(OC_hyst)}

0.05

Thermal-shutdown junction

temperature

T_(TSD)

T_(HYS)

T_(PTW)

150

165

15

ºC

Thermal shutdown or warning

junction temperature hysteresis

Pre-thermal warning junction-

temperature threshold

125

135

150

6

TLC6C5712-Q1

www.ti.com.cn

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

MHz

ns

f_(SCK)

Clock frequency, cascade operation

1

10

t_c(SCK)

SCK cycle time

100

380

50

t_w(LAH), t_w(WLAH)

t_w(CKH), t_w(WCKH)

t_w(CKL), t_w(WCKL)

t_w(SEW), t_w(WDI)

t_su(SEST)

Pulse duration, LATCH

SCK high pulse duration

SCK low pulse duration

SDI high and low pulse duration

SDI setup time prior to SCK rise

SDI hold time after SCK rise

Output rise time (SCK)

Output fall time (SCK)

ns

50

ns

150

75

ns

t_h(SEHD)

75

ns

t_r

50

ns

t_f

ns

6.7 Switching Characteristics

T_A= –40°C to 105°C, V_CC= 3 V to 5.5 V

PARAMETER

TEST CONDITIONS

Cascade operation

MIN

TYP

MAX

UNIT

MHz

ns

f_(SCK)

Clock frequency

10

3000

1000

3000

t_d(LAH)

t_pd(SOH)

t_pd(SOL)

Latch switching delay

SDO propagation delay time (L to H)

SDO propagation delay (H to L)

ns

High to low propagation delay time

(LATCH – OUT)

t_pd(LAOL)

750

3000

ns

Low-to-high propagation delay time

(SCK – LATCH)

t_pd(CKLAH)

t_pd(CKDOH)

t_pd(CKDOHL)

200

Low-to-high propagation delay time

(SCK – SDO)

30

75

High-to-low propagation delay time

(SCK – SDO)

t_r(o)

t_f(o)

Rise time, outputs (OFF) SDO

Fall time, outputs (ON) SDO

50

ns

PWMx falling threshold from 0.4 V_CC

to I_(OUTx)rising threshold 10% of

I_(OUTx,max)

Output delay time from PWMx to

I_(OUTx)

t_{d(PWM_ON)}

0.09

0.13

0.2

0.3

0.8

0.3

µs

PWMx rising threshold from 0.4 V_CC

to I_(OUTx)falling threshold 90% of

I_(OUTx,max)

t_{d(PWM_OFF)}Output delay time PWMx to I_OUTx

Default slew rate, rise time from

10% to 90% current, 30-pF loading

capacitance

t_r

Output rise time

µs

With slow-slew-rate register option,

rise time from 10% to 90% current,

30-pF loading capacitance

Default slew rate, fall time from 90%

to 10% current, 30-pF loading

capacitance

t_f

Output fall time

With slow-slew-rate register option,

fall time from 90% to 10% current,

30-pF loading capacitance

0.8

3

t_(DEG)

Output open or short degllitch time

1

2

µs

Reference open or short deglitch

time

t_{(REF_DEG)}

100

Timer length for PWM edge

detection

t_(PWM)

PWM edge detection timer

17

20

23

ms

7

TLC6C5712-Q1

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

www.ti.com.cn

V_CC

LATCH

40%

0 V

t_d(LAH)

V_(supply)

OUTPUT

50%

OUT0– OUT11

0.5 V

V_CC

SCK

30%

0 V

t_d(SOH)

t_d(SOL)

V_CC

SDO

50%

0 V

图 1. Input Signal Timing Diagram Showing Absolute Minimal Timing

V_CC

LATCH

40%

0 V

t_d(LAH)

V_(supply)

OUTPUT

OUT0– OUT11

50%

0.5 V

V_CC

SCK

30%

0 V

t_d(SOH)

t_d(SOL)

V_CC

SDO

50%

0 V

图 2. Output Signal Delay Time

8

TLC6C5712-Q1

www.ti.com.cn

ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

6.8 Typical Characteristics

100.05%

100%

60

50

40

30

20

10

0

Ratio_CH0

Ratio_CH5

Ratio_CH6

Ratio_CH11

99.95%

99.9%

99.85%

99.8%

99.75%

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

8

V_(OUTx)(V)

D013

D001

V_CC= 3.3 V

R_(IREF)= 12.2 kΩ

T_A= 25ºC

V_CC= 5.5 V

T_A= 25ºC

R_(IREF)= 12.2 kΩ

Dot correction = 255

图 3. Output Current vs Output Voltage

图 4. Output Current Ratio vs Output Voltage

60

50

40

30

20

10

0

55

50

45

40

35

30

25

20

15

10

5

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

0

20

40

60

80

100

120

0

20

40

60

80

100

120

Reference Current (mA)

D002

D003

V_CC= 5.5 V

T_A= 25ºC

Dot correction = 255

V_CC= 5.5 V

T_A= –40ºC

Dot correction = 255

图 5. Output Current vs Reference Current

图 6. Output Current vs Reference Current

55

50

45

40

35

30

25

20

15

10

5

55

50

45

40

35

30

25

20

15

10

5

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

-40èC

25èC

125èC

0

20

40

60

80

100

120

0

20

40

60

80

100

120

Reference Current (mA)

Input Reference Current (mA)

D004

D005

V_CC= 5.5 V

T_A= 125ºC

Dot correction = 255

V_CC= 5.5 V

Channel = IOUT5

Dot correction = 255

图 7. Output Current vs Reference Current

图 8. Output Current vs Reference Current

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Typical Characteristics (接下页)

60

50

40

30

20

10

0

1%

51 mA

46 mA

41 mA

36 mA

31 mA

26 mA

21 mA

16 mA

11 mA

5 mA

0.5%

0

-0.5%

-1%

0 mA

-1.5%

-2%

-40èC Current Error to 25èC

125èC Current Error to 25èC

-2.5%

0

10

20

30

40

50

60

0

1

2

3

4

5

6

7

8

9

10

Output Current (mA)

V_OUT(V)

D006

D007

V_CC= 5.5 V

T_A= 25ºC

Dot correction = 255

V_CC= 5.5 V

T_A= 25ºC

Dot correction = 255

图 9. Output Temperature Error vs Output Current

图 10. Output Current vs Output Voltage

60

50

40

30

20

10

0

60

50

40

30

20

10

0

3 V

5.5 V

0

20

40

60

80

100

120

0

20

40

60

80

100

120

Reference Resistor (kW)

Reference Current (mA)

D008

D009

V_CC= 5.5 V

T_A= 25ºC

V_O= 0.7 V

Dot correction = 255

V_O= 0.7 V

T_A= 25ºC

Dot correction = 255

图 11. Output Current vs Reference Resistor

图 12. Output Current vs Reference Current

60

50

40

30

20

10

0

60

50

40

30

20

10

0

51.4 mA

30.8 mA

10.5 mA

-40èC

25èC

125èC

0

50

100

150

200

250

0

50

100

150

200

250

Dot Correction - Decimal

D010

D011

V_O= 0.7 V

I_O= 51.4 mA

V_O= 0.7 V

T_A= 25ºC

图 13. Output Current vs Dot Correction

图 14. Output Current vs Dot Correction

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7 Detailed Description

7.1 Overview

The TLC6C5712-Q1 device is a 12-channel constant-current-sink LED driver. At the TLC6C5712-Q1 output

stage, 12 regulated current channels provide uniform and constant current for driving LEDs within a wide range

of forward-voltage variations.

Users can adjust output current from 10 mA to 75 mA through an external resistor, R_(IREF), which provides

flexibility in controlling the light intensity of the LEDs. The maximum constant-current value (full-scale range) of

all 12 channels is set by a single external resistor. The current of each individual output can be programmed in

256 linear steps, allowing further calibration. The design of the TLC6C5712-Q1 device supports up to 7 V at the

output ports. The serial communication interface is designed for high-throughput data transmission with

cascaded devices. The device has six PWM input channels and 12 output channels that can be mapped

arbitrarily to any of the 6 PWM inputs.

The TLC6C5712-Q1 device has advanced diagnostics, LED open-load detection, shorted-LED detection, short-

circuit to ground detection, reference resistor open and short protection, PWM input-frequency supervision,

adjacent-pin short diagnostics, thermal pre-warning and thermal protection. LED open-and-short and output

short-to-ground detection is available even when an LED channel is off. The diagnostic functions and errors can

be activated or de-activated individually by functions or channels. Users can configure the open-drain error

output to signalize various types of errors.

7.2 Functional Block Diagram

V_CC

OUT0

OUT1

OUT10 OUT11

IREF

IO Regulator

V_CC

R_(PU)

SENSE

PWM0

Output Driver

and

Error Detection

PWM

MUX

V_CC

R_(PU)

12

PWM5

LATCH

12-Bit Output

Latch

Configuration

Latches

Open-Drain

Error Output

ERR

SPI

and

Control

Logic

SCK

SDI

12

16-Bit Shift

Register

SDO

GND

PGND

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7.3 Feature Description

7.3.1 Power-On Reset (POR)

The device supports two types of POR, start-up or UVLO POR and software POR, with software reset capability.

7.3.1.1 Start-Up or UVLO POR

When power is applied to V_CC, or when V_CCis undervoltage (V_CC< V_(POR)), an internal power-on reset (POR)

holds the TLC6C5712-Q1 device in a reset condition with the following conditions until V_CCreaches VPOR.

During RESET:

•

The device cannot receive data.

The SDO pin is held LOW, so the device cannot transmit data.

The ERR open-drain output is pulled down.

During POR, communication between the controller and the device is lost. Any data transmitted during this

period is lost. The state machine inside the device is undefined. After POR, the reset status is released, the

TLC6C5712-Q1 registers and SPI state machine are re-initialized to default states (see the Default column in 表

2). [POR_ERR_FLAG] is set to HIGH during start-up or UVLO POR.

7.3.1.2 Software POR

A software reset command (<SOFTWARE_POR>) resets all internal register settings to default values. The

command executes on a LATCH rising edge. All fault bits and diagnostic status are cleared and set to their

default values. The <SOFTWARE_POR> command also executes the RESET_STATUS] command. The

[POR_ERR_FLAG] bit in the <READ_STATUS0> register is set to HIGH on a software POR.

7.3.1.3 Reset POR

Either start-up or a UVLO POR or a software POR sets [POR_ERR_FLAG] to HIGH. when the device enters

POR status, the [POR_ERR_FLAG] bit is latched HIGH. To clear the [POR_ERR_FLAG], a RESET_POR

command must be issued.

If [POR_ERR_FLAG] is set either by start-up, UVLO, or software, and the device is not in any UVLO state,

[POR_ERR_FLAG] is latched and does not block any operation.

7.3.1.4 POR Masking

[POR_ERR_FLAG] reporting to the ERR output can be masked by the [POR_MASK] bit. If a POR event happens

when [POR_MASK] is set HIGH, POR events do not trigger the ERR

̅

output, and [POR_ERR_FLAG] is set

HIGH.

POR_MASK

ERR

Start-Up and

UVLO POR

POR_ERROR_FLAG

SOFTWARE_POR

Other Faults

图 15. POR Error Report Topology

See the following addresses in 表 2: 61h, 62h, 63h, and A2h.

7.3.2 Error Feedback

The TLC6C5712-Q1 device supports an active-low open-drain output for error information through the ERR pin

for the MCU error-monitor interrupt. If any FLAG bit is set to HIGH in the <READ_STATUS0> register, and is not

masked by a corresponding mask bit in the <WRITE_ERROR_MASK> register, the ERR pin pulls low to indicate

an ERROR scenario. The MCU should immediately execute the error monitor routine.

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Feature Description (接下页)

7.3.2.1 Recovery From Error

When any fault occurs, all FAULT information can be read in separate FAULT registers, for example,

<READ_OPEN_FAULT0>. When the error condition recovers, the register information is still latched and the

ERR pin remains low until the fault is masked or the RESET_STATUS command has been issued. However, if

the error condition still exists after issuing the RESET_STATUS command, the ERR pin pulls low again and the

corresponding FAULT register is set HIGH.

7.3.2.2 RESET_STATUS Command

The RESET_STATUS command clears all flags in the following registers:

<READ_ADJSHORT0>

<READ_ADJSHORT1>

<READ_SHORT_FAULT0>

<READ_SHORT_FAULT1>

<READ_SHORT_GND_FAULT0>

<READ_SHORT_GND_FAULT1>

<READ_OPEN_FAULT0>

<READ_OPEN_FAULT1>

<READ_PWM_FAULT>

<READ_STATUS0>, excluding the [POR_ERR_FLAG] bit.

As mentioned in the POR section, only the RESET_POR command can clear the [POR_ERR_FLAG] bit.

[POR_ERR_FLAG] bit: Read only (R) bit. HIGH: A POR error has occurred. To reset this flag, issue a

RESET_POR command.

[POR_MASK] bit: Read and write (R/W) bit. HIGH: A POR error is stored in the [POR_ERR_FLAG] bit

and is not reported to ERR.

RESET_POR: A command to reset [POR_ERR_FLAG].

SOFTWARE_POR: A command to generate a POR. It also clears STATUS flags.

See the following addresses in 表 2: 62h, 9Ah through A2h, A8h, and A9h.

7.3.3 PWM Input

The TLC6C5712-Q1 device has six PWM inputs with independently configurable mapping to modulate any of the

12 channels for external PWM dimming. A PWM monitor can be used to supervise PWM input-signal integrity.

7.3.3.1 PWM Dimming

PWM dimming is supported on all 12 channels by six PWM inputs. The input PWMx signal is active-low. Due to

the minimal pulse duration needed for diagnostics, at 200 Hz the minimum achievable duty cycle is 0.1%, or 5 µs

minimal on-time. Similarly, the maximum achievable duty cycle is 99.2%, or 40 µs minimum off-time. The setting

of this boundary allows enough time for diagnostic functions. In the case of 0% or 100% PWM, diagnostics are

not reported.

7.3.3.2 PWM Monitor

Independent rising-edge triggered timers are implemented as PWM monitors for each PWMx input channel.

when the timer length reaches the threshold t_PWM, [PWM_FAULTx] is set to HIGH. If the corresponding masking

register [PWM_FAULT_MASKx] is also set HIGH, the fault is stored in [PWM_FAULTx] and is not reported to the

[ANY_PWM_FAULT_FLAG] register. [ANY_PWM_FAULT_FLAG] is set to HIGH and the ERR pin is pulled LOW

if any of the PWM monitors reported a fault and the mask register [PWM_MASK] is disabled. The PWM rising

edge resets the timer and restarts counting from 0. For 0% or 100% PWM, the [PWM_FAULTx] registers should

be independently masked for each PWMx input via the [PWM_FAULT_MASKx] registers.

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Feature Description (接下页)

PWM_FAULT_MASK x

PWM_MASK

ERR

PWM

Monitor x

PWM_FAULT x

ANY_PWM_

FAULT_FLAG

Other PWM Faults

Other Faults

图 16. PWM Fault Report Topology

After being set HIGH, [PWM_FAULTx] FAULT_PWMx is latched even if the corresponding PWM input toggling

has recovered. The RESET_STATUS command must be issued to clear the [ANY_PWM_FAULT_FLAG] bit.

7.3.3.3 PWM Mapping

Each of the 12 output channels has a 3-bit [PWM_MAP_CH] field to assign to one PWMx input. All output

channels are assigned to PWM0 by default. 表 1 lists the mapping for each PWMx input..

表 1. PWMx Mapping

BIT 2

BIT 1

BIT 0

PWMx

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

7.3.3.4 PWM MAP Register Lock

To avoid unintended modification of the <PWM MAPx> registers, the <PWM MAPx> registers can be locked via

the LOCK_MAP command and unlocked via the UNLOCK_MAP command. For details, see the Register

Protection feature.

See the following addresses in 表 2: 40h through 45h, 60h, 62h, 66h through 68h, 6Ch, A0h through A3h, A6h,

and A7h.

[PWM_MAP_CH] field:

[PWM_FAULT_MASKx] bit:

[PWM_MASK] bit:

R/W. 3 bits. Mapping output channel PWM source to PWMx input.

R/W. Active-high. Mask the PWM fault flag PWMx.

R/W. Active-high. Disable the ANY_PWM_FAULT_FLAG from reporting to

ERR.

[PWM_FAULTx] bit:

R only. Active-high. HIGH: PWM monitor timer has triggered for PWMx.

[ANY_PWM_FAULT_FLAG] bit: R only. Active-high. HIGH: One or more PWMx inputs have triggered the

PWM monitor.

[SLOW_SLEW_RATE] bit:

R/W. Active-high. HIGH: Slow slew rate.

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7.3.4 Constant-Current Output

The TLC6C5712-Q1 device has 12 constant-current output channels. An external resistor, R_(IREF), sets the

maximum current of all channels globally. The current of each channel is individually configurable by

independent 8-bit current digital-to-analog converters to support dot-correction capability, also known as

calibration capability. Dot correction can be used to calibrate out brightness differences introduced by LED bin-to-

bin differences or plastic transmittance variation by software instead of manually selecting matching resistors.

7.3.4.1 Global Current Reference

Maximum channel output current (dot-correction register [OUTPUT_DC_CHx] is set at full range, FFh) is globally

set by reference resistor R_(IREF). The V_(IREF)voltage biases external reference resistor R_(IREF), generating

reference current I_(IREF). I_(IREF)is sensed and amplified by the ratio of K_(OUT)as the maximum output current.

Choose the external resistor R_(IREF)value using 公式 1, based on maximum current I_{(OUT,MAX|DC=255}

.

V_(IREF)

R_(IREF)

=

´K_(OUT)

I_{(OUT)max |Dot Correction = 255}

(1)

7.3.4.2 Current Reference Monitor and Protection

The TLC6C5712-Q1 device implements a current-reference monitor for current-reference resistor open-and-short

diagnostic and protection. The device monitors the current I_(IREF)flowing out of the IREF pin. If I_(IREF)is higher

than I_{(IREF_scth)}, a reference-short condition is asserted, limiting the I_(IREF)output current for short protection. If the

I_(IREF)current is smaller than I_{I(IREF_octh)}, a reference-open condition is asserted.

To maintain output function when the IREF resistor is in a short or open condition, device switches to a fail-safe

current source. In fail-safe mode, the maximum output current is defined as I_{(OUTx_default)}. when the external fault

condition is removed, the external resistor sets the I_(IREF)current.

V

(IREF)

I_(IREF)

=

R_(IREF)

(2)

To avoid switching into default current unintentionally, the device implements a digital deglitch filter on the

reference open and short diagnostics. The filter length is defined as t_{(REF_deg)}. On assertion of the reference

open-or-short fault, the [REF_FAULT_FLAG] bit is set. The [REF_MASK] bit can be used to mask the reference

fault output to the ERR pin. If [REF_MASK] is enabled, a reference fault is not reported to the ERR output. If

[REF_MASK] is enabled, a reference fault is not reported to the ERR output. Clearing the [REF_FAULT_FLAG]

bit requires issuing the RESET_STATUS command.

REF_MASK

ERR

IREF Short

REF_FAULT_FLAG

IREF Open

Other Faults

图 17. Reference Fault Report Topology

7.3.4.3 Channel Activation Control

[CH_ON_MASKx] are the channel activation mask bits which control each channel output ACTIVATED-

DEACTIVATED. Logic LOW stands for channel ACTIVATED status.

DEACTIVTING a channel output does not clear the diagnostics registers.

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7.3.4.4 Individual Dot Correction Control

Each channel has an internal 8-bit linear-current digital-to-analog converter for individual dot correction control.

The 8-bit [OUTPUT_DC_CHx] fields are used to control DAC output current according to 公式 3. Note that the

minimum current is 1 / 256 of I_OUT,MAX. If absolutely zero current is required in some scenarios, the channel can

be disabled by setting the corresponding channel-enable [CH_ON_MASKx] bit HIGH.

Dot Correction +1

I_(OUT)= I_(OUT)max ´

256

(3)

7.3.4.5 Output Slew-Rate Adjustment

To accommodate different slew rate requirements for EMC optimization, the [SLOW_SLEW_RATE] bit is

provided. Setting [SLOW_SLEW_RATE] HIGH makes both the rising and falling times, t_rand t_f, longer.

7.3.4.6 Register Lock

To avoid unintended modification of registers, the [OUTPUT_DC_CHx] fields can be locked with the

LOCK_CORR command and unlocked with the UNLOCK_CORR command. The [CH_ON_MASKx] bits can be

locked with the LOCK_MASK command and unlocked with the UNLOCK_MASK command. For details, see the

Register Protection section.

7.3.4.7 Deactivated-Channel Internal Pullup

To avoid floating outputs on a deactivated channel, optional pullup current to the SENSE node I_{(OUT_PULLUP)}is

provided. The pullup current is disabled by default and can be enabled by setting the [DIS_PULL_UP_CHx] bit

HIGH.

See the following addresses in 表 2: 46h through 43h, 69h, 6Ah, 6Dh, 6Eh, and 86h through 93h.

[OUTPUT_DC_CHx] field: R/W. 8-bit. Dot correction current DAC setting register for channel x.

[CH_ON_MASKx]:

R/W. HIGH: Channel output disabled; LOW: Channel output enabled

7.3.5 Advanced Diagnostics

The TLC6C5712-Q1 device supports a variety of diagnostic features, including:

•

Pre-thermal warning and thermal shutdown protection

LED short-to-supply detection

LED short-to-GND detection

LED open-load detection

Deactivated-channel LED-open or -short detection

Weak-LED-supply detection

Adjacent-pin short detection

Reference resistor open or short detection and protection

PWM frequency monitor

7.3.5.1 Pre-Thermal Warning and Thermal Shutdown Protection

When the junction temperature exceeds the pre-thermal-warning threshold T_(PTW), [PRE_TSD_FLAG] in the

<READ_STATUS0> register is set HIGH to signal the pre-thermal warning. The ERR̅ open-drain output is also

pulled down. The microcontroller should respond to the fault warning and take actions to prevent junction

temperature rising.

If junction temperature continues to rise and exceeds thermal-shutdown threshold T_(TSD), the overtemperature

fault bit [TSD_FLAG] in the <READ_STATUS0> register is set HIGH to signal thermal shutdown, the ERR open-

drain output is also pulled down, and all output channels are turned off for protection.

[PRE_TSD_FLAG] and [TSD_FLAG] are latched when triggered. To clear either of the flags, issue the

RESET_STATUS command.

[TSD_FLAG] is latched after having been set. After the die temperature falls below T_(TSD)– T_(HYS), the LED

outputs are activated using the previous settings without re-initializing.

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The flag bits can be individually masked by [PRE_TSD_MASK] and [TSD_MASK]. [PRE_TSD_MASK] prevents

the ERR open-drain output. [TSD_MASK] prevents the ERR open-drain output and thermal shutdown of all

channels. Even if the faults are masked, the fault status can still be read in the registers.

̅

PRE_TSD_MASK

PRE_TSD_FLAG

TSD_FLAG

ERR

Pre-Thermal

Detector

Thermal Shutdown

Detector

Other Faults

Thermal

Shutdown

TSD_MASK

图 18. Thermal Fault Report Topology

7.3.5.2 LED Short-to-Supply Detection

The device has independent LED short-to-supply detection for each channel. Whether the channel PWM source

is HIGH or LOW, the voltage difference between the SENSE and OUTx pins is monitored.

If an LED short to the supply is detected, the [SHORT_FAULT_CHx] bit of the channel is set HIGH and the

[ANY_SHORT_FLAG] bit is set HIGH The [ANY_SHORT_FLAG] also pulls down the ERR̅ open-drain output.

The LED short-to-supply fault does not disable the corresponding channel output. when the fault condition is

removed, the LED should resume normal operation. Fault conditions are latched in the [SHORT_FAULT_CHx]

bits. To clear the [SHORT_FAULT_CHx] bits, issue the RESET_STATUS command.

The [SHORT_FAULT_CHx] bits can be masked independently for each channel by the [SHORT_MASK_CHx]

bits. when the [SHORT_MASK_CHx] bit of any channel is set HIGH, the short-to-supply fault on the specific

channel is not reported to [ANY_SHORT_FLAG].

7.3.5.3 LED Short-to-GND Detection

The TLC6C5712-Q1 device is able to distinguish an LED short-to-GND condition from an LED open-detection

condition by having an internal pullup current to the SENSE node. The pullup is enabled during the PWM OFF

state or channel-deactivated state.

If an LED short-to-GND is detected, the [SG_FAULT_CHx] bit for the channel is set HIGH, and the

[ANY_SHORT_FLAG] bit is also set HIGH. [ANY_SHORT_FLAG] also pulls down the ERR̅ open-drain output.

An LED short-to-GND fault does not disable the corresponding channel output. when a fault condition is

removed, the LED should resume normal operation. Fault conditions are latched in the [SG_FAULT_CHx] fault

bits. Issue a RESET_STATUS command to clear the [SG_FAULT_CHx] fault bits.

The [SG_FAULT_CHx] channel-fault bits can be masked independently by [SG_MASK_CHx]. when the

[SG_MASK_CHx] bit of any channel is set HIGH, the short-to-GND fault on the specific channel is not reported to

[ANY_SHORT_FLAG].

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SG_MASK_CHx

SG_FAULT_CHx

SHORT_MASK

ERR

ANY_SHORT_FLAG

SHORT_FAULT_CHx

SHORT_MASK_CHx

Other Faults

图 19. Short Fault Report Topology

7.3.5.4 LED Open-Load Detection

The device has independent LED open-load detection for each channel. If an LED open-load condition is

detected, the [OPEN_FAULT_CHx] bit for the channel is set HIGH, and the [ANY_OPEN_FLAG] bit also is set

HIGH. [ANY_OPEN_FLAG] also pulls down the ERR open-drain output.

An LED open-load fault does not disable the corresponding channel output. when a fault condition is removed,

the LED should resume normal operation. Fault conditions are latched in the [OPEN_FAULT_CHx] fault bits.

Issue a RESET_STATUS command to clear the [OPEN_FAULT_CHx] fault bits.

The [OPEN_FAULT_CHx] channel-fault bits can be masked independently by the [OPEN_MASK_CHx] bits.

when the [OPEN_MASK_CHx] bit of any channel is set HIGH, the open-load fault on the specific channel is not

reported to the [ANY_OPEN_FLAG] bit.

[ANY_OPEN_FLAG] is the indicator for open-load detectors. [ANY_OPEN_FLAG] can be masked by

[OPEN_MASK] to avoid pulling down the ERR̅ open-drain output.

OPEN_MASK_CHx

OPEN_FAULT_CHx

OPEN_MASK

ERR

ANY_OPEN_FLAG

Other Channels

Other Faults

图 20. Open Fault Report Topology

7.3.5.5 Deactivated-Channel LED Open or Short Detection

Deactivating a channel by setting [CH_ON_MASKx] automatically enables detection of an off-state LED open

load, short to the supply, or short to GND. If a fault is detected when the pullup is enabled, the respective fault

register is set and the ERR̅ open-drain output is pulled down.

To clear the fault, issue the RESET_STATUS command, the same as for activated-state diagnostics. The fault-

masking mechanism is also the same as for activated-state diagnostics.

If an application allows absolutely no current during the channel disabled state, disable the off-state LED open-

or-short detection feature using the [DIS_OFF_FAULT_DIAG] bit.

There is a provision for pulling each channel up to SENSE to avoid a floating node during off-state. This function

can be enabled by setting the [DIS_PULL_UP_CHx] bit to HIGH. If any [DIS_PULL_UP_CHx] bit is set HIGH, the

[DIS_PULL_UP_FLAG] bit is also set HIGH.

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7.3.5.6 Weak LED Supply (WLS) Detection

The TLC6C5712-Q1 device provides weak-LED-supply detection to avoid reporting false faults due to supply

failure. Implementation of weak-LED-supply detection is by monitoring the V_(SENSE)voltage using the internal

threshold voltage V_(WLS)as a reference.

The default threshold V_(WLS)is set for a 5-V supply. If a 3.3-V LED supply is needed, the threshold voltage can

be tuned to V_{(WLS_OPT)}by setting the [WLS_TH] bit HIGH.

when a fault is detected, the [WLS_FAULT_FLAG] bit is set if the [WLS_MASK] masking bit is not active. The

[WLS_FAULT_FLAG] bit remains latched even if the voltage recovers. To clear the fault, issue the

RESET_STATUS command.

WLS_MASK

ERR

WLS_FAULT_FLAG

Other Faults

图 21. Weak-LED-Supply Fault-Report Topology

7.3.5.6.1 Adjacent-Pin Short Detection

On-demand adjacent-pin short detection is provided. This feature requires off-line diagnostics when the outputs

are disabled. Otherwise, interruptions in normal operation and visual brightness glitches may result.

To start adjacent-pin short detection, set the [ADJ_DIAG_START] bit to HIGH. This bit automatically returns to

LOW when the adjacent pin diagnostic procedure is finished.

After [ADJ_DIAG_START] has been set to HIGH and back to LOW, if any two adjacent pins are shorted, the

[ADJ_FLAG_CHx] bit for the faulty channel is set HIGH. The microcontroller can read [ADJ_FLAG_CHx] to

determine which two adjacent pins are shorted.

Deactivating all the channels by using the [CH_ON_MASKx] bits is suggested before starting adjacent-pin

diagnostics.

when the [ADJ_FLAG_CHx] bit is set, it can only be cleared by issuing the RESET_STATUS command.

7.3.5.6.2 Force Error

To validate the ERR pulldown feedback without a real fault, the [FORCE_ERR] bit is provided to enable an ERR

force-down to simulate a faulty scenario. When [FORCE_ERR] is HIGH, the ERR open-drain output is pulled

down. To clear the fault, issue the RESET_STATUS command.

7.3.5.6.3 Reference Resistor Open and Short Detection

See the Constant-Current Output section.

7.3.5.6.4 PWM Monitor

See the PWM Input section.

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7.3.6 Register Protection

To avoid an unintended change of critical registers, register locking and unlocking functions are provided. when

the registers are locked, they cannot be overwritten until an unlock command is issued. When the registers are

locked, they are still available for reading. Critical registers include:

Dot correction register

PWM mapping register

Masking registers

<WRITE_CORRx>, x = 0–11

<WRITE_MAPx>, x = 0–5

<WRITE_CH_ON_MASK0>

<WRITE_CH_ON_MASK1>

<WRITE_SHORT_MASK0>

<WRITE_SHORT_MASK1>

<WRITE_SHORT_GND_MASK0>

<WRITE_SHORT_GND_MASK1>

<WRITE_OPEN_MASK0>

<WRITE_OPEN_MASK1>

<WRITE_PWM_FAULT_MASK>

<WRITE_ERROR_MASK>

Miscellaneous register

<WRITE_MISC_CMD>

7.3.6.1 Dot Correction Register Lock and Unlock

The <WRITE_CORRx> dot correction register can be locked via the LOCK_CORRcommand. When it is locked,

no data in the <WRITE_CORRx> registers can be altered. To unlock, issue the UNLOCK_CORR command.

7.3.6.2 PWM Mapping Register Lock and Unlock

The <WRITE_MAPx> dot correction register can be locked via the LOCK_MAP command. When it is locked, no

data in the <WRITE_MAPx> registers can be altered. To unlock, issue the UNLOCK_MAP command.

7.3.6.3 Masking Register Lock and Unlock

Masking registers can be locked via LOCK_MASK command. When it is locked, no data in the masking registers

listed in the Register Protection section can be altered. To unlock, issue the UNLOCK_MASK command.

7.3.6.4 Miscellaneous Register Lock and Unlock

Miscellaneous registers can be locked via the LOCK_MISC command. When it is locked, no data in the

miscellaneous register listed in the Register Protection section can be altered. To unlock, issue the

UNLOCK_MISC command.

7.3.6.5 Lock Flag Indication

The status of all lock registers is stored in the [LOCK_CORR_FLAG], [LOCK_MASK_FLAG],

[LOCK_MAP_FLAG] and [LOCK_MISC_FLAG] bits of the <READ_STATUS1> register.

7.3.7 Serial Interface – SPI

The serial port is used to write data to, read diagnostic status from and configure settings of the TLC6C5712-Q1

device by transferring the input data to the desired address. During normal operation, an 8-bit serial address and

8-bit serial data are written into the 16-bit shift register. On an SCK rising-edge input, data is sampled. Data is

shifted on a SCK falling edge and the shift registers advance, converting the 16 most-recent inputs to parallel

signals on the LATCH rising edge.

At the rising edge on the LATCH input, a decoder which controls data transfer between shift and storage

registers interprets the addresses. Depending on the address, valid data is conveyed from or to the appropriate

latch or a command is interpreted. On latching a read address, data is read out from a storage register and

shifted out of SDO to the microcontroller or daisy chained TLC6C5712-Q1 device.

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Because for each address the TLC6C5712-Q1 device shifts out a fixed amount of data at the end of a write-read

cycle, it is possible to send different address codes to each IC in a daisy chain.

For a number N of daisy-chained devices, a communication cycle comprises 16 × N SCK cycles with the

corresponding data, transferred from shift registers to latches or from latches to shift registers on the rising edge

of LATCH. The falling edge of LATCH indicates the end of a communication cycle.

The TLC6C5712-Q1 device supports multiple devices in cascaded daisy-chain mode. Each communication

sequence must only have one LATCH rising edge, and therefore cannot be split into multiple smaller sequences.

CLK

W1

d15

W1

d14

W1

d13

W1

d12

W1

d2

W1

d1

W1

d0

W2

d15

W2

d14

SDI

LATCH

SDO

D/C

TLADZ

Write,

Read

W1

d14

W1

d13

W1

d12

W1

d11

W0

d0

W1

d15

W1

d0

W2

d15

SHRN (18)

图 22. Write-Access Data for a Typical Use Case

7.3.8 Thermal Information

TLC6C5712-Q1 has internal thermal shutdown (TSD) protection from device overheating. For continuous

operation, the junction temperature should not exceed thermal-shutdown threshold. If TSD is not disabled by

register and junction temperature exceeds thermal shutdown threshold, all outputs are turned off for protection.

When the junction temperature falls below the thermal threshold minus hysteresis, outputs resume.

Use 公式 4 to estimate the device power.

11

V

(IREF)

P_D(tot)= V_CC´ I_CC

+

V

(

´ I_(OUTx)-

)

(OUTx)

å

2

R_(IREF)

x=0

where

•

P_D(tot)= Total power dissipation of the device

V_(OUTx)= Voltage drop for channel x

I_(OUTx)= Average LED current for channel x

V_(IREF)= Reference voltage

R_(IREF)= Reference resistor

(4)

7.4 Device Functional Modes

7.4.1 Operation With V_CC< 2.8 V (Power-On-Reset Threshold)

The TLC6C5712-Q1 device might not work properly with V_CCbelow 2.8 V. When POR is triggered, the device

latches a POR fault and reports it through the ERR output. If V_CCcontinuous to drop, the content of the registers

could be reset to their default value, with all outputs shutting down by default.

7.4.2 Operation With V_CC≥ 2.8 V (Power-On-Reset Threshold)

The TLC6C5712-Q1 device is fully functional with V_CCat or above 2.8 V. The output current depends on the

channel output voltage, V_(OUTx). Given enough headroom for output transistors, the device should sink current as

programmed. If the headroom voltage is not enough, the output current could be lower than programmed.

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7.5.1 WRITE_MAP0 Register (address = 40h) [reset = 00h]

图 23. WRITE_MAP0 Register, Address 40h

7

6

5

4

PWM_MAP_CH1[2:0]

R/W

3

2

1

PWM_MAP_CH0[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 3. WRITE_MAP0 Register Field Descriptions

Bit

7–6

5–3

2–0

Field

Type

R

Reset

0h

Description

RESERVED

PWM_MAP_CH1

PWM_MAP_CH0

R/W

0h

Select PWM mapping for channel 1

Select PWM mapping for channel 0

0h

7.5.2 WRITE_MAP1 Register (address = 41h) [reset = 00h]

图 24. WRITE_MAP1 Register, Address 41h

7

6

5

4

PWM_MAP_CH3[2:0]

R/W

3

2

1

PWM_MAP_CH2[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 4. WRITE_MAP1 Register Field Descriptions

Bit

7–6

5–3

2–0

Field

Type

R

Reset

0h

Description

RESERVED

PWM_MAP_CH3

PWM_MAP_CH2

R/W

0h

Select PWM mapping for channel 3

Select PWM mapping for channel 2

0h

7.5.3 WRITE_MAP2 Register (address = 42h) [reset = 00h]

图 25. WRITE_MAP2 Register, Address 42h

7

6

5

4

PWM_MAP_CH5[2:0]

R/W

3

2

1

PWM_MAP_CH4[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 5. WRITE_MAP2 Register Field Descriptions

Bit

7–6

5–3

2–0

Field

Type

R

Reset

0h

Description

RESERVED

PWM_MAP_CH5

PWM_MAP_CH4

R/W

0h

Select PWM mapping for channel 5

Select PWM mapping for channel 4

0h

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7.5.4 WRITE_MAP3 Register (address = 43h) [reset = 00h]

图 26. WRITE_MAP3 Register, Address 43h

7

6

5

4

PWM_MAP_CH7[2:0]

R/W

3

2

1

PWM_MAP_CH6[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 6. WRITE_MAP3 Register Field Descriptions

Bit

7–6

5–3

2–0

Field

Type

R

Reset

0h

Description

RESERVED

PWM_MAP_CH7

PWM_MAP_CH6

R/W

0h

Select PWM mapping for channel 7

Select PWM mapping for channel 6

0h

7.5.5 WRITE_MAP4 Register (address = 44h) [reset = 00h]

图 27. WRITE_MAP4 Register, Address 44h

7

6

5

4

PWM_MAP_CH9[2:0]

R/W

3

2

1

PWM_MAP_CH8[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 7. WRITE_MAP4 Register Field Descriptions

Bit

7–6

5–3

2–0

Field

Type

R

Reset

0h

Description

RESERVED

PWM_MAP_CH9

PWM_MAP_CH8

R/W

0h

Select PWM mapping for channel 9

Select PWM mapping for channel 8

0h

7.5.6 WRITE_MAP5 Register (address = 45h) [reset = 00h]

图 28. WRITE_MAP5 Register, Address 45h

7

6

5

4

PWM_MAP_CH11[2:0]

R/W

3

2

1

PWM_MAP_CH10[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 8. WRITE_MAP5 Register Field Descriptions

Bit

7–6

5–3

2–0

Field

Type

R

Reset

0h

Description

RESERVED

PWM_MAP_CH11

PWM_MAP_CH10

R/W

0h

Select PWM mapping for channel 11

Select PWM mapping for channel 10

0h

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7.5.7 WRITE_CORR0 Register (address = 46h) [reset = 00h]

图 29. WRITE_CORR0 Register, Address 46h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH0[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9. WRITE_CORR0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH0

R/W

00h

Dot correction register for channel 0

7.5.8 WRITE_CORR1 Register (address = 47h) [reset = 00h]

图 30. WRITE_CORR1 Register, Address 47h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH1[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 10. WRITE_CORR1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH1

R/W

00h

Dot correction register for channel 1

7.5.9 WRITE_CORR2 Register (address = 48h) [reset = 00h]

图 31. WRITE_CORR2 Register, Address 48h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH2[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 11. WRITE_CORR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH2

R/W

00h

Dot correction register for channel 2

7.5.10 WRITE_CORR3 Register (address = 49h) [reset = 00h]

图 32. WRITE_CORR3 Register, Address 49h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH3[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 12. WRITE_CORR3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH3

R/W

00h

Dot correction register for channel 3

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7.5.11 WRITE_CORR4 Register (address = 4Ah) [reset = 00h]

图 33. WRITE_CORR4 Register, Address 4Ah

7

6

5

4

3

2

1

0

OUTPUT_DC_CH4[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 13. WRITE_CORR4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH4

R/W

00h

Dot correction register for channel 4

7.5.12 WRITE_CORR5 Register (address = 4Bh) [reset = 00h]

图 34. WRITE_CORR5 Register, Address 4Bh

7

6

5

4

3

2

1

0

OUTPUT_DC_CH5[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 14. WRITE_CORR5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH5

R/W

00h

Dot correction register for channel 5

7.5.13 WRITE_CORR6 Register (address = 4Ch) [reset = 00h]

图 35. WRITE_CORR6 Register, Address 4Ch

7

6

5

4

3

2

1

OUTPUT_DC_CH6[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 15. WRITE_CORR6 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH6

R/W

00h

Dot correction register for channel 6

7.5.14 WRITE_CORR7 Register (address = 4Dh) [reset = 00h]

图 36. WRITE_CORR7 Register, Address 4Dh

7

6

5

4

3

2

1

OUTPUT_DC_CH7[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 16. WRITE_CORR7 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH7

R/W

00h

Dot correction register for channel 7

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7.5.15 WRITE_CORR8 Register (address = 4Eh) [reset = 00h]

图 37. WRITE_CORR8 Register, Address 4Eh

7

6

5

4

3

2

1

0

OUTPUT_DC_CH8[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 17. WRITE_CORR8 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH8

R/W

00h

Dot correction register for channel 8

7.5.16 WRITE_CORR9 Register (address = 4Fh) [reset = 00h]

图 38. WRITE_CORR9 Register, Address 4Fh

7

6

5

4

3

2

1

0

OUTPUT_DC_CH9[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 18. WRITE_CORR9 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH9

R/W

00h

Dot correction register for channel 9

7.5.17 WRITE_CORR10 Register (address = 50h) [reset = 00h]

图 39. WRITE_CORR10 Register, Address 50h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH10[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 19. WRITE_CORR10 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH10

R/W

00h

Dot correction register for channel 10

7.5.18 WRITE_CORR11 Register (address = 51h) [reset = 00h]

图 40. WRITE_CORR11 Register, Address 51h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH11[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 20. WRITE_CORR11 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

OUTPUT_DC_CH11

R/W

00h

Dot correction register for channel 11

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7.5.19 WRITE_CH_ON_MASK0 Register (address = 52h) [reset = 3Fh]

图 41. WRITE_CH_ON_MASK0, Address 52h

7

6

5

4

3

2

1

0

RESERVED

R

CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK

5

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 21. WRITE_CH_ON_MASK0 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

CH_ON_MASK5

R/W

1h

Channel-activate mask register for channel 5. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

4

3

2

1

0

CH_ON_MASK4

CH_ON_MASK3

CH_ON_MASK2

CH_ON_MASK1

CH_ON_MASK0

R/W

1h

Channel-activate mask register for channel 4. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

Channel-activate mask register for channel 3. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

Channel-activate mask register for channel 2. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

Channel-activate mask register for channel 1. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

Channel-activate mask register for channel 0. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

7.5.20 WRITE_CH_ON_MASK1 Register (address = 53h) [reset = 3Fh]

图 42. WRITE_CH_ON_MASK1, Address 53h

7

6

5

4

3

2

1

0

RESERVED

R

CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK

11

10

9

8

7

6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 22. WRITE_CH_ON_MASK1 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

CH_ON_MASK11

R/W

1h

Channel-activate mask register for channel 11. Active-low.

HIGH: Channel output deactivated. LOW: Channel output

activated

4

CH_ON_MASK10

R/W

1h

Channel-activate mask register for channel 10. Active-low.

HIGH: Channel output deactivated. LOW: Channel output

activated

3

2

1

0

CH_ON_MASK9

CH_ON_MASK8

CH_ON_MASK7

CH_ON_MASK6

R/W

1h

Channel-activate mask register for channel 9. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

Channel-activate mask register for channel 8. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

Channel-activate mask register for channel 7. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

Channel-activate mask register for channel 6. Active-low. HIGH:

Channel output deactivated. LOW: Channel output activated

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7.5.21 WRITE_SHORT_MASK0 Register (address = 54h) [reset = 3Fh]

图 43. SLVSCO9WRITE_SHORT_MASK0, Address 54h

7

6

5

4

3

2

1

0

RESERVED

R

SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK

_CH5

_CH4

_CH3

_CH2

_CH1

_CH0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 23. WRITE_SHORT_MASK0 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

SHORT_MASK_CH5

R/W

1h

Short-to-supply fault mask register for channel 5. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

4

3

2

1

0

SHORT_MASK_CH4

SHORT_MASK_CH3

SHORT_MASK_CH2

SHORT_MASK_CH1

SHORT_MASK_CH0

R/W

1h

Short-to-supply fault mask register for channel 4. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

Short-to-supply fault mask register for channel 3. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

Short-to-supply fault mask register for channel 2. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

Short-to-supply fault mask register for channel 1. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

Short-to-supply fault mask register for channel 0. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

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7.5.22 WRITE_SHORT_MASK1 Register (address = 55h) [reset = 3Fh]

图 44. WRITE_SHORT_MASK1, Address 55h

7

6

5

4

3

2

1

0

RESERVED

R

SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK

_CH11

_CH10

_CH9

_CH8

_CH7

_CH6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 24. WRITE_SHORT_MASK1 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

SHORT_MASK_CH11

R/W

1h

Short-to-supply fault mask register for channel 11. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

4

3

2

1

0

SHORT_MASK_CH10

SHORT_MASK_CH9

SHORT_MASK_CH8

SHORT_MASK_CH7

SHORT_MASK_CH6

R/W

1h

Short-to-supply fault mask register for channel 10. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

Short-to-supply fault mask register for channel 9. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

Short-to-supply fault mask register for channel 8. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

Short-to-supply fault mask register for channel 7. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

Short-to-supply fault mask register for channel 6. Active-high.

HIGH: Short-to-supply fault masked. LOW: Short-to-supply fault

not masked

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7.5.23 WRITE_SHORT_GND_MASK0 Register (address = 56h) [reset = 3Fh]

图 45. WRITE_SHORT_GND_MASK0, Address 56h

7

6

5

4

3

2

1

0

RESERVED

R

SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH

5

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 25. WRITE_SHORT_GND_MASK0 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

SG_MASK_CH5

R/W

1h

Short-to-GND fault mask register for channel 5. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

4

3

2

1

0

SG_MASK_CH4

SG_MASK_CH3

SG_MASK_CH2

SG_MASK_CH1

SG_MASK_CH0

R/W

1h

Short-to-GND fault mask register for channel 4. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

Short-to-GND fault mask register for channel 3. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

Short-to-GND fault mask register for channel 2. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

Short-to-GND fault mask register for channel 1. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

Short-to-GND fault mask register for channel 0. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

7.5.24 WRITE_SHORT_GND_MASK1 Register (address = 57h) [reset = 3Fh]

图 46. WRITE_SHORT_GND_MASK1, Address 57h

7

6

5

4

3

2

1

0

RESERVED

R

SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH

11

10

9

8

7

6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 26. WRITE_SHORT_GND_MASK1 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

SG_MASK_CH11

R/W

1h

Short-to-GND fault mask register for channel 11. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

4

3

2

1

0

SG_MASK_CH10

SG_MASK_CH9

SG_MASK_CH8

SG_MASK_CH7

SG_MASK_CH6

R/W

1h

Short-to-GND fault mask register for channel 10. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

Short-to-GND fault mask register for channel 9. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

Short-to-GND fault mask register for channel 8. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

Short-to-GND fault mask register for channel 7. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

Short-to-GND fault mask register for channel 6. Active-high. HIGH:

Short-to-GND fault masked. LOW: Short-to-GND fault not masked

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7.5.25 WRITE_OPEN_MASK0 Register (address = 58h) [reset = 3Fh]

图 47. WRITE_OPEN_MASK0, Address 58h

7

6

5

4

3

2

1

0

RESERVED

R

OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_

CH5

CH4

CH3

CH2

CH1

CH0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 27. WRITE_OPEN_MASK0 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

OPEN_MASK_CH5

R/W

1h

Open-fault mask register for channel 5. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

4

3

2

1

0

OPEN_MASK_CH4

OPEN_MASK_CH3

OPEN_MASK_CH2

OPEN_MASK_CH1

OPEN_MASK_CH0

R/W

1h

Open-fault mask register for channel 4. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

Open-fault mask register for channel 3. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

Open-fault mask register for channel 2. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

Open-fault mask register for channel 1. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

Open-fault mask register for channel 0. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

7.5.26 WRITE_OPEN_MASK1 Register (address = 59h) [reset = 3Fh]

图 48. WRITE_OPEN_MASK1, Address 59h

7

6

5

4

3

2

1

0

RESERVED

R

OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_

CH11

CH10

CH9

CH8

CH7

CH6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 28. WRITE_OPEN_MASK1 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

OPEN_MASK_CH11

R/W

1h

Open-fault mask register for channel 11. Active-high. HIGH:

Open fault masked. LOW: Open fault not masked

4

3

2

1

0

OPEN_MASK_CH10

OPEN_MASK_CH9

OPEN_MASK_CH8

OPEN_MASK_CH7

OPEN_MASK_CH6

R/W

1h

Open-fault mask register for channel 10. Active-high. HIGH:

Open fault masked. LOW: Open fault not masked

Open-fault mask register for channel 9. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

Open-fault mask register for channel 8. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

Open-fault mask register for channel 7. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

Open-fault mask register for channel 6. Active-high. HIGH: Open

fault masked. LOW: Open fault not masked

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7.5.27 WRITE_PWM_FAULT_MASK Register (address = 60h) [reset = 3Fh]

图 49. WRITE_PWM_FAULT_MASK Register, Address 60h

7

6

5

4

3

2

1

0

RESERVED

R

PWM_FAULT_ PWM_FAULT_ PWM_FAULT_ PWM_FAULT_ PWM_FAULT_ PWM_FAULT_

MASK5

MASK4

MASK3

MASK2

MASK1

MASK0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 29. WRITE_PWM_FAULT_MASK Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

PWM_FAULT_MASK5

R/W

1h

PWM-fault mask register for input PWM channel 5. Active-high.

HIGH: PWM fault masked. LOW: PWM fault not masked

4

3

2

1

0

PWM_FAULT_MASK4

PWM_FAULT_MASK3

PWM_FAULT_MASK2

PWM_FAULT_MASK1

PWM_FAULT_MASK0

R/W

1h

PWM-fault mask register for input PWM channel 4. Active-high.

HIGH: PWM fault masked. LOW: PWM fault not masked

PWM-fault mask register for input PWM channel 3. Active-high.

HIGH: PWM fault masked. LOW: PWM fault not masked

PWM-fault mask register for input PWM channel 2. Active-high.

HIGH: PWM fault masked. LOW: PWM fault not masked

PWM-fault mask register for input PWM channel 1. Active-high.

HIGH: PWM fault masked. LOW: PWM fault not masked

PWM-fault mask register for input PWM channel 0. Active-high.

HIGH: PWM fault masked. LOW: PWM fault not masked

7.5.28 RESET_POR Register (address = 61h) [reset = 00h]

图 50. RESET_POR Register, Address 61h

7

6

5

4

3

2

1

0

RESET_POR

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 30. RESET_POR Field Descriptions

Bit

Field

Type

Reset

Description

7–0

RESET_POR

W

00h

A RESET_POR command is issued if the register content = 69h.

The register content is automatically cleared.

7.5.29 RESET_STATUS Register (address = 62h) [reset = 00h]

图 51. RESET_STATUS Register, Address 62h

7

6

5

4

3

2

1

0

RESET_STATUS

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 31. RESET_STATUS Field Descriptions

Bit

Field

Type

Reset

Description

7–0

RESET_STATUS

W

00h

A RESET_STATUS command is issued if the register content =

66h. The register content is automatically cleared.

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7.5.30 SOFTWARE_POR Register (address = 63h) [reset = 00h]

图 52. SOFTWARE_POR Register, Address 63h

7

6

5

4

3

2

1

0

SOFTWARE_POR

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 32. SOFTWARE_POR Field Descriptions

Bit

Field

Type

Reset

Description

7–0

SOFTWARE_POR

W

00h

A SOFTWARE_POR command is issued if the register content =

99h. The register content is automatically cleared.

7.5.31 WRITE_DIS_PULL_UP_0 Register (address = 64h) [reset = 00h]

图 53. WRITE_DIS_PULL_UP_0 Register, Address 64h

7

6

5

4

3

2

1

0

RESERVED

DIS_PULL_UP DIS_PULL_UP DIS_PULL_UP DIS_PULL_UP DIS_PULL_UP DIS_PULL_UP

_CH5

_CH4

_CH3

_CH2

_CH1

_CH0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 33. WRITE_DIS_PULL_UP_0 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

DIS_PULL_UP_CH5

R/W

0h

Disable deactivated-channel internal pullup register for channel

5. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

4

3

2

1

0

DIS_PULL_UP_CH4

DIS_PULL_UP_CH3

DIS_PULL_UP_CH2

DIS_PULL_UP_CH1

DIS_PULL_UP_CH0

R/W

0h

Disable deactivated-channel internal pullup register for channel

4. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

Disable deactivated-channel internal pullup register for channel

3. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

Disable deactivated-channel internal pullup register for channel

2. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

Disable deactivated-channel internal pullup register for channel

1. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

Disable deactivated-channel internal pullup register for channel

0. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

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ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

7.5.32 WRITE_DIS_PULL_UP_1 Register (address = 65h) [reset = 00h]

图 54. WRITE_DIS_PULL_UP_1 Register, Address 65h

7

6

5

4

3

2

1

0

RESERVED

R

DIS_PULL_UP DIS_PULL_UP DIS_PULL_UP DIS_PULL_UP DIS_PULL_UP DIS_PULL_UP

_CH11

_CH10

_CH9

_CH8

_CH7

_CH6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 34. WRITE_DIS_PULL_UP_1 Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

DIS_PULL_UP_CH11

R/W

0h

Disable deactivated-channel internal pullup register for channel

11. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

4

3

2

1

0

DIS_PULL_UP_CH10

DIS_PULL_UP_CH9

DIS_PULL_UP_CH8

DIS_PULL_UP_CH7

DIS_PULL_UP_CH6

R/W

0h

Disable deactivated-channel internal pullup register for channel

10. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

Disable deactivated-channel internal pullup register for channel

9. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

Disable deactivated-channel internal pullup register for channel

8. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

Disable deactivated-channel internal pullup register for channel

7. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

Disable deactivated-channel internal pullup register for channel

6. Active-high. HIGH: internal pullup disabled; LOW: internal

pullup enabled.

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7.5.33 WRITE_ERROR_MASK Register (address = 66h) [reset = 00h]

图 55. WRITE_ERROR_MASK Register, Address 66h

7

6

5

4

3

2

1

0

REF_MASK

POR_MASK

OPEN_MASK SHORT_MASK

PWM_MASK

WLS_MASK

PRE_TSD_

MASK

TSD_MASK

R/W

R/W R/W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 35. WRITE_ERROR_MASK Field Descriptions

Bit

Field

Type

Reset

Description

7

REF_MASK

R/W

0h

Reference fault mask bit. Active-high. HIGH: Reference fault is

masked; LOW: Reference fault is not masked.

6

5

4

3

2

1

0

POR_MASK

R/W

0h

Power-on-reset fault mask bit Active-high. HIGH: POR fault is

masked; LOW: POR fault is not masked.

OPEN_MASK

SHORT_MASK

PWM_MASK

WLS_MASK

Open fault mask bit. Active-high. HIGH: Open fault is masked;

LOW: Open fault is not masked.

Short fault mask bit. Active-high. HIGH: Short fault is masked;

LOW: Short fault is not masked.

PWM fault mask bit. Active-high. HIGH: PWM fault is masked;

LOW: PWM fault is not masked.

Weak-LED-supply (WLS) fault mask bit. Active-high. HIGH: WLS

fault is masked; LOW: WLS fault is not masked.

PRE_TSD_MASK

TSD_MASK

Pre-thermal-warning fault mask bit. Active-high. HIGH:

PRE_TSD fault is masked; LOW: PRE_TSD fault is not masked.

Thermal-shutdown fault mask bit. Active-high. HIGH: TSD fault

is masked; LOW: TSD fault is not masked.

7.5.34 WRITE_MISC_CMD Register (address = 67h) [reset = 00h]

图 56. WRITE_MISC_CMD Register, Address 67h

7

6

5

4

3

2

1

0

RESERVED

DIS_OFF_

FAULT_DIAG

ADJ_DIAG_

START

SLOW_SLEW_ FORCE_ERR

RATE

WLS_TH

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 36. WRITE_MISC_CMD Field Descriptions

Bit

7–5

4

Field

Type

R

Reset

0h

Description

RESERVED

DIS_OFF_FAULT_DIAG

R/W

0h

Off-state output fault diagnostics control bit. Active-high. HIGH:

Off-state fault diagnostics disabled; LOW: Off-state fault

diagnostics enabled

3

2

ADJ_DIAG_START

SLOW_SLEW_RATE

R/W

0h

Adjacent-pin diagnostics start control bit. Active-high, returns low

when adjacent-pin diagnostic procedure is concluded.

HIGH: Start adjacent-pin diagnostics or adjacent-pin diagnostics

are ongoing; LOW: Adjacent-pin diagnostics are not running.

Slow slew rate control bit. Active-high. HIGH: Output-current

slew rate is in slow mode. LOW: Output-current slew rate is in

normal mode.

1

0

FORCE_ERR

WLS_TH

R/W

0h

Force error control bit. Active-high. HIGH: ERR output is forced

low. LOW: ERR output is not forced low.

Weak-LED-supply threshold-control bit. Active-high. HIGH: WLS

threshold is set to 3.3-V mode. LOW: WLS threshold is set to 5-

V mode.

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7.5.35 LOCK_MAP Register (address = 68h) [reset = 00h]

图 57. LOCK_MAP Register, Address 68h

7

6

5

4

3

2

1

0

LOCK_MAP

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 37. LOCK_MAP Field Descriptions

Bit

Field

Type

Reset

Description

7–0

LOCK_MAP

W

00h

A LOCK_MAP command is issued if the register content = A5h.

The register content is automatically cleared.

7.5.36 LOCK_CORR Register (address = 69h) [reset = 00h]

图 58. LOCK_CORR Register, Address 69h

7

6

5

4

3

2

1

0

LOCK_CORR

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 38. LOCK_CORR Field Descriptions

Bit

Field

Type

Reset

Description

7–0

LOCK_CORR

W

00h

A LOCK_CORR command is issued if the register content =

55h. The register content is automatically cleared.

7.5.37 LOCK_MASK Register (address = 6Ah) [reset = 00h]

图 59. LOCK_MASK Register, Address 6Ah

7

6

5

4

3

2

1

0

LOCK_MASK

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 39. LOCK_MASK Field Descriptions

Bit

Field

Type

Reset

Description

7–0

LOCK_MASK

W

00h

A LOCK_MASK command is issued if the register content =

AAh. The register content is automatically cleared.

7.5.38 LOCK_MISC Register (address = 6Bh) [reset = 00h]

图 60. LOCK_MISC Register, Address 6Bh

7

6

5

4

3

2

1

0

LOCK_MISC

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 40. LOCK_MISC Field Descriptions

Bit

Field

Type

Reset

Description

7–0

LOCK_MISC

W

00h

A LOCK_MISC command is issued if the register content = 5Ah.

The register content is automatically cleared.

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7.5.39 UNLOCK_MAP Register (address = 6Ch) [reset = 00h]

图 61. UNLOCK_MAP Register, Address 6Ch

7

6

5

4

3

2

1

0

UNLOCK_MAP

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 41. UNLOCK_MAP Field Descriptions

Bit

Field

Type

Reset

Description

7–0

UNLOCK_MAP

W

00h

An UNLOCK_MAP command is issued if the register content =

CCh. The register content is automatically cleared.

7.5.40 UNLOCK_CORR Register (address = 6Dh) [reset = 00h]

图 62. UNLOCK_CORR Register, Address 6Dh

7

6

5

4

3

2

1

0

UNLOCK_CORR

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 42. UNLOCK_CORR Field Descriptions

Bit

Field

Type

Reset

Description

7–0

UNLOCK_CORR

W

00h

An UNLOCK_CORR command is issued if the register content =

33h. The register content is automatically cleared.

7.5.41 UNLOCK_MASK Register (address = 6Eh) [reset = 00h]

图 63. UNLOCK_MASK Register, Address 6Eh

7

6

5

4

3

2

1

0

UNLOCK_MASK

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 43. UNLOCK_MASK Field Descriptions

Bit

Field

Type

Reset

Description

7–0

UNLOCK_MASK

W

00h

An UNLOCK_MASK command is issued if the register content =

3Ch. The register content is automatically cleared.

7.5.42 UNLOCK_MISC Register (address = 6Fh) [reset = 00h]

图 64. UNLOCK_MISC Register, Address 6Fh

7

6

5

4

3

2

1

0

UNLOCK_MISC

W

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表 44. UNLOCK_MISC Field Descriptions

Bit

Field

Type

Reset

Description

7–0

UNLOCK_MISC

W

00h

An UNLOCK_MISC command is issued if the register content =

C3h. The register content is automatically cleared.

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ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

7.5.43 READ_MAP0 Register (address = 80h) [reset = 00h]

Address 40h is used for writing the MAP0 data using the register pseudonym WRITE_MAP0, and address 80h is

used for reading the MAP0 data using the register pseudonym READ_MAP0. See the WRITE_MAP0 Register

(address = 40h) [reset = 00h] section for a description of the register contents.

图 65. READ_MAP0 Register, Address 80h

7

6

5

4

PWM_MAP_CH1[2:0]

R/W

3

2

1

PWM_MAP_CH0[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.44 READ_MAP1 Register (address = 81h) [reset = 00h]

Address 41h is used for writing the MAP1 data using the register pseudonym WRITE_MAP1, and address 81h is

used for reading the MAP1 data using the register pseudonym READ_MAP1. See the WRITE_MAP1 Register

(address = 41h) [reset = 00h] section for a description of the register contents.

图 66. READ_MAP1 Register, Address 81h

7

6

5

4

PWM_MAP_CH3[2:0]

R/W

3

2

1

PWM_MAP_CH2[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.45 READ_MAP2 Register (address = 82h) [reset = 00h]

Address 42h is used for writing the MAP2 data using the register pseudonym WRITE_MAP2, and address 82h is

used for reading the MAP2 data using the register pseudonym READ_MAP2. See the WRITE_MAP2 Register

(address = 42h) [reset = 00h] section for a description of the register contents.

图 67. READ_MAP2 Register, Address 82h

7

6

5

4

PWM_MAP_CH5[2:0]

R/W

3

2

1

PWM_MAP_CH4[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.46 READ_MAP3 Register (address = 83h) [reset = 00h]

Address 43h is used for writing the MAP3 data using the register pseudonym WRITE_MAP3, and address 83h is

used for reading the MAP3 data using the register pseudonym READ_MAP3. See the WRITE_MAP3 Register

(address = 43h) [reset = 00h] section for a description of the register contents.

图 68. READ_MAP3 Register, Address 83h

7

6

5

4

PWM_MAP_CH7[2:0]

R/W

3

2

1

PWM_MAP_CH6[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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7.5.47 READ_MAP4 Register (address = 84h) [reset = 00h]

Address 44h is used for writing the MAP4 data using the register pseudonym WRITE_MAP4, and address 84h is

used for reading the MAP4 data using the register pseudonym READ_MAP4. See the WRITE_MAP4 Register

(address = 44h) [reset = 00h] section for a description of the register contents.

图 69. READ_MAP4 Register, Address 84h

7

6

5

4

PWM_MAP_CH9[2:0]

R/W

3

2

1

PWM_MAP_CH8[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.48 READ_MAP5 Register (address = 85h) [reset = 00h]

Address 45h is used for writing the MAP5 data using the register pseudonym WRITE_MAP5, and address 85h is

used for reading the MAP5 data using the register pseudonym READ_MAP5. See the WRITE_MAP5 Register

(address = 45h) [reset = 00h] section for a description of the register contents.

图 70. READ_MAP5 Register, Address 85h

7

6

5

4

PWM_MAP_CH11[2:0]

R/W

3

2

1

PWM_MAP_CH10[2:0]

R/W

0

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.49 READ_CORR0 Register (address = 86h) [reset = 00h]

Address 46h is used for writing the CORR0 data using the register pseudonym WRITE_CORR0, and address

86h is used for reading the CORR0 data using the register pseudonym READ_CORR0. See the WRITE_CORR0

Register (address = 46h) [reset = 00h] section for a description of the register contents.

图 71. READ_CORR0 Register, Address 86h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH0[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.50 READ_CORR1 Register (address = 87h) [reset = 00h]

Address 47h is used for writing the CORR1 data using the register pseudonym WRITE_CORR1, and address

86h is used for reading the CORR1 data using the register pseudonym READ_CORR1. See the WRITE_CORR1

Register (address = 47h) [reset = 00h] section for a description of the register contents.

图 72. READ_CORR1 Register, Address 87h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH1[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

7.5.51 READ_CORR2 Register (address = 88h) [reset = 00h]

Address 48h is used for writing the CORR2 data using the register pseudonym WRITE_CORR2, and address

88h is used for reading the CORR2 data using the register pseudonym READ_CORR2. See the WRITE_CORR2

Register (address = 48h) [reset = 00h] section for a description of the register contents.

图 73. READ_CORR2 Register, Address 88h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH2[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.52 READ_CORR3 Register (address = 89h) [reset = 00h]

Address 49h is used for writing the CORR3 data using the register pseudonym WRITE_CORR3, and address

89h is used for reading the CORR3 data using the register pseudonym READ_CORR3. See the WRITE_CORR3

Register (address = 49h) [reset = 00h] section for a description of the register contents.

图 74. READ_CORR3 Register, Address 89h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH3[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.53 READ_CORR4 Register (address = 8Ah) [reset = 00h]

Address 4Ah is used for writing the CORR4 data using the register pseudonym WRITE_CORR4, and address

8Ah is used for reading the CORR4 data using the register pseudonym READ_CORR4. See the WRITE_CORR4

Register (address = 4Ah) [reset = 00h] section for a description of the register contents.

图 75. READ_CORR4 Register, Address 8Ah

7

6

5

4

3

2

1

0

OUTPUT_DC_CH4[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.54 READ_CORR5 Register (address = 8Bh) [reset = 00h]

Address 4Bh is used for writing the CORR5 data using the register pseudonym WRITE_CORR5, and address

8Bh is used for reading the CORR5 data using the register pseudonym READ_CORR5. See the WRITE_CORR5

Register (address = 4Bh) [reset = 00h] section for a description of the register contents.

图 76. READ_CORR5 Register, Address 8Bh

7

6

5

4

3

2

1

0

OUTPUT_DC_CH5[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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7.5.55 READ_CORR6 Register (address = 8Ch) [reset = 00h]

Address 4Ch is used for writing the CORR6 data using the register pseudonym WRITE_CORR6, and address

8Ch is used for reading the CORR6 data using the register pseudonym READ_CORR6. See the

WRITE_CORR6 Register (address = 4Ch) [reset = 00h] section for a description of the register contents.

图 77. READ_CORR6 Register, Address 8Ch

7

6

5

4

3

2

1

0

OUTPUT_DC_CH6[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.56 READ_CORR7 Register (address = 8Dh) [reset = 00h]

Address 4Dh is used for writing the CORR7 data using the register pseudonym WRITE_CORR7, and address

8Dh is used for reading the CORR7 data using the register pseudonym READ_CORR7. See the

WRITE_CORR7 Register (address = 4Dh) [reset = 00h] section for a description of the register contents.

图 78. READ_CORR7 Register, Address 8Dh

7

6

5

4

3

2

1

0

OUTPUT_DC_CH7[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.57 READ_CORR8 Register (address = 8Eh) [reset = 00h]

Address 4Eh is used for writing the CORR8 data using the register pseudonym WRITE_CORR8, and address

8Eh is used for reading the CORR8 data using the register pseudonym READ_CORR8. See the WRITE_CORR8

Register (address = 4Eh) [reset = 00h] section for a description of the register contents.

图 79. READ_CORR8 Register, Address 8Eh

7

6

5

4

3

2

1

0

OUTPUT_DC_CH8[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.58 READ_CORR9 Register (address = 8Fh) [reset = 00h]

Address 4Fh is used for writing the CORR9 data using the register pseudonym WRITE_CORR9, and address

8Fh is used for reading the CORR9 data using the register pseudonym READ_CORR9. See the WRITE_CORR9

Register (address = 4Fh) [reset = 00h] section for a description of the register contents.

图 80. READ_CORR9 Register, Address 8Fh

7

6

5

4

3

2

1

0

OUTPUT_DC_CH9[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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7.5.59 READ_CORR10 Register (address = 90h) [reset = 00h]

Address 50h is used for writing the CORR10 data using the register pseudonym WRITE_CORR10, and address

90h is used for reading the CORR10 data using the register pseudonym READ_CORR10. See the

WRITE_CORR10 Register (address = 50h) [reset = 00h] section for a description of the register contents.

图 81. READ_CORR10 Register, Address 90h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH10[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.60 READ_CORR11 Register (address = 91h) [reset = 00h]

Address 51h is used for writing the CORR11 data using the register pseudonym WRITE_CORR11, and address

91h is used for reading the CORR11 data using the register pseudonym READ_CORR11. See the

WRITE_CORR11 Register (address = 51h) [reset = 00h] section for a description of the register contents.

图 82. READ_CORR11 Register, Address 91h

7

6

5

4

3

2

1

0

OUTPUT_DC_CH11[7:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.61 READ_CH_ON_MASK0 Register (address = 92h) [reset = 3Fh]

Address 52h is used for writing the CH_ON_MASK0 data using the register pseudonym

WRITE_CH_ON_MASK0, and address 92h is used for reading the CH_ON_MASK0 data using the register

pseudonym READ_CH_ON_MASK0. See the WRITE_CH_ON_MASK0 Register (address = 52h) [reset = 3Fh]

section for a description of the register contents.

图 83. READ_CH_ON_MASK0, Address 92h

7

6

5

4

3

2

1

0

RESERVED

R

CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK

5

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.62 READ_CH_ON_MASK1 Register (address = 93h) [reset = 3Fh]

Address 53h is used for writing the CH_ON_MASK1 data using the register pseudonym

WRITE_CH_ON_MASK1, and address 93h is used for reading the CH_ON_MASK1 data using the register

pseudonym READ_CH_ON_MASK1. See the WRITE_CH_ON_MASK1 Register (address = 53h) [reset = 3Fh]

section for a description of the register contents.

图 84. READ_CH_ON_MASK1, Address 93h

7

6

5

4

3

2

1

0

RESERVED

R

CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK CH_ON_MASK

11

10

9

8

7

6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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7.5.63 READ_SHORT_MASK0 Register (address = 94h) [reset = 3Fh]

Address 54h is used for writing the SHORT_MASK0 data using the register pseudonym

WRITE_SHORT_MASK0, and address 94h is used for reading the SHORT_MASK0 data using the register

pseudonym READ_SHORT_MASK0. See the WRITE_SHORT_MASK0 Register (address = 54h) [reset = 3Fh]

section for a description of the register contents.

图 85. READ_SHORT_MASK0, Address 94h

7

6

5

4

3

2

1

0

RESERVED

R

SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK

_CH5

_CH4

_CH3

_CH2

_CH1

_CH0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.64 READ_SHORT_MASK1 Register (address = 95h) [reset = 3Fh]

Address 55h is used for writing the SHORT_MASK1 data using the register pseudonym

WRITE_SHORT_MASK1, and address 95h is used for reading the SHORT_MASK1 data using the register

pseudonym READ_SHORT_MASK1. See the WRITE_SHORT_MASK1 Register (address = 55h) [reset = 3Fh]

section for a description of the register contents.

图 86. READ_SHORT_MASK1, Address 95h

7

6

5

4

3

2

1

0

RESERVED

R

SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK SHORT_MASK

_CH11

_CH10

_CH9

_CH8

_CH7

_CH6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.65 READ_SHORT_GND_MASK0 Register (address = 96h) [reset = 3Fh]

Address 56h is used for writing the SHORT_GND_MASK0 data using the register pseudonym

WRITE_SHORT_GND_MASK0, and address 96h is used for reading the SHORT_GND_MASK0 data using the

register pseudonym READ_SHORT_GND_MASK0. See the WRITE_SHORT_GND_MASK0 Register (address =

56h) [reset = 3Fh] section for a description of the register contents.

图 87. READ_SHORT_GND_MASK0, Address 96h

7

6

5

4

3

2

1

0

RESERVED

R

SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH

5

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.66 READ_SHORT_GND_MASK1 Register (address = 97h) [reset = 3Fh]

Address 57h is used for writing the SHORT_GND_MASK1 data using the register pseudonym

WRITE_SHORT_GND_MASK1, and address 97h is used for reading the SHORT_GND_MASK1 data using the

register pseudonym READ_SHORT_GND_MASK1. See the WRITE_SHORT_GND_MASK1 Register (address =

57h) [reset = 3Fh] section for a description of the register contents.

图 88. READ_SHORT_GND_MASK1, Address 97h

7

6

5

4

3

2

1

0

RESERVED

R

SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH SG_MASK_CH

11

10

9

8

7

6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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7.5.67 READ_OPEN_MASK0 Register (address = 98h) [reset = 3Fh]

Address 58h is used for writing the OPEN_MASK0 data using the register pseudonym WRITE_OPEN_MASK0,

and address 98h is used for reading the OPEN_MASK0 data using the register pseudonym

READ_OPEN_MASK0. See the WRITE_OPEN_MASK0 Register (address = 58h) [reset = 3Fh] section for a

description of the register contents.

图 89. READ_OPEN_MASK0, Address 98h

7

6

5

4

3

2

1

0

RESERVED

R

OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_

CH5

CH4

CH3

CH2

CH1

CH0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.68 READ_OPEN_MASK1 Register (address = 99h) [reset = 3Fh]

Address 59h is used for writing the OPEN_MASK1 data using the register pseudonym WRITE_OPEN_MASK1,

and address 99h is used for reading the OPEN_MASK1 data using the register pseudonym

READ_OPEN_MASK1. See the WRITE_OPEN_MASK1 Register (address = 59h) [reset = 3Fh] section for a

description of the register contents.

图 90. READ_OPEN_MASK1, Address 99h

7

6

5

4

3

2

1

0

RESERVED

R

OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_ OPEN_MASK_

CH11

CH10

CH9

CH8

CH7

CH6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.69 READ_SHORT_FAULT0 (address = 9Ah) [reset = 00h]

图 91. READ_SHORT_FAULT0, Address 9Ah

7

6

5

4

3

2

1

0

RESERVED

R

SHORT_

FAULT5

SHORT_

FAULT4

SHORT_

FAULT3

SHORT_

FAULT2

SHORT_

FAULT1

SHORT_

FAULT0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 45. READ_SHORT_FAULT0 Register Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

SHORT_FAULT5

R

0h

Channel 5 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

4

3

2

1

0

SHORT_FAULT4

SHORT_FAULT3

SHORT_FAULT2

SHORT_FAULT1

SHORT_FAULT0

R

0h

Channel 4 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

Channel 3 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

Channel 2 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

Channel 1 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

Channel 0 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

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7.5.70 READ_SHORT_FAULT1 (address = 9Bh) [reset = 00h]

图 92. READ_SHORT_FAULT1, Address 9Bh

7

6

5

4

3

2

1

0

RESERVED

R

SHORT_

FAULT11

SHORT_

FAULT10

SHORT_

FAULT9

SHORT_

FAULT8

SHORT_

FAULT7

SHORT_

FAULT6

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 46. READ_SHORT_FAULT1 Register Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

SHORT_FAULT11

R

0h

Channel 11 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

4

3

2

1

0

SHORT_FAULT10

SHORT_FAULT9

SHORT_FAULT8

SHORT_FAULT7

SHORT_FAULT6

R

0h

Channel 10 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

Channel 9 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

Channel 8 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

Channel 7 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

Channel 6 LED short-to-supply fault flag. Active-high. HIGH:

LED short-to-supply detected; LOW: LED short-to-supply not

detected.

7.5.71 READ_SHORT_GND_FAULT0 (address = 9Ch) [reset = 00h]

图 93. READ_SHORT_GND_FAULT0, Address 9Ch

7

6

5

SG_FAULT5

R

4

SG_FAULT4

R

3

SG_FAULT3

R

2

SG_FAULT2

R

1

SG_FAULT1

R

0

SG_FAULT0

R

RESERVED

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 47. READ_SHORT_GND_FAULT0 Register Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

SG_FAULT5

R

0h

Channel 5 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

4

3

2

1

0

SG_FAULT4

SG_FAULT3

SG_FAULT2

SG_FAULT1

SG_FAULT0

R

0h

Channel 4 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

Channel 3 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

Channel 2 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

Channel 1 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

Channel 0 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

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7.5.72 READ_SHORT_GND_FAULT1 (address = 9Dh) [reset = 00h]

图 94. READ_SHORT_GND_FAULT1, Address 9Dh

7

6

5

4

3

SG_FAULT9

R

2

SG_FAULT8

R

1

SG_FAULT7

R

0

SG_FAULT6

R

RESERVED

R

SG_FAULT11

R

SG_FAULT10

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 48. READ_SHORT_GND_FAULT1 Register Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

SG_FAULT11

R

0h

Channel 11 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

4

3

2

1

0

SG_FAULT10

SG_FAULT9

SG_FAULT8

SG_FAULT7

SG_FAULT6

R

0h

Channel 10 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

Channel 9 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

Channel 8 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

Channel 7 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

Channel 6 LED short-to-GND fault flag. Active-high. HIGH: LED

short-to-GND detected; LOW: LED short-to-GND not detected.

7.5.73 READ_OPEN_FAULT0 (address = 9Eh) [reset = 00h]

图 95. READ_OPEN_FAULT0, Address 9Eh

7

6

5

4

3

2

1

0

RESERVED

R

OPEN_FAULT_ OPEN_FAULT_ OPEN_FAULT_ OPEN_FAULT_ OPEN_FAULT_ OPEN_FAULT_

CH5

CH4

CH3

CH2

CH1

CH0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 49. READ_OPEN_FAULT0 Register Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

OPEN_FAULT_CH5

R

0h

Channel 5 LED-open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

4

3

2

1

0

OPEN_FAULT_CH4

OPEN_FAULT_CH3

OPEN_FAULT_CH2

OPEN_FAULT_CH1

OPEN_FAULT_CH0

R

0h

Channel 4 LEDopen fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

Channel 3 LED-open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

Channel 2 LED-open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

Channel 1 LED-open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

Channel 0 LED-open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

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7.5.74 READ_OPEN_FAULT1 (address = 9Fh) [reset = 00h]

图 96. READ_OPEN_FAULT1, Address 9Fh

7

6

5

4

3

2

1

0

RESERVED

R

OPEN_FAULT_ OPEN_FAULT_ OPEN_FAULT_ OPEN_FAULT_ OPEN_FAULT_ OPEN_FAULT_

CH11

CH10

CH9

CH8

CH7

CH6

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 50. READ_OPEN_FAULT1 Register Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

OPEN_FAULT_CH11

R

0h

Channel 11 LED open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

4

3

2

1

0

OPEN_FAULT_CH10

OPEN_FAULT_CH9

OPEN_FAULT_CH8

OPEN_FAULT_CH7

OPEN_FAULT_CH6

R

0h

Channel 10 LED open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

Channel 9 LED open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

Channel 8 LED open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

Channel 7 LED open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

Channel 6 LED open fault flag. Active-high. HIGH: LED open

detected; LOW: LED open not detected.

7.5.75 READ_PWM_FAULT_MASK Register (address = A1h) [reset = 3Fh]

Address 60h is used for writing the PWM_FAULT_MASK data using the register pseudonym

WRITE_PWM_FAULT_MASK, and address A0h is used for reading the PWM_FAULT_MASK data using the

register pseudonym READ_PWM_FAULT_MASK. See the WRITE_PWM_FAULT_MASK Register (address =

60h) [reset = 3Fh] section for a description of the register contents.

图 97. READ_PWM_FAULT_MASK, Address A1h

7

6

5

4

3

2

1

0

RESERVED

R

PWM_FAULT_ PWM_FAULT_ PWM_FAULT_ PWM_FAULT_ PWM_FAULT_ SG_MASK_CH

MASK5

MASK4

MASK3

MASK2

MASK1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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7.5.76 READ_STATUS0 (address = A2h) [reset = 40h]

图 98. READ_STATUS0, Address A2h

7

6

5

4

3

2

1

0

REF_FAULT_

FLAG

POR_ERR_

FLAG

ANY_OPEN_

FLAG

ANY_SHORT_

FLAG

ANY_PWM_

FAULT_FLAG

WLS_FAULT_

FLAG

PRE_TSD_

FLAG

TSD_FLAG

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 51. READ_STATUS0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

REF_FAULT_FLAG

R

0h

Reference-resistor fault flag. Active-high. HIGH: Reference fault

detected; LOW: Reference fault not detected.

6

5

POR_ERR_FLAG

ANY_OPEN_FLAG

R

1h

0h

Power-on-reset error flag. Active-high. HIGH: POR error

detected; LOW: POR error not detected.

Any-channel-open fault flag. Active-high. HIGH: One or more

channels has an open fault; LOW: an open fault is not detected

or an open fault is masked.

4

3

2

1

0

ANY_SHORT_FLAG

ANY_PWM_FAULT_FLAG

WLS_FAULT_FLAG

PRE_TSD_FLAG

R

0h

Any channel short-to-supply fault flag. Active-high. HIGH: One or

more channels has a short-to-supply fault; LOW: a short-to-

supply fault is not detected or a short-to-supply fault is masked.

Any-input PWM-fault flag. Active-high. HIGH: One or more PWM

channels has a fault; LOW: a PWM fault is not detected or a

PWM fault is masked.

Weak-LED-supply fault flag. Active-high. HIGH: WLS fault

detected; LOW: a WLS fault is not detected or a WLS fault is

masked.

PRE-TSD warning flag. Active-high. HIGH: a PRE TSD warning

is detected; LOW: a PRE-TSD warning is not detected or a

PRE_TSD warning is masked.

TSD_FLAG

Thermal shutdown flag. Active-high. HIGH: a thermal shutdown

has been triggered; LOW: a thermal shutdown is not triggered or

it is masked.

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7.5.77 READ_STATUS1 (address = A3h) [reset = 00h]

See the PWM MAP Register Lock section for a list of miscellaneous (MISC), mapping (MAP), masking (MASK),

and correction (CORR) registers.

图 99. READ_STATUS1, Address A3h

7

6

5

4

3

2

1

0

RESERVED

DIS_PULL_

UP_FLAG

LOCK_MISC_

FLAG

LOCK_MAP_

FLAG

LOCK_MASK_ LOCK_CORR_

FLAG

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 52. READ_STATUS1 Register Field Descriptions

Bit

7–5

4

Field

Type

R

Reset

0h

Description

RESERVED

DIS_PULL_UP_FLAG

R

0h

Off-state pullup disabled flag. Active-high. HIGH: One or more

channels have off-state pullup disabled. LOW: No channel has

off-state pullup disabled.

3

2

1

0

LOCK_MISC_FLAG

LOCK_MAP_FLAG

LOCK_MASK_FLAG

LOCK_CORR_FLAG

R

0h

LOCK_MISC status flag. Active-high. HIGH: MISC registers are

locked. LOW: MISC registers are not locked.

LOCK_MAP status flag. Active-high. HIGH: MAP registers are

locked. LOW: MAP registers are not locked.

LOCK_MASK status flag. Active-high. HIGH: MASK registers

are locked. LOW: MASK registers are not locked.

LOCK_CORR status flag. Active-high. HIGH: CORR registers

are locked. LOW: CORR registers are not locked.

7.5.78 READ_DIS_PULL_UP_0 Register (address = A4h) [reset = 00h]

Address 64h is used for writing the DIS_PULL_UP_0 data using the register pseudonym

WRITE_DIS_PULL_UP_0, and address A4h is used for reading the DIS_PULL_UP_0 data using the register

pseudonym READ_DIS_PULL_UP_0. See the WRITE_DIS_PULL_UP_0 Register (address = 64h) [reset = 00h]

section for a description of the register contents.

图 100. READ_DIS_PULL_UP_0 Register, Address A4h

7

6

5

4

3

2

1

0

RESERVED

R

DIS_PULL_

UP_CH5

DIS_PULL_

UP_CH4

DIS_PULL_

UP_CH3

DIS_PULL_

UP_CH2

DIS_PULL_

UP_CH1

DIS_PULL_

UP_CH0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.79 READ_DIS_PULL_UP_1 Register (address = A5h) [reset = 00h]

Address 65h is used for writing the DIS_PULL_UP_1 data using the register pseudonym

WRITE_DIS_PULL_UP_1, and address A5h is used for reading the DIS_PULL_UP_1 data using the register

pseudonym READ_DIS_PULL_UP_1. See the WRITE_DIS_PULL_UP_1 Register (address = 65h) [reset = 00h]

section for a description of the register contents.

图 101. READ_DIS_PULL_UP_1 Register, Address A5h

7

6

5

4

3

2

1

0

RESERVED

R

DIS_PULL_

UP_CH11

DIS_PULL_

UP_CH10

DIS_PULL_

UP_CH9

DIS_PULL_

UP_CH8

DIS_PULL_

UP_CH7

DIS_PULL_

UP_CH6

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

52

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7.5.80 READ_ERROR_MASK (address = A6h) [reset = 00h]

Address 66h is used for writing the ERROR_MASK data using the register pseudonym WRITE_ERROR_MASK,

and address A6h is used for reading the ERROR_MASK data using the register pseudonym

READ_ERROR_MASK. See the WRITE_ERROR_MASK Register (address = 66h) [reset = 00h] section for a

description of the register contents.

图 102. READ_ERROR_MASK, Address A6h

7

6

5

4

3

2

1

0

REF_MASK

POR_MASK

OPEN_MASK SHORT_MASK

PWM_MASK

WLS_MASK

PRE_TSD_

MASK

TSD_MASK

R/W

R/W R/W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

7.5.81 READ_MISC_CMD Register (address = A7h) [reset = 00h]

Address 67h is used for writing the MISC_CMD data using the register pseudonym WRITE_MISC_CMD, and

address A7h is used for reading the MISC_CMD data using the register pseudonym READ_MISC_CMD. See the

WRITE_MISC_CMD Register (address = 67h) [reset = 00h] section for a description of the register contents.

图 103. READ_MISC_CMD Register, Address A7h

7

6

5

4

3

2

1

0

RESERVED

R

RESERVED

DIS_OFF_

FAULT_DIAG

ADJ_DIAG_

START

SLOW_SLEW_ FORCE_ERR

RATE

WLS_TH

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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7.5.82 READ_ADSHORT0 (address = A8h) [reset = 00h]

图 104. READ_ADSHORT0, Address A8h

7

6

5

4

3

2

1

0

RESERVED

R

AD_FLAG_

CH11

AD_FLAG_

CH10

AD_FLAG_CH9 AD_FLAG_CH8 AD_FLAG_CH7 AD_FLAG_CH6

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 53. READ_ADSHORT0 Register Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

AD_FLAG_CH11

R

0h

Adjacent-pin short fault flag for channel 11. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

4

3

2

1

0

AD_FLAG_CH10

AD_FLAG_CH9

AD_FLAG_CH8

AD_FLAG_CH7

AD_FLAG_CH6

R

0h

Adjacent-pin short fault flag for channel 10. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

Adjacent-pin short fault flag for channel 9. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

Adjacent-pin short fault flag for channel 8. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

Adjacent-pin short fault flag for channel 7. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

Adjacent-pin short fault flag for channel 6. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

7.5.83 READ_ADSHORT1 (address = A9h) [reset = 00h]

图 105. READ_ADSHORT1, Address A9h

7

6

5

4

3

2

1

0

RESERVED

R

AD_FLAG_CH5 AD_FLAG_CH4 AD_FLAG_CH3 AD_FLAG_CH2 AD_FLAG_CH1 AD_FLAG_CH0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 54. READ_ADSHORT1 Register Field Descriptions

Bit

7–6

5

Field

Type

R

Reset

0h

Description

RESERVED

AD_FLAG_CH5

R

0h

Adjacent-pin short fault flag for channel 5. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

4

3

2

1

0

AD_FLAG_CH4

AD_FLAG_CH3

AD_FLAG_CH2

AD_FLAG_CH1

AD_FLAG_CH0

R

0h

Adjacent-pin short fault flag for channel 4. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

Adjacent-pin short fault flag for channel 3. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

Adjacent-pin short fault flag for channel 2. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

Adjacent-pin short fault flag for channel 1. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

Adjacent-pin short fault flag for channel 0. Active-high. HIGH:

Adjacent-pin short detected; LOW: adjacent-pin short not detected.

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ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLC6C5712-Q1 device is capable of driving different numbers of LEDs with accurate current driving and the

most-advanced diagnostics. The device is suitable for automotive cluster tell-tale lighting, gear-shifter PRNDL

indicators, and other safety-critical LED applications.

8.2 Typical Applications

8.2.1 Multiple Devices Connected in Cascade

The TLC6C5712-Q1 design supports multiple devices in cascaded daisy-chain mode. Each communication

sequence must only have one LATCH rising edge and, therefore, cannot be split into multiple smaller sequences.

VSUPPLY

OUT0

OUT11

SENSE

OUT0

OUT11

VCC

TLC6C5712-Q1

GND

PGND

MOSI

SDI

SDO

SDI

SDO

ERR

SCK

ERR

SCK

LATCH

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

MISO

LATCH

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

LATCH

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

Controller

IREF

R_IREF

图 106. Application Schematic for TLC6C5712-Q1 Devices Connected in Cascade

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TLC6C5712-Q1

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Typical Applications (接下页)

8.2.1.1 Design Requirements

For this design example, use the parameters listed in 表 55.

表 55. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

20 mA

(1)

I_{(LED_FULLRANGE)}

(2)

I_(LED)

16 mA

(1) I_{(LED_FULLRANGE)}is the maximum LED current allowed.

(2) I_(LED)is the required output driving current for this application.

8.2.1.2 Detailed Design Procedure

This design has multiple TLC6C5712-Q1 devices connected by a SPI daisy chain. Use 公式 5 to calculate the

reference resistor value.

V

1.229 V

0.02 A

(IREF)

R_(IREF)

=

´K_(OUT)

=

´ 500 = 30.725 kW

I_{(LED _FULLRANGE)}

(5)

(6)

Use 公式 6 to calculate the dot correction for each channel.

16

Dot correction =

´ 256 -1= 204, (0xCC)

20

8.2.1.3 Application Curves

图 107. PWM Delay and Output Rise Time

图 108. PWM Delay and Output Fall Time

CH3: PWM0, CH4: OUT0

8.2.2 Parallel Channels for Driving Higher Current

In some applications, capability to drive higher current is needed. To deliver higher current while maintaining

adjacent-short detection capability, channels with odd numbers can be shorted together; similarly, channels with

even numbers can be shorted together. If odd and even numbers are shorted together, the device reports a false

error during adjacent-pin short detection.

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VSUPPLY

OUT9 OUT11

OUT0 OUT2 OUT1 OUT3

VCC

OUT0 OUT2 OUT1OUT3

VCC

SENSE

TLC6C5712-Q1

GND

PGND

MOSI

SDI

SDO

SDI

SDO

ERR

SCK

ERR

SCK

LATCH

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

MISO

LATCH

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

LATCH

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

Controller

IREF

R_IREF

图 109. Application Schematic for TLC6C5712-Q1 Devices With Parallel Outputs

8.2.2.1 Design Requirements

For this design example, use the parameters listed in 表 56.

表 56. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

(1)

I_{(LED_FULLRANGE)}

20 mA

16 mA

2

(2)

I_(LED)

Channels in parallel

(1) I_{(LED_FULLRANGE)}is the maximum LED current allowed.

(2) I_(LED)is the required output driving current for this application.

8.2.2.2 Detailed Design Procedure

This design has multiple TLC6C5712-Q1 devices connected by a SPI daisy chain. Use 公式 7 to calculate the

reference resistor value.

V

1.229 V

(IREF)

R_(IREF)

=

´ K_(OUT)

=

´ 500 = 878 W

I_{(LED _FULLRANGE)}

0.14A / 2

No. of parallel channels

(7)

(8)

Use 公式 8 to calculate the dot correction for each channel.

140

Dot correction =

´ 256 -1= 255, (0xFF)

140

57

TLC6C5712-Q1

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www.ti.com.cn

9 Power Supply Recommendations

The TLC6C5712-Q1 device is qualified for automotive applications. Because of voltage-level limitations, the

device requires a first-stage power supply to provide LED and device power. V_CCand V_(SENSE)voltages can be

provided by the same voltage supply or independent voltage supplies. The supply voltage range is specified in

Recommended Operating Conditions.

10 Layout

10.1 Layout Guidelines

To prevent thermal shutdown, the junction temperature, T_J, must be less than 150°C. If the voltage drop across

the output channels is high, the device power dissipation can be large. The TLC6C5712-Q1 device has very

good thermal performance because of the thermal pad design; however, the PCB layout is also very important to

ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is

essential for the long-term reliability of the device.

Use the following guidelines when designing the device layout:

•

Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-

flow path from the package to the ambient is through copper on the PCB. Maximum copper density is

extremely important when no heat sinks are attached to the PCB on the other side of the package.

•

Add as many thermal vias as possible directly under the package ground pad to optimize the thermal

conductivity of the board.

Use either plated shut or plugged and capped vias for all the thermal vias on both sides of the board to

prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.

58

TLC6C5712-Q1

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ZHCSEM2A –AUGUST 2015–REVISED AUGUST 2015

10.2 Layout Example

Power ground

on top and

bottom layers

TLC6C5712-Q1

1

2

3

4

SCK

28

27

GND

V_CC

SDI

LATCH

SDO

IREF

PGND

26

25

24

5

ERR

SENSE

OUT11

OUT0

6

7

8

23

22

OUT1

OUT2

OUT10

OUT9

OUT8

21

20

OUT3

OUT4

9

10

OUT7

OUT6

PWM5

19

18

OUT5

PWM0

PWM1

11

12

13

14

17

16

15

PWM4

PWM3

PWM2

图 110. TLC6C7512-Q1 Layout Diagram

59

TLC6C5712-Q1

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www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档ꢀ


型号：	TLC6C5712-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 12 位恒流 LED 灌流驱动器驱动驱动器
文件：	总69页 (文件大小：2174K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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