TLC6C5716-Q1 [TI]
汽车类 16 通道完整诊断恒流 RGB LED 驱动器;
| 型号： | TLC6C5716-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 16 通道完整诊断恒流 RGB LED 驱动器 驱动 驱动器 |
| 文件： | 总55页 (文件大小：1001K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC6C5716-Q1
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
TLC6C5716-Q1 车用 16 通道完整诊断恒流 LED 驱动器
1 特性
TLC6C5716-Q1 器件是一款车用 16 通道恒定电流
1
RGB LED 驱动器，其可在 LED 进行测试。
TLC6C5716-Q1 器件可提供最高 50mA 的输出电流
（由外部电阻器设置）。该器件具有一个 7 位点校
正，每路输出 2 个范围。该器件还具有一个针对每个
颜色组输出的 8 位亮度控件。
•
符合面向汽车应用的 AEC-Q100 标准， 具有
器件温度等级 1：–40°C 至 125°C，TA
16 个恒定电流阱输出通道
–
•
–
–
–
50mA 最大输出电流
8V 最大输出电压
两个输出组：OUTRn、OUTBn
可通过 12 位、10 位或 8 位灰度控制调整每个输出的
亮度。该器件的电路能够检测各种系统故障，其中包括
LED 故障、邻近引脚短路故障、基准电阻器故障等。
压摆率控件具有 2 个可调节位置，可最大限度的降低
系统噪声。输出电平由一个 LED 组流向另一个 LED
组时，其变化存在一定的时间间隔。此时间间隔有助于
降低起动电流。SDI 和 SDO 引脚允许串联多个器件，
并通过 1 个串行接口控制。
•
•
•
输出电流调整
–
–
7 位点校正 (DC)，适用于每个通道
8 位亮度控制功能 (BC)，适用于每个组
集成 PWM 灰度发生器
–
–
可为每个单独通道进行 PWM 调光
可调节全局灰度模式：12 位、10 位和 8 位
保护和诊断
–
LED 开路检测 (LOD)、LED 短路检测 (LSD)、
器件信息(1)
输出 GND 短路检测 (OSD)
邻近的引脚短路 (APS) 检测
预热警告 (PTW)、热关断 (TSD)
器件型号
封装
封装尺寸（标称值）
–
–
–
TLC6C5716-Q1
HTSSOP (38)
6.20mm x 12.50mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
IREF 电阻器开路 (IOF) 及短路检测 (ISF) 和保
护
–
–
用于 GCLK 错误检测和 LOD_LSD 寄存器错误
检查的负位切换
典型应用原理图
VCC = 3 V - 5.5 V
LED Supply
LOD_LSD 电路自检
•
•
•
可编程输出转换率
输出通道组延迟
串行数据接口
VCC
SENSE
SDI
SCK
OUTR0
OUTB0
OUTR1
LATCH
GCLK
BLANK
SDO
µC
2 应用
•
•
•
•
•
•
•
车用仪表盘
车用局部调光显示屏
车用面板
ERR
OUTB6
OUTR7
OUTB7
车用 HVAC 控制面板
车用中心堆栈显示屏
车内 RGB 环境照明
车用线控换档和变速器
IREF
3 说明
汽车行业 需要 指示灯和 LCD 局部调光背光照明应
用。对于此类 应用，多数人认为多通道恒定电流 LED
驱动器是必要的。要求是获取相同的 LED 亮度和色
温。从系统级安全方面考虑，LED 驱动器必须能够检
测故障。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEB5
TLC6C5716-Q1
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 31
7.5 Programming .......................................................... 31
7.6 Register Maps......................................................... 37
Application and Implementation ........................ 48
8.1 Application Information............................................ 48
8.2 Typical Application ................................................. 48
Power Supply Recommendations...................... 50
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 8
6.7 Switching Characteristics.......................................... 9
6.8 Typical Characteristics............................................ 20
Detailed Description ............................................ 21
7.1 Overview ................................................................. 21
7.2 Functional Block Diagram ....................................... 21
7.3 Feature Description................................................. 22
8
9
10 Layout................................................................... 50
10.1 Layout Guidelines ................................................. 50
10.2 Layout Example .................................................... 50
11 器件和文档支持 ..................................................... 51
11.1 接收文档更新通知 ................................................. 51
11.2 社区资源................................................................ 51
11.3 商标....................................................................... 51
11.4 静电放电警告......................................................... 51
11.5 术语表 ................................................................... 51
12 机械、封装和可订购信息....................................... 51
7
4 修订历史记录
Changes from Original (July 2018) to Revision A
Page
•
•
•
•
•
Changed the description for GCLK in .................................................................................................................................... 4
Changed "indicates" to "initiates" in the Global Reset section ............................................................................................. 30
Added "the SID" to the Fault Mode section to identify the register where the overtemperature fault is latched.................. 31
Changed "APS time" to "APS detection time" for bit 199 in 表 12 ....................................................................................... 32
Changed "24 zones" to "16 zones" and "six TLC6C5716-Q1 units" to "eight TLC6C5716-Q1 units" in the Detailed
Design Procedure section ................................................................................................................................................... 49
•
•
•
Added a new sentence preceding 图 32 .............................................................................................................................. 49
Added the Application Curves section.................................................................................................................................. 49
Added two sentences to the Power Supply Recommendations section .............................................................................. 50
2
Copyright © 2018, Texas Instruments Incorporated
TLC6C5716-Q1
www.ti.com.cn
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
5 Pin Configuration and Functions
DAP PowerPAD™ Package
38-Pin HTSSOP With Exposed Thermal Pad
Top View
SDI
SCK
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SENSE
NC
2
LATCH
GCLK
GCLK
GCLK
NU
3
BLANK
4
V
CC
5
IREF
6
GND
7
NU
OUTR0
OUTB0
NU
8
OUTR7
OUTB7
NU
9
Thermal
Pad
10
11
12
13
14
15
16
17
18
19
OUTR1
OUTB1
NU
OUTR6
OUTB6
NU
OUTR2
OUTB2
NU
OUTR5
OUTB5
NU
OUTR3
OUTB3
SDO
OUTR4
OUTB4
ERR
Not to scale
NC – No internal connection
NU – Make no external connection
Copyright © 2018, Texas Instruments Incorporated
3
TLC6C5716-Q1
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Blank all outputs. BLANK low forces all channels off. The grayscale counter resets
and the grayscale PWM timing controller is initialized. BLANK high starts the
grayscale PWM timing controller. Channels are controlled by the PWM timing
controller.
BLANK
36
I
ERR
20
O
I
Open-drain error feedback
Clock input for the grayscale PWM counter, three pins are internally connected
together
GCLK
4, 5, 6
GND
IREF
LATCH
NC
33
34
3
—
I
Power ground
Reference-current pin for setting the full-scale output current
Latch-enable input pin
I
37
—
No internal connection
7, 10, 13,16,
23, 26, 29, 32
NU
—
O
O
Not used, keep floating
9, 12, 15, 18,
21, 24, 27, 30
OUTB0–OUTB7
OUTR0–OUTR7
Constant-current outputs for group B
Constant-current outputs for group R
8, 11, 14,17,
22, 25, 28, 31
SCK
2
I
I
Input pin for the data-shift clock
Serial data-in pin
SDI
1
SDO
19
38
35
—
O
I
Serial data-out pin
SENSE
VCC
LED supply sensing pin
I
Power supply pin
Thermal pad
—
Connect to ground to improve thermal performance
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
UNIT
VCC
6
Input voltage
SENSE
8
VCC + 0.3
VCC + 0.3
8
V
BLANK, GCLK, LATCH, SCK, SDI
ERR, IREF, SDO
Output voltage
V
OUTR0–OUTR7, OUTB0–OUTB7
OUTR0–OUTR7, OUTB0–OUTB7
Output current
50
mA
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–55
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6.2 ESD Ratings
VALUE
UNIT
(1)
Human-body model (HBM), per AEC Q100-002,
HBM ESD classification level H2
±2000
V(ESD)
Electrostatic discharge
V
All pins
±500
±750
Charged-device model (CDM), AEC Q100
classification C4B, per AEC Q100-011
Corner pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
4
Copyright © 2018, Texas Instruments Incorporated
TLC6C5716-Q1
www.ti.com.cn
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VCC
VSENSE
VO
Device supply voltage
LED supply voltage
Output voltage
3
5.5
V
V
8
8
V
VIL
Input logic-low voltage
Input logic-high voltage
High-level output current
BLANK, GCLK, LATCH, SCK, SDI
0
0.3 VCC
VCC
1
V
VIH
BLANK, GCLK, LATCH, SCK, SDI
0.7 VCC
V
IOH
SDO
mA
mA
mA
mA
°C
°C
SDO
1
IOL
Low-level input current
ERR
5
IO
Constant output sink current
Operating ambient temperature
Operating junction temperature
OUTR0–OUTR7, OUTB0–OUTB7
2
–40
–40
50
TA
TJ
125
150
Copyright © 2018, Texas Instruments Incorporated
5
TLC6C5716-Q1
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
www.ti.com.cn
6.4 Thermal Information
TLC6C5716-Q1
THERMAL METRIC(1)
DAP (HTSSOP)
UNIT
38 PINS
39.6
31.2
18.0
0.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
18.1
2.0
RθJC(bot)
(1) For more information about traditional and newthermalmetrics, see SemiconductorandICPackageThermal Metrics .
6.5 Electrical Characteristics
VCC = 3 V to 5.5 V, TJ=–40°Cto150°C,VSENSE = 5 V, GS = FFFh, BC = FFh, DC = 7Fh with upper dotcorrection(DC)range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VCC, GND)
SDI, SCK, LATCH = L, BLANK = L, GCLK
= L, VOUT = 1 V, IOUT = 2 mA
4.2
7.7
5.5
9
SDI, SCK, LATCH = L, BLANK = L, GCLK
= L, VOUT = 1 V, IOUT = 20 mA
SDI, SCK, LATCH = L, BLANK = H, GCLK
= 8 MHz, VOUT = 1 V, IOUT = 20 mA , auto-
repeat on
ICC
Supply current
mA
8.3
10
16
SDI, SCK, LATCH = L, BLANK = H, GCLK
= 8 MHz, VOUT = 1 V, IOUT = 50 mA , auto-
repeat on
13.5
LOGIC INPUTS (SDI, SCK, LATCH, GCLK, BLANK)
VI at SCK, LATCH, GCLK = VCC; VI at
SDI, SCK, LATCH, BLANK, GCLK = GND
IIkg
Input leakage current
–1
1
µA
Pulldown resistance at
BLANK, GCLK
Rpd
250
500
1.2
750
kΩ
CONTROL OUTPUTS (IREF, ERR, SDO)
VIREF
VOH
VOL
IREF voltage
RIREF = 0.96 kΩ
1.17
1.23
VCC
0.4
V
V
V
High-level output voltage
Low-level output voltage
At SDO, IOH = –1 mA
At SDO, IOL = 1 mA
VCC – 0.4
ERR pin open-drain voltage
drop
VERR
IERR = 4 mA
VERR = 5 V
0.1 VCC
1
V
Ilkg(ERR)
ERR pin leakage current
µA
OUTPUT STAGE
VCC = 3.6 V, IOUT = 50 mA
VCC = 3 V, IOUT = 50 mA
0.67
0.7
V(OUT,min)
Minimum output voltage
Ratio of output current to
V
K(OUT)
IREF current, K = I(OUTx)
I(IREF)
/
40
mA/mA
µA
BLANK = L, VOUT = 7 V, VSENSE = 7 V,
IOUT = 50 mA
Ilkg(OUT)
Output leakage current
0.1
6
Copyright © 2018, Texas Instruments Incorporated
TLC6C5716-Q1
www.ti.com.cn
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
Electrical Characteristics (continued)
VCC = 3 V to 5.5 V, TJ=–40°Cto150°C,VSENSE = 5 V, GS = FFFh, BC = FFh, DC = 7Fh with upper dotcorrection(DC)range
(unless otherwise noted)
PARAMETER
CHANNEL ACCURACY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT = 1 V, RIREF = 24 kΩ
1.86
46.5
7
2
50
10
2.14
53.5
13
I(OUT)
Constant output current
VOUT = 1 V, RIREF = 0.96 kΩ
mA
VOUT = 1V, RIREF open or short
Current accuracy (channel- VOUT = 1 V, IOUT = 50 mA
to-channel in same color
–4%
4%
(1)
ΔI(Ch-Ch)
VOUT = 1 V, IOUT = 2 mA
group)
–4%
4%
VOUT= 1 V, IOUT = 50 mA
VOUT = 1 V, IOUT = 2 mA
VOUT = 1 V, IOUT = 50 mA
VOUT = 1 V, IOUT = 2 mA
VOUT = 1 V, IOUT = 50 mA
VOUT = 1 V, IOUT = 2 mA
VOUT = 1 V to 3 V, IOUT = 50 mA
VOUT = 1 V to 3 V, IOUT = 2 mA
–4%
–4%
–7%
–7%
–0.7
–0.7
–0.7
–0.7
4%
4%
7%
7%
0.7
0.7
0.7
0.7
Current accuracy (device-
to-device)
(2)
(3)
ΔI(Dev-Dev)
Current accuracy (channel-
to-ideal output)
ΔI(Ch-Ideal)
(4)
ΔI(OUT-VCC)
Line regulation
Load regulation
%/V
(5)
ΔI(OUT-VOUT)
PROTECTION CIRCUITS
LED open-circuit detection
LOD_VOLTAGE = 0b
LOD_VOLTAGE = 1b
0.275
0.48
0.3
0.5
0.32
0.52
VLOD
V
threshold
(1) Channel to channel accuracy in the same color group iscalculated by the formula below. (X = color group; i,j = 0 to 7 )
≈
∆
∆
∆
’
÷
8ìIOUTXi
÷
DI(Ch-Ch)
=
-1 ì100%
7
÷
I
∆ ƒ OUTXj
÷
◊
j=0
«
(2) Device to device accuracy is calculated by the formulabelow.
7
≈
’
÷
÷
÷
÷
÷
I
+ IOUTBi
(
)
∆ ƒ
OUTRi
i=0
∆
-IOUT,ideal
16
IOUT,ideal
∆
∆
∆
DI(Dev-Dev)
=
ì100%
∆
∆
÷
÷
V
IREF
IOUT,ideal
=
ìK(OUT)
RIREF
(3) Channel to ideal accuracy is calculated by the formulabelow.
≈
’
IOUTXi
DI(Ch-Ideal)
=
-1 ì100%
∆
∆
÷
÷
IOUT,ideal
«
◊
(4) Line regulation accuracy is calculated by the formulabelow.
≈
’
I(OUTXi,VCC=5.5V -I(OUTXi,VCC=3V
100
)
)
∆
∆
«
÷
÷
◊
DI(OUT-VCC)
=
ì
% / V
I(OUTXi,VCC=3V
5.5 - 3
)
(5) Load regulation accuracy is calculated by the formulabelow.
≈
’
I(OUTXi,VOUT=3V -I(OUTXi,VOUT=1V
100
)
)
∆
∆
«
÷
÷
◊
DI(OUT-VOUT
=
ì
% / V
)
I(OUTXi,VOUT=1V
3 -1
)
Copyright © 2018, Texas Instruments Incorporated
7
TLC6C5716-Q1
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
www.ti.com.cn
Electrical Characteristics (continued)
VCC = 3 V to 5.5 V, TJ=–40°Cto150°C,VSENSE = 5 V, GS = FFFh, BC = FFh, DC = 7Fh with upper dotcorrection(DC)range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSENSE
–
VSENSE
–
VSENSE
–
LSD_VOLTAGE = 0b
0.4
0.3
0.2
LED short-circuit detection
threshold
VLSD
V
VSENSE
–
VSENSE
–
VSENSE
–
LSD_VOLTAGE = 1b
VCC = 5 V
0.8
0.7
0.6
IREF resistor open-circuit
detection threshold
IIREF_OC
8
2
10
12
µA
µA
IREF resistor open-circuit
detection threshold
hysteresis
IIREF_OCHYS
VCC = 5 V
VCC = 5 V
VCC = 5 V
5
IREF resistor short-circuit-
detection threshold
IIREF_SC
2.7
0.3
3.2
mA
mA
IREF resistor short-circuit-
detection threshold
hysteresis
IIREF_SCHYS
Pre-thermal warning flag
threshold
TPTW
125
150
135
10
145
170
°C
°C
°C
°C
Pre-thermal warning flag
hysteresis
THYS_PTW
TSD
Thermal error flag
threshold
160
10
Thermal error flag
hysteresis
THYS_TEF
6.6 Timing Requirements
VCC = 3 V to 5.5 V,TJ=–40°Cto150°C.
MIN
NOM
MAX
UNIT
MHz
MHz
ns
fCLK(SCK)
SCK data-shift clock frequency
4
8
fCLK(GCLK) GCLK grayscale clock frequency
tWH0
tWL0
tWH1
tWL1
tWL2
tWH3
tWL3
tSU0
tSU1
tSU2
SCK high pulse duration
SCK low pulse duration
LATCH high pulse duration
LATCH low pulse duration
BLANK pulse duration
60
60
80
80
80
40
40
55
60
200
ns
ns
ns
ns
GCLK high pulse duration
GCLK low pulse duration
SDI↑ – SCK↑ setup time
BLANK↑– GCLK↑ setup time
LATCH↑–SCK↑ setup time
ns
ns
ns
ns
ns
LATCH↑ for GS data–GCLK↑when display timing reset mode is disabled,
setup time
tSU3
tSU4
90
ns
ns
LATCH↑for GS data–GCLK↑ when display timing reset mode is enabled,
setup time
150
tH0
tH1
tH2
tRI0
tRI1
tFI0
tFI1
SCK↑– SDI↑hold time
SCK↑– LATCH↑ hold time
SCK↑–LATCH↓ hold time
SDI SCK LATCH rise time
GCLK rise time
55
85
55
ns
ns
ns
ns
ns
ns
ns
50
30
50
30
SDI SCK LATCH fall time
GCLK fall time
8
Copyright © 2018, Texas Instruments Incorporated
TLC6C5716-Q1
www.ti.com.cn
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
6.7 Switching Characteristics
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Rise time from 10% VSDO to 90%
VSDO
tro0
tro1
tro2
tfo0
tfo1
60
ns
Rise time from 10% VOUT to 90%
VOUT
IOUT = 50 mA, SLEW_RATE = 0b
IOUT = 50 mA, SLEW_RATE = 1b
200
100
30
ns
ns
ns
ns
Rise time from 10% VOUT to 90%
VOUT
60
140
Fall time from 90% VSDO to 10%
VSDO
Fall time from 90% VOUT to 10%
VOUT
IOUT = 50 mA , SLEW_RATE = 0b
IOUT = 50 mA, SLEW_RATE = 1b
200
Fall time from 90% VOUT to 10%
VOUT
tfo2
30
100
130
80
140
180
130
200
220
ns
ns
ns
tpd0
tpd1
Propagation delay, SCK↑to SDO
Propagation delay, LATCH↑to
SDO
Propagation delay, BLANK↓ to
OUTR0, -B0, -R4, -B4 off
tpd2
tpd3
tpd4
tpd5
tpd6
10
80
120
160
200
250
280
260
260
330
370
400
ns
ns
ns
ns
ns
Propagation delay, GCLK↑ to
OUTR0, -B0, -R4, -B4 on
Propagation delay, GCLK↑ to
OUTR1, -B1, -R5, -B5 on
120
160
190
Propagation delay, GCLK↑ to
OUTR2, -B2, -R6, -B6 on
Propagation delay, GCLK↑ to
OUTR3, -B3, -R7, -B7 on
Changing by dot correction control
(control data are 0Ch→72h or 72h→0Ch
with upper DC range), BC -R, -B = FFh
Propagation delay, LATCH↑ to
VOUT
tpd7
tpd8
tpd9
10
10
80
130
5
120
200
ns
ns
ns
Changing by global brightness control
(control data are 19h→E6h or E6h→19h
with DC -Rn, -Bn = 7Fh with upper DC
range
Propagation delay, LATCH↑ to
VOUT
Propagation delay, LATCH↑ to
APS register and APS flag
change
SINK_CURRENT = 0b
Propagation delay, LATCH↑ to
APS register and APS flag
change
tpd10
SINK_CURRENT = 1b
10
24
ns
ns
Propagation delay, LATCH↑ to
LOD self-flag change
tpd11
No failure in LOD-LSD detector circuit
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GSR0
0A
GSB7
11B
GSB7
10B
GSB7
9B
GSB7
8B
GSB7
7B
GSR0
3B
GSR0
2B
GSR0
1B
GSR0
0B
GSB7
11C
GSB7
10C
GSB7
9C
GSB7
8C
GSB7
7C
GSB7
6C
GSB7
5C
GSB7
4C
GSB7
3C
SDI
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH1
tWH1
LATCH
tSU3
BLANK
GCLK
SDO
tSU1
fCLK(GCLK)
tWL2
tpd0
tpd1
GSB7
11A
GSB7
10A
GSB7
9A
GSB7
8A
GSB7
7A
GSB7
6A
GSR0
2A
GSR0
1A
GSR0
0A
GSB7
11B
GSB7
10B
GSB7
9B
GSB7
8B
GSB7
7B
GSB7
6B
GSB7
5B
GSB7
4B
GSB7
3B
GSB7
2B
GSB7
1B
tpd3
tpd4
tD5
tpd2
OUTR0/4
OUTB0/4
Output Voltage
OFF
ON
tro1
tfo1
OUTR1/5
OUTB1/5
ON
OFF
Output Voltage
Output Voltage
OUTR2/6
OUTB2/6
ON
OFF
tD6
OUTR3/7
OUTB3/7
Output Voltage
ON
OFF
图 1. Grayscale Data (GS) Write
10
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GSR0
SDI
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
DCR0
3B
DCR0
2B
DCR0
1B
DCA0
0B
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
0A
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
LATCH
BLANK
GCLK
SDO
fCLK(GCLK)
tWL2
tSU1
tpd0
tro0, tfo0
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
CMD
6B
CMD
5B
CMD
4B
CMD
3B
CMD
2B
CMD
1B
tpd3
tpd4
tpd5
tpd6
tpd7,tpd8
tpd2
OUTR0/4
OUTB0/4
OFF
ON
tfo1
OUTR1/5
OUTB1/5
OFF
ON
OUTR2/6
OUTB2/6
ON
OFF
OUTR3/7
OUTB3/7
OFF
ON
图 2. Function-Control, Brightness-Control, and Dot-Correction (FC-BC-DC) Data Write
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12bit Command code CMD11 to CMD0 is 5AFh, indicate this is a GS Read command, the original GS data in GS data latch are loaded into common shift register
GSR0
0A
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
CMD
2C
SDI
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
LATCH
SDO
tpd0
tro0, tfo0
tpd1
GSB7
2
GSB7
1
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11B
GSB7
11
GSB7
10
GSB7
9
GSB7
8
GSB7
7
GSB7
6
GSB7
5
GSB7
4
GSB7
3
Since decoded as GS Read command, the grayscale data in GS data latch is latched into common shift register at this moment
图 3. Grayscale (GS) Data Read
12bit Command code CMD11 to CMD0 is 5A3h, indicate this is a SID Read command, the 96bits LOD1/2, LSD1/2 detection result, 1bit NEG1, 1bit NEG2, 10bit
Error Status and 24bits Adjacent pin short result are loaded into common shift register
CMD
2C
GSR0
0A
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
SDI
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
LATCH
SDO
tpd0
tro0, tfo0
tpd1
Reserv
ed
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11B
LOD2
OUTB7
LOD2
OUTB6
LOD2
OUTB5
LOD2
OUTB4
LOD2
OUTB3
LOD2
OUTB2
LOD2
OUTB1
LOD2
OUTB0
Reserv
ed
Since decoded as SID Read command, the LOD1/2, LSD1/2 detection result, NEG1, NEG2, Error Status and Adjacent pin
short result in the corresponding registers are latched into common shift register at this moment
图 4. Status Information Data (SID) Read
12
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ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
12bit Command code CMD11 to CMD0 is 53Ah, indicate this is a APS Check command, IC will automatically detect all the adjacent pin short condition, and set APS
register(16bits) and APS_Flag in Error status register. BLANK should be kept low during this test
GSR0
0A
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
SDI
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
LATCH
BLANK
tpd9, tpd10
APS Register
Previous Data
Updated Data
Updated Data
APS_Flag
(Error Status Register)
Previous Data
Since decoded as APS Check command, the adjacent pin short self test is executed, the result is latched into APS register and APS_FLAG of
Error Status register at this moment
图 5. Adjacent-Pin-Short (APS) Check
12bit Command code CMD11 to CMD0 is 55Ah, indicate this is a NEG_BIT Toggle command, the Negate bit will be toggled and LOD_LSD data will be inverted
GSR0
SDI
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
0A
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
LATCH
tpd12
Negate Bit
Previous Data
Updated Data
Since decoded as NEG_BIT Toggle command, the Negate bit is toggled at this moment and
LOD_LSD register value will be inverted.
图 6. Negate Bit Toggle
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12bit Command code CMD11 to CMD0 is 535h, indicate this is a LOD_LSD Self Test command, IC will execute LOD_LSD detector circuit self test and set LOD_LSD_FLAG
in Error Status register. BLANK should be kept low during this test
GSR0
0A
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
SDI
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
LATCH
BLANK
tpd11
LOD_LSD_FLAG
(Error Status Register)
Previous Data
Updated Data
Since decoded as LOD_LSD Self Test command, the LOD_LSD detector circuit self-test is executed, the result is latched into LOD_LSD_FLAG of
Error Status register at this moment
图 7. LOD_LSD Self-Test
12bit Command code CMD11 to CMD0 is 5ACh, indicate this is a FC-BC-DC Read command. the 205bits FC-BC-DC data are loaded into common shift register; This reading
function can also be achieved by latching GS data from common shifter to GS data latch
GSR0
0A
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
SDI
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
LATCH
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
tpd1
Common Shift Register
Previous Data
Lowest 205bit are updated with latest FC-BC-DC data
Since decoded as FC-BC-DC Read command, the data in FC-BC-DC data latch are latched
into common shift register at this moment
图 8. Function Control, Brightness Control, and Dot Correction (FC-BC-DC) Data Read
14
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ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
12bit Command code CMD11 to CMD0 is A53h, indicate this is a ERROR Clear command, the 96bits LOD1/2, LSD1/2 detection result, 1bit NEG1, 1bit NEG2, 10bit Error
Status and 24bits Adjacent pin short result are loaded into common shift register, and then the Error status register and APS register will be reset to 0.
GSR0
0A
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
SDI
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
LATCH
tpd1
APS Register
Previous Data
Reset to Zero
Reset to Zero
Error Status Register
Previous Data
tpd0
tro0, tfo0
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11B
LOD2
OUTB7
LOD2
OUTB6
LOD2
OUTB5
LOD2
OUTB4
LOD2
OUTB3
LOD2
OUTB2
LOD2
OUTB1
LOD2
OUTB0
Reserv
ed
Reserv
ed
SDO
Since decoded as ERROR Clear command, LOD1/2, LSD1/2 detection result, NEG1, NEG2, Error Status and Adjacent pin
short result are loaded into common shift register, and then the Error status register and APS register will be reset to 0.
图 9. ERROR Clear
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12bit Command code CMD11 to CMD0 is A5Ch, indicate this is a Global Reset command, not only the Error status register, LOD-LSD register and APS register will be reset to default, but
also GS data, FC-BC-DC data will be reset to default. Besides, all output channels will be turn off, PWM timing will be initialized. This command has the same function as power on reset
GSR0
0A
CMD
11B
CMD
10B
CMD
9B
CMD
8B
CMD
7B
Don‘t
Care
Don‘t
Care
Don‘t
Care
Don‘t
Care
CMD
11C
CMD
10C
CMD
9C
CMD
8C
CMD
7C
CMD
6C
CMD
5C
CMD
4C
CMD
3C
SDI
tSU0
tH0
fCLK(SCK)
tWH0
tWL0
tH1
tSU2
SCK
285
1
2
3
4
5
284
286
287
288
1
2
3
4
5
6
7
8
9
10
tH2
tWL1
LATCH
LOD-LSD Register
Previous Data
Previous Data
Previous Data
Reset to default
Reset to default
Reset to default
Channel Off
APS Register
Error Status Register
OUTn
Since decoded as Global Reset command, the Error status register, LOD-LSD register, APS register, GS data latch and FC-BC-DC data latch will
be reset to default at this moment. Besides, all output channels will be turn off, PWM timing will be initialized at this moment.
图 10. Global Reset
16
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ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
GS counter starts to count GCLK after BLANK goes high
GCLK
2047
1
2
3
4
5
2046
2048
2049
2050
2051
2052
4093
4094
4095
4096
4097
4098
1
2
3
4
BLANK
OFF
ON
OUTn Output Voltage
GS data = 000h
Output Voltage
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OUTn
OFF
GS data = 001h
OUTn
OFF
Output Voltage
Output Voltage
ON
OFF
GS data = 002h
OUTn
OFF
OFF
ON
ON
GS data = 003h
OUTn
OFF
Output Voltage
Output Voltage
GS data = 7FFh
OUTn
ON
ON
OFF
GS data = 800h
Output Voltage
OUTn
OFF
GS data = 801h
OFF
OUTn
Output Voltage
Output Voltage
ON
ON
GS data = FFDh
OUTn
OFF
GS data = FFEh
Output Voltage
OUTn
OFF
OUTx does not turn on again until BLANK goes low once when disable auto repeat mode
ON
GS data = FFFh
OUTn turns on at first rising edge of GCLK after BLANK goes high except when
Grayscale data is zero.
Note1: The internal blank signal is generated when LATCH is input for GS data with display timing reset enable. Also the signal is generated at
4096th GCLK when auto repeat mode is enabled. BLANK can be connected to VCC when TIMING_RESET or AUTO_REPEAT is enabled.
图 11. 12-Bit Mode PWM Counter Without Auto-Repeat Mode
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GS counter starts to count GSCKR/G/B after BLANK goes high level.
GCLK
257
1
2
3
4
255
256
258
1023
1024
1025
1026
4093
4094
4095
4096
4097
4098
1
2
3
4
BLANK
OUTn
8-bit Mode
GS data = FFFh
ON
ON
OFF
ON
ON
ON
Output Voltage
Output Voltage
Output Voltage
OFF
OUTn
10-bit Mode
GS data = FFFh
OUTn
12-bit Mode
OFF
ON
GS data = FFFh
图 12. 8-, 10-, 12-Bit Mode PWM Counter Without Auto-Repeat Mode
GS counter starts to count GSCKR/G/B after BLANK goes high level.
GCLK
1
257
1
2
255
256
1024
1025
4095
4096
4095
4096
1
3
1
BLANK
OUTn
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Output Voltage
8-bit Mode
OFF Period * 15
OUTn is forced off even if
GS data is more than 0FFh.
OFF Period * 11
GS data = 0FFh - FFFh
OFF Period * 2
OFF
OFF
OFF
OFF
Output Voltage
Output Voltage
OFF
OUTn
10-bit Mode
OFF
OFF
OUTn is forced off even if
GS data is more than 3FFh.
OFF Period * 3
OFF Period * 2
GS data = 3FFh - FFFh
OUTn
12-bit Mode
ON
GS data = FFFh
图 13. 8-, 10-, 12-Bit Mode PWM Counter With Auto-Repeat Mode
18
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ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
GCLK
4093
1
2
3
8
9
4092
4094
4095
4096
1
2
3
4
5
6
7
8
9
10
LATCH
LOD1-LSD1 registers are updated
at 9th GCLK rising edge
LOD1-LSD1
Old LOD1-LSD1 Data
New LOD1-LSD1 Data
LOD2-LSD2 registers are updated
at 4095th GCLK rising edge
LOD2-LSD2
Old LOD2-LSD2 Data
New LOD2-LSD2 Data
图 14. LOD-LSD Register Update Timing
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6.8 Typical Characteristics
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
-40°C
25°C
125°C
0
0
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
RIREF (kW)
VOUT (V)
D006
D005
VCC = 3.3 V
BC = FFh
GS = FFFh
DC = 7Fh in high range
图 15. I(OUT)max vs RIREF
图 16. IOUT vs VOUT
55
50
45
40
35
30
25
20
15
10
5
55
High DC Range
Low DC Range
-40°C
25°C
125°C
50
45
40
35
30
25
20
15
0
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
DC
DC
D003
D004
VCC = 3.3 V
BC = FFh
TA = 25°C
GS = FFFh
VCC = 3.3 V
BC = FFh in the high DC range
GS = FFFh
图 18. IOUT vs Dot Correction at Different Ambient
Temperatures
图 17. IOUT vs Dot Correction in Different DC Ranges
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
DC = 7Fh with High Range
DC = 00h with High Range
DC = 7Fh with Low Range
-40°C
25°C
125°C
0
0
0
30
60
90
120 150 180 210 240 270
BC
0
30
60
90
120 150 180 210 240 270
BC
D001
D002
VCC = 3.3 V
TA = 25°C
GS = FFFh
VCC = 3.3 V
DC = 7Fh with high range
GS = FFFh
图 19. IOUT vs Brightness Control in Different DC Ranges
图 20. IOUT vs Brightness Control at Different Ambient
Temperatures
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7 Detailed Description
7.1 Overview
In automotive indicator and local dimming backlighting applications, the demand for multi-channel constant
current LED drivers is increasing to achieve uniformity of LED brightness and color temperature. System-level
safety considerations require fault detection capability and device self-check features.
The TLC6C5716-Q1 is an automotive 16-channel constant-current LED driver with LED diagnostics. The
TLC6C5716-Q1 provides up to 50 mA of output current set by an external resistor. The current can be adjusted
by 7-bit dot correction with two subranges for individual outputs, and an 8-bit brightness control for all the outputs
of each color group. The brightness can be adjusted individually for each channel through a 12-, 10-, or 8-bit
grayscale control. Fault-detection circuits are available to detect system faults including LED faults, adjacent-pin
short faults, reference-resistor faults, and more. Negate bit toggle and LOD-LSD self-test provide a device self-
check function to improve system reliability. Configurable slew-rate control optimizes the noise generation of the
system and improves the system EMC performance. Output-channel group delay helps to reduce inrush current
to optimize the system design. The SDI and SDO pins allow more than one device to be connected in a daisy
chain for control through one serial interface.
7.2 Functional Block Diagram
ERR
LED_ERR_MASK
IOF/ISF
LOD-LSD Self Test
LOD-LSD Self
Test
Thermal
Detection
Logic
LOD-LSD info
NEG-BIT Toggle
2
3
2
APS Check
3
APS Detection
Error Status Register
LOS-LSD info
Negate Bit
24
APS_Current
LOD-LSD Register
99
APS Register
24
10
SDI
SCK
SOUT
288-bit Common Shift Register
Lower 205
288
288
Read GS
Latch
GS
Latch
Selection
288-bit GS Data
LATCH
205
SENSE
VCC
Latch
FC
12-bit CMD
APS_CURRENT
Command
Decoder
205-bit FC-BC-DC Data
3
GS Read
SID Read
APS Check
...
288
205
4
GCLK
GS Counter
12bit/10bit/8bit PWM Timing Control
48
200
BLANK
IREF
197
Reference
Current
GND
16-CH Constant Sink with Group Delay
3
ISF/IOF
IREF Open/
Short Detector
LED Open/Short Detection
...
OUTR0
OUTB0
OUTB7
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7.3 Feature Description
7.3.1 Maximum Constant-Sink-Current Setting
LED full-scale current can be set using an external resistor connected between the IREF pin and GND. The
RIREF resistor value is calculated with the following formula.
V
IREF
RIREF = K ì
I(OUT)max
where
•
•
•
VIREF is the reference voltage
K is the IREF current to output current ratio
I(OUT)max is full-scale current for each output
(1)
图 15 shows the reference-resistor calculation curve.
7.3.2 Brightness Control and Dot Correction
The TLC6C5716-Q1 device implements an 8-bit group brightness control (BC) and 7-bit individual dot correction
(DC) to calibrate the output current. The 16 output channels are divided into two groups: OUTRn and OUTBn.
Each group contains 8 output channels. There are two configurable ranges for the DC value of each group. One
is the low DC range with output current from 0 to 66.7% I(OUT)max, the other is the high DC range with output
current from 33.3% I(OUT)max to 100% I(OUT)max. The IREF resistor, BC, DC, and DC range together determine the
channel output current, as shown in 图 21. 公式 2 and 公式 3 are the detailed output current calculation formulas.
公式 2 determines the output sink current for each group when DC is in high adjustment range.
1
2
3
DC
BC
IOUT = ( ìI(OUT)max
+
ìI(OUT)max
ì
)ì
127 255
3
(2)
(3)
公式 3 determines the output sink current for each group when DC is in the low adjustment range.
2
3
DC BC
IOUT
=
ìI(OUT)max ì ì
127 255
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Feature Description (接下页)
OUTR0
Individual DC
7-bit DC
GND
OUTR1
Group BC
High/
Low
DC
Digital
8-bit BC
Setting
7-bit DC
Range
GND
I(OUT)max
IREF
OUTR7
7-bit DC
GND
GND
OUTR
OUTB
图 21. Brightness Control and Dot Correction Block Diagram
7.3.3 Grayscale Configuration
The TLC6C5716-Q1 device implements a grayscale configuration function to realize an individual PWM dimming
function for the output channels. The grayscale has three global configuration modes, 12-bit, 10-bit and 8-bit. The
GCLK input provides the clock source for the internal PWM generator. The GS counter counts the GCLK number
and compares the number with channel grayscale register value, and the output channel turns off when the GS
counter value reaches the grayscale register value. 图 22 shows the detailed block diagram of the PWM
generator.
To start a new PWM cycle, users can use two methods. One is to toggle the BLANK pin after the GS counter
reaches the maximum count value, because BLANK low resets the GS counter and BLANK high restarts the GS
counter. Another is to pull BLANK high and set the AUTO_REPEAT&TIMING_RESET register bit to 1, 表 12.
The PWM starts a new cycle automatically after the GS counter reaches its maximum count value.
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Feature Description (接下页)
GS Counter
Max Count
OUTB1_GS
OUTB1_GS
OUTR1_GS
OUTR1_GS
Time
Time
Time
OUTR1 Current
25% Duty Cycle
OUTB1 Current
75% Duty Cycle
12-bit GS mode, Max Count = 4096
10-bit GS mode, Max Count = 1024
8-bit GS mode, Max Count = 256
VLED
OUTn
OUTn_GS [11:0]
PWM Generator
GS Counter
12/10/8-Bit
GCLK
GS Mode
GND
图 22. PWM Generator
7.3.3.1 PWM Auto Repeat
The PWM auto repeat function is configured by the AUTO_REPEAT bit. The AUTO_REPEAT bit is 0 by default,
and the PWM auto repeat function is disabled in this condition. The PWM cycle only executes once, so users
must toggle BLANK to start a new PWM cycle. 图 11 and 图 12 show the PWM operation in this mode. When the
AUTO_REPEAT bit is 1, the PWM auto repeat function is enabled, and the PWM cycle automatically repeats as
long as BLANK is high and GCLK is present, as shown in 图 13.
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Feature Description (接下页)
7.3.3.2 PWM Timing Reset
The PWM timing reset function is configured by the TIMING_RESET bit. The PWM timing reset function can
restart a PWM cycle with a newly configured duty cycle after a GS data write. The TIMING_RESET bit is 0 by
default, and the PWM timing reset function is disabled in this condition. The PWM cycle is not influenced by a
GS data write, and the newly configured PWM duty cycle only is valid after the current PWM cycle finishes.
When the TIMING_RESET bit is 1, the PWM timing reset function is enabled, and the PWM cycle restarts with
new PWM duty cycle immediately after the GS data write.
7.3.4 Diagnostics
The TLC6C5716-Q1 device integrates a full LED diagnostics function, such as LED-open detection (LOD), LED-
short detection (LSD), and output short-to-GND detection (OSD), which helps to improve the system safety.
7.3.4.1 LED Diagnostics
An LOD-LSD detection circuit compares the output voltage with the LOD threshold and LSD threshold, and 表 1
shows the output results.
表 1. LOD-LSD Detection
DETECTOR OUTPUT BIT VALUE
OUTPUT VOLTAGE CONDITION
LOD
LSD
VOUTn < LOD_VOLTAGE
1
0
0
0
0
1
LOD_VOLTAGE < VOUTn < LSD_VOLTAGE
VOUTn > LSD_VOLTAGE
The LOD threshold can be configured by the LOD_VOLTAGE bit in the FC-BC-DC register, 表 12 . The threshold
is 0.3 V when LOD_VOLTAGE = 0, and the threshold is 0.5 V when LOD_VOLTAGE = 1.
表 2. LOD Threshold
LOD_VOLTAGE BIT
LOD THRESHOLD
0 (Default)
1
0.3 V
0.5 V
The LSD threshold is configured by the LSD_VOLTAGE bit in the FC-BC-DC register, 表 12. The threshold is
VVSENSE – 0.3 V when LSD_VOLTAGE = 0, and the threshold is VVSENSE – 0.7 V when LSD_VOLTAGE = 1.
表 3. LSD Threshold
LSD_VOLTAGE BIT
LSD THRESHOLD
VSENSE – 0.3 V
VSENSE – 0.7 V
0 (Default)
1
There are two sets of LOD-LSD registers in the device, one is the LOD1-LSD1 registers, the other is the LOD2-
LSD2 registers. Each group of registers consists of 24 bits of LOD data and 24 bits of LSD data, corresponding
to the 24 channel outputs. The device updates the LOD1-LSD1 registers at the 9th GCLK rising edge. The
device updates the LOD2-LSD2 registers at the Nth GCLK rising edge. N is the maximum GCLK number in a
PWM period minus 1, see 表 4.
To detect all kinds of LED faults, the output channel should turn ON at the 9th GCLK rising edge, and turn OFF
at the Nth GCLK rising edge.
The device integrates an internal pullup circuit for LED diagnostics, shown in 图 23. The circuit turns off during
the channel on-state, but turns on to charge the output pin during the channel-off state. For an LED-short fault,
both LSD1 and LSD2 are 1. For an LED-open fault, both LOD1 and LSD2 are 1. For an output short-to-GND
fault, both LOD1 and LOD2 are 1. 表 5 shows the details.
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VSENSE
VSENSE
OUTn
Channel OFF
OUTn
Channel ON
GND
GND
图 23. Internal Pullup Circuit
表 4. LOD-LSD Register Latch Timing
GS COUNTER MODE
LOD1-LSD1
LOD2-LSD2
12-bit
10-bit
8-bit
9th GCLK rising edge
9th GCLK rising edge
9th GCLK rising edge
4095th GCLK rising edge
1023rd GCLK rising edge
255th GCLK rising edge
表 5. LED Status Lookup Table
LOD-LSD RESULT
LED STATUS
LOD1-LSD1 Updated at 9th GCLK
LOD2-LSD2 Updated at Nth GCLK(1)
LOD1
LSD1
LOD1
LSD1
LOD1
LSD1
LOD1
LSD1
0
0
1
0
0
1
1
0
LOD2
LSD2
LOD2
LSD2
LOD2
LSD2
LOD2
LSD2
0
1
0
1
0
1
1
0
LED Ok
LED open
LED short
Output short-to-GND
(1) N = 4095 for 12-bit GS mode, 1023 for 10-bit GS mode, 255 for 8-bit GS mode.
In some cases, users may need to turn off output channels before the 9th GCLK to disable the output channels,
or turn on the output channels at the Nth GCLK to get more brightness. LOD_LSD faults are reported as shown
in 表 6. Users can ignore the fault according to the GS register setting value.
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表 6. PWM Status Lookup Table
LOD-LSD Result
PWM STATUS
LOD1-LSD1 UPDATED AT 9th GCLK
LOD2-LSD2 UPDATED AT Nth GCLK
(1)
LOD1
LSD1
LOD1
LSD1
LOD1
LSD1
0
0
0
1
0
0
LOD2
LSD2
LOD2
LSD2
LOD2
LSD2
0
1
0
1
0
0
PWM OK
Channel off before 9th
GCLK
Channel on at Nth GCLK
(1) N = 4095 for 12-bit GS mode, 1023 for 10-bit GS mode, 255 for 8-bit GS mode
The LOD_LSD status is updated every PWM cycle. 图 14 is an example of the LOD-LSD register update timing
for the 12-bit GS mode.
7.3.4.2 Adjacent-Pin-Short Check
The device implements an APS check function to detect the adjacent-pin-short failure during system initialization.
TI recommends to do an APS check when the channels are all off. The APS check can be executed by writing
the APS check command.
If there is no adjacent-pin-short failure, the device passes the APS check and 011b is latched into the APS FLAG
in the error status register. The 24-bit APS register is 0. If there are two adjacent pins shorted, 110b is latched
into the APS_FLAG in the error status register. The corresponding bit in the APS register is set to 1. Users can
read out the 24-bit data from APS register to check if two channels have this short fault. 表 7 shows the details of
the APS_FLAG and APS register. 表 8 shows the bit arrangement of APS register. To read these APS
information, see Status Information Data Read in the Status Information Data Read section.
表 7. APS Flag and APS Register
REGISTER
VALUE
011b
110b
0b
DESCRIPTION
Pass, no adjacent pins short
APS_FLAG
Fail, adjacent pins short
This OUTn pin is not shorted with other pins
This OUTn pin is shorted with other pins
Bit in APS register (24-bit total)
1b
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表 8. Bit Arrangement of APS register
BITS OF APS REGISTERS
CORRESPONDING OUTPUTS
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
OUTB7
OUTB6
OUTB5
OUTB4
OUTB3
OUTB2
OUTB1
OUTB0
Pin 7
Pin 10
Pin 13
Pin 16
Pin 23
Pin 26
Pin 29
Bit 8
Pin 32
Bit 7
OUTR7
OUTR6
OUTR5
OUTR4
OUTR3
OUTR2
OUTR1
OUTR0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The APS_FLAG and APS registers are all 0 by default. After an APS check command, the APS_FLAG should be
011b or 110b. Otherwise, there is a failure on the APS check circuit. If the APS check result fails, the ERR pin is
pulled low, the APS_FLAG value is 110b and the ERR pin status stays unchanged until the fault is removed and
the user executes an ERROR clear command. 图 5 and 图 4 show more detail.
As different LEDs have different parasitic capacitance, to make sure the APS Check function is suitable for all
kinds of LEDs, the device provides two configuration bits for APS current and APS time. The APS current is
selected by APS_CURRENT as 表 9. The APS time is selected by APS_TIME as shown in 表 10.
表 9. APS Current Selection
APS_CURRENT BIT
APS CURRENT
20 µA
0b
1b
40 µA
表 10. APS Time Selection
APS_TIME BIT
ADJACENT-PIN SHORT-DETECTION TIME
0b
1b
10 µs
20 µs
7.3.4.3 IREF-Short and IREF-Open Detection
To protect the device from reference resistor short and open faults, the device integrates IREF short and open
protection. In an IREF short or open fault condition, the device reports the fault and sets the output current to a
default value to help improve the system safety.
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By default, the ISF and IOF flags are 0. When the IREF current exceeds the fault detection threshold, the ERR
pin is pulled down, the ISF or IOF flag is set to 1, and the error flag and ERR pin status stay unchanged until the
fault is removed and there is an ERROR clear command.
Once there is an ISF or IOF failure, the output current is set to a default value, and I(OUT)max is 10 mA; see 表 11.
Once the ISF or IOF failure is removed, the output current returns back to the set IREF value immediately.
表 11. Criteria of ISF and IOF Judgement and Corresponding Actions
IIREF
ISF
0
IOF
1
OUTPUT
I(OUT)max= 10 mA
I
IREF ≤ 10 µA
10 µA < IIREF ≤ 3 mA
0
0
I(OUT)max = VIREF × 40 / RIREF
I(OUT)max = 10 mA
IIREF > 3 mA
1
0
7.3.4.4 Pre-Thermal Warning Flag
The TLC6C5716-Q1 device implements a pre-thermal warning (PTW) function. Once the junction temperature
exceeds the PTW threshold, the ERR pin is pulled low, the PTW flag in the error status register is set to 1, and
the PTW_FLAG and ERR pin status stay unchanged until the junction temperature drops below TPTW – THYS_PTW
and there is an ERROR clear command.
7.3.4.5 Thermal Error Flag
The TLC6C5716-Q1 device monitors the junction temperature all the time. Once the junction temperature
exceeds the thermal shutdown threshold, all of the constant-current outputs turn off, the ERR pin is pulled low,
and the thermal error flag and ERR pin status are set to 1 and stay unchanged until the fault is removed and
there is an ERROR clear command. During this state, all the digital functions work normally, and users can read
or write data through the common shift registers. After the junction temperature drops below TTEF – THYS_TEF, the
device goes back to normal operation again. Users can reset the TEF flag by sending an ERROR clear
command.
7.3.4.6 Negate-Bit Toggle
TLC6C5716-Q1 implements a negate-bit toggle function to check the LOD-LSD registers and GCLK signal,
which is useful for safety-related applications.
There are NEG1 and NEG2 bits in the registers, and their values are both 0 by default. After executing the
negate-bit toggle command, both NEG1 and NEG2 change to 1. The LOD-LSD results are reversed in this
condition. If the LOD-LSD registers get stuck, the LOD-LSD results are not be toggled, which means there is a
fault in the LOD-LSD registers.
The LOD1-LSD1 registers only update on the 9th GCLK rising edge, and the LOD2-LSD2 registers only update
on the Nth GCLK rising edge. So after a negate-bit toggle command, users must wait for at least one GS counter
cycle (4096 GCLKs for the 12-bit GS counter mode, 1024 GCLKs for the 10-bit GS counter mode, and 256
GCLKs for the 8-bit GS counter mode) before reading the SID registers. So if the GCLK signal is lost, the loss
can also be detected by the negate-bit toggle function.
7.3.4.7 LOD_LSD Self-Test
The TLC6C5716-Q1 device implements an LOD_LSD self-test function to check the LOD_LSD detection circuit
to help improve the system reliability. If the LOD_LSD detection circuit fails to detect the LED failure, the
LOD_LSD self-test function can identify and report the malfunction.
The LOD_LSD self-test function can be executed by sending the LOD_LSD self-test command. The
LOD_LSD_FLAG is 000b by default. After the LOD_LSD self-test command, if there is no fault on the LOD_LSD
detection circuit, the LOD_LSD_FLAG value is 011b. If there are failures on LOD_LSD detection circuits, the
LOD_LSD_FLAG value is 110b, the ERR pin is pulled low, and the bit values stay unchanged until the fault is
removed and an ERROR clear command is executed. If the LOD_LSD_FLAG is neither 011b nor 110b, there
should be something wrong in the self-test procedure.
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7.3.4.8 ERR Pin
The TLC6C5716-Q1 device supports an active-low open-drain error output. 图 24 shows the error pulldown block
diagram. Ten bits of error status information control the error pulldown circuit directly. But an LED failure can be
masked by the LED_ERR_MASK bit. The LED_ERR_MASK default value is 1, and the LED failure is masked
from the error pulldown circuit. Even if there is an LED failure, the ERR pin is not pulled down by this LED failure.
If the LED_ERR_MASK is 0, the ERR pin is pulled down by the LED failure to indicate an error scenario. Users
can use an MCU interrupt to read out the fault information.
APS Check
LOD_LSD Self Test
TEF SENSOR
APS_FLAG
LOD_LSD_FLAG
TEF FLAG
PTW SENSOR
ISF DETECTION
IOF DETECTION
PTW FLAG
ISF FLAG
ERR
IOF FLAG
LOD1
LSD1
LOD2
LSD2
LED_ERR_MASK
OUTRn
OUTBn
图 24. ERR Pin Pulldown Scheme
7.3.4.9 ERROR Clear
This command is used to clear the error flags in the error status register and APS register. The A53h 12-bit
command code initiates an ERROR clear command. After executing an ERROR clear command, the 96-bit
LOD_LSD registers, 1-bit NEG1, 1-bit NEG2, 10-bit error status, and 24-bit adjacent-pin-short results are loaded
into the common shift register, and the error status registers and APS registers are reset to 0 if the error is
removed. See 图 9 for more detail.
7.3.4.10 Global Reset
This command is used to implement a power-on reset with software input. The A5Ch 12-bit command code
initiates a global reset command. After executing a global reset command, all internal registers are reset to their
default values. See 图 10 for more detail.
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7.3.4.11 Slew Rate Control
To improve system EMI performance, the TLC6C5716-Q1 device implements a programmable slew rate control
for the output channels. This output slew rate is configured by the SLEW_RATE bit in the FC-BC-DC register.
The SLEW_RATE bit is 0 by default, with output rise and fall times of 200 ns. When the SLEW_RATE bit is 1,
the rise and falll times of each output are 100 ns.
7.3.4.12 Channel Group Delay
Large surge currents may flow through the system if all 24 channels turn on simultaneously. These large current
surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits. The
TLC6C5716-Q1 device implements channel turnon delay for each group to reduce the surge current. The output
channels are grouped into four groups.
Group 1: OUTR0, -B0, OUTR4, -B4.
Group 2: OUTR1, -B1, OUTR5, -B5.
Group 3: OUTR2, -B2, OUTR6, -B6.
Group 4: OUTR3, -B3, OUTR7, -B7.
All group 2 channels turn on and off 50 ns later then group 1 channels, all group 3 channels turn on and off 50 ns
later than group 2 channels, and all group 4 channels turn on and off 50 ns later than group 3 channels. 图 1
shows the details.
7.4 Device Functional Modes
7.4.1 Power Up
To make the device work normally, users must provide two power supples to the TLC6C5716-Q1 device. One is
VCC, 3 V–5.5 V, for device internal logic power; the other is a supply up to 8 V, which is the power supply for the
LED loads. To make sure the LED diagnostic features work normally, the LED supply must connect to the
SENSE pin directly.
7.4.2 Device Initialization
After device power on, users must send the error clear command and global reset command to initialize the
device and make sure there are no existing faults in the circuit.
7.4.3 Fault Mode
The TLC6C5716-Q1 has full diagnostics features. The device can detect faults and latch the faults into registers.
For device faults such as IREF resistor open or short, the device enters a self-protection state, in which it reports
the faults and sets the output current to a default value. For the overtemperature fault, the device turns off the
output channels and latches the fault into the SID register. Except for these two faults, for all other faults
including LED faults, the device only detects and reports the faults, but does not take actions to handle the faults,
and the channels keep their configured status. Users must read out faults and decide how to handle the faults.
7.4.4 Normal Operation
Users must program the device through the serial interface for normal operation. Users write to the FC-BC-DC
registers to set the operation mode and output current, write to the grayscale registers to set the PWM duty cycle
for each channel, and read the SID registers to get device fault information.
7.5 Programming
7.5.1 Register Write and Read
The TLC6C5716-Q1 device is programmable via serial interface. It contains a 288-bit common shift register to
shift data from SDI into the device. The register LSB connects to SDI and the MSB connects to SDO. On each
SCK rising edge, the data on SDI shifts into the register LSB and all 288-bit data shifts towards the MSB. The
data appears on SDO when the 288-bit common shift register overflows.
The TLC6C5716-Q1 data write command contains 288-bit data. According to the following different criteria, there
are three types of data write commands: FC-BC-DC write, GS data write, and special commands.
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Programming (接下页)
•
When LATCH is high at the 288th SCK rising edge, and the 12 MSBs of the 288-bit data are 0, the 205 LSBs
of the 288-bit data shift to the function control (FC), brightness control (BC). and dot correction (DC) registers
on the LATCH rising edge, as shown in 图 2.
•
•
When LATCH is low at the 288th SCK rising edge, all 288-bit data shifts into the grayscale (GS) configuration
registers on the LATCH rising edge, as shown in 图 1.
When LATCH is high at the 288th SCK rising edge, and the 12 MSBs of the 288-bit data match any of the
eight 12-bit command codes, the device executes the corresponding command after the LATCH rising edge,
as shown in Special Command Function.
When the device powers on, the default value of the 288-bit common shift register is 0.
MSB
LSB
Common
Data
Bit 287
Common
Data
Bit 286
Common
Data
Bit 285
Common
Data
Bit 284
Common
Data
Bit 283
Common
Data
Bit 283
Common
Data
Bit 5
Common
Data
Bit 4
Common
Data
Bit 3
Common
Data
Bit 2
Common
Data
Bit 1
Common
Data
Bit 0
SDI
SDO
图 25. TLC6C5716-Q1 Common Register
7.5.1.1 FC-BC-DC Write
The device latches the 205 LSBs of data in the 288-bit common shift register into the FC-BC-DC registers at the
rising edge of the latch signal when the 12 MSBs of the 288-bit data are 0.
When the device is powered on, the FC-BC-DC data latch is reset to all 0s. Therefore, data must be written to
the 288-bit common shift register and latched into the FC-BC-DC registers before turning on the constant-current
outputs. It is better to keep BLANK low to prevent the outputs from turning on.
MSB
LSB
287 - 276
275 - 205
Reserved
204 - 192
191 - 184
183 - 176
Reserved
175 - 168
167 - 161
160 - 154
Reserved
153 - 147
41 - 35
34 - 28
27 -21
20 - 14
13 - 7
6 - 0
BC Data
OUTB Group
Bit 7-0
BC Data
OUTR Group
Bit 7-0
DC Data
OUTB7
Bit 6-0
DC Data
OUTR7
Bit 6-0
DC Data
OUTB1
Bit 6-0
DC Data
OUTR1
Bit 6-0
DC Data
OUTB0
Bit 6-0
DC Data
OUTR0
Bit 6-0
CMD
Bit 11-0
FC Data
Bit 12-0
Reserved
Reserved
SDO
SDI
Command
Code
Function
Control
Reserved
Global Brightness Control
Dot Correction
图 26. FC-BC-DC Register
7.5.1.1.1 FC Data Write
The FC data is 13 bits in length, located from bit 204 to bit 192. See 表 12 for the detailed description. The
default value for all FC data is 0, except for the LED_ERR_MASK bit which is 1.
表 12. Function-Control Data-Bit Assignment
BIT
NAME
DESCRIPTION
LOD-LSD failure or PWM error information mask bit
204
LED_ERR_MASK
0b = Any LOD-LSD failure or PWM error pulls down the ERR pin
1b = LOD-LSD failure or PWM error is masked from affecting the ERR pin
Turnon and turnoff speed configuration bit
0b = 200-ns rise and fall times.
1b = 100-ns rise and fall times.
203
202
201
200
199
SLEW_RATE
LOD_VOLATGE
LSD_VOLTAGE
APS_CURRENT
APS_TIME
LED open-detection (LOD) threshold
0b = LOD threshold is 0.3 V
1b = LOD threshold is 0.5 V
LED short-detection (LSD) threshold
0b = LSD threshold is VSENSE – 0.3 V
1b = LSD threshold is VSENSE – 0.7 V
Adjacent-pin short-detection sink current
0b = 20-µA APS current
1b = 40-µA APS current
Adjacent-pin short-detection time
0b = 10-µs APS detection time
1b = 20-µs APS detection time
32
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Programming (接下页)
表 12. Function-Control Data-Bit Assignment (接下页)
BIT
NAME
DESCRIPTION
Grayscale-counter mode selection.
00 or 01b = 12-bit mode
10b = 10-bit mode
198–197
GS_MODE
11b = 8-bit mode
Display-timing reset mode
0b = Disabled
1b = Enabled
196
195
TIMING_RESET
AUTO_REPEAT
Auto-display repeat mode
0b = Disabled
1b = Enabled
Dot-correction adjustment range for the BLUE color output
0b = Low range, 0%–66.7%
1b = High range, 33.3%–100%
194
193
192
DC_RANGE_B
Reserved
Reserved
Dot–correction adjustment range for the RED color output
0b = Low range, 0%–66.7%
DC_RANGE_R
1b = High range, 33.3%–100%
The grayscale counter has 12-bit, 10-bit, and 8-bit configurations. Bits 198–197 in the FC register configure the
grayscale counter mode.
表 13. GS Counter Mode Table
GRAYSCALE COUNTER MODE (GS_MODE)
FUNCTION MODE
Bit 198
Bit 197
0
Don't care
12-bit counter mode
10-bit counter mode, the lowest 10 bits of the
12-bit GS data are valid
1
0
1
8-bit counter mode, the lowest 8 bits of the
12-bit GS data are valid
1
7.5.1.1.2 BC Data Write
The BC data is 24 bits in length, located from bit 191 to bit 168. The data of the BC data latch are used to adjust
the constant-current values for eight channels of constant-current drivers for each color group. The current can
be adjusted by a brightness control with 8-bit resolution from 0% to 100% of maximum for each output.
表 14. Brightness-Control Data-Bit Assignments
BITS
BRIGHTNESS CONTROL DATA
OUTB0-OUTB7 group
Reserved
191–184
183–176
175–168
OUTR0-OUTR7 group
7.5.1.1.3 DC Data Write
The DC data is 168 bits in length, which located from bit 167 to bit 0. The TLC6C5716-Q1 device can adjust the
output current of each channel using the DC function. Each DC function has two adjustment ranges with 7-bit
resolution. 表 15 shows the DC data assignments in the DC registers. The high adjustment range DC can adjust
output current from 33.3% to 100% of I(OUT)max. The low adjustment range DC can configure output current from
0% to 66.7% of I(OUT)max. The range control bits, which are bits 194–192 in the function control data latch, select
the high or low adjustment. Bit 194 controls the OUTB DC range. Bit 192 controls the OUTR DC range. For
details, see 表 12.
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表 15. DC Data Assignments
BITS
DATA
BITS
83–77
76–70
69–63
62–56
55–49
48–42
41–35
34–28
27–21
20–14
13–7
DATA
167–161
160–154
153–147
146–140
139–133
132–126
125–119
118–112
111–105
104–98
97–91
OUTB7
Reserved
OUTR7
OUTB6
OUTB3
Reserved
OUTR3
OUTB2
Reserved
OUTR6
OUTB5
Reserved
OUTR2
OUTB1
Reserved
OUTR5
OUTB4
Reserved
OUTR1
OUTB0
Reserved
OUTR4
Reserved
OUTR0
90–84
6–0
表 16. Output Current vs High DC Range
CURRENT
(I(OUT)max = 40
mA)
DC DATA
(BINARY)
DC DATA
(DECIMAL)
CURRENT
DC DATA (HEX) BC DATA (HEX)
RATIO (%)
CURRENT
(I(OUT)max = 2 mA)
000 0000
000 0001
000 0010
...
0
1
00
01
02
...
FF
FF
FF
...
33.3
33.9
34.4
...
13.33
13.54
13.75
...
0.67
0.68
0.69
...
2
...
111 1101
111 1110
111 1111
125
126
127
7D
7E
7F
FF
FF
FF
99
39.58
39.79
40
1.98
1.99
2
99.5
100
表 17. Output Current vs Low DC Range
CURRENT
(I(OUT)max = 40
mA)
CURRENT
(I(OUT)max = 2 mA
)
DC DATA
(BINARY)
DC DATA
(DECIMAL)
CURRENT
DC DATA (HEX) BC DATA (HEX)
RATIO (%)
000 0000
000 0001
000 0010
...
0
1
00
01
02
...
FF
FF
FF
...
0
0.
0
0.5
1
0.21
0.42
...
0.01
0.02
...
2
...
...
111 1101
111 1110
111 1111
125
126
127
7D
7E
7F
FF
FF
FF
65.6
66.1
66.7
26.25
26.46
26.67
1.31
1.32
1.33
表 18. Output Current vs BC (High DC Range)
CURRENT
(I(OUT)max = 40
mA)
CURRENT
(I(OUT)max = 2 mA
)
BC DATA
(BINARY)
BC DATA
(DECIMAL)
CURRENT
BC DATA (HEX) BC DATA (HEX)
RATIO (%)
0000 0000
0000 0001
0000 0010
...
0
1
00
01
02
...
7F
7F
7F
...
0
0
0
0.4
0.8
...
0.16
0.32
...
0.01
0.02
...
2
...
1111 1101
1111 1110
1111 1111
253
254
255
FD
FE
FF
7F
7F
7F
99.2
99.6
100
39.69
39.84
40
1.98
1.99
2
34
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7.5.1.2 Grayscale Data Write
The grayscale data is 288 bits long, and contains a 12-bit grayscale value for each output. The grayscale value
sets the channel turnon time.图 27 shows the GS register configuration. 图 1 is the GS write timing diagram.
Data is latched from the 288-bit common shift register into the GS data latch at the rising edge of the LATCH pin.
When data is latched into the GS registers, the new data is immediately available on the constant-current
outputs. If the data is latched with BLANK high, the outputs may turn on or off unexpectedly. So users should
update the GS data when BLANK is low.
The 12-bit GS function has 4096 brightness steps, from 0% to 99.97% brightness. The GS function is controlled
by a 12-bit GS counter. The GS counter increments on each rising edge of the grayscale reference clock GCLK.
The falling edge of BLANK resets the GS counter value to 0. The GS counter value stays at 0 while BLANK is
low, even if there is a GCLK input. Pulling BLANK high enables the 12-bit GS counter. The first rising edge of a
GS clock after BLANK goes high increments the GS counter by one and turns on the outputs. Each additional
rising edge increases the GS counter by one. The GS counter monitors the number of clock pulses on the GCLK
pin. The output stays on while the counter value is less than or equal to the GS setting value. The output turns
off at the rising edge of the GS counter value when the counter is larger than the GS setting value. 表 20 is the
on-time duty cycle of each GS data bit when the 12-bit GS counter mode is selected.
When the device is powered up, the 288-bit common shift register and GS data latch are reset to 0.
公式 4 describes each output on-time.
tON = tGCLK ìGS
where
•
•
tGCLK is the GS clock period
GS is the programmed grayscale value for each output.
(4)
公式 5 shows the duty-cycle calculation equation.
GS
Dutycycle =
4096
(5)
MSB
LSB
287 - 276
275 - 264
Reserved
264 - 253
252 - 241
240 - 239
Reserved
238 - 227
71 - 60
59 - 48
47 - 36
35 - 24
23 - 12
11 - 0
GS Data
OUTB7
Bit 11-0
GS Data
OUTR7
Bit 11-0
GS Data
OUTB6
Bit 11-0
GS Data
OUTR6
Bit 11-0
GS Data
OUTB1
Bit 11-0
GS Data
OUTR1
Bit 11-0
GS Data
OUTB0
Bit 11-0
GS Data
OUTR0
Bit 11-0
Reserved
Reserved
SDI
SDO
图 27. TLC6C5716-Q1 Grayscale Register
Once the GS data is latched into the GS registers at the rising edge of the LATCH signal, the FC-BC-DC data
latch shifts into the lowest 205 bits of the common shift register. So, the FC-BC-DC data can be read out from
SDO in GS write. This FC-BC-DC read function can also be realized by the read FC-BC-DC command, see FC-
BC-DC Read and 图 8 for the timing diagram.
表 19. Grayscale Data Bit Assignments
BITS
DATA
OUTB7
Reserved
OUTR7
OUTB6
Reserved
OUTR6
OUTB5
Reserved
OUTR5
OUTB4
Reserved
OUTR4
BITS
143–132
131–120
119–108
107–96
95–84
DATA
OUTB3
Reserved
OUTR3
OUTB2
Reserved
OUTR2
OUTB1
Reserved
OUTR1
OUTB0
Reserved
OUTR0
287–276
275–264
263–252
251–240
239–228
227–216
215–204
203–192
191–180
179–168
167–156
155–144
83–72
71–60
59–48
47–36
35–24
35–24
11–0
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表 20. GS Data vs Output On Time
ON-TIME BASED ON 33-
MHz GS CLOCK (ns)
GS DATA (BINARY)
GS DATA (DECIMAL)
GS DATA (HEX)
DUTY CYCLE (%)
0000 0000 0000
0000 0000 0001
0000 0000 0010
...
0
000
001
002
...
0
0
1
0.02
0.05
...
30
2
61
...
...
0111 1111 1111
1000 0000 0000
1000 0000 0001
...
2047
2048
2049
...
7FF
800
801
...
49.97
50.00
50.02
...
62 030
62 061
62 091
...
1111 1111 1101
1111 1111 1110
1111 1111 1111
4093
4094
4095
FFD
FFE
FFF
99.93
99.95
99.98
124 030
124 061
124 091
7.5.1.3 Special Command Function
There are eight special command codes defined in the TLC6C5716-Q1 device, shown in 表 21. To input the
command, the level of LATCH at the last SCK before the LATCH rising edge must be high, and the highest 12
bits should be one of the below 8 command codes. In this condition, the device ignores other bits and no data
are latched into FC-BC-DC registers. Normally users can write other bits to 0 in the special command. The
corresponding command function executes after the rising edge of LATCH signal.
If no special command code is identified, the command is a NULL command and no special command is
executed. The command is the same as the FC-BC-DC write function.
表 21. Special Command Codes
COMMAND
GS read
COMMAND CODE
5AFh (0101 1010 1111b)
5A3h (0101 1010 0011b)
FUNCTION
Load GS data into common register.
SID read
Load SID data into common register.
Load FC-BC-DC data into common register. This reading function
can also be achieved by GS data write.
FC-BC-DC read
APS check
5ACh (0101 1010 1100b)
53Ah (0101 0011 1010b)
535h (0101 0011 0101b)
Adjacent pin short detection, APS test starts at the rising edge of
Latch signal, then set APS register(24bits) and APS_Flag in SID
register according to the test result. Keep all channels off during this
test.
LOD-LSD detector circuit self test and set LOD_LSD_FLAG in SID
register according to the test result.
LOD_LSD self-test
Toggle Negate Bit. When Negate Bit = 0, the 48 bits LOD-LSD
detector output data will be latched into LOD1-LSD1 and LOD2-LSD2
register without invert. When Negate Bit =1, the 48 bits LOD-LSD
detector output data will invert, and latch into LOD1-LSD1 and LOD2-
LSD2 register.
Negate bit toggle
55Ah (0101 0101 1010b)
Load SID data into common register, and then reset the Error status
register and APS register to 0.
ERROR clear
A53h (1010 0101 0011b)
A5Ch (1010 0101 1100b)
All internal registers are reset. The command has the same function
as power on reset.
GLOBAL reset
NULL
Different from any of the above commands The same function as FC-BC-DC write.
7.5.1.3.1 GS Read
The GS read command loads the 288-bit GS data into the common register. By applying 288 SCK clocks, the
GS data shifts out from SDO pin. For details, see 图 3.
7.5.1.3.2 FC-BC-DC Read
There are two ways to read the FC-BC-DC data latch.
36
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One way is latching data into the GS data latch. After the GS write finishes, the FC-BC-DC data latches into the
lowest 205 bits of the common shift register.
Another way is using the FC-BC-DC read command. After the FC-BC-DC read command finishes, the FC-BC-DC
data latches into the lowest 205 bits of the common shift register.
By applying 288 SCK clocks, the FC-BC-DC data shifts out from the SDO pin. For details, see 图 8
7.5.1.3.3 Status Information Data Read
Status information data (SID) is 132 bits long and contains device status information and LED fault information.
表 22 describes the bit mapping when the SID data loads into the common shift register.
Bits 287–240 are the LED-open information for the output channels, bits 203–144 are the LED-short information
for the output channels, bits 239–216 are the adjacent-pin-short information for the output channels, bits
215–206 are the error status registers, bits 205–204 are the negate bits, and the others are reserved registers.
After power on, all error status registers are set to 0. If any one of the error-status-register flags (bits 215-206)
asserts, the registers latch the faults until a reset error command is executed to clear the faults. But the
LOD_LSD data continues to update every PWM cycle.
表 22. SID Register
BITS OF COMMON
DESCRIPTION
SHIFT REGISTER
287–280
279–272
271–264
263–256
255–248
247–240
239–232
231–224
223–216
215
LOD2 data for OUTB7–OUTB0
Reserved
LOD2 data for OUTR7–OUTR0
LOD1 data for OUTB7–OUTB0
Reserved
LOD1 data for OUTR7–OUTR0
APS data for OUTB7–OUTB0
APS data for NU pins [pin 7, pin 10, pin 13, pin 16, pin 23, pin 26, pin 29, pin 32]
APS data for OUTR7–OUTR0
Thermal error flag (TEF). 0b = Normal temperature condition, 1b = High-temperature condition.
Pre-thermal warning (PTW). 0b = No pre-thermal warning, 1b = Pre-thermal threshold triggered.
Adjacent-pin short-check result (APS_FLAG). 011b: pass, 110b: fail.
IREF-resistor short flag (ISF). 0b = IREF resistor is not shorted, 1b = IREF resistor short detected.
IREF-resistor open flag (IOF). 0b = IREF Resistor is not open, 1b = IREF resistor open detected.
LOD-LSD detection circuit self-test result (LOD_LSD_FLAG). 011b: pass, 110b: fail.
Negate bit for LOD1-LSD1 register (NEG1)
214
213–211
210
209
208–206
205
204
Negate bit for LOD2-LSD2 register (NEG2)
203–192
191–184
183–176
175–168
167–160
159–152
151–144
143–0
Reserved
LSD2 data for OUTB7–OUTB0
Reserved
LSD2 data for OUTR7–OUTR0
LSD1 data for OUTB7–OUTB0
Reserved
LSD1 data for OUTR7–OUTR0
Reserved
7.6 Register Maps
The TLC6C5716-Q1 register map includes three sections: GS registers, FC_BC_DC registers, and SID registers.
Users can write to the GS registers and FC_BC_DC registers through the serial interface. Status information can
be read out though the serial interface.
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Register Maps (continued)
7.6.1 GRAYSCALE Registers
Table 23 lists the memory-mapped registers for the GRAYSCALE. All register offset addresses not listed in
Table 23 should be considered as reserved locations and the register contents should not be modified.
Grayscale Register
Table 23. GRAYSCALE Registers
Offset
Acronym
Register Name
Section
0h
OUTn_GS
OUTn_GS Register
Go
Complex bit access types are encoded to fit into small table cells. Table 24 shows the codes that are used for
access types in this section.
Table 24. GRAYSCALE Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.1.1 OUTn_GS Register (Offset = 0h)
OUTn_GS is shown in Figure 28 and described in Table 25.
Return to Summary Table.
OUTn Grayscale Register
Figure 28. OUTn_GS Register
287
275
263
251
239
227
215
286
274
262
250
238
226
214
285
273
261
249
237
225
213
284
272
260
248
236
224
212
283
271
259
247
235
223
211
282
OUTB7_GS
R/W-0h
281
280
268
256
244
232
220
208
279
267
255
243
231
219
207
278
266
254
242
230
218
206
287
265
253
241
229
217
205
286
264
252
240
228
216
204
270
269
RESERVED
R/W-0h
258
257
OUTR7_GS
R/W-0h
246
245
OUTB6_GS
R/W-0h
234
233
RESERVED
R/W-0h
222
221
OUTR6_GS
R/W-0h
210
209
OUTB5_GS
R/W-0h
38
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203
202
190
178
166
154
142
130
118
106
94
201
189
177
165
153
141
129
117
105
93
200
188
176
164
152
140
128
116
104
92
199
187
175
163
151
139
127
115
103
91
198
RESERVED
R/W-0h
197
196
184
172
160
148
136
124
112
100
88
195
183
171
159
147
135
123
111
99
194
182
170
158
146
134
122
110
98
193
181
169
157
145
133
121
109
97
192
180
168
156
144
132
120
108
96
191
179
167
155
143
131
119
107
95
186
185
OUTR5_GS
R/W-0h
174
173
OUTB4_GS
R/W-0h
162
161
RESERVED
R/W-0h
150
149
OUTR4_GS
R/W-0h
138
137
OUTB3_GS
R/W-0h
126
125
RESERVED
R/W-0h
114
113
OUTR3_GS
R/W-0h
102
101
OUTB2_GS
R/W-0h
90
89
87
86
85
84
RESERVED
R/W-0h
83
82
81
80
79
78
77
76
75
74
73
72
OUTR2_GS
R/W-0h
71
70
69
68
67
66
65
64
63
62
61
60
OUTB1_GS
R/W-0h
59
58
57
56
55
54
53
52
51
50
49
48
RESERVED
R/W-0h
47
46
45
44
43
42
41
40
39
38
37
36
OUTR1_GS
R/W-0h
35
34
33
32
31
30
29
28
27
26
25
24
OUTB0_GS
R/W-0h
23
22
21
20
19
18
17
16
15
14
13
12
RESERVED
R/W-0h
11
10
9
8
7
6
5
4
3
2
1
0
OUTR0_GS
R/W-0h
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Table 25. OUTn_GS Register Field Descriptions
Bit
Field
Type
Default
Description
287–276
OUTB7_GS[11:0]
R/W
0h
Grayscale register for OUTB7
Reserved
275–264
263–252
251–240
239–228
227–216
215–204
203–192
191–180
179–168
167–156
155–144
143–132
131–120
119–108
107–96
95–84
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
OUTR7_GS[11:0]
OUTB6_GS[11:0]
RESERVED
Grayscale register for OUTR7
Grayscale register for OUTB6
Reserved
OUTR6_GS[11:0]
OUTB5_GS[11:0]
RESERVED
Grayscale register for OUTR6
Grayscale register for OUTB5
Reserved
OUTR5_GS[11:0]
OUTB4_GS[11:0]
RESERVED
Grayscale register for OUTR5
Grayscale register for OUTB4
Reserved
OUTR4_GS[11:0]
OUTB3_GS[11:0]
RESERVED
Grayscale register for OUTR4
Grayscale register for OUTB3
Reserved
OUTR3_GS[11:0]
OUTB2_GS[11:0]
RESERVED
Grayscale register for OUTR3
Grayscale register for OUTB2
Reserved
83–72
OUTR2_GS[11:0]
OUTB1_GS[11:0]
RESERVED
Grayscale register for OUTR2
Grayscale register for OUTB1
Reserved
71–60
59–48
47–36
OUTR1_GS[11:0]
OUTB0_GS[11:0]
RESERVED
Grayscale register for OUTR1
Grayscale register for OUTB0
Reserved
35–24
23–12
11–0
OUTR0_GS[11:0]
Grayscale register for OUTR0
7.6.2 FC-BC-DC Registers
Table 26 lists the memory-mapped registers for the CONFIGURATION. All register offset addresses not listed in
Table 26 should be considered as reserved locations and the register contents should not be modified.
Configuration Register
Table 26. FC-BC-DC Registers
Offset
Acronym
Register Name
Section
1h
Config
Configuration Register
Go
Complex bit access types are encoded to fit into small table cells. Table 27 shows the codes that are used for
access types in this section.
40
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Table 27. FC-BC-DC Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.2.1 FC-BC-DC Register (Offset = 1h)
FC-BC-DC is shown in Figure 29 and described in Table 28.
Return to Summary Table.
FC-BC-DC Register
Figure 29. FC-BC-DC Register
287
271
255
239
223
207
286
270
254
238
222
285
269
253
237
221
205
284
268
252
236
220
204
283
267
251
235
219
203
282
CMD
R/W-0h
266
281
280
279
278
262
246
230
214
198
277
261
245
229
213
197
276
260
244
228
212
196
275
259
243
227
211
195
274
273
272
256
240
224
208
192
RESERVED
R/W-0h
265
249
233
217
201
264
263
258
242
226
210
194
257
241
225
209
193
RESERVED
R/W-0h
250
234
218
202
248
247
RESERVED
R/W-0h
232
231
RESERVED
R/W-0h
216
215
RESERVED
R/W-0h
206
200
199
RESERVED
LED_E SLEW LOD_ LSD_V APS_ APS_T
GS_MODE
TIMIN AUTO DC_R RESE DC_R
G_RE _REP ANGE RVED ANGE
RR_M _RAT VOLT OLTA CURR
IME
ASK
E
AGE
GE
ENT
SET
EAT
_B
_R
R/W-0h
190
R/W-
1h
R/W-
0h
R/W-
0h
R/W-
0h
R/W-
0h
R/W-
0h
R/W-0h
R/W-
0h
R/W-
0h
R/W-
0h
R/W-
0h
R/W-
0h
191
175
159
189
173
157
188
187
186
170
154
138
185
169
153
137
184
168
152
183
167
151
135
182
166
181
165
149
133
180
179
178
162
146
130
177
176
OUTB_BC
R/W-0h
172 171
RESERVED
R/W-0h
174
158
142
164
163
147
131
161
160
OUTR_BC
R/W-0h
OUTB7_DC
R/W-0h
→
→
156
155
150
148
145
144
←
RESERVED
R/W-0h
OUTR7_DC
R/W-0h
OUTB6_DC
R/W-0h
←
143
141
140
139
136
134
132
129
128
OUTB6_DC
R/W-0h
RESERVED
R/W-0h
OUTR6_DC
R/W-0h
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127
126
125
109
93
124
123
107
91
122
121
105
89
120
104
88
119
103
118
102
86
117
116
100
84
115
114
98
113
112
OUTR6_DC
R/W-0h
OUTB5_DC
R/W-0h
RESERVED
R/W-0h
111
110
108
106
101
99
83
67
97
96
OUTR5_DC
R/W-0h
OUTB4_DC
R/W-0h
RESERVED
R/W-0h
95
94
92
90
87
85
69
53
82
81
80
RESERVED
R/W-0h
OUTR4_DC
R/W-0h
OUTB3_DC
R/W-0h
79
78
77
76
60
44
75
74
73
72
71
55
39
70
68
66
65
64
OUTB3_DC
R/W-0h
RESERVED
R/W-0h
OUTR3_DC
R/W-0h
→
→
63
62
46
30
61
45
59
58
42
26
10
57
41
25
56
54
52
51
35
19
3
50
34
18
49
48
←
OUTB2_DC
R/W-0h
RESERVED
R/W-0h
→
→
←
47
43
27
11
40
38
37
21
5
36
20
4
33
32
←
←
OUTR2_DC
R/W-0h
OUTB1_DC
R/W-0h
RESERVED
R/W-0h
31
29
28
24
23
7
22
17
16
0
RESERVED
R/W-0h
OUTR1_DC
R/W-0h
OUTB0_DC
R/W-0h
15
14
13
12
9
8
6
2
1
OUTB0_DC
R/W-0h
RESERVED
R/W-0h
OUTR0_DC
R/W-0h
Table 28. FC-BC-DC Register Field Descriptions
Bit
Field
Type
Default
Description
287–276
CMD[11:0]
R/W
0h
Command function
25Ch = Global reset
535h = LOD_LSD self-test
53Ah = APS check
55Ah = NEG-BIT toggle
5A3h = SID read
5ACh = FC_BC_DC read
5AFh = GS read
A53h = ERROR clear
All other values = NULL
275–205
204
RESERVED
R/W
R/W
0h
1h
Reserved
LED_ERR_MASK
LED error mask
0h = Unmask LED error
1h = Mask LED error
203
202
201
SLEW_RATE
R/W
R/W
R/W
0h
0h
0h
Output slew-rate
0h = 100 ns
1h = 200 ns
LOD_VOLTAGE
LSD_VOLTAGE
LED-open detection voltage
0h = 0.3 V
1h = 0.5 V
LED-short detection voltage
0h = VVSENSE – 0.3 V
1h = VVSENSE – 0.7 V
42
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Table 28. FC-BC-DC Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
200
APS_CURRENT
R/W
0h
Adjacent-pin short-detection sink current
0h = 20 µA
1h = 40 µA
199
APS_TIME
R/W
R/W
0h
0h
Adjacent-pin short-detection time
0h = 10 µs
1h = 20 µs
198–197
GS_MODE[1:0]
Grayscale counter mode
0h or 1h = 12-bit counter mode
2h = 10-bit counter mode
3h = 8-bit counter mode
196
195
194
TIMING_RESET
AUTO_REPEAT
DC_RANGE_B
R/W
R/W
R/W
0h
0h
0h
Display timing reset
0h = Disabled
1h = Enabled
Auto repeat
0h = Disabled
1h = Enabled
Dot correction range for OUTB group
0h = Low range
1h = High range
193
192
RESERVED
R/W
R/W
0h
0h
Reserved
DC_RANGE_R
Dot correction range for OUTR group
0h = Low range
1h = High range
191–184
183–176
175–168
167–161
160–154
153–147
146–140
139–133
132–126
125–119
118–112
111–105
104–98
97–91
OUTB_BC[7:0]
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Brightness control for OUTB group
Reserved
OUTR_BC[7:0]
OUTB7_DC[6:0]
RESERVED
Brightness control for OUTR group
Dot correction for OUTB7
Reserved
OUTR7_DC[6:0]
OUTB6_DC[6:0]
RESERVED
Dot correction for OUTR7
Dot correction for OUTB6
Reserved
OUTR6_DC[6:0]
OUTB5_DC[6:0]
RESERVED
Dot correction for OUTR6
Dot correction for OUTB5
Reserved
OUTR5_DC[6:0]
OUTB4_DC[6:0]
RESERVED
Dot correction for OUTR5
Dot correction for OUTB4
Reserved
90–84
OUTR4_DC[6:0]
OUTB3_DC[6:0]
RESERVED
Dot correction for OUTR4
Dot correction for OUTB3
Reserved
83–77
76–70
69–63
OUTR3_DC[6:0]
OUTB2_DC[6:0]
Dot correction for OUTR3
Dot correction for OUTB2
62–56
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Table 28. FC-BC-DC Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
55–49
RESERVED
R/W
0h
Reserved
48–42
41–35
34–28
27–21
20–14
13–7
OUTR2_DC[6:0]
OUTB1_DC[6:0]
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
Dot correction for OUTR2
Dot correction for OUTB1
Reserved
OUTR1_DC[6:0]
OUTB0_DC[6:0]
RESERVED
Dot correction for OUTR1
Dot correction for OUTB0
Reserved
6–0
OUTR0_DC[6:0]
Dot correction for OUTR0
7.6.3 SID Registers
Table 29 lists the memory-mapped registers for the SID. All register offset addresses not listed in Table 29
should be considered as reserved locations and the register contents should not be modified.
SID Register
Table 29. SID Registers
Offset
Acronym
Register Name
Section
2h
SID
SID Register
Go
Complex bit access types are encoded to fit into small table cells. Table 30 shows the codes that are used for
access types in this section.
Table 30. SID Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Reset or Default Value
-n
Value after reset or the default
value
7.6.3.1 SID Register (Offset = 2h)
SID is shown in Figure 30 and described in Table 31.
Return to Summary Table.
Status information data
Figure 30. SID Register
287
271
255
239
286
270
254
238
285
269
253
237
284
283
282
266
250
234
281
265
249
233
280
264
248
232
279
263
247
231
278
262
246
230
277
261
245
229
276
275
274
258
242
226
273
257
241
225
272
256
240
224
OUTB_LOD2
R-0h
RESERVED
R-0h
268
267
260
259
OUTR_LOD2
R-0h
OUTB_LOD1
R-0h
252
251
244
243
RESERVED
R-0h
OUTR_LOD1
R-0h
236
235
228
227
OUTB_APS
R-0h
NU_PIN_APS
R-0h
44
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223
222
221
205
220
219
218
202
217
201
216
200
215
TEF
R-0h
214
PTW
R-0h
213
197
212
APS_FLAG
R-0h
211
210
ISF
209
IOF
208
OUTR_APS
R-0h
→
R-0h
R-0h
→
207
206
204
203
199
198
196
195
194
193
192
←
←
LOD_LSD_ NEG1 NEG0
FLAG
RESERVED
R-0h
190
R-0h
189
R-0h
188
R-0h
191
187
186
170
154
138
122
106
90
185
169
153
137
121
105
89
184
168
152
136
183
167
151
135
182
166
150
134
118
102
86
181
165
149
133
117
101
85
180
179
178
162
146
130
114
98
177
161
145
129
113
97
176
160
144
128
112
96
OUTB_LSD2
R-0h
RESERVED
R-0h
175
159
143
127
111
95
174
158
142
126
110
94
173
157
141
125
109
93
172
171
164
163
OUTR_LSD2
R-0h
OUTB_LSD1
R-0h
156
155
148
147
RESERVED
R-0h
OUTR_LSD1
R-0h
140
124
108
92
139
123
107
91
132
116
100
84
131
115
99
83
67
51
35
19
3
RESERVED
R-0h
120
119
RESERVED
R-0h
104
103
RESERVED
R-0h
88
87
82
81
80
RESERVED
R-0h
79
78
77
76
75
74
73
72
71
70
69
68
66
65
64
RESERVED
R-0h
63
62
61
60
59
58
57
56
55
54
53
52
50
49
48
RESERVED
R-0h
47
46
45
44
43
42
41
40
39
38
37
36
34
33
32
RESERVED
R-0h
31
30
29
28
27
26
25
24
23
22
21
20
18
17
16
RESERVED
R-0h
15
14
13
12
11
10
9
8
7
6
5
4
2
1
0
RESERVED
R-0h
Table 31. SID Register Field Descriptions
Bit
Field
Type
Default
Description
287–280
OUTB_LOD2[7:0]
R
0h
LOD2 for OUTB7–OUTB0. For each channel:
0h = No fault detected
1h = Fault detected
279–272
RESERVED
R
0h
Reserved
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Table 31. SID Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
271–264
OUTR_LOD2[7:0]
R
0h
LOD2 for OUTR7–OUTR0. For each channel:
0h = No fault detected
1h = Fault detected
263–256
OUTB_LOD1[7:0]
R
0h
LOD1 for OUTB7–OUTB0. For each channel:
0h = No fault detected
1h = Fault detected
255–248
247–240
RESERVED
R
R
0h
0h
Reserved
OUTR_LOD1[7:0]
LOD1 for OUTR7–OUTR0. For each channel:
0h = No fault detected
1h = Fault detected
239–232
231–224
OUTB_APS[7:0]
R
R
0h
0h
APS status for OUTB7–OUTB0. For each channel:
0h = No fault detected
1h = Fault detected
NU_PIN_APS[7:0]
APS status of not-used pins , NU_PIN_APS[7:0] = [pin7, pin10,
pin13, pin16, pin23, pin26, pin29, pin32]
0h = No fault detected
1h = Fault detected
223–216
215
OUTR_APS[7:0]
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
0h
APS status for OUTR7–OUTR0. For each channel:
0h = No fault detected
1h = Fault detected
TEF
Thermal error flag
0h = No fault detected
1h = Fault detected
214
PTW
Pre-thermal warning flag
0h = No fault detected
1h = Fault detected
213–211
210
APS_FLAG[2:0]
APS test flag fault
3h = APS test passes
6h = APS test fails
ISF
IOF
ISF fault
0h = No fault detected
1h = Fault detected
209
IOF fault
0h = No fault detected
1h = Fault detected
208– 206 LOD_LSD_FLAG[2:0]
LOD_LSD self-test flag
3h = LOD_LSD self-test passes
6h = LOD_LSD self-test fails
205
204
NEG1
R
R
R
R
0h
0h
0h
0h
Neg1 bit value
Neg0 bit value
Reserved
NEG0
203–192
191–184
RESERVED
OUTB_LSD2[7:0]
LSD2 for OUTB7–OUTB0. For each channel:
0h = No fault detected
1h = Fault detected
183–176
RESERVED
R
0h
Reserved
46
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Table 31. SID Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
175–168
OUTR_LSD2[7:0]
R
0h
LSD2 for OUTR7–OUTR0. For each channel:
0h = No fault detected
1h = Fault detected
167–160
OUTB_LSD1[7:0]
R
0h
LSD1 for OUTB7– OUTB0. For each channel:
0h = No fault detected
1h = Fault detected
159–152
151–144
RESERVED
R
R
0h
0h
Reserved
OUTR_LSD1[7:0]
LSD1 for OUTR7–OUTR0. For each channel:
0h = No fault detected
1h = Fault detected
143–0
RESERVED
R
0h
Reserved
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Below is a typical application for an automotive local dimming application.
8.2 Typical Application
In automotive LCD display applications such as a solid-state cluster or center information display, LED
backlighting is one of the key parts of the display. Today most LED backlighting is the traditional edge-lit type,
which means the backlighting is globally dimmed. This method consumes much power and causes light leakage
from the liquid crystals in the black areas, because the backlighting is always turned on. Recently, local-dimming
backlighting, a direct-lit type of backlighting, has been proposed to overcome this drawback. The lighting level of
the backlighting follows the display contents. The lighting level is dynamically adjusted by the content of the
image blocks for local-dimming control. When an image block is bright, the lighting level of the backlighting turns
high also. Conversely, the backlighting level is adjusted to low in a black region. This arrangement reduces
power dissipation and light leakage from the LCD and creates pure black, increasing the image contrast ratio.
Users can use the TLC6C5716-Q1 device to drive LED backlighting in such local dimming applications.
Depending how many zones are in the display, users can connect different numbers of TLC6C5716-Q1s in a
daisy chain to drive the LEDs.
LED supply
GND
OUTR0
SENSE
SDI
OUTB7
SDO
ERR
SENSE
SDI
OUTR0
OUTB7
SDO
ERR
SCK
SCK
LATCH
LATCH
µC
TLC6C5716-Q1
TLC6C5716-Q1
GCLK
GCLK
BLANK
IREF
VCC
VCC
BLANK
IREF
GND
GND
GND
GND
图 31. Typical Block Diagram for Local Dimming
48
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Typical Application (接下页)
8.2.1 Design Requirements
表 32 shows the design requirements for the local dimming application.
表 32. Design Requirements
PARAMETER
LCD size
VALUE
12.3 inches
128
Zones
Number of LEDs per string
LED current
1
50 mA
8.2.2 Detailed Design Procedure
As the backlighting includes 128 zones, each TLC6C5716-Q1 device can drive 16 zones, so a total of eight
TLC6C5716-Q1 units are needed.
According to Maximum Constant-Sink-Current Setting, to realize 50-mA output current, users can choose a
0.96–kΩ reference resistor.
Users can use a daisy chain connection to control all of the eight TLC6C5716-Q1 devices through one serial
interface, just as 图 31 shows. 图 32 shows how to send the data into cascaded devices, where M is the number
of cascaded devices.
If more current is needed, users can parallel two outputs together to get more current.
M*288 bits
M*288 bits
M*288 bits
M*288 bits
SDI
LATCH
Write FC-BC-DC Data
Write FC-BC-DC Data
Write GS Data
Write GS Data
图 32. Cascading Data Write
8.2.3 Application Curves
Below are two test waveforms. 图 33 shows different PWM duty cycles for different output channels, which can
realize a local dimming feature. 图 34 shows a data-write waveform typical for each write of M × 288 bits of data
into the serial interface.
图 33. Individual PWM Dimming for Each Channel
图 34. Data Write Through the Serial Interface
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9 Power Supply Recommendations
The TLC6C5716-Q1 device requires two power supplies. One is VCC, which can range from 3 V to 5.5 V. The
other is VLED, which can be up to 8 V. Users must add a capacitor on the VCC power supply to filter noise. Place
the capacitor as close to the VCC pin and SENSE pin as possible.
10 Layout
10.1 Layout Guidelines
图 35 shows a layout example for the TLC6C5716-Q1 device. To improve the thermal performance, TI
recommends to use the GND plane to dissipate the heat. To filter the supply noise, users can put the capacitor
as close to the VCC and SENSE pins as possible. The IREF resistor also should be connected as close to IREF
pin as possible.
10.2 Layout Example
To µC
To µC
To µC
SDI
SCK
SENSE
NC
LED Supply
LATCH
GCLK
GCLK
GCLK
NU
BLANK
VCC
To µC
VCC = 3 to 5.5V
To µC
IREF
GND
NU
OUTR0
OUTB0
NU
OUTR7
OUTB7
NU
TLC6C5716-Q1
OUTR1
OUTB1
NU
OUTR6
OUTB6
NU
OUTR2
OUTB2
OUTR5
OUTB5
NU
NU
OUTR3
OUTB3
SDO
OUTR4
OUTB4
ERR
To µC
To µC
图 35. TLC6C5716-Q1 Example Layout Diagram
50
版权 © 2018, Texas Instruments Incorporated
TLC6C5716-Q1
www.ti.com.cn
ZHCSIG2A –JULY 2018–REVISED AUGUST 2018
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航面板。
版权 © 2018, Texas Instruments Incorporated
51
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2018 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC6C5716QDAPRQ1
ACTIVE
HTSSOP
DAP
38
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TLC6C5716Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
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